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Readme for SPB Release version 17.2/ H# f* X5 B4 X& K6 m; O, R2 j7 l
9 [7 z9 O# \; g$ k: zCopyright (c) 2019 Cadence Design Systems, Inc.! E+ X1 \# U3 B6 M1 J( w
All rights reserved worldwide.8 x* J7 q. c7 [* D# U
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* [ R8 B. w- _7 OFixed CCRs: SPB 17.2 HF060" b3 t% D5 s$ h3 t. c/ i9 h( }
10-11-2019. G% A7 @; u( |: e
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) c4 ?" f& C& u# [# A) p* R6 ECCRID Product ProductLevel2 Title8 i3 @& o# n3 `) Z2 `' _. W
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2137594 ADW DBADMIN EDM is not allowing to modify step model
, A9 @/ i" Y& U* s9 P+ w a2115805 ADW DBEDITOR 'BOTH' in ALT_SYMBOLS prevents correct generation of part_table.ptf3 G' n9 y: c6 I2 R) P3 R1 e5 v
2135452 ADW DBEDITOR DBEditor poor performance in high latency networks @) K3 H% \0 L y3 d& @# W! l
2142315 ADW LIBDISTRIBUTI EDM Library Server stops often and adwserver.out file is extremely large, more than 1GB
/ Z" ~8 Z0 J1 a; x2155396 ALLEGRO_EDITOR DATABASE Netlist error when importing from Capture CIS
& l' ^! n" }8 G+ w6 o6 a$ Z. N* f4 e2118231 ALLEGRO_EDITOR DRC_CONSTR Crash during DRC: DBDoctor exits with error 'Illegal database pointer encountered'$ Y* \) E( r/ d( }/ n" d. w
2150923 ALLEGRO_EDITOR DRC_CONSTR Via at SMD fit DRC not detected with rounded rectangle pads
6 h# ^! v! O( v) r x. {2140441 ALLEGRO_EDITOR EDIT_ETCH Drill hole to line DRC while sliding but 'Allow DRC' is not selected in the Options tab1 w/ h, Y, G5 f: d- x/ g+ U
2141329 ALLEGRO_EDITOR INTERFACE_DES Error message (SPMHSY-49) displayed on running 'Tools' - 'Database Check'
( e }/ z0 {1 y' g( N1 l3 H! G2126562 ALLEGRO_EDITOR MODULES Create Module File / Place replicate assigns incorrect netname
$ I5 g2 X9 ?8 O. j8 J( v2150410 ALLEGRO_EDITOR SCHEM_FTB netrev.lst is created in the wrong folder; E" V; ^) q& {2 M
2136158 ALLEGRO_EDITOR STEP Update STEP Mapping Data Only should be seperate Menu/Command.& A4 E- @3 R9 `" z" B
2137801 APD VIA_STRUCTURE High speed via structure instance not adding properly0 s7 d6 B- D" f, e- X, i7 W$ |
2145072 CONCEPT_HDL CORE Error on choosing 'Enable Hierarchical Variant'. J* `$ y$ w0 }- b8 s( e
2124843 PCB_LIBRARIAN CORE Prompt displayed for license choice marked to be used as default
6 n' z( G( i3 c& D) V2141656 PCB_LIBRARIAN CORE Part Developer pop-up option 'Edit' for symbols displays an error message
, c8 t7 j; c3 |! ]# W1 }! F1 j2125794 PCB_LIBRARIAN SYMBOL_EDITOR Part Developer new Symbol Editor: cannot move inverted pins that contain circle and dot) m" X' T) P7 x6 Z
2161864 PULSE R2PLM Second publish with CPM-derived item number and cadName set to $NUMBER causes 'an item is not unique' error/ w8 n) Y# Q' ~
1997911 SIP_LAYOUT ORBITIO_IF Support keepout translation between OrbitIO and Allegro layout/physical editors
' Y/ h* j( x4 Q7 M( `- W+ q T( }5 @5 K0 g% ?
" a* O* l; C- |" T4 j2 tFixed CCRs: SPB 17.2 HF059( \: W! }" C/ R# {2 y# t: u
09-13-2019* k: }/ @ b" @( M4 `4 l1 @; Y
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CCRID Product ProductLevel2 Title# Q \$ ~ e, H# B
========================================================================================================================================================
8 w& t) N* W! m) r/ d2112454 ADW DBEDITOR Icons in DBEditor do not start applications after renaming a model$ E( M+ Y5 O- Y. h4 L& g
2120548 ADW LIBIMPORT Missing alternate footprints from vault area after library import.
2 c% U1 D9 \* K2143314 ADW PART_BROWSER Component Browser does not start after installing HotFix 057 of release 17.2-2016% K# E" }9 U% ~% f9 S, o% n
2122302 ALLEGRO_EDITOR ARTWORK Coverlay details not being output to Artwork data as per the visibility
" ~$ Y' ]) B% ?2135521 ALLEGRO_EDITOR ARTWORK Artwork dimensions do not match Allegro PCB Editor8 Y: c/ M! w# Z1 M0 }* c# k; _
2054584 ALLEGRO_EDITOR DATABASE Through hole mechanical pin in zone area without Soldermask Top still shows a pad on Soldermask Top
8 v! ^/ S6 i2 i2111444 ALLEGRO_EDITOR DATABASE No soldermask for mechanical holes within zone6 v( t+ s" `( y2 T- A" w- x
2115596 ALLEGRO_EDITOR DATABASE Unused Pad Suppression removes pin connected to shape using Net_short property
. f0 q/ o+ B; I1 K c* p: I: E% _, B2135436 ALLEGRO_EDITOR EDIT_ETCH Allegro PCB Editor crashes when routing with VOID_SAME_NET property on cline
, W( h# N5 e: ?$ f& P1 e% x' |. l) [1825020 ALLEGRO_EDITOR INTERACTIV GUI ( Quickplace ) not adjusted to current resolution' I* D1 [' \. K
1949705 ALLEGRO_EDITOR INTERACTIV Quickplace GUI not adjusted to lower resolution k; n) q8 p2 P+ j7 q# C* `! H
2023090 ALLEGRO_EDITOR INTERACTIV Dialog boxes do not fit vertically on the screen
4 X$ a; M1 o6 {% z/ F) P( S3 t2109940 ALLEGRO_EDITOR INTERACTIV Quickplace pop-up window does not fit vertically on the screen- d: L' ^4 k5 ~ \) h; C
2136823 ALLEGRO_EDITOR INTERACTIV Cannot resize or move dialog box to access buttons
' J" P A4 S! r6 K' `2116748 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets1 L0 ?1 D& \: {/ e0 U7 Z/ ^
2138977 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to HotFix 057- g8 e9 I- Z% T4 r& ~
2132628 ALLEGRO_EDITOR NC Improve the User Preference description for BACKDRILL_OVERSIZE_OPTION. o" M$ L {* o2 ]; V$ K. ]4 \! X+ h
2152244 ALLEGRO_EDITOR SCHEM_FTB Netrev.lst is written in the package folder
0 j% |/ G7 c: {, P2152493 ALLEGRO_EDITOR SCHEM_FTB netrev.lst is not created in the correct folder - error displayed for neltist import' T7 l7 F6 \3 m" g" v6 Y
2104559 ALLEGRO_EDITOR SHAPE PCB Editor crashes while performing shape operation 'andnot'
( d+ t* T/ W# ~' n5 u. G e2108207 ALLEGRO_EDITOR SHAPE No Void Overlap option is not working in AMB
; W/ m& P9 S# C2125571 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes for a RAVEL rule
4 r. p; q3 A! t) l; p2140707 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes on creating dynamic shape9 r3 ~4 D& J8 k3 h1 c$ v- W% L% }
2078434 ALLEGRO_PROD_TOOLB CORE Shield Router - cline end caps treated differently than cline-segment end caps
9 l o% c# D& B+ l/ c2101020 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC with multiple net classes: script selects only the last two classes in a group7 b- y; A3 Z& g: J
2029279 CAPTURE SCHEMATICS Slow response when selecting parts in schematic
" f5 E) }1 L! Y, w" z* h! J2039931 CAPTURE SCHEMATICS Slowness in OrCAD Capture when ITC is enabled
z8 s, Y0 B: u3 W' I/ Z# @) I2106942 CAPTURE SCHEMATICS Inter-tool communication needs to be disabled to resolve the lag issues in Capture! y. |2 G( p; M8 \1 e! B
2131683 RF_PCB ROUTING PCB Editor stops responding on using RF - Add Connect
3 w9 |$ d4 I3 r/ t2126505 SCM OTHER Thevenin Termination dialog displays resistors incorrectly3 ]/ C7 e" R Y. M' v. K
2102383 SIP_LAYOUT WLP Advanced WLP Non-standard fillets not working properly: fillets not added( v4 S6 @, N" B9 r, o# w
$ G, p7 Z* S" [+ ?8 Z& D3 Q2 P3 W! y1 {% d9 t ?
Fixed CCRs: SPB 17.2 HF058: e7 e M& `+ s3 B* R3 X2 y
08-16-2019
0 S, v! o+ W, N========================================================================================================================================================: Y Z% a5 A! l' o* _0 q) x
CCRID Product ProductLevel2 Title, z5 [: |2 T5 P* v$ W1 a& O
========================================================================================================================================================
- Y1 ]- N2 y5 |2 P3 a2 N2113265 ADW LIBDISTRIBUTI Various DB operations take too long, rebooting server seems to fix the problem; l7 O; I4 Q) ]6 f
2122941 ADW LIBDISTRIBUTI Lib_dist execution taking too long to run, Capture CIS DBC File appears to be taking the most of the time
+ R7 \1 l' D5 ~& N* U* \, o2127319 ADW LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250)
+ i% a/ j) N8 s/ T# f% Z0 s2107578 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Canvas shows split layer" J# G: n) f1 m8 t) ^
2099538 ALLEGRO_EDITOR EDIT_ETCH 'Glossing - Via Eliminate' shifts traces to another layer
6 c. T' n" J3 m* n2 {2031883 ALLEGRO_EDITOR INTERACTIV Sub-Drawing: clipboard origin point is not set correctly" Z1 P8 ^/ k2 W/ J! U; O+ ~
2100433 ALLEGRO_EDITOR INTERACTIV Pad Edit displays error for extents (SPMHA1-69) if pads are at 90 or 270 degrees
W* x$ K3 s0 T; o) ^' K( v2127239 ALLEGRO_EDITOR INTERACTIV Exporting a query result changes the working directory" z* r# L" r4 _2 s: w
2117160 ALLEGRO_EDITOR MCAD_COLLAB Error encountered when importing IDX file into MCAD tool in HotFix 056- s: ]: D4 x# [& J
2117427 ALLEGRO_EDITOR MCAD_COLLAB IDX files exported from HotFix 056 cannot be read in MCAD tool (the same files from HotFix 055 can be read)( C- d" y0 \5 z5 V. O
2117839 ALLEGRO_EDITOR MCAD_COLLAB IDX file created from release 17.2-2016 with Hotfix 056 is not readable in MCAD tools
7 {5 U+ [* ~+ j2118019 ALLEGRO_EDITOR MCAD_COLLAB Export IDX is not working in Hotfix 056 but working in HotFix 055: @3 X/ Q# B) M- J
2106425 ALLEGRO_EDITOR NC Disable undersize regular pad and oversize soldermask pad for start layers
/ S# o4 n& U0 Y+ ?) Z$ Y2126766 ALLEGRO_EDITOR REPORTS Cannot generate reports and export ODB on board
- `/ J4 ?, w' w) k( ]$ x, a% k2107849 ALLEGRO_EDITOR SHAPE PCB Editor stops responding on updating shapes
4 S5 s) {$ \- o% E+ Q1778109 ALLEGRO_EDITOR UI_GENERAL Constraint Manager exits on doing 'Undo' in PCB Editor
4 h/ D# b8 w# `& j# ^5 w2064092 ALLEGRO_EDITOR UI_GENERAL Allegro Constraint Manager closes on clicking Undo in the layout editor4 }" V- H/ J* @3 C+ G
2093341 ALLEGRO_EDITOR UI_GENERAL Show Element incorrectly displays in report window on a single line if an HTML Report is open when show element runs
+ Z f7 Y+ p+ \2110909 CONSTRAINT_MGR UI_FORMS Cannot type dot (.) in DFA Table of Package to Package Spacing in DFA of Constraint Manager.7 J7 C* e% S0 [; M' s
2096846 INSTALLATION ADW Component Browser does not open if adwservice.exe is not added to the Windows firewall exception list
- J+ @ `3 u+ |3 M2128118 INSTALLATION ADW Unable to connect to Component Browser.( q2 B1 D' o# H; E
2116749 PCB_LIBRARIAN OTHER Cannot open Part Developer with a Venture PCB license (PA3810)
+ r% T+ p4 S; b( S" {+ f6 h U+ t5 Y2115302 SIP_LAYOUT IMPORT_DATA Performance issues with die text in and pin use codes, function utcle pwrgnd: M$ A; G. N/ O* ?! A+ v
2103784 SIP_LAYOUT MULTI_USER Symphony Server rejects the move void commands on a specific shape instance
9 d, Z$ R$ R+ E* |, m- `0 [2096239 SIP_LAYOUT STREAM_IF Database fails to create stream out file; J) e+ M, [& w5 O& Z6 }
2117572 SYSTEM_CAPTURE EXPORT_PCB System Capture crashes with multiple Export to PCB Layout
" L( X$ f/ L% B: M; {! H. N6 C0 E) m" a9 ?. |7 k
( d/ S& p9 _: j. Y/ x
Fixed CCRs: SPB 17.2 HF057
& s4 t/ J% M* G5 V& F07-19-2019, ^9 O% W$ o2 n( m8 f% e$ O+ N% j1 H
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% ^ Q4 V! B8 W5 x6 p; QCCRID Product ProductLevel2 Title
* t4 M5 w4 s+ s# i6 A; t========================================================================================================================================================! M7 R9 M6 O) P7 N3 T( z7 L
1920958 ADW ADWSERVER Designer server will not start due to corrupt inr file
* L; L/ u' ?' N9 c( {! L2039243 ADW LIBIMPORT libimport ignores footprints generated by Library Creator due to changes of attribute names0 T8 M2 N/ h& ~8 K/ w$ |
2113226 ADW PART_MANAGER System Capture stops responding while importing DE-HDL sheets# r u9 }4 @& O0 {) n& B
2035942 ALLEGRO_EDITOR ARTWORK 'Create Artwork' is slow when all films are selected: O1 r, L' y, @0 ?
2096958 ALLEGRO_EDITOR DFA Cannot launch Constraint Manager after assigning CSet and closing9 s( U# H% M; {6 r3 ]$ [% r+ {
2087181 ALLEGRO_EDITOR DFM DFM reporting false positive hole to hole with stacked microvias
- L2 u. u W; |2099400 ALLEGRO_EDITOR DFM Placing a mechanical pin on a cutout causes PCB Editor to crash& ~3 K5 G5 P) N
2067214 ALLEGRO_EDITOR DRC_CONSTR Constraint Manager crashes for design linked board
' j* B& C0 ]3 c6 L+ y% c2097464 ALLEGRO_EDITOR MULTI_USER Design data lost if network connection drops in Symphony) {, x7 q3 A4 g& R r
2108211 ALLEGRO_EDITOR MULTI_USER Error: Update #1 (Perm shape) was rejected by server
$ I4 l' u3 I: W! c" w9 N% o2117154 ALLEGRO_EDITOR MULTI_USER Error message needed for Symphony for client disconnections k- X+ X! P( B/ e
2100149 ALLEGRO_EDITOR REPORTS Error message (SPMHDX-9) for too many field names while generating dangling via report, W/ r8 C/ x3 _4 _- U" P
2101932 ALLEGRO_EDITOR REPORTS PCB Editor internal error (SPMHDX-9) for too many field names when running BOM report7 z( Q2 ~' A6 f: c+ s6 e( [+ h; @
2111449 ALLEGRO_EDITOR SYMBOL 'Layout - Renumber' results in error
& G: N% P& J" a2 P2102177 ALLEGRO_EDITOR UI_GENERAL axlDMBrowsePath returns incomplete information% g; l8 p8 G9 G6 m
2105342 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding for 'Show Element - Find - Symbol Type' on a particular board
3 i4 v( N% m3 }! w5 H. d! k2085443 APD ARTWORK Gerber lacks precision required to void some vias for a design in artwork output: need warning
* s% U( P' ?, C2080118 CONCEPT_HDL CORE Getting error after adding offpage to bus and assigning a new value to $sig_name
2 E: H; g# p' o, ]6 W/ e2099438 CONCEPT_HDL CORE Genview allows dragging group of signals in split symbol distribution form
2 s, y5 f8 W, J y% }( Y5 O2108289 CONCEPT_HDL CORE Variant data is not in sync with the packaged data6 J, ]6 K$ p3 |. ~( c8 w
2087217 CONCEPT_HDL OTHER Variant back annotation will not work if there is a double quote (") in the description field of a part0 r$ x. g3 e! h
2107430 CONCEPT_HDL PAGE_MGMT Insert page is not working( u0 J# a7 `4 n1 G5 o* L
2063875 CONSTRAINT_MGR OTHER PCB Editor crashes on deleting match group without closing Constraint Manager
' ~1 ?8 f1 s$ j5 }: b3 \ N) t- m2103729 F2B DESIGNVARI Cannot enable hierarchical variants for block
( x4 b1 S0 }. A5 Y6 U2099076 F2B PACKAGERXL Package fails for 'Save Hierarchy', but succeeds for 'Save'' k* v) B1 L2 B1 D" H
2081132 INSTALLATION SPB Part Information Manager cannot connect to EDM server after upgrading to HotFix 053- ^7 d6 m {: J* S' H& f
1599964 PSPICE ENVIRONMENT Version Info displays 'OrCAD Version Viewer MFC Application has stopped working'1 s- \. N& o) A t# }6 S
2045497 PSPICE SIMULATOR 'Illegal Parameter Value in File' error when loading Monte Carlo parameter file+ o* @: C% F7 B7 q: I _/ X/ U
2025997 SCM TABLE Copy-Paste Broken in Physical View
. t K0 ~" W# e3 ^) y1 N# T2102652 SCM TABLE Unable to copy the Associated Components Ref Des values to Excel9 z) o f9 |' b5 ?* Q
2054225 SIG_INTEGRITY SIGNOISE Cross Section Editor bug after changing the impedance value in Analyze - Preferences
& q" i4 X+ q6 ]4 k p3 G U P. Y2100075 SIP_LAYOUT DIE_ABSTRACT_ Refresh co-design die running slow+ @+ e& ^1 o3 W, f4 k. s& a
2106312 SIP_LAYOUT DIE_ABSTRACT_ Die abstract I/F to bring into SiP Layout and OrbitIO power/ground and signals not designated as RDL
* {0 ?+ w+ {1 i; e# E7 _8 H2106314 SIP_LAYOUT INTERACTIVE Large design causing severe lag in Windows Server machine1 U; o0 j# ~: d/ M+ i, L
2101622 SIP_LAYOUT MULTI_USER Symphony Server rejects the slide commands when tapered trace option is on
w; |1 X/ {0 K: R# T2107897 SIP_LAYOUT WIREBOND Design stops responding when running Wire Bond Auto Spread in HotFix 0558 {0 D/ E: [! F l, X: U
2104885 SIP_LAYOUT WLP Advanced WLP: Metal Density Scan, scan area in report is incorrect% G9 _# }7 A& e4 a* i8 P
' G* {6 _, R5 n. z* R$ q L2 q7 w7 y1 g; P! F
Fixed CCRs: SPB 17.2 HF056( e' H. y4 @/ P+ }- c4 A* N
06-21-2019: D6 c4 X8 M9 E4 _9 C* t1 F
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0 @% U/ r9 T. [" d, m4 u1 F( tCCRID Product ProductLevel2 Title$ }9 b( m" t2 j+ u1 V9 ]. n
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2086463 ADW PART_MANAGER System Capture cannot add components when accessing remote machine via Citrix
7 w1 C& _$ t8 {- u) Z' W9 K2092868 ADW PART_MANAGER Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not to flow from pstchip
O( T5 B7 t, g% V9 h9 [$ V+ H2092872 ADW PART_MANAGER Import DE-HDL Sheets stops responding; E; s. C/ ^6 w$ o( h
2088975 ALLEGRO_EDITOR 3D_CANVAS Bending in 3D Canvas causes PCB Editor to crash/ S/ t, ^; D( R9 ?; @
2088577 ALLEGRO_EDITOR COLOR Export color nets does not write all the nets in param file, y7 N+ A1 B2 J& `
2028867 ALLEGRO_EDITOR DFM False DFF Trace to Thru via pad spacing DRC
+ C+ j' L# x3 k( t0 g' W5 P* e1 \( a2037361 ALLEGRO_EDITOR DFM Soldermask features drawn with a line do not DRC to pin, via, or shape soldermask features4 _- l% N9 m6 Y; I" y0 }
2077913 ALLEGRO_EDITOR DRC_CONSTR When running a simple SKILL command, the tool will run for a very long time
2 O' P+ b* d' L( v2 [2079642 ALLEGRO_EDITOR DXF Drill symbols are rotated in exported DXF in release 17.2-2016
1 Q$ Z- o+ ~/ i* b/ R* ~/ C7 E' B2083493 ALLEGRO_EDITOR MANUFACT Manufacture - Cross section chart is not readable for rigid-flex designs$ n& z2 Z& h4 |; D* v) G
2073607 ALLEGRO_EDITOR MCAD_COLLAB IDX_IN batch program to allow a batch update of an .idx file
) R3 M9 J4 d+ L6 ]2095632 ALLEGRO_EDITOR MULTI_USER Design server on Symphony stops responding and cannot be closed or downloaded! N, M1 r) ]- H! U0 t1 ]2 E
2098221 ALLEGRO_EDITOR MULTI_USER Symphony Server Manager allows connection to databases deleted from the project area
3 s) x: P/ f3 H# |; q4 R* y2087315 ALLEGRO_EDITOR NC Backdrill exclusions raised on pins of a component% S. |/ R/ i9 ?; K6 O% A4 e+ y
1947929 ALLEGRO_EDITOR OTHER The 'show measure' function crashes when measuring pin to pin distance% o5 d: v U8 b& k4 u
2091932 ALLEGRO_EDITOR OTHER Unsupported Prototypes command missing for the OrCAD licenses
}7 Y0 x( k2 I- j, L3 F1 J" f2089470 ALLEGRO_EDITOR REPORTS Summary report shows the exclamation character (!) in the middle of numbers and words
0 U! W9 w7 v- t) }* ?" O7 k d* ~2067324 ALLEGRO_EDITOR SHAPE Netin crash during third-party Netlist import: j. q$ Q/ |( Y6 R0 O) l
2075191 ALLEGRO_EDITOR SHAPE Delete islands in the design: update out of date shapes and Database Check5 w( }1 r: U4 E9 |" ~8 |
2090604 ALLEGRO_EDITOR UI_FORMS Undo/Redo UI grayed out when invoking Color192& J: ~% u* I' m3 [* i. _2 U( |9 X! ^
2043825 ALLEGRO_EDITOR UI_GENERAL Custom toolbar settings are not retained upon restart of Allegro PCB Designer
$ o/ T9 a X) i) L/ B. A, r2090185 ALLEGRO_EDITOR UI_GENERAL UI setting in INI file not retained
7 n! l/ `& p0 h2 y2090517 ALLEGRO_EDITOR UI_GENERAL Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane
+ o# i/ @7 a* D6 W/ T2 |( y" S2092436 ALLEGRO_EDITOR UI_GENERAL RefDes length of input string for Modify Design Padstack is limited to 20 characters
, o) m5 h, o4 P* ]- Y \2099070 ALLEGRO_EDITOR UI_GENERAL UI setting not working properly, Icons missing after restart.
0 A( I! {+ O1 Y& ~" @3 {/ N# s2088484 APD DATABASE Some objects (Vias and Cline) cannot be modified (edit, delete and slide) in the mcm database9 g+ z& T" X8 c" ^: k( N
1951623 APD DEGASSING Shape Degassing fails with specific Void to Shape boundary value+ S9 N2 J ?' W3 [' ~8 w; d/ K
2081363 APD DEGASSING Cannot degas for specific shape2 i/ [7 R4 @0 X/ F/ N5 J/ n% O& f N7 b0 c# F
2083498 APD WIREBOND Cannot wire bond from a diepad to another diepad on the same component
, i4 W! T4 g& h% B. ~3 G( t2086589 CAPTURE NETLIST_ALLEG The generate the CM enabled files from the command line using pstswp.exe.
( Z5 V' T, ]3 |: ]2 p8 E2098248 CAPTURE NEW_SYM_EDITO Ignore pin is not working for individual pins in Edit pin spreadsheet when edited for all pins
& w/ x2 a& l6 ~& J1773047 CIS PART_MANAGER Pin numbers and names for DNI parts will get disappeared in variant view mode if they are relocated in part editor
8 B& H" ~0 |( m, W7 { `" D2003818 CIS PART_MANAGER Pin name and number of 'do not stuff' parts are not visible in the View variant mode
8 D4 H K8 V' @2 s2 a) y2076265 CIS PART_MANAGER Variant view pinnr/pinname disappears1 g" K3 P" H( O" q; M# r7 W
2076282 CIS PART_MANAGER View variant does not show pinnr and pinname
! e! n) U; [# n! m1 n2083394 CIS PART_MANAGER No pin names and numbers on variant view for specific parts
+ _# o4 r o: u7 F% l# J2090027 CONCEPT_HDL CORE Cut and move of split hierarchical symbol to another page results in error due to lock or write permission issues
6 J9 _" ^& n7 C2 P4 \* p* A2071355 ORBITIO ALLEGRO_SIP_I Dummy nets creation in die after performing Merge Updated SiP
7 C5 ^; Z' U6 D7 b8 {+ q3 ^2067703 PCB_LIBRARIAN OTHER PDV crashes immediately for vector pins if MSB is lower than LSB
( Z6 g: Z, y; W m) ?9 w. k2041348 PCB_LIBRARIAN SYMBOL_EDITOR Grid setting change cannot be saved in new Symbol Editor4 A8 k4 N* R! b2 J# L
2041365 PCB_LIBRARIAN SYMBOL_EDITOR Improve copy drawing objects in new Symbol Editor
8 c5 ?, F5 y" D, a8 L/ m" K; O+ h* O2067931 PCB_LIBRARIAN SYMBOL_EDITOR New symbol editor grid issue: documentation grid spacing value changes' {2 t) w' }6 j
2093849 PCB_LIBRARIAN SYMBOL_EDITOR Symbol font text and appearance different when placed in Schematics
$ K; a* K1 j/ g# q! z1919298 PSPICE FRONTENDPLUGI Capture crashes on archiving project; E- S0 U" n" s6 j" T, n
1953001 PSPICE FRONTENDPLUGI Archive project causes Capture crash./ K+ _+ V: i- D1 d$ e8 j
2035572 PSPICE FRONTENDPLUGI Crash on archiving project
# y! S2 g& t) q8 o+ p: k2041286 PSPICE FRONTENDPLUGI Archive project crashes when using lib as global./ ?, R. a+ h8 C. o5 ?
2081796 PSPICE FRONTENDPLUGI 'Archive Project' crashes Capture in release 17.2-2016, HotFix 053# z' Z& t( J# d4 b. J
2106017 PSPICE FRONTENDPLUGI Capture crashes when archiving PSpice-enabled project+ k* {( `5 h6 e6 f
2051450 PSPICE PWL PWL Sources application: pop-ups and messages when browsing and placing source- t, t: u1 J" b- o
2090021 PSPICE PWL Modeling Application - Sources - PWL Sources Dialog is not properly displayed
7 h# @- l7 q3 G( H2094548 PSPICE SIMULATOR Model undefined error on TL4946 | ~* l) S3 ~6 ?" \
2058018 SCM PACKAGER Reference designator mismatch in 'exportsch' schematics and board file
2 A8 {( e2 t" e5 W% c9 F2 P1955868 SIP_LAYOUT STREAM_IF APD/SiP Layout: Export rounded features as circumscribed and not inscribed polygon in GDS
$ h% T/ J+ h& R3 F3 D$ F2081914 SIP_LAYOUT STREAM_IF Release 17.2-2016: GDSII stream out drops shapes+ w) k- c {; P
2013647 SYSTEM_CAPTURE CANVAS_EDIT Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections6 ~: t% P0 [/ ^/ E0 c3 L7 s" V/ R
* D/ R5 Q5 Z* t' B% k. D. I# s0 S7 u4 p. R7 M* ?
Fixed CCRs: SPB 17.2 HF055+ ^% j' Y3 f8 J
05-24-2019# U" z( @4 @: ~
========================================================================================================================================================
0 e* M0 ?, t. ECCRID Product ProductLevel2 Title
* H1 S3 {- m3 \' R========================================================================================================================================================- z& [4 O* ~' e; E/ u
2078057 ADW PART_BROWSER Symbol Graphics preview is not available in the Designer Server
6 k# g- G, p9 o6 a0 A" |/ S2092863 ADW PART_BROWSER Component Browser is not displaying the symbol & footprint preview; O7 y/ K' v* M
2076339 ALLEGRO_EDITOR 3D_CANVAS Floating parts on bending a board in 3D Canvas with HotFix 053, C( F8 |/ T0 b7 H- G; X ]# @
2051075 ALLEGRO_EDITOR ARTWORK Incorrect Gerber import in Allegro PCB Editor
3 R& [ h8 l; p/ y' A2073407 ALLEGRO_EDITOR DATABASE axlDeleteByLayer deletes fixed shapes2 o: F6 ^! N6 o
2079117 ALLEGRO_EDITOR DATABASE Release 17.2-2016: Board file saved in HotFix 049 cannot be opened in HotFix 014
9 P E+ n; }8 g4 {2079204 ALLEGRO_EDITOR DFM Enabling option to update analysis mode and run DesignTrue DFM wizard causes PCB Editor to exit
0 m! u$ y2 d ]' Z2082394 ALLEGRO_EDITOR DRAFTING Angular dimension not owned by the same parent symbol in the layout are not deleted on moving object+ a: f* R0 I/ Z
2067916 ALLEGRO_EDITOR INTERACTIV Place replicate module bounding box does not move with circuit after module is updated
! p4 n n0 M" c' s+ X( m! ^2068449 ALLEGRO_EDITOR MANUFACT Stackup chart and table shift slightly from original location on re-generation in Allegro PCB Editor release 17.2-2016& C* ?3 R$ f* Q g% Z- g6 u
2065820 ALLEGRO_EDITOR MCAD_COLLAB Selected objects deleted from the design on clicking Cancel in IDX Flow Manager Import
5 ?* [3 ]; ~3 u. I1 f. o2080164 ALLEGRO_EDITOR MCAD_COLLAB IDX outputs two sets of masks
: `, P8 C( Y% }+ F2081955 ALLEGRO_EDITOR NC Artwork file error for via size e3 u/ O: |; j r
2045061 ALLEGRO_EDITOR PLACEMENT Setting PSMPATH: axlSetVariableFile() does not update Place Manual but User Preference Editor does0 w+ v6 s. r' H7 G$ L8 o8 r
2049949 ALLEGRO_EDITOR PLACEMENT Get import errors and cannot place some parts if user-defined option is turned on for netlist import
* h. S8 P' u) o1 ~4 C. |! \2069289 ALLEGRO_EDITOR PLACEMENT Cannot place part because attribute definitions are incompatible for the 'DESCRIPTION' attribute (SPMHDB-154)! o: m/ [( N: s7 k' A! H- _
2056573 ALLEGRO_EDITOR SCHEM_FTB Import Logic takes a long time when checks are turned on7 ?8 ^; r7 A0 p$ E
2076452 ALLEGRO_EDITOR SHAPE Shape Degassing crashes if 'Inside Shape' is selected$ r# `+ B5 i n
2076873 ALLEGRO_EDITOR SHAPE Symbol Editor stops responding on editing shape with a .dra file# u- p0 D! f5 ]" e9 S1 a
1788703 ALLEGRO_EDITOR SKILL axlPadSuppressSet does not work when 'none' switch is used' w" j0 l. _) Z* u1 V2 I
1955127 ALLEGRO_EDITOR SKILL axlPadSuppressSet( 'off 'none ) returns a warning message and does not work per the documentation
1 i9 {0 U \, c6 r! j2031711 ALLEGRO_EDITOR SKILL Syntax error related to allegro.ini shown if allegro.ilinit loads INI on startup, X# S4 V$ J j' F
2062527 ALLEGRO_EDITOR SRM RF elements are shown in Symbol Revision Manager
; H, r8 z6 S4 ^8 Z2074249 ALLEGRO_EDITOR TESTPREP Testprep re-sequence causes PCB Editor to crash if 'Labels with Net Name' is selected
; O$ Z2 }1 w u- {9 f; ^8 K2070534 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox bar code generator is creating corrupted shapes in the database
/ [9 U+ Y0 p9 n* I5 t* y9 V+ d2046278 ALTM_TRANSLATOR CAPTURE Third-party import fails
/ d! m- @0 f4 q/ z, ?( @% q8 e2052399 ALTM_TRANSLATOR CAPTURE Third-party CAD translation stopped with error message& a" M- H( ^& F$ X
2005087 ALTM_TRANSLATOR DE_HDL Cannot translate third-party to Allegro Design Entry HDL
6 d8 D* U2 c* w1922222 ALTM_TRANSLATOR PCB_EDITOR Third-party translation converts to board with unconnected nets5 c# s7 B9 T# J
1987263 ALTM_TRANSLATOR PCB_EDITOR Third-party board file: copper not imported. w9 S& t9 i% L8 ~* O8 j" L
2017988 ALTM_TRANSLATOR PCB_EDITOR Third-party to Allegro PCB Editor import issues with routes, constraints, size, and accuracy7 d% v2 c3 c6 J' A& r. W
2021300 ALTM_TRANSLATOR PCB_EDITOR Third-party translator does not show any results on PCB Editor canvas
3 f1 A- k8 ]7 ?1890675 APD DIE_EDITOR Mirror Geometry is Mirroring the symbol from TOP to BOTTOM Layer in SIP file' w9 d" u7 N4 w9 o3 y
2064219 APD DIE_EDITOR Applying mirror geometry results in mirroring: moved from TOP to BOTTOM layer
% b h/ T2 o' e3 W( P. M2086574 APD OTHER Duplicate layer text shown on the vias
* U3 B* H& ?3 y9 o6 S" L) [1948169 CIS CONFIGURATION Auto Symbol Refresh Checking not working for shared folders
% z3 \0 P& F: l" Q; \% I2025385 CONCEPT_HDL CORE Hierarchy Viewer expands/collapses randomly after clicking the '+' or '-' symbols0 E, R7 ]3 A ~ Y: {) O
2050010 CONCEPT_HDL CORE Copyproject does not properly copy the variant files
+ g1 M: E# V$ e2063457 CONCEPT_HDL CORE DE-HDL: very slow rendering on some systems* w' g2 h: W; i- i" s% L: T5 \
2076312 CONCEPT_HDL CORE Getting 'Variant out of sync' warning when creating BOM for a design with no variants
1 A) \) Y- y/ i. |2083650 CONCEPT_HDL CORE Lower-level signals are appended with _1, _2, and so on7 G% |/ E$ L; o( F2 V
2083651 CONCEPT_HDL CORE The physical net names still do not sync with the assigned signal name; x4 m* ]3 S/ {6 B
2056736 CONCEPT_HDL GLOBALCHANGE Global Property Delete does not operate on the entire design unless the top-level page 1 is open+ _' I$ s3 C) R+ n/ ^, F
1955357 SIG_EXPLORER OTHER Signal explorer invocation with OrCAD PCB Expert Suite license
% s# o, l& t0 v% F/ a2079071 SIP_LAYOUT SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die3 T, H0 ]2 {1 H
2081884 SYSTEM_CAPTURE CANVAS_EDIT Symbols take a long time to move, and results in DRCs and broken connections
# e* Y0 P2 o% f E7 m+ `" C/ m- ~" I1 u1942542 SYSTEM_CAPTURE IMPORT_PCB System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks4 C4 ^& _. n2 j' \
2071303 SYSTEM_CAPTURE MISCELLANEOUS cds.lib file is picked up from wrong location
) A* C3 Q! u; [- y* v2058979 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture prevents a project from opening by putting a single quote at the end of a line in CPM file
! Q+ Z- W0 M- I; b2088210 SYSTEM_CAPTURE OPEN_CLOSE_PR The 'enable pspice' entry in CPM file is occasionally corrupted r0 a( s8 |" d8 ]3 F& I* T
( ]) x& t+ O$ S N8 P9 Q' j' m
! `, r0 l& W) j) y2 A6 w5 zFixed CCRs: SPB 17.2 HF0545 D8 Z5 k! s! H0 _! \; d8 R, g
04-26-2019
# n) s+ Z0 \, _: H: s========================================================================================================================================================5 c4 z3 f2 n/ [$ G# Z' [- p, O5 [, E# `
CCRID Product ProductLevel2 Title8 f6 R- I9 k | @
========================================================================================================================================================
: m- h8 D: y3 A6 Y* E u1 T6 Q% I2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes1 L8 `8 G- L, C! p* c5 T
2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property
) _& C. D" R8 x! Q! w! h1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser
. c/ j0 }( `9 U0 z9 `7 o+ B: X2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache
" O% H; V+ { l1 k( T# n8 P2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
3 @* y: K% `' I0 X( w2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
" r+ S3 n( k) T" F. X Y# V2 ^2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object% B9 x+ o2 H( {/ }/ D
2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas) e2 w! M' V# G
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
% G6 ?* w% I3 t2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded! N( L+ u/ G9 h1 d1 K
2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off
) b$ v! s0 [5 @( p+ c6 T9 X6 o2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set
' n) `: o. A N% Q7 [2 |2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
( k- x% C" _: G: [3 Z! w) _2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements
- ?4 t( q1 P6 W$ k8 U" g2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin4 C9 w0 A, m4 C
2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element
% G: S x1 C2 u/ \% z2056497 ALLEGRO_EDITOR DATABASE Place manual is slow
* `6 G$ J# F! Z1 o, o2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error# @% Q, y" P$ A7 x" K+ c
2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code( V- ~- W% ]& @4 q
2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016
9 f P4 ~1 U$ ~1 a V2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error. h4 ?. L$ ^+ i; h
2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets' I+ p+ O- F$ Y" _2 {# E8 y# I) V" m
2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.+ U: M; m0 z0 t* \/ G }6 u) O% b$ h% P
2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.
" B# k) m8 W K/ v5 t2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
. _6 ?; ]* C5 H1 P4 l- A2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations$ i& [, k f E2 e- I
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
# u' e' S) X6 G' q2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill* l( Z- M* ?5 z$ ^# [
2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets+ L: H% Y& S( f+ ^# z) Y
2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor
3 F x3 ? f( @3 ~4 P9 Q# p* N2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias( z* x" Q6 o/ `, }8 ?
2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor" S6 }1 P8 V; n2 g D' [! I2 V9 R
2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable3 |+ S! r9 K% n. u- T9 |; E" H
2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components1 a2 g9 R% H* G# f- [1 q. G- e4 p
2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report( `7 o! G$ P9 G' s4 ?
2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL) `! }5 q0 n- s: J) \* E/ e5 {
2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window/ ?2 v H x, H/ A) e6 S% s' O
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
+ q3 X0 n; U* B- `1 E+ I- z2 l; E. D2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'$ m% s2 ~' c6 @' T$ e# D5 o
2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape' Z( }- r2 g4 J; H# @8 ?
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present, n( I) h5 ?1 R1 {
2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes: z/ O" G+ f2 J- |" Z1 F
2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself' n4 r+ B; c* C1 l* D: T
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
7 k3 a5 k) @9 P7 ~; A2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
; ]4 I* J& H, I' r6 N: W6 _9 n2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.
/ v; i% z! ?5 @) A1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)4 y" |# J) B/ r
1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)3 E! {1 M( R. W( f
2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
, X. [ f6 q. n2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design" ~/ L" e! X* g& W
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas
; r" q8 ]) ~, U0 s. M2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice2 ?! L) V( d9 T5 k3 F
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html
6 u1 l9 t/ o6 }; ]+ O/ R2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden4 o9 H" q- q9 l# K% U# C, ~* @
2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.6/ r+ B4 ]! \, h3 r; X3 K5 Y
2050674 APD PARTITION Cannot remove C-Point from a partitioned design
" D% T3 P9 ^5 B) A2068814 APD WIREBOND Bond wires cross on auto-separate
% e5 N2 ?3 d7 p' a9 W8 {( w1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open, D# g, F' Y1 O6 A
1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
1 Q1 b) e/ k# A; k/ I3 A& j0 {2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL4 A' L" e5 ^" P. d# |" q
2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window) p! G# @4 ]: p
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
/ {+ n l2 }/ E0 y2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix' _4 w. U) v- Z, G- C
2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager5 C6 z/ D+ U2 v# ?
2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps6 [3 {4 m! r0 k2 @! \- b+ v: A
2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM: Q! _+ U N1 O0 g! M' i% t& M
2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties
9 h% ]0 W) N$ v1 C2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.
7 f% q6 Q3 O i; [2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses7 R2 u% Q( `+ }1 s" _4 g
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
- g) c3 v* E: {4 Y1 ^- \7 j2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.# N3 ^- p& Q6 s0 P. H
2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma; a9 k7 }# E& N/ f9 t7 v4 f J
2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked. H0 {8 W# F) k+ S* `3 |
2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character- |3 o7 ^- E8 p% c* z) r' {1 |3 q
2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped
; h5 H% q- F. w2 s3 o2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties
9 {: u# x4 I( ?1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated0 r& Y6 W7 c9 N
2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated, b, |+ G4 j" o8 H( O5 |
2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated- h8 J* e, b/ S7 j8 r: z9 _
2038021 PSPICE FRONTENDPLUGI Bias display is not updated1 f1 q4 e, k% c+ V. Z
2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open
4 H4 ?( Z; @/ } F2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component5 c6 ^9 f W8 i' Q% d
2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks5 a) F; T: |+ ~- v. O
2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
1 Y4 l) n& w# p1 a9 X. ] V2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign
" ^1 F1 b* ?" [: @2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed
) s. @9 t+ o3 a, K2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'
/ A5 E+ z* k4 H+ U1 e( w2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
' m5 ?7 @9 h1 o$ K; C4 t2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
& t5 B0 T" i" b. r1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
& ~: l6 W6 U1 U2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files* m+ t0 n' d& M. A
1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed./ Z, q$ z6 w( e# D7 m
1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
$ ^. b4 F' L' ~% F1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
9 C @5 a1 z. ^/ z1 x# P2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written2 o( j5 E' d# o- N0 _
1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping
, |& M) c; ?4 E- a2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor
. y9 v' N% \ x* i1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste$ Y) D* a& X& n
1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position
- W' E5 {2 z1 v5 }4 m! s1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM! H8 k$ C. }2 O& o6 Q+ u( G
1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range! Z5 V( g3 M3 j9 [ K {
2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.2 x0 v; B# r4 z7 ~# F
2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF$ n6 L) v" ?( h0 O( U0 d2 O
1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space" k* i i/ F. M: R3 E" y
1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
! y; @- J4 I% O8 l1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project" Z: m9 I9 V: u; x7 u
# [# D8 K( p0 [& F9 l5 a" ?; ^
" k7 r" g6 A& H" [6 z
Fixed CCRs: SPB 17.2 HF053
; w5 [* R$ x7 P; O$ L3 f4 l03-30-2019! P- a0 [6 G0 x: |& p- O1 V, A
========================================================================================================================================================) I: I. c: D6 z! J
CCRID Product ProductLevel2 Title
% ]2 o! U5 b. r. n+ p( G2 A- W========================================================================================================================================================
1 W9 k7 ^- C6 T0 K( C2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right
/ F$ ]3 ^8 F+ Z3 E( K+ v8 L5 M* t2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag
3 n7 V5 T+ S1 ~0 T; V! r( ~7 |2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
s/ [. }/ R, w4 P2 M2 z$ J2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
+ G5 f' |$ b/ k3 A7 r1 {2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error
0 p! [/ j7 q1 J# f2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object; _: k9 E+ w; } ]
2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer9 _/ A( A# a3 d/ c7 ?" K
2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down9 P4 q+ r. g; L+ M. o
2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
8 `1 Z3 { D, f7 K2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
; v: @2 H" a1 L7 k2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned' H. Q I' Q! H- Z' [" U/ j/ y+ l
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
# t U) T \* e8 q, ?- I2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
0 O* v/ y1 V! T0 B# i, f2 o1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.$ E7 y' ]% }. k% }9 Y, j- y
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization
$ P j9 n+ Y* x; u9 q' w2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack
$ o, ~# o! ^5 `* \9 W0 m; O1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols/ u% p) E5 e/ {2 |0 Q- W3 G
1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines
: `0 s: |6 J0 I/ G* j1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.3 O3 T' K; Z) T$ I; _& r
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types5 n* _# a- ^' n$ Z5 p6 b( |8 m$ S
2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.# ]6 S" R/ |6 `; Q S
2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
8 a! A5 C9 n. d+ g2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation5 e# U" d/ y( e2 N/ D
2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
2 d0 Y' B, ~ M- @( W2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column) U8 a& W, Q; {+ c# |+ I
2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.& Z/ D1 V% A3 Z( x0 H( v7 |: N. m6 f5 T
2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table
, X4 q/ U" U3 @) |! |2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data4 r# F2 c+ G( [. {* D Z/ d$ e
2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value& q: S* l F# K* W2 Q& Q" c
2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added2 E$ o" N/ N5 v6 p% `
2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created! ?; {) c/ n5 y# ?$ m; b) G6 \4 ]
2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev
. Z/ p3 `3 v1 B2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
$ L$ b" `5 E6 A/ i# I7 G+ m$ W2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding6 ?1 `1 t9 o$ x# J! R
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update0 M- Y! {4 z" ]# m4 A" \& j+ K' L h
2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.1 }: {1 O, `3 [* ]6 f
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present( j( S# n0 [( L' z$ x
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.
2 H+ l6 C6 H- `) r. ?2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash G# @9 y2 O% ?' n
1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint' h1 d9 i8 c8 L [+ W( `3 h" D
2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
. @* g2 }" h3 }3 A7 {. Y/ t2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash3 J8 q: A! t! ~) ?9 r) \
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas
7 W! G3 E/ E) j2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden, s! c) ?% I' r) \0 W3 u* A
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash
% _* N }) t2 |6 t& F0 g1 |: p! I' W6 C1699433 APD EDIT_ETCH Field solver runs when not expected
, |5 `" k6 O0 l+ s. q0 l5 A1937159 APD EDIT_ETCH Routing clines takes long time
- ^9 ]2 b) ]1 _, T7 X( k3 Y2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region5 n5 e9 q, v/ b+ d6 k
2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051
0 F8 X7 }) [ V9 \! c2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture
- k6 s" L- E; R, Z2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
$ w9 N& r( A/ b3 W, D! |/ _" f$ M2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project X7 C9 v6 M4 j
2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification& b; H8 p+ R- o
2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
4 Q- }' y$ B5 T2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source7 [- j, a2 [' ^
2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol& M" ]* Z6 a3 o% h' M
2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
9 ~. o5 p" G; p' p% G2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor: J" K4 \. o# W7 y. R; U u
2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library* T4 Y# G0 O/ c3 H2 C4 Z6 Q4 Z
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
& J# ^! N) J* c! V# O1 ?, ~1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error% S; J0 C) A9 k+ i6 V% Y1 Z
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled( a) p" A6 R+ U& {
1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components' j8 ^$ m) g, T$ I" x: Z! i
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names
3 j& c7 f* y; W. n3 @0 x6 r7 v2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character& N) A1 N9 _1 M
1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
7 ?) h/ n' f/ h0 @7 L/ z8 n1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
6 h$ v4 M8 v8 z% v# _" h7 T1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped3 n# X5 D" K9 G0 r4 ^7 L3 x
1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical# G- p/ l Y7 y- K
1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
. f7 F* t5 {: v6 V# _3 u' @1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas
! d! o: {* R3 u. ?$ G2 W1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment/ R' y, S3 c1 |7 w
1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast5 Z4 w& _1 V* l) c- {5 H
1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently5 m8 k* _" d* C1 I' r! n
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page2 H0 x/ `" O; X5 c0 L8 D
1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI2 a+ {) R+ _6 H/ E. \
1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created5 Z$ z* O, }0 Y# ~7 N
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
4 C D$ J" ? \ f5 T% ]1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it7 R4 s# ^$ B: l$ Q; t
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL# m, b$ v. H0 L, {1 B$ @( `
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
* L1 e7 k; `/ ?6 C, \1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message
+ \4 T7 r0 |4 c9 \, [. \$ J1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor E7 D8 P, p6 D
2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder
" F: n' I* v" W3 e" i+ z2 h% j1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
* X1 M: Y0 A( e$ W) ~7 b3 }2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component
6 y8 M. F! ?/ O, H1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES
# a' S9 q( A* f0 c) {9 {! [1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option
k; Y0 w- G8 ^; Y: Z2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor' M! }) ?* U5 B+ B$ Q
0 k. z7 h( r/ \1 B% S$ ~
! P( U" [% V$ \% I: {7 u6 R
Fixed CCRs: SPB 17.2 HF052% C" e; P! g0 q: h$ D. Y3 B
03-01-2019+ h$ x3 q2 N+ s/ O/ f
========================================================================================================================================================
6 ^7 h! A) A+ g% W% }CCRID Product ProductLevel2 Title
' `! T( n( p! D9 y: T) d, G========================================================================================================================================================
% D) t+ K* ^. \, R6 {2020429 ADW ADWSERVER Incorrect adwservice status on Linux* L1 |$ `% p! D% J' ^7 q& `
2034815 ADW LIBDISTRIBUTI Cannot mark classification obsolete because it is associated to objects in the database$ s. w( w' o5 F7 o/ U! l
2015461 ADW PART_BROWSER New Component Browser should read the mapping of symbol and associated package as it results in error PKG-1005
. c/ N" `$ ?( t9 Y# d) K7 H2049380 ADW PART_BROWSER System Capture Import HDL not importing complete PTF File data8 J4 B2 ^1 h6 h
1948608 ADW TDA CUSTOMVAR directive value in project CPM was not updated by TDA UPDATE command., q5 y# U; f; x* o9 {
1992662 ADW TDA Custom directive added to the cpm file not updated after check-in
% w6 Y& g' {8 |% L+ E. _% O& T1733129 ALLEGRO_EDITOR COLOR 'Display - Highlight', double-click permanently highlights symbol
/ G+ l' Y% p# _, `- h1861938 ALLEGRO_EDITOR COLOR Changing layer color changes layer visibility7 B" M& U5 U( j z
2034753 ALLEGRO_EDITOR CROSS_SECTION Allegro PCB Editor crashes when a cross-section technology file is imported in Overwrite mode
! _% d; ^0 E! d$ U2036895 ALLEGRO_EDITOR CROSS_SECTION Replay script error during import of tcfx Xsection file% E7 p& C; u/ Z5 F' [
1929360 ALLEGRO_EDITOR DATABASE Via color is inconsistent on Vias with color assigned6 { a6 O% s1 f+ S" E, k$ w/ j
1984203 ALLEGRO_EDITOR DATABASE Drill holes not displayed correctly in the Zone area
' l% n% b. d+ M2013596 ALLEGRO_EDITOR DATABASE Assigning net name on Vias does not change the Via Color to that on Net Color automatically: W$ N& ^) w# }4 E `
2025798 ALLEGRO_EDITOR DATABASE Assign net to via changes color of the via to the default color
4 u% O% l% e6 ~2032678 ALLEGRO_EDITOR DATABASE Unable to delete layer on design! _' M& y( V" c2 W4 B, U
2032725 ALLEGRO_EDITOR DATABASE Dehighlight removes color assignment from color dialog' p3 E) ?7 m; b- C S0 ^0 t* s
2029542 ALLEGRO_EDITOR DFA Interactive Placement with Manufacturing Package to Package spacing* i' o. u- ~4 B; d; L, `
2020548 ALLEGRO_EDITOR DFM Cadence DFM Customer site cannot Submit Request8 w, ]) [/ ~# V+ b# _& a
2020566 ALLEGRO_EDITOR DFM Error when sending Design True DFM Rules Request/ E+ p+ B2 T! ^% S7 h
2030179 ALLEGRO_EDITOR DFM Allegro PCB Editor .brd file will not save after routing using Automatic Router1 L! |6 V+ N/ m. [
2052907 ALLEGRO_EDITOR DFM The Submit Request button for DesignTrue DFM Rules Request does not work
. f2 P9 i a* d/ W' u1928915 ALLEGRO_EDITOR EDIT_ETCH PCB Editor constraint status bar does not match Constraint Manager data when z-axis delay is turned on.
/ n, |8 k! g. Y% q1932165 ALLEGRO_EDITOR EDIT_ETCH Arc slide behavior with clines at odd angles: notches on slides6 w' i9 Q! X: Z# z ~
1943901 ALLEGRO_EDITOR EDIT_ETCH arc segment incorrect on slide.
4 z6 r$ r) _& ]+ e2 Q2031055 ALLEGRO_EDITOR EDIT_ETCH On drawing cline the width on a Layer is larger than defined constraint
3 O7 T% |) }* a) _. N2 m+ J' W) H1877891 ALLEGRO_EDITOR GRAPHICS Allegro PCB Editor crashes when started from EDM for projects without a board file or empty master.tag file
% K X0 p0 ]$ x3 V V2040689 ALLEGRO_EDITOR NC The decimal digits of a rotated oval padstack do not match the Drill Chart.
9 Y& D# {6 x& ?( F4 o# Y6 k; Q2028105 ALLEGRO_EDITOR PLACEMENT Delay in moving a large count pin symbol! H+ J5 O- R' L' O% G0 O; {, ~) C
2019027 ALLEGRO_EDITOR REPORTS Information shown in the Report Viewer is not correct.3 C: \# g5 g q* r8 R8 G
2022461 ALLEGRO_EDITOR SHAPE Abnormal termination of thieving function in Allegro PCB Editor$ C+ L5 }* Z4 i( w9 Z$ Q! M
2032048 ALLEGRO_EDITOR SHAPE shape void difference from hotfix 026 to 048: need square corners for full round
" C( o2 ^) ^5 C$ F$ `2040138 ALLEGRO_EDITOR SHAPE shape_rki_autoclip affects the overlapping shape boundary- c7 J$ _( Y1 K: }
2040259 ALLEGRO_EDITOR SHAPE Same net shape and cline adds shape void around cline3 N+ x! |+ I" q
2031468 ALLEGRO_EDITOR TECHFILE Cross section import (.tcfx) not working correctly.
6 o3 C2 C+ C; j* j2006425 ALLEGRO_EDITOR UI_FORMS Option to disable 'Create a New Design' window in OrCAD PCB Designer1 Z) Y" U! y1 P: p+ t
2007451 ALLEGRO_EDITOR UI_FORMS Option to suppress 'Create a New Design" window for File > Open in OrCAD PCB Editor from hotfix 048
* [ ^& q7 w5 m2009314 ALLEGRO_EDITOR UI_FORMS Existing scripts that open OrCAD PCB Editor not working in hotfix 0488 J1 Q) b- y5 v; z8 j( b
2021476 ALLEGRO_EDITOR UI_FORMS PCB Editor is slow when using the command 'add connect'5 c, p5 r) W0 O2 y, a$ a w
2039462 ALLEGRO_EDITOR UI_FORMS Hovering over Default symbol height in Design Parameter Editor does not display a description
! j* y- D8 L8 q5 H$ R' ^1808054 ALLEGRO_EDITOR UI_GENERAL Illegal value in axlFormSetField crashes PCB Editor3 p+ L6 ~* |* z7 v7 Q
1822679 ALLEGRO_EDITOR UI_GENERAL 'Symbol pin #' field is truncated on rotating components in the Placement Edit mode* W' ^9 C$ j6 z( K
1856438 ALLEGRO_EDITOR UI_GENERAL Script recording messages not displayed in the PCB Editor task bar when using the script window.8 Y, S4 Z7 V3 _% O& ^+ p" D
1879078 ALLEGRO_EDITOR UI_GENERAL Running PCB Editor from command prompt with '-product help' should list all products and options6 n% X) r: o- J0 q+ k6 {
1944225 ALLEGRO_EDITOR UI_GENERAL Cannot close log file window till we close report dialog box k9 h; w9 u) h# [$ @# C& Z3 E6 m
1967708 ALLEGRO_EDITOR UI_GENERAL New Command Window Shows Last Command in UI' U, ^4 P5 [6 i. J& U5 c
1968380 ALLEGRO_EDITOR UI_GENERAL Write all open editing sessions in MRU
' d- S$ Z3 P! `0 O1982138 ALLEGRO_EDITOR UI_GENERAL axlFormListDeleteItem(fw field -1) not deleting last item of a list4 p& ^, u3 Z( d9 v( m* {" v
2003054 ALLEGRO_EDITOR UI_GENERAL Grids not shown when 'nolast_file' is set
1 `2 e! s0 E$ \& Z2010760 ALLEGRO_EDITOR UI_GENERAL Pressing tabs is selecting only vias and not selecting clines in PCB Editor in hotfix 048 ?3 a7 I, h" F4 B
2019120 ALLEGRO_EDITOR UI_GENERAL Tab key is not working when there are two objects on top of each other3 _8 \: Z, K% L( i/ x) @; ?" U0 J
2029248 ALLEGRO_EDITOR UI_GENERAL Colorview load is not working when using absolute path
( _0 F# Q4 A2 j" \" k2030985 ALLEGRO_EDITOR UI_GENERAL The view of the PCB is offset after closing and opening the board. A) @, T' V2 B4 J' m
2037968 ALLEGRO_EDITOR UI_GENERAL Tab key will not cycle between cline elements.
, i1 k o0 u6 d B2015766 ALLEGRO_PROD_TOOLB CORE Advanced Testpoint Check does not work
' Z' I0 S1 g* A4 t2023356 ALLEGRO_PROD_TOOLB CORE Edit new session does not work in quick symbol editor tool box
! Y& X- J6 H5 I( w. t8 \8 I2017162 CAPTURE CONSTRAINT_MG Cannot apply ECSets in Constraint Manager-enabled Capture
$ n0 J& |7 I7 L/ f2026777 CAPTURE CONSTRAINT_MG Cannot apply electrical CSet (ECSet) in Constraint Manager-enabled Design Entry CIS
1 S! R& X) g" t E% W7 R2027545 CAPTURE CONSTRAINT_MG Getting error (ORCAP-40320) while creating ECSet
7 y& D+ S: w1 T: o$ f0 h/ f2012967 CAPTURE OTHER Capture license is loaded slowly in hotfix 0484 F. _* K; c B# A. J
2010093 CONCEPT_HDL ARCHIVER Archive .zip file keeps the whole folder hierarchy and not only the project hierarchy: D! m9 p. Z G( ]: q8 L7 |" l$ L( C
2040431 CONCEPT_HDL EDIF300 EDIF300, Schematic Writer, crashes in release 17.2-20168 |0 r/ O7 Y# F- h1 O6 f
2034077 SIP_LAYOUT DFA DRC is not catching all Shape minimum width violations1 ^+ ?4 [- u2 ~9 {+ j% F
2034094 SIP_LAYOUT DIE_ABSTRACT_ [VSDP-RDL Exchange] some traces are lost in SiP Layout4 g+ p/ z6 F, l* H5 L
2037462 SIP_LAYOUT DIE_ABSTRACT_ Cline Segments are lost on saving and re-opening the design in next session5 s" Y9 ?# }9 B
2025321 SIP_LAYOUT IMPORT_DATA compose symbol from geometry defaults need to change due to performance
6 a; A- Q) d+ t" h2 w2017759 SIP_LAYOUT PLACEMENT Placing a die creates extra place bound and puts pin numbers in the wrong place, causing future netlist import failure! V" Z2 {7 t. a/ Z6 S
2021057 SIP_LAYOUT SHAPE Polybool assert error when adding dynamic shape prevents shape voiding.
2 ~) L1 S1 j% j m2 t2012381 SIP_LAYOUT SKILL Ability to check if the Dynamic Unused Pads Suppression box is selected using SKILL
y) S% x, j7 u5 ^9 T+ u1990299 SIP_LAYOUT UI_GENERAL Pressing 'Esc' cancels DRC checking when there is no focus on the Allegro PCB Editor canvas
1 Z5 `, S7 F O8 d. e9 V( K- c6 L1997317 SIP_LAYOUT WLP Advanced WLP, Metal Density Scan does not correctly calculate scan region count in Y direction. d% E2 L% e4 Y) y7 D% k1 |
2029524 SPECCTRA ROUTE SPECCTRA stops responding when executing the quit command$ Q' G9 c+ E# M, k& I* X& U
1670888 SYSTEM_CAPTURE CANVAS_EDIT Rotation error when connected to a power symbol: W8 E+ F" D- v
1880809 SYSTEM_CAPTURE CANVAS_EDIT Can modify only one RefDes from canvas for duplicate RefDes; can modify both from the Properties window6 d0 Z/ W% q n6 L/ y, w+ N, A
1979063 SYSTEM_CAPTURE CANVAS_EDIT System Capture : File > Close is grayed out
* \. W P% u# W8 N4 t5 x2034498 SYSTEM_CAPTURE CAPTURE_IMPOR Cannot find parts via Find & Replace after importing Capture design4 s- q% b7 L; T& ?, K
1984561 SYSTEM_CAPTURE CROSSPROBE System Capture: Cross-probing from layout does not work when zoomed into a specific area on canvas
" r3 m- v! O5 K$ M% N1863460 SYSTEM_CAPTURE DARK_THEME thumbnail preview of pages is in light them but dragging the page the previes is dark
6 |' O, s' Q& P c3 c2025876 SYSTEM_CAPTURE EDIT_OPERATIO Route failures when dragging a circuit
& O" q$ n& ^8 m" q7 d2005904 SYSTEM_CAPTURE FORMAT_OBJECT Pin name text is smaller in System Capture than in DE-HDL by about 25%
% X1 C; b- _2 |# z2036782 SYSTEM_CAPTURE IMPORT_BLOCK Unable to import the block from project.
2 H2 [) |! l( N$ {6 W) {2025949 SYSTEM_CAPTURE IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not translate in System Capture9 N+ X* l2 V/ }5 G
2025950 SYSTEM_CAPTURE IMPORT_DEHDL_ Broken connectivity on imported ground symbols
- J! R0 n7 H; \2040923 SYSTEM_CAPTURE MISCELLANEOUS System Capture - Multiple Symbol Replace, disconnects and changes orientation
/ M, v3 B4 [0 o4 a2017526 SYSTEM_CAPTURE NAVLINKS Page information missing in NAVLINKS. ~- t: U, D4 x1 Y; M! o
2015346 SYSTEM_CAPTURE PAGE_MANAGEME Rename page fails in some cases5 A: M3 E- U" m% y2 n& j: Q9 m
2038811 SYSTEM_CAPTURE PRINT Black & White PDF showing colors
. l6 |8 R$ l! x5 ~ \$ F8 q) P2048493 SYSTEM_CAPTURE SYMBOL_GEN Symbol Editor, Modify outline adds an 'X' in symbol incorrectly
; X) y6 @+ i* s; Y) W6 u3 Z! M, d2031995 SYSTEM_CAPTURE VARIANT_MANAG Variant Editor does not load the design and restarts the machine after sometime.
- V* k$ U$ e1 u2032005 SYSTEM_CAPTURE VARIANT_MANAG Custom variables not saved for variants
2 w1 E" N! ?7 Y: J. H7 m7 k1968431 SYSTEM_CAPTURE WORKSPACE Unable to reorder the pages (tabs) when opened in the workspace! c2 R2 K. X, E" x; |
2040995 XTRACTIM GUI Running XIM from APD enables "skip DC R simulation" by mistake6 S( x% L- _/ S+ p8 e% ^( O
/ S% G- Q! X& `# ~) h) E3 W/ s) O
# }) { T9 A! Y6 B- l TFixed CCRs: SPB 17.2 HF051
, L# i, ] \4 l, {! v01-30-2019 u2 D* T* y5 I: ?; M( \
========================================================================================================================================================
7 b3 N* a3 p, U4 L: F1 i4 D$ q& \3 a' ]CCRID Product ProductLevel2 Title
6 w- V" X6 u7 p: x7 n9 ?5 i/ U========================================================================================================================================================) b/ W- ` X5 Q, [6 n) L! M; l
2015843 ADW LIBDISTRIBUTI Error for library distribution (lib_dist_client) regarding string index out-of-range6 I5 ]# h* _, U, [0 Y) q+ l5 ]# j9 W
1869914 ADW PART_BROWSER Adding components to System Capture schematic canvas takes long time in Linux clusters! U9 G4 @% V d: i& c! I4 w9 S
2010458 ADW PART_BROWSER RefDes values not appearing on parts( t. Z1 T% {9 w" b4 y
2022630 ADW PART_MANAGER Unable to successfully import a DE-HDL Design into System Capture+ ?3 F6 v# T, s' O% j
2005033 ALLEGRO_EDITOR 3D_CANVAS 3D Flex issues: Error message when opening design with bends in 3D viewer a$ b0 k u9 q/ H) W+ G
2023496 ALLEGRO_EDITOR 3D_CANVAS Error for designs with bend in 3D Viewer* Z5 _4 @* ]: P$ X1 k6 ^- @( y
2033459 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
) Q& @0 u8 W4 l" W& g1996431 ALLEGRO_EDITOR ARTWORK Via holes for connection have incorrect coordinates in Gerber: b' H6 x% |+ y. u# l$ b3 c
1995656 ALLEGRO_EDITOR DATABASE Attaching and Detaching a text file created with SKILL writeTable() function corrupts the text file
~* w# B; r Z8 b( w! [2027122 ALLEGRO_EDITOR DATABASE PCB Editor crashes when creating Place Replicate module5 r* X" K: R% m) v6 @
2023916 ALLEGRO_EDITOR DFM DFF Annular Ring: Thru via pad to Mask violates on via in pad instances. [& ~' R8 Y* w* M {0 Q
2024523 ALLEGRO_EDITOR DFM PCB Editor crashes in Mask To Trace check of DFF.
; ]4 `6 N! w5 [2 l9 t: ?2021318 ALLEGRO_EDITOR IN_DESIGN_ANA Integrated Analysis and Checking: Unable to run simulation with Crosstalk flow$ K: i- ] N1 }7 K; w# i% c, x
2014162 ALLEGRO_EDITOR NC Backdrill results using an OrCAD Professional license showing wrong values with hotfix 048
) v+ O3 E/ ?7 I2010791 ALLEGRO_EDITOR PLACEMENT Setting dfa_pause_level to 3 and then moving and rotating part places the part with offset4 |8 c# H* }7 S! C2 p
2017112 ALLEGRO_EDITOR PLACEMENT place_boundary shown at wrong location when moved with User pick and footprints rotated; A% d! _; a$ K5 U! ]
2028048 ALLEGRO_EDITOR PLACEMENT Rotate option using pick is rotating the outlines in different axis in view
4 ~4 |6 x7 {: E! X! M2028314 ALLEGRO_EDITOR PLACEMENT Crash on moving components in Allegro PCB Editor7 @5 k6 o+ K$ R% g
2029235 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when moving more than one component and hovering on IC
; E7 C. C( p; C0 {) s2022644 ALLEGRO_EDITOR SHAPE dv_fixfullcontact obsolete in release 17.2-2016
6 T* r0 \" C/ I2023322 ALLEGRO_EDITOR SHAPE Gloss does not add teardrops on all clines.
% U2 V/ J9 n- @! P8 h: B. L2024235 ALLEGRO_EDITOR SHAPE Copper Pour disappears when area includes parts. W$ f$ u/ b: I4 m. m
2024531 ALLEGRO_EDITOR SHAPE rki_autoclip is not working at a special XY location
g4 Y5 i, O; I# Z" k+ K" A2024599 ALLEGRO_EDITOR SHAPE Cannot create round corner for shape4 b4 J9 {9 E4 \ K
2024707 ALLEGRO_EDITOR SHAPE In-line void control does not work when there is no_shape_connect property attached
5 f U. W! Y1 U) M( N2026849 ALLEGRO_EDITOR SHAPE Cannot assign region name using the 'next' operation
% e3 d$ f, }+ C5 ~5 u3 @2030156 ALLEGRO_EDITOR SHAPE Shape Area report for cross-hatched shape includes hatching and boundary
9 g: u. B8 O/ A2 j U8 Z: ]- B1852981 ALLEGRO_EDITOR SKILL Error message while creating Copper Mask layer without a name using SKILL not clear
( @/ l% [" f( m( |. f3 \+ }, @1968054 ALLEGRO_EDITOR SKILL Document of axlClearObjectCustomColor should indicate that it can clear color for DBID of Net+ y$ |, j; N1 }, G- w; } k
2026429 ALLEGRO_EDITOR UI_FORMS PCB Footprint wizard: horizontal and vertical lead pitch level reversed in the image% R3 a5 b0 i5 | X& ^$ E5 y& m
1768032 ALLEGRO_EDITOR UI_GENERAL Numeric keypad does not work for file selection shortcut
. V6 B7 K# p( t1797376 ALLEGRO_EDITOR UI_GENERAL Release 17.2-2016: Padstack Designer saves padstack to the working directory when script is used
9 s( }+ i9 K' g( M, u1 B1798524 ALLEGRO_EDITOR UI_GENERAL Unable to save a padstack using script" D) e* O! B9 e- a5 x
1823031 ALLEGRO_EDITOR UI_GENERAL Help not working for OrCAD Productivity Toolbox
1 w6 V4 r3 m. q) p1849921 ALLEGRO_EDITOR UI_GENERAL Analyze menu missing in OrCAD PCB SI
6 f( Q6 v" C2 ]( _. E1951740 ALLEGRO_EDITOR UI_GENERAL Trigger for 'open' does not work when opening a .dra file
+ s' s- |, {3 J( C1952163 ALLEGRO_EDITOR UI_GENERAL Analyze menu missing in OrCAD PCB SI
y. v- }2 b5 @5 a* Y7 C( E( Y! p e/ D) S1982966 ALLEGRO_EDITOR UI_GENERAL SKILL command to access the Option window fields while in Interactive commands.
" a* p% u K, w" Q7 r+ H" w1983567 ALLEGRO_EDITOR UI_GENERAL Alias with Ctrl not working with 'command window history' variable enabled
7 h( r; q% o5 E" T9 t7 Z. h( i; w$ W1989507 ALLEGRO_EDITOR UI_GENERAL Third-party tool causes PCB Editor to stop responding to command
/ Y( o$ |+ F( S9 v S9 C, O6 u2003511 ALLEGRO_EDITOR UI_GENERAL Aliases using control (tilde) characters stopped working after upgrading to hotfix 0487 a; j- F- _& X7 f, o9 ?
2010418 ALLEGRO_EDITOR UI_GENERAL New command window breaks funckeys' S- K) G+ `& V6 ~
2018201 ALLEGRO_EDITOR UI_GENERAL SKILL axlDBControl ('activeLayer /') updates active class/subclass but ministatus form not updated
; j+ U( n! ?% {$ I5 d2023468 ALLEGRO_EDITOR UI_GENERAL axlZoomInOut does not zoom out, always zooms in regardless of zoom factor (positive or negative)+ N6 C+ N x3 T/ C M2 L
2026428 ALLEGRO_EDITOR UI_GENERAL PCB Editor takes several minutes when saving a design9 d: i3 u+ w- D t3 C' S
2032697 ALLEGRO_EDITOR UI_GENERAL Funckeys with Ctrl not working with 'command window history' variable enabled
# Q- J6 }2 I0 s2032717 ALLEGRO_EDITOR UI_GENERAL Funckey combinations, such as Ctrl + M, not working U2 U* u6 d& |- Z6 d( @
2014211 ALLEGRO_VIEWER OTHER Arrow keys are not panning in Allegro Physical Viewer
4 ~. Z0 J, f1 X: q0 v5 r2039081 CAPTURE NETLISTS Netlist not created: netlist fails for numeric pin names with backslash '\'; e% V8 \: Q6 x( A' B- O
1993057 CONCEPT_HDL CONSTRAINT_MG Constraints disappear in hierarchical design (Electrical->Net->Routing->Relative Propagation Delay)
, Q# i6 l" F* E/ m' o: R( v2004641 CONCEPT_HDL CONSTRAINT_MG 'Save Hierarchy' (hier_write) deletes bus object in Constraint Manager4 l' B/ e" T i4 N- Z- ]- ^$ C4 x
2020901 CONCEPT_HDL CONSTRAINT_MG Incorrect match Groups created in CM (TDO design)
* ~4 o, B. E9 Z- g( n2014979 CONCEPT_HDL CORE The active schematic page randomly changes while editing text
) n/ d8 d' e+ b8 u, ^% G2027905 CONSTRAINT_MGR DATABASE Pin Property changes in CM during uprev to release 17.2-2016; H; x0 z- u" w4 w9 B; I
1762263 ORBITIO INTERFACES Add set allegro_orbit_import variable to user preference$ M @ K7 g6 v3 i
2005860 PSPICE LIBRARIES Error when simulating design with TL494 part in release 17.2-20160 w) K9 K2 B/ R- c
1980072 PSPICE SIMULATOR Noise in the waveform when using DELAYT and DELAYT1 with capacitor* H( }1 K, o/ ]
1977615 RELEASE INTEGRATION Cannot import third-party schematics into OrCAD Capture in release 16.6
% h9 s3 R# _$ `5 i \2027009 RF_PCB SETUP 'RF-PCB' - 'Setup' changes not saved on Apply
# [2 |8 A! G% A, q: i; N6 H/ o0 h2002040 SIP_LAYOUT MANUFACTURING IPC 356 'ignore die layers' does not work: netlists to die
; n' p' B: o) ~# I. G( ?% n2024703 SIP_LAYOUT WLP Cannot Add Pin Text: Error on 'Manufacturing' - 'Documentation' - 'Display Pin Text'$ X, B* q1 \: Y" J* |# I1 ~
2010045 SYSTEM_CAPTURE CANVAS_EDIT Cannot snap back vertical CAP until moved up and down horizontally
, H4 `5 g* N. ^0 h! J' L( d3 P2010443 SYSTEM_CAPTURE CANVAS_EDIT Cannot select the CAP part, v! X1 Z* K2 \& o: ~- ^5 A
2012843 SYSTEM_CAPTURE PACKAGER Cannot short two grounds in the schematic
( W* p& D9 b8 ~7 e0 l' `/ ?" x2015574 SYSTEM_CAPTURE PACKAGER System Capture is treating quotes in PTF files differently from DE-HDL
; N5 ~+ N; ~9 g9 N" \7 R, u2022653 SYSTEM_CAPTURE VARIANT_MANAG Variant Editor - Allow Alternates where ALT_SYMBOL is a valid match for JEDEC_TYPE
6 e1 A% U+ C/ i6 o* S2024742 TDA SHAREPOINT Accessing projects is taking time
2 O( [- @, a7 F8 c1 i$ s2010531 XTRACTIM OTHER Allegro crash on repaint of command window
: ~5 S0 I+ k- i. y& R& ~2022351 XTRACTIM OTHER XtractIM is crashing the latest HF S049
% v+ n! }% u6 s% b+ O0 b( V k0 ?& q! @6 w4 R
. E4 C4 m& L2 D( `Fixed CCRs: SPB 17.2 HF050
/ I6 U! l: S2 o. ?4 n3 y12-23-2018 B$ v' m' t9 x3 U C, e% i6 |
========================================================================================================================================================0 f2 i; [4 G+ g( y! H
CCRID Product ProductLevel2 Title
8 v; q* x: C: Y) ^========================================================================================================================================================
5 ?0 P, Q @+ z8 q( q% [2012119 ADW ADWSERVER Cannot connect Component Browser to server
4 o2 r7 x0 A- q1998856 ADW ADW_UPREV adw_uprev fails and a typo in rule name r& i7 |6 n: E$ x0 U
1673333 ADW CONF Configuration Manager stops working and gives Java Timer-1 Error
/ \! Q7 D; B/ @* u0 \1900342 ADW DBEDITOR 'Link To' on a schematic classification attribute does not work with linked attributes containing parenthesis" i0 o7 O/ t: i+ i
1997516 ADW DBEDITOR DBEditor stops responding on changing attributes
+ ^) i( d& W% [( r" o( T6 j1986292 ADW LIBDISTRIBUTI Some parts are not updated in the part table in all_noauto and ini_noauto (restricted_sites).
8 i% Q1 k4 u2 e; }6 T2010460 ADW PART_BROWSER PKG-1002 error when opening a DE-HDL design
$ s4 y4 D4 N: a& w: o2013430 ADW PART_BROWSER Add component is inactive if WB_SHARED_RESOURCES is not pointing to the installation directory( M5 n- `; a( `9 @+ {
2022806 ADW PART_BROWSER PKG-10005: Cannot package the following primitive instance in any section of the physical part* |- A. X: q# d* h* E
2006528 ADW PART_MANAGER Part Manager does not update parts when Key PTF property value changes! o! S. L+ q+ t- z- @
1980397 ALLEGRO_EDITOR DATABASE Mechanical pins with route keepouts (RKO) not updated
$ m/ X+ q1 l8 W6 {1 m6 p1988171 ALLEGRO_EDITOR DATABASE Backdrill clearance Keepout is not applied consistently
5 B/ N" b7 Z6 ]% r( F- H% e1994280 ALLEGRO_EDITOR DFM PCB Editor crashes during Unplace component' e& e4 i c; N
2012742 ALLEGRO_EDITOR DFM DFT for testpoint to outline not showing DRC
3 M9 d" B, X0 I5 C2002680 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on choosing Add Connect for two selected nets
; H( n2 p4 r- O8 M2004597 ALLEGRO_EDITOR EDIT_ETCH Illegal BMS Identifier error when copying multiple via structures
! F% w+ _" S. V- D% v2004929 ALLEGRO_EDITOR EDIT_ETCH Net with physical pin pair constraints is using incorrect line width when routed" g9 ~9 l4 d$ T& x
2008314 ALLEGRO_EDITOR EDIT_ETCH Adding nets in tabbed routing crashes PCB Editor
9 L: x2 }! U" ~. i: B2018710 ALLEGRO_EDITOR GRAPHICS Using the mouse to zoom by scrolling stops working randomly
5 y' q: M/ ?+ c# Q0 Z" u, f2018841 ALLEGRO_EDITOR GRAPHICS Canvas does not regain mouse focus after working in the Options pane in hotfix 0490 H6 d2 J) a; T H+ W& e
2019482 ALLEGRO_EDITOR GRAPHICS Canvas does not regain mouse focus after working with the Options pane in hotfix 049 on Windows 7
1 ^8 x2 v6 y( s2 J4 l/ U2019864 ALLEGRO_EDITOR GRAPHICS Using the mouse scroll button to scroll the canvas: focus is in the Options pane1 g1 y+ G# _6 e- N
2020750 ALLEGRO_EDITOR GRAPHICS Zoom in/Zoom out scroll does not work, e- C( ?0 X+ `! x" M' i
2020847 ALLEGRO_EDITOR GRAPHICS Scroll up/down key focus remains in command screen even when canvas is selected
! d0 c5 b5 }. b) \" h1 j7 K1 _1908812 ALLEGRO_EDITOR INTERACTIV Tools > Design Compare command does not work on Windows2 _1 P: A6 e& W7 Q
1995846 ALLEGRO_EDITOR INTERACTIV When there is an embedded component, the result of Metal Usage report is incorrect.; T& o5 @2 `; t0 v4 Q& S, @% e
2011449 ALLEGRO_EDITOR INTERACTIV Command not found error (_impvision) for Impedance and Return Path DRC visions3 L) a1 ~0 d( [
1982867 ALLEGRO_EDITOR INTERFACES DBDoctor displays error for objects outside extent that cannot be fixed because the extents cannot be increased
: n' e( f( |5 r( H; w1983177 ALLEGRO_EDITOR INTERFACES PCB Editor crashes when reading IDX file
; }2 V1 U$ N) T# g) I/ m3 ]1985623 ALLEGRO_EDITOR INTERFACES STEP model not exported from PCB Editor7 Z! i3 a4 e! _1 r+ r7 v
1994855 ALLEGRO_EDITOR MANUFACT Drill legend with counter-bore: legend size not uniform when database set to inches' \5 u1 d' H4 Q6 Z
2001355 ALLEGRO_EDITOR NC PCB Editor crashes with NC route parameter- {- S3 P0 l {. s
1753414 ALLEGRO_EDITOR OTHER Ability to add Rigid Flex class in a format symbol
8 S2 p, ^# E) T `: G1 P$ [; f. [2004786 ALLEGRO_EDITOR OTHER Legacy menu option missing in OrCAD Professional: C9 `8 t& B5 p& E& ]4 {
1949695 ALLEGRO_EDITOR PADS_IN Third-party to PCB Editor translation does not make a clean conversion
% W. c7 z. `- `) N6 C* A1949658 ALLEGRO_EDITOR PLACEMENT SKILL module creation issue: subsequent runs rotate module incorrectly
, } D/ `5 I! G4 D: I, m, @1 {2001496 ALLEGRO_EDITOR PLACEMENT Constraint Region not replicated as part of the Place replicate apply command7 T, z5 p4 M4 i$ \" r6 _- I
2002989 ALLEGRO_EDITOR PLACEMENT Default rotation point is set to 'User Pick'6 ]+ a- M/ M( W) i& B0 Q
2007301 ALLEGRO_EDITOR PLACEMENT DFA boundary is shifted when moving components with User Pick2 b2 Y6 ? @4 y4 F9 |9 _5 \- v
2007312 ALLEGRO_EDITOR PLACEMENT DFA boundary is shifted when moving components with User Pick( R0 Y; Q5 p2 C5 Q: J
2008098 ALLEGRO_EDITOR PLACEMENT DFA boundary shows a shift if anchor point is set to 'User pick'' Q- m, v8 e& J2 N, t
2009085 ALLEGRO_EDITOR PLACEMENT DFA boundary is shifted when moving components with User Pick: Z" f% m' o! i8 }) _' B+ y, v9 d q
2009090 ALLEGRO_EDITOR PLACEMENT DFA boundary is being offset when moving components with User Pick2 @$ k+ v* I5 d7 n& K
2009580 ALLEGRO_EDITOR PLACEMENT Component outline offsets during move process
* C. n7 l3 W& D3 |# f3 R7 e/ f7 P2010726 ALLEGRO_EDITOR PLACEMENT Two images appear when moving component in release 17.2-2016, hotfix 048
$ W A) R2 }. e2 P1 y, L2010819 ALLEGRO_EDITOR PLACEMENT A separate outline appears when moving components using User Pick2 i6 p+ a) j8 Y6 v; s% b6 [
2011454 ALLEGRO_EDITOR PLACEMENT DFA boundary is not centered correctly on moving components) k% \: t: [: b
2011497 ALLEGRO_EDITOR PLACEMENT DFA boundary shifted from the part when moved
9 }: c& w' A5 {4 \8 p& r2014250 ALLEGRO_EDITOR PLACEMENT Moving a symbol using the 'User Pick' causing an offset image of the symbol outline getting attached to cursor
. @5 {% `$ M* j" D j2 D% F: e2015676 ALLEGRO_EDITOR PLACEMENT Strange end-to-end DFA checking: offset of DFA from component when in user pick
& x4 a3 E! {/ _2 Y5 L' n" l( u2 e1 C2016421 ALLEGRO_EDITOR PLACEMENT Fail to place symbols because definition is incompatible for attribute 'PW_GENERATED'9 J K! M( y2 k$ t
2016452 ALLEGRO_EDITOR PLACEMENT Some symbols cannot be placed due to property definition differences& F0 M8 ~" r& k% V8 Q. a* t
2016527 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes on moving all components on board
9 {/ v) f6 g- l7 K2017364 ALLEGRO_EDITOR PLACEMENT Strange behavior when moving component: DFA or place bound area is centered around the User Pick position
$ q) F a. G) F. r! _) D* a, c4 z2018859 ALLEGRO_EDITOR PLACEMENT Moving parts by 'User Pick' or 'Sym Pin #' shows two component placement boundary outlines$ k6 `5 |& ]2 V" \3 G$ e- t
2019364 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when moving components
9 X: e2 ]. z" x7 c5 w2019478 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when moving more than one component across the design5 w" H" F0 A- f, k- L. l! T9 |# `
2019624 ALLEGRO_EDITOR PLACEMENT DFA Boundary is offset from definition when moving symbols with user pick
/ r9 A+ T) p6 e% l* E d5 u/ m" K$ O2021625 ALLEGRO_EDITOR PLACEMENT Graphical Issue with Edit - Move and User Pick: additional outline image shown8 O: K# D& G: Y9 ?" R; N4 i; a
2022203 ALLEGRO_EDITOR PLACEMENT Place bound outline is shown at the center of the pick when moving a part by User Pick
: |; I" D9 o9 k2024655 ALLEGRO_EDITOR PLACEMENT Moving multiple components causes PCB Editor to crash
% U4 N" P# ^- D* G; T9 M/ |2025895 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when multiple symbols are moved and on getting too close to another symbol2 Z) K+ L6 `2 {6 x$ n" S
2004497 ALLEGRO_EDITOR SHAPE Automatically deleting antenna shape is not deleting thermal reliefs associated with those shapes
2 H0 ]" E* L& O2007832 ALLEGRO_EDITOR SHAPE Cannot void shape properly after rotating symbol
/ k0 l4 ?. {: Z1 J+ w* C0 F. x, N2009601 ALLEGRO_EDITOR SHAPE Error for shape created using third-party SKILL utility: f+ h+ r# U- x* p! l: V
2010924 ALLEGRO_EDITOR SHAPE Dynamic shape does not void in route keepout areas9 S& M/ D3 h A5 R+ x' l
2011176 ALLEGRO_EDITOR SHAPE Nothing happens on choosing 'Shape- - Change Shape Type' in Allegro Sigrity SI
; F# Z& p; w" E* _' R* g2015446 ALLEGRO_EDITOR SHAPE Thermal relief connection created for static shape covering pin when inside a void in a dynamic shape.
x0 s/ \8 N6 L2 ~( P2017273 ALLEGRO_EDITOR SHAPE Same net spacing does not void properly for shape to hole.
: N+ J6 f$ J5 A% d4 [2012878 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as size differs for customState and customExteded in registry
. E+ d) M5 i2 `2018177 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as size differs for customState and customExteded in registry: ], R$ R: ?% G% k
2019437 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as size differs for customState and customExteded in registry# `" {+ T% B* }* {' I6 p, l- |$ [
2020491 ALLEGRO_EDITOR UI_FORMS Cannot load custom toolbars because the customState and customExtended Windows Registry entries are incorrect2 ?" [" Q; v1 {) Z
1897843 ALLEGRO_EDITOR UI_GENERAL Function Keys, such as F3, F6, and F7, are not working if tool is idle for some time
6 Q! F2 Z6 `) o0 A a& I) L8 _& v. o j2000445 ALLEGRO_EDITOR UI_GENERAL Funckeys not working in hotfix 048 with the new Command Pane as default, C- Z% t; `& O% _( E) E- o6 Q
2001847 ALLEGRO_EDITOR UI_GENERAL Ctrl related funckeys not working in hotfix 048
/ p5 t# X& U& H* C# j2008112 ALLEGRO_EDITOR UI_GENERAL Funckeys using Ctrl and Shift do not work in hotfix 048 (QIR 7)
, O3 j! f# A6 k# P7 k! c- _9 i2010370 ALLEGRO_EDITOR UI_GENERAL Shift + arrow key does not move component in release 17.2-2016, hotfix 048
& l* h3 L/ P4 ?' x7 M2015418 ALLEGRO_EDITOR UI_GENERAL Funckey not working4 ~: d+ P- v& v, h. A1 ? a
2015443 ALLEGRO_EDITOR UI_GENERAL Text does not regain focus even on clicking after using a drop-down menu
5 P: c. E( j! E5 ?) j2016899 ALLEGRO_EDITOR UI_GENERAL Dynamic zoom and funckeys are disabled after clicking a combo box in the Options pane
6 Y1 e3 Y- u- n2019753 ALLEGRO_EDITOR UI_GENERAL Infinite Cursor disappears regularly in hotfix 049 when infinite_cursor_bug_nt is set) o" n1 U9 K" I- c. @9 f
2019990 ALLEGRO_EDITOR UI_GENERAL Mouse over does not highlight pin, need to click
# t' @9 H! n4 P9 W2020162 ALLEGRO_EDITOR UI_GENERAL Funckeys not working in hotfix 049: pressing F4 not running Show Element" g( p3 p* h4 m: Y9 ~$ i$ W) }
2020168 ALLEGRO_EDITOR UI_GENERAL Data tips not shown on mouse hover
4 f: b! U# y$ S7 O2020840 ALLEGRO_EDITOR UI_GENERAL Page-up/Page-down (remapped to zoom-in/zoom-out) stop working until mouse scroll button is pressed
2 k# ?, m9 m. o2021416 ALLEGRO_EDITOR UI_GENERAL New user interface does not shift input focus and zoom in/out does no longer work in layout window! v- G, `0 {# x
2022185 ALLEGRO_EDITOR UI_GENERAL Ctrl related funckeys are not working
N; y5 | R; z. \/ X' L8 H4 D2023402 ALLEGRO_EDITOR UI_GENERAL During Add text, focus does not move from the subclass dropdown to the canvas.
* f/ t* R$ h8 M3 ~1 H) D2025806 ALLEGRO_EDITOR UI_GENERAL Function keys and shortcuts not detected
* I; a6 r4 I! W2027581 ALLEGRO_EDITOR UI_GENERAL Funckey problem: focus lost from canvas on using another window* a' v# X3 d6 {2 j# v* i
2009382 ALLEGRO_EDITOR ZONES When deleting zone by Zones - Manage, the shape in zone is out-of-date7 r5 }* ]4 Q v [" E
1977211 APD DXF_IF APD: die pads shift after export DXF
: m3 p; D+ v6 d5 t6 J2 R: @2018483 CAPTURE NETLISTS Error when extracting netlist from schematic (ORNET-1193)
% [0 \' @2 t8 j8 c# p2 V# w2022764 CAPTURE NETLISTS Schematic will not generate pstchip.dat file; p, G) R7 R2 l- b2 F
1921557 CAPTURE NEW_SYM_EDITO Zoom to region option grayed out
% G" y1 j# O8 ^& B' x+ ?8 o8 L* m* i1945203 CAPTURE NEW_SYM_EDITO Symbol Editor: No Zoom to Region and cannot edit Pin Type and User Pin Properties for multiple pins
$ R2 G) [- W! y% m1950178 CAPTURE NEW_SYM_EDITO Ability to remove convert view of a component
& j0 S% g- l( H/ m9 f1966792 CAPTURE NEW_SYM_EDITO JavaScript error on trying to edit pin name for GP0
# t" N9 j3 b$ |6 c+ P1969099 CAPTURE NEW_SYM_EDITO Cannot add convert view after creating a part% n# m* N$ j5 B( ?1 ^0 d
1969834 CAPTURE NEW_SYM_EDITO Shapes not mirrored around center if more than one shape selected in Symbol Editor) M& [# U9 f/ ^/ X! L! H w& s8 ~
1970984 CAPTURE NEW_SYM_EDITO New part is getting Numeric Numbering automatically
{* n- Y5 _! u% Y; v# h1 E: H1972607 CAPTURE NEW_SYM_EDITO New Symbol Editor: name cannot be edited unless value is entered for a new property
7 J+ }3 Z! G6 q' `1972635 CAPTURE NEW_SYM_EDITO New Symbol Editor: wrong listing of Symbol Properties in right pane- @, i0 R; I, D* Y4 u0 G
1974296 CAPTURE NEW_SYM_EDITO Design Template font settings are not being honored for new library/part creation
" `7 P6 m7 S0 s% G7 G1982783 CAPTURE NEW_SYM_EDITO Part Editor is blurry when zoomed out.
) d; J; B% H# Q% E6 V) ?/ L/ y1993361 CAPTURE NEW_SYM_EDITO Cannot change part numbering, set to Numeric by default
* g1 o- J- g/ Q$ O* H! B2003749 CAPTURE NEW_SYM_EDITO Cannot save edits to hierarchical blocks in new Symbol Editor in hotfix 048
& d, f# \8 ~% c* P" x+ Q2004395 CAPTURE NEW_SYM_EDITO 'Pin ignore' modifications not saved in new Symbol Editor 'Edit Pins' after hotfix 048
/ O$ D7 O4 K, `$ t% J) K0 y2007747 CAPTURE NEW_SYM_EDITO Cannot add Convert View after creating a part+ u% f1 H8 U. f' r
2011321 CAPTURE NEW_SYM_EDITO 'Place - Picture' is not working for blocks in hotfix 048
6 E7 L. S. S; c: @7 K2013146 CAPTURE NEW_SYM_EDITO 'Part Edit' not updating changes in hierarchical block
2 ^) I! c$ s1 a: m2002904 CAPTURE OTHER Unable to check out Capture license in release 17.2-2016, HotFix 048, Y; I3 H" x0 \4 J* N) L4 y2 R& ?
2002922 CAPTURE OTHER Unable to check out Capture license in release 17.2-2016, HotFix 048
) m; |/ R, D' G$ b8 f1988812 CAPTURE PART_EDITOR Parts created or edited with hotfix 038 Part editor do not use default font size
5 \$ L- K0 i7 s- \" k2008912 CAPTURE SCHEMATIC_EDI Design Compare shows 'NaN' in the graphical output. s. L3 {9 V' K* M) q* K! b9 E
1985701 CONCEPT_HDL CHECKPLUS Library symbols are missing from the examples folder/ K+ V9 t) a$ x6 [+ M- I2 Y
1933789 CONCEPT_HDL CORE honor_sch_custom_texts: `" y3 f0 X' n# n& B+ W
1933892 CONCEPT_HDL CORE HONOR_SCH_CUSTOM_TEXTS4 Q. ?- M- n2 `# c2 X
2001737 CONCEPT_HDL PDF DE-HDL crashes on choosing File - Publish PDF" d1 S0 i7 J! ~0 w4 R6 s+ ?
2010508 CONSTRAINT_MGR CONCEPT_HDL Schematic data corrupted on reading the data from CM database using the CM SKILL APIs) P' G5 t# r2 \( }' |
1997461 PSPICE AA_FLOW 'Edit PSpice Model' from 'Assign Tolerance' window does not work
) }- K' k$ v7 C, R9 B2005948 SIP_LAYOUT DIE_EDITOR CTE expansion tool shifts pins off the die/ K% O; N/ S% O
1893045 SIP_LAYOUT INTERACTIVE Refreshing bond finger labels causes all the labels to shift location
: L/ I6 I" B8 _2006926 SIP_LAYOUT ORBITIO_IF Bundle translation from OrbitIO is incorrect
3 c" X1 s$ |( t* T4 c5 H6 _2006659 SIP_LAYOUT SHAPE Cannot form fillets inside a shape in hotfix 048$ u' F3 u+ i) B( I/ w8 _+ `& I3 [
1969192 SYSTEM_CAPTURE CANVAS_EDIT Pin Numbers of Discrete Symbols visible
" t' ?( `3 c$ D f! ?7 W) k* s$ t( v; C1982368 SYSTEM_CAPTURE CANVAS_EDIT System Capture switches to Auto Pan, even if the option is disabled, in the Notes mode- c' _2 p5 m7 W- q% k! l
1995012 SYSTEM_CAPTURE CANVAS_EDIT Connect lines do not move with components! m* @. _2 q* q) m4 b7 }
1907992 SYSTEM_CAPTURE CONNECTIVITY_ Draw stubs is not respecting stub length setting.
s1 k5 t f4 J/ `1960100 SYSTEM_CAPTURE CONNECTIVITY_ Moving components after routing failure: connect lines do not move resulting in disconnected route
- s$ j2 v7 k/ G2 K; J4 H0 {' ^! V1988284 SYSTEM_CAPTURE CONSTRAINT_MA Log files and topology files are being stored at the top-level design (CPM) folder level: R5 R& s4 F+ L5 e% c( o
1996039 SYSTEM_CAPTURE COPY_PASTE Cut and Paste change the pin numbers for connector after saving design.# W) n% @/ g' C5 O
1951700 SYSTEM_CAPTURE EXPORT_PCB System Capture: Export Physical - Change Directory UI entry block not displaying properly. F: W: S6 j! ]" j7 }0 v$ a5 n+ H
1970761 SYSTEM_CAPTURE EXPORT_PCB Cannot import System Capture netlist if PCB Editor is launched with -proj argument% y W4 Y" M8 S
1997533 SYSTEM_CAPTURE IMPORT_PCB Pins do not swap in System Capture on backannotation
: C* a& E7 f0 j$ \1910962 SYSTEM_CAPTURE MISCELLANEOUS Dragging GND symbol placed on a pin sometimes disconnects the GND symbol2 t o2 | v6 [" Y9 S0 ~! r
1962037 SYSTEM_CAPTURE TABLE_OF_CONT Table of content link number not same as page number in the title block, P* Q* c/ ?4 y' h' R
1986317 TDA SHAREPOINT Cannot enable Design Management and SSO session expires
/ h' I' f3 v6 x4 X0 g
; p( n# }! O) J8 z7 b$ D5 H+ [3 p2 H j, ~- Z7 t# J: r: F0 T
Fixed CCRs: SPB 17.2 HF049
1 |# c2 X4 Q( g0 p2 X11-16-2018
' n% m8 o4 ]- h/ ~7 z% O========================================================================================================================================================; D3 u4 q4 e1 m t
CCRID Product ProductLevel2 Title, \; P; k" r9 e) J; m- c' ~; {
========================================================================================================================================================* \" i; x" p) t6 X8 \
2002642 ADW ADWSERVER Exception in adwserver.out with LDAP enabled
; N0 U3 ^, v% c( z3 V! I- {2007046 ADW ADWSERVER Component Browser is not connecting to server in hotfix 048
+ a) G/ T. g2 h' F* I1997678 ADW DBEDITOR Model not deleted due to missing cell model relation
4 S* ~0 U, m; X. Y) d5 O( t) _2 k1985059 ADW FLOW_MGR Flow Manager issues warning about project path that contains a period, removes from catalog file2 E9 D; B s* P- O
1991515 ADW FLOW_MGR Flow Specific Tools: Launch error after upgrading to Hotfix 044 and extending code8 ?1 h, ?: z- F; O4 G
1972762 ADW PART_BROWSER The Schematic Models icon does not match the definition in EDM Component Browser: x1 ?* c% U) I2 o0 i/ y
1830062 ALLEGRO_EDITOR DATABASE Uprevving release 14.0 design with stand-alone DBDoctor in release 17.2-2016 crashes; works in release 16.6, w9 ^9 t5 A8 H4 A* d8 k( l
1980161 ALLEGRO_EDITOR DATABASE NODRC_ETCH_OUTSIDE_KEEPIN assigned to text in library part is not passed to PCB Editor, _& o9 P; K( a- A$ O# I: n. k- U( a
2003757 ALLEGRO_EDITOR DATABASE Open circuit not detected by PCB Editor: reports unconnected pin as connected
9 M' Z5 S9 E) I2009748 ALLEGRO_EDITOR DFM PCB Editor crashes on Update DRC4 ^- u' d) U0 a
1796895 ALLEGRO_EDITOR DRC_CONSTR Increase precision of Inter Layer Spacing check1 V& x7 J8 ?+ i% L
1997487 ALLEGRO_EDITOR DRC_CONSTR Cannot add teardrops to some pins4 f5 _0 o3 i4 Q6 `
1857024 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using funckey 'y FORM mini padstack_list -+'
2 C1 q' O7 V$ Z' C) }- B1 U# I9 G1979750 ALLEGRO_EDITOR INTERFACES axlStepSet not working for component definitions- ?( r* w& [9 H5 j
1988168 ALLEGRO_EDITOR MANUFACT Graphical Compare in productivity toolbox terminates with errors
6 C8 z& m6 \8 R! d6 T1982233 ALLEGRO_EDITOR SCHEM_FTB Netlist files cannot be imported into board as the process is not finishing4 b" |0 _6 E. O! ^
2000367 ALLEGRO_EDITOR SCHEM_FTB Cross-probing between OrCAD Capture and PCB Editor does not work in HotFix 048! k" U3 G6 ^8 O* M2 B/ q2 D4 m$ E4 J
2000397 ALLEGRO_EDITOR SCHEM_FTB Cross-probing not working with hotfix 048; r8 m; ^, O7 D' S7 _
2000552 ALLEGRO_EDITOR SCHEM_FTB Cross-probing is not working if we are importing Netlist from PCB Editor
" r6 q" U! C4 O) k9 b. t H2001165 ALLEGRO_EDITOR SCHEM_FTB Cross-probing between Capture - Allegro PCB Editor fails after hotfix 0484 i: w6 ~( |3 k3 o1 l# l
2002635 ALLEGRO_EDITOR SCHEM_FTB Cross-probing issue because of Unique MPS Session in HotFix 048 (QIR7)
2 l0 W# G6 H) N2004252 ALLEGRO_EDITOR SCHEM_FTB Cannot do cross-probing between Capture and PCB Editor
8 L3 b3 L% P: z# i6 f Q2004305 ALLEGRO_EDITOR SCHEM_FTB Inter-tool communication is not working properly in PCB Editor release 17.2-2016, hotfix 048
! M* ~3 K. G" f) J' g; H) n% N1978660 ALLEGRO_EDITOR SHAPE Static shape on dynamic shape issue: thermals not removed when component is moved c0 F) Q1 f' A4 M4 `8 B
1985035 ALLEGRO_EDITOR SHAPE Thermal reliefs not removed on moving parts
* c l% `% a4 ~, z& `" x1960966 ALLEGRO_EDITOR SKILL Stackup import is not working in release 17.2-2016 via automation* G9 F( B0 U3 K
2003651 ALLEGRO_EDITOR UI_FORMS Error on starting and loading footprints in hotfix 048: message about customExtended and customState( G9 N' q( a4 b0 v6 M# k0 E
2003810 ALLEGRO_EDITOR UI_FORMS OrCAD layout editor font size is too small for almost all UI/ J3 v* r/ `8 R1 W8 u
2003832 ALLEGRO_EDITOR UI_FORMS Error on loading footprint in hotfix 048: custom toolbar cannot be loaded due to registry problem
0 P( U7 Y4 }8 C4 q+ W4 r- I" G2004769 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as the size of customState and customExtended differs in registry
; u1 ~- i! L) h ]7 q* H1 _8 S2007669 ALLEGRO_EDITOR UI_FORMS Broken scalability between OrCAD PCB Editor and Allegro PCB Editor
) T' t" e: L& U8 H! s) r! G1987164 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding when multiple sessions are accessing third-party tool
/ N6 v" r2 [) }. I) l; D% {1983512 ALLEGRO_PROD_TOOLB CORE Allegro Productivity toolbox: Advanced Testpoint Check is not working
) g; r/ q6 o: J1996008 APD 3D_CANVAS New 3D Canvas does not work in APD, C' ~+ i0 f0 T9 I5 f8 y2 y4 E
1993698 APD SHAPE APD stops responding and database is corrupted on moving, deleting, or updating a symbol2 h9 @3 L0 N0 a+ f ]
1999446 CAPTURE OTHER Update symbol database in Trial
2 m) L8 l% o. y7 P1962222 CONCEPT_HDL CORE Nested hierarchy block RefDes transfer issue: suffix added to RefDes# Q/ t# t6 c; c, k
1964260 CONCEPT_HDL CORE RefDes not updated in a hierarchy block on repackaging release 16.6 design
3 W, w- C& o, t% d" [. ]9 N1972243 CONCEPT_HDL CORE Version filter does not work correctly9 b: z2 L5 C! g& v. V
1993448 CONSTRAINT_MGR DATABASE CSet is duplicated with same name when modified in SigXplorer+ u' b+ [3 b A: k) B; j/ L
1976148 CONSTRAINT_MGR INTERACTIV DRC worksheet in Allegro PCB Editor: 'Go to Source' flickers worksheet and does not switch
9 ?7 J5 s, X- {2 K. Q- a% f( k1948372 CONSTRAINT_MGR UI_FORMS cmDiffUtility fails to compare and gives the message 'Failed to read the configuration file'
/ U3 J& \" \0 {" w* u9 g1961750 EAGLE_TRANSLATOR PCB_EDITOR Voids and some shapes of third-party board not translated correctly
3 F% r; v3 O% E% l) R. m) A1984569 FSP DECAP When a pin function is in an interface or custom connector is changed, decaps defined for the part is deleted
0 Y0 I! B2 n8 Y1984588 FSP DECAP FSP crashes when changing pin functions or bank settings for a connector
M( m; M. i6 t/ k" [1984590 FSP DECAP FSP design fails to load if pins are defined with a pin function that is later changed in custom_connector.crf
4 v: O7 }0 N \* b7 P2 m1985555 PCB_LIBRARIAN IMPORT_EXPORT JavaScript exceptions on opening libraries converted using con2cap% y" x* H- ~# M- r# P5 Y/ ^! ~
1961944 PCB_LIBRARIAN SYMBOL_EDITOR Hide symbol outline in new Symbol Editor
$ U7 p7 t, h5 P1967532 PCB_LIBRARIAN VERIFICATION libimport fails with ERROR(SPDWPAR-102): Metadata has the ErrorStatus value set.( u/ q/ g V3 ]7 o* C6 C$ ]% V$ |7 s
1976965 PSPICE SIMULATOR PSpice 'Tools - Generate Report' not working in release 17.2-2016
4 u3 X! [. n. c2 t: j( P: i3 Y5 s, {$ D1982260 RF_PCB FE_IFF_IMPORT Unable to successfully pull in .IFF file created in ADS.
1 Z2 D1 X! O# [1981585 RF_PCB LIBRARY Cannot load RF symbol via2 into PCB Editor
2 \2 r, k9 Z% c, \% r0 [3 x5 A+ G" K1976845 SIG_EXPLORER OTHER CPW trace models do not solve in SigXplorer after changing some trace parameters
; ]! T( [( U1 i8 _9 y1986466 SIG_INTEGRITY OTHER Delay in Relative Propagation Delay worksheet is displayed as a negative value+ `9 K6 j0 D; f! M) f
1980264 SIP_LAYOUT INTERACTIVE SiP Layout crashes on running 'Manufacture - Documentation - Display Pin Text'2 g3 }7 m3 D, W
1983381 SIP_LAYOUT REPORTS Incomplete Design Summary Report' J. m$ k5 J3 s1 g' D; b
2005709 SIP_LAYOUT SHAPE Dynamic shape voiding around same net cline segment: no property attached
( I( i$ U9 \9 a" r1 k2008064 SIP_LAYOUT SHAPE Hotfix 048 (QIR 7): Shape creates void for same net cline, it should be shorted, r" d: s+ q9 x8 v8 H6 `
1980967 SYSTEM_CAPTURE CANVAS_EDIT System Capture does not reflect part symbol changes
* Y3 o) W( Y9 C1988928 SYSTEM_CAPTURE CANVAS_EDIT Changing version 2 of the resistor part makes the PART_NUMBER property visible
* V0 V: P0 j5 T! e! C( z: M) m/ L1990215 SYSTEM_CAPTURE CANVAS_EDIT Draw Multiple Bits: Bits do not follow mouse smoothly" c% @4 T0 f4 w: K& f6 N+ @
1972658 SYSTEM_CAPTURE EXPORT_PCB Modified injected properties do not get updated in the pstchip.dat file after running Part Manager and Export Physical
7 C8 y! I2 |/ V5 X9 C; j1989421 SYSTEM_CAPTURE EXPORT_PCB Part Manager does not update the PTF values
" t b9 a/ \* z5 q+ _" q% ~, a1992407 SYSTEM_CAPTURE PART_MANAGER Part Manager removes part properties and main window and details window updates are inconsistent
! L4 C/ X9 G% B+ \ ?5 F; W/ U3 s9 ?
) F7 P; U0 t$ w* A: ~ @
Fixed CCRs: SPB 17.2 HF048
2 r! p+ c6 y% w8 b' X. k5 [3 @10-13-2018
) T& C. n1 v0 B, N: W/ X& _3 ]- A========================================================================================================================================================# X3 Q M7 t+ v# G7 A
CCRID Product ProductLevel2 Title
9 W; M4 Z$ u6 Z========================================================================================================================================================
& w, J% ]' {* O4 i/ _6 G% G: t1913039 ADW ADWSERVER EDM Library Server exits with error message on starting library server service+ X% G! C! ]) ?; D. _) N' ?
1709155 ADW COMPONENT_BRO Search query does not search for all the parts in the library
Y, d9 z H' {" c1827231 ADW COMPONENT_BRO Clicking the 'a' key in Part Manager launched from DE-HDL crashes DE-HDL
7 B# h6 t; Y) v! a, E1903818 ADW COMPONENT_BRO Parts that have comment_body do not display version9 v# _8 a. `- Q! c: _1 b$ {
1917961 ADW COMPONENT_BRO Component Browser PPL column values are truncated when selecting the top '*' filter+ c! S( u, i' G8 }- Q+ c4 \2 I, w2 g8 c
1938172 ADW COMPONENT_BRO Symbol version with COMMENT_BODY set to TRUE cannot be instantiated
! p/ F7 v" g4 v. f) @# g( _, b1914103 ADW CONF conf creates incorrect path in fetch_dump.ini when MLR is enabled.8 x2 G( { ]( U. a, A
1911422 ADW DBADMIN RuleP101 - PACK_TYPE check against schematic model not working
$ v5 @9 ?& F' c4 ] M1926691 ADW DBEDITOR Adding a new classification and immediately trying to delete it results in errors- y! Z7 t! I% L
1926694 ADW DBEDITOR Renaming a classification and then renaming it back to the original results in error
1 ^2 E$ O N8 d1934870 ADW DBEDITOR Adding a new classification and immediately trying to delete it results in errors
) `/ r6 |7 n ^- O1872387 ADW DSN_MIGRATION Design Migration does not cache all used parts into flatlib/part_table.ptf# d; b- M2 I0 s# H. ~
1254292 ADW FLOW_MGR Flow Manager Open Last Project should open last project closed/ k/ Q+ B9 l' h/ v
1281817 ADW FLOW_MGR '-proj' switch in 'pcbdw_fm' does not work; launches Flow Manager without loading any project+ D- q' j6 T$ ~, w( d+ E
1727286 ADW FLOW_MGR Product options for PCB SI and Power Integrity are incorrect in the flow and tool launchers
& T" I- Z! Y5 Z1875498 ADW FLOW_MGR EDM fails to open or becomes unresponsive.
9 D3 f: ^. N$ a* r* z+ f: O1879386 ADW FLOW_MGR Unable to access COS with the default Firefox version in the 17.2 installation
7 E( |4 q+ s2 g; ~: G ]4 o1922541 ADW FLOW_MGR Warning message for unavailability of Java version appears on opening a project on Linux- d! g9 Z% n! Y
1945451 ADW FLOW_MGR Checklist does not work with two-byte characters
6 U6 s2 U+ S4 S2 ?" h& t1956213 ADW FLOW_MGR Not able to invoke Flow Manager on the remote system% r5 D3 ]$ x- I2 i
1892285 ADW LIBDISTRIBUTI Symbol not consistently available in 16.6 ADW Library* l. z( f, v' A# ?
1961731 ADW LIBIMPORT libimport fails to create tar for two Capture models% f f4 R3 W& O
1836620 ADW LRM Library Revision Manager crashes on clicking Help( g" J9 |) [7 ]
1961845 ADW PART_BROWSER Error regarding environment variable
: p- L9 H4 _' [: A1 x1890782 ADW TDA Launching TDO dashboard connected to PLM returns a license error
5 T0 K. v c d9 M; w1980914 ADW TDA Cannot start Design Entry HDL and Component Browser in a TDO design
6 G' |, a2 v) T% c% @1833750 ALLEGRO_EDITOR 3D_CANVAS Soldermask Text is not shown in 3D Canvas
+ {( E( r: V {2 V4 u- h4 x1891230 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas Viewer not bending PCB with proper radius# }7 Q3 n" L) U' C) @, a
1913338 ALLEGRO_EDITOR 3D_CANVAS STEP models missing from exported .stp file! F0 E4 Q7 X! E% p7 X9 J* r
1927507 ALLEGRO_EDITOR 3D_CANVAS Get Error: All bend operations are disabled due to licensing and/or DLL installation issues on invoking 3D Canvas
7 X& M2 {0 g% c- c7 P8 m1931508 ALLEGRO_EDITOR 3D_CANVAS Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas0 v% i6 o8 r* r# J4 c3 w
1943060 ALLEGRO_EDITOR 3D_CANVAS Placebound bottom is not showing correctly.
8 v" Z2 D, G F9 @4 p7 j9 g. s1950099 ALLEGRO_EDITOR 3D_CANVAS Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas! \- w: E2 h3 P
1988307 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
3 x9 S& p" `5 j7 V( Q8 e4 I5 i1923585 ALLEGRO_EDITOR ARTWORK Additional unwanted subclasses appear in film control when a new film definition is added: j7 X8 A% v3 @+ p6 J
1944079 ALLEGRO_EDITOR COLOR Export of Board Parameters (Net Colors) does not contain entries for nets with spaces
7 ^3 S$ w- U1 A3 R+ _1856320 ALLEGRO_EDITOR DATABASE Donut pad fails to connect with cross-hatched shape in full contact thermal mode, despite hatch overlap of donut.
% Y5 f9 C7 S0 [1912313 ALLEGRO_EDITOR DATABASE Database corrupted during background process
6 ]/ {; _$ d. t* `3 U; Z$ ^7 k1913344 ALLEGRO_EDITOR DATABASE When changing accuracy of design, the thermal relief for donut pad's outer pad connects to inner pad
0 N! B; o, C$ U% O- h, K$ T/ i1914470 ALLEGRO_EDITOR DATABASE Release 17.2-2016: export libraries command does not inherit posi/nega information8 L+ m3 J# P+ \/ }8 K3 M
1932086 ALLEGRO_EDITOR DATABASE Unable to resolve DBDoctor error
' ]- ?+ u% ? S2 D- x9 F6 `1963932 ALLEGRO_EDITOR DATABASE DB Doctor is not recognizing placed parts and showing them as unplaced.
" y/ R* N6 H* n0 s1987735 ALLEGRO_EDITOR DATABASE Interior sub-lamination backdrill holes are displayed with Top Soldermask pads where backdrill does not exist$ b, ^% c3 h% ~4 P1 ?& |
1977622 ALLEGRO_EDITOR DFM Not able to add value '5' or multiples of 5 in in DFF constraints for maximum stacked via count
0 q1 F1 K, A6 c/ [( V7 Y* H8 z1892809 ALLEGRO_EDITOR DRC_CONSTR NODRC_ETCH_OUTSIDE_KEEPIN property is not working on TEXT; L; h+ _ X! w
1894765 ALLEGRO_EDITOR DRC_CONSTR DRC for no_drc_component_board_overlap is not created if the place bound is outside Place Keepin
$ Y# W+ d' R; j# n8 B1896627 ALLEGRO_EDITOR DRC_CONSTR Moving components takes long time while doing placement
. v7 G! {6 x- i ]# V7 v& p, S1914591 ALLEGRO_EDITOR DRC_CONSTR Spacing constraints for Mechanical to Hole shows resolved constraints different from the actual air-gap/space
/ A, H7 e5 O% A1 f5 h+ [% B1956468 ALLEGRO_EDITOR DRC_CONSTR DRC getting generated while moving the uvia and getting removed after updating DRC.
- V. b4 U* W+ e7 j1884149 ALLEGRO_EDITOR EDIT_ETCH Arced Routing of differential pair creates unexpected arc radii
* n# }$ u( E8 ~' _1891985 ALLEGRO_EDITOR EDIT_ETCH Etch edit does not follow the constraints" v5 V( O4 K& F& ]& C
1860056 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes on right-click after choosing the Move command. u8 U9 v& L: ?0 P# r
1860723 ALLEGRO_EDITOR GRAPHICS APD crashes on right-click when using the Move command
9 o0 Y V# u0 z1870058 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes when using Place Manual -H command0 X8 X# h9 _! I! s1 h
1930282 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes on executing axlVisibleDesign(nil) from allegro.ilinit3 c% }4 p6 U/ @, x7 F
1882813 ALLEGRO_EDITOR INTERACTIV Unable to set the end point with 'snap pick to' when adding an arc
% |7 W( g7 m4 y5 S4 j1884725 ALLEGRO_EDITOR INTERACTIV Edit and Move vertex operation not working as desired1 @6 u; X( q& b" D& p' ? z4 q
1902359 ALLEGRO_EDITOR INTERACTIV Connector boundary remains ON for a layer if visibility toggles in Shape Edit application mode2 A- u+ {, r7 _8 y$ V1 y, \" ?
1909004 ALLEGRO_EDITOR INTERACTIV Parameter description showing wrong for Padless Holes under Design Parameter Editor
4 o; L3 w6 k! z1912055 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes on Delete By Query - AutoSilkscreen - Find By Query
) g% ^& O8 H* O! y3 L+ |7 A: e1924503 ALLEGRO_EDITOR INTERACTIV Editing shape causes PCB Editor to crash7 F3 X$ h# \0 ~5 g! A7 ?* p
1929614 ALLEGRO_EDITOR INTERACTIV Unable to Place Via Array when Staggered ring is selected in Global Ring Parameters.6 e4 o, s, J {1 ~# Y6 I6 I
1938523 ALLEGRO_EDITOR INTERACTIV Change Shape Type message is same for dynamic and static shapes
% X, x y- l* J4 Y) G1940827 ALLEGRO_EDITOR INTERACTIV Irrelevant/incorrect warning message when doing Edit- Change on Clines
+ b4 s% ]# P5 o1872653 ALLEGRO_EDITOR INTERFACES DXF export shows embedded layers in the layer configuration file! E1 r5 g- `# ?* H7 e
1873971 ALLEGRO_EDITOR INTERFACES IDX proposal comments are not shown when importing the IDX file into Allegro
: H( O$ ?" b* ^5 F" h/ v1892172 ALLEGRO_EDITOR INTERFACES STEP Package Mapping form needs to be larger
2 u- C9 t& b5 ~% j/ V1893311 ALLEGRO_EDITOR INTERFACES A line became two lines after import dxf
* F# C7 x6 S8 V2 a6 o2 x! b1937816 ALLEGRO_EDITOR INTERFACES Unit as % in Property Definition not supported by SubDrawing! g# }; o( e/ k. A' z9 q, I+ p M
1973084 ALLEGRO_EDITOR INTERFACES Physical library not placed if design and IDF database not matched while running! q1 B4 Y( |4 j: e3 R
1987526 ALLEGRO_EDITOR INTERFACES IDX import Fails to recognize SURFACE FINISHES Class' O; L' W3 X! g8 L) N# M
1872856 ALLEGRO_EDITOR IN_DESIGN_ANA Message displayed when creating directed groups needs to be improved
, \1 F* u# m" A1900832 ALLEGRO_EDITOR IN_DESIGN_ANA RTP: Return Path DRC does not check circle void correctly6 w2 x8 ]# G' y8 N/ E
1935641 ALLEGRO_EDITOR IN_DESIGN_ANA Return path DRC crashes PCB Editor, o2 u$ V. p! O% {2 Q2 ^1 u
1649465 ALLEGRO_EDITOR MANUFACT Manufacturing options are not visible in OrCAD PCB Designer legacy menu2 j6 E3 v' Z9 I
1873417 ALLEGRO_EDITOR MANUFACT Autosilk fails to add line information. Only part of the line is getting copied to the autosilk layer.
6 L) ]7 H; n+ G1911596 ALLEGRO_EDITOR MANUFACT Documentation Editor drill chart shows two different rows for the same slot.
- `" K- B: @9 B7 G1 E* i1937721 ALLEGRO_EDITOR MANUFACT Drill figure character scaled up in GERBER3 O- {, s$ _4 w* \1 r+ X- q
1957768 ALLEGRO_EDITOR MANUFACT Import IPC2581 on cross-section does not import line width and impedance
* n* v( [' w; x$ e& e y1969363 ALLEGRO_EDITOR MANUFACT Pressfit connector backdrill depth is considering MNC Layer
7 r1 D; G; s2 a1891102 ALLEGRO_EDITOR MULTI_USER Rejected by server error messages when using Symphony Team Design
) W) c* @# G6 C& Q' J1928082 ALLEGRO_EDITOR MULTI_USER Unknown SubClass BOUNDARY/MULTI_USER_LOCK automatically added when defining Artwork Output.5 R8 n u% x4 J4 M: r
1976705 ALLEGRO_EDITOR MULTI_USER Symphony client disconnects from server without any notification - despite ping mechanism' v7 `& X3 z1 Y) P
1972554 ALLEGRO_EDITOR NC Mill symbol moved from Nclegend-slots-1-2 to Nclegend-1-2 subclass if nc_param.txt not present
9 U, c" g. ~" C7 z* Z" \1914412 ALLEGRO_EDITOR OTHER Autosilk lines do not clear padstacks that are not rectangular
: Z) E% e% H' n' k- }* R w, s. e1921933 ALLEGRO_EDITOR PAD_EDITOR column clearance cannot reset to 0 in padstack editor
% y! a' ~6 p+ w k/ q1922234 ALLEGRO_EDITOR PAD_EDITOR DBDoctor reports 'illegal value for pad' and does not fix when zero corner radius for Rounded Rectangle is defined
: h Y# z( i* |0 S& w+ [8 i1932183 ALLEGRO_EDITOR PAD_EDITOR Drill Symbol information not exported in Padstack XML if Drill Figure in none. c2 z" Y4 N2 Q" {# U
1934880 ALLEGRO_EDITOR PAD_EDITOR Shapes with offsets not displaying properly in Padstack Editor views+ z( a; S; @; Y8 G0 K! Z, Z
1813270 ALLEGRO_EDITOR PLACEMENT When a place replicate module is updated, the vias used in thermal pad are removed) M: p% L) V z5 I, O
1840275 ALLEGRO_EDITOR PLACEMENT Placing component with the Mirror option causing display problems
2 \9 b4 z: C# c1 y1854099 ALLEGRO_EDITOR PLACEMENT Align components to zero spacing causing mirrored components to overlap
0 @/ r3 Y* S3 v: [7 n1 Q, v1854696 ALLEGRO_EDITOR PLACEMENT Pins shown incorrectly when the Alt Symbol and Mirror commands used consecutively
; k8 h+ d' Y- y' m) |5 B. ~) ^1862863 ALLEGRO_EDITOR PLACEMENT Too many messages in the command window when symbol does not support mirroring
) q: n. n! f7 U+ G. ~2 w1909857 ALLEGRO_EDITOR PLACEMENT Using Mirror with Alt Symbol placement displays incorrect graphics! w3 Y: E. ]4 ~, c8 O/ d2 u5 v
1917128 ALLEGRO_EDITOR PLACEMENT Place - Autoplace - Room when all the components of the room are placed on board causing crash1 g4 l- A& n E9 q
1925144 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding on using the Autoplace - Room command
* f- O6 m* ]7 F' R7 t5 J1961509 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes on choosing Place - Autoplace -Room& y# n; Q0 `/ k
1930669 ALLEGRO_EDITOR REPORTS Net 'VSS' not included in the Etch Length By Pin Pair Report
7 {* F. Z* m' i4 ^0 s1982934 ALLEGRO_EDITOR SCRIPTS PCB Editor stops responding if Generate button is used to create script from journal file7 ~7 }" b) I5 j( q
1337346 ALLEGRO_EDITOR SHAPE Shape Check is generating problem point errors that seem unnecessary: f+ c, R1 {% w+ i: w
1396692 ALLEGRO_EDITOR SHAPE Zcopy with expansion not following board outline
) W2 I% e& Y1 {+ t f7 S! p1902001 ALLEGRO_EDITOR SHAPE Shape behaving differently across hotfixes
% d5 b& _# K2 ^) C, S* `/ z: i8 {1921287 ALLEGRO_EDITOR SHAPE 3D canvas is showing some stray objects. E6 e( _. I7 R8 a: X
1936482 ALLEGRO_EDITOR SHAPE Option for Fillet to not obey NO_SHAPE_CONNECT Property
7 d8 u1 i% C! v1 I+ K/ h- L% N8 @& x2 V1943899 ALLEGRO_EDITOR SHAPE Only one Shape to Route Keep In DRC in release 17.2-2016 compared to two in release 16.62 O8 O, J2 M, Z3 h# O
1944041 ALLEGRO_EDITOR SHAPE shape_rki_autoclip makes shape voiding incorrect6 c3 g& b8 A5 k& a: x4 T! j Z
1947675 ALLEGRO_EDITOR SHAPE Shape void error when dv_squarecorners is enabled
# w7 h. J1 X z" M$ `/ X% p1949250 ALLEGRO_EDITOR SHAPE Shapes are filled even after raising and lowering priority
+ X2 a9 X1 ~9 b" q3 V6 b1 Y4 z1984526 ALLEGRO_EDITOR SHAPE Same net shape voided is inconsistent with respect to vias/ N# T( {! \. |! u9 S- A
1984955 ALLEGRO_EDITOR SHAPE Dynamic shape creating same net spacing drcs.- a+ b. |+ L9 s5 E- v; ^+ s2 ?* k
1839147 ALLEGRO_EDITOR SKILL axlDBGetLength() reports that the segments of a filled rectangle shape are invalid database ID arguments& q" W8 Q8 o# a
1882776 ALLEGRO_EDITOR SKILL SKILL documentation for axlIsBetween() is wrong
d/ ?4 _5 K% O# i; Z5 V6 `/ C2 Y' S. L1882882 ALLEGRO_EDITOR SKILL Example for axlMathConstants needs correction in Allegro SKILL Reference0 |4 h4 [ Q, z4 W Q, w
1902712 ALLEGRO_EDITOR SKILL axlAltSymbolReplace moves symbol to the top of design while replacing: Z% s! r! z. o5 R8 T' C) R# d
1906329 ALLEGRO_EDITOR SYMBOL Mechanical Pin to Conductor property set on a pin in a symbol does not pass to the board7 a; s5 V' m8 l+ ~$ D9 \
1911343 ALLEGRO_EDITOR UI_FORMS Global Visibility not turning all layers off
E1 }. f+ h2 Z# j8 u0 z0 }% O5 ]1985584 ALLEGRO_EDITOR UI_FORMS Import logic changes the Current Working Directory
- i- y2 G) n- c+ k1987829 ALLEGRO_EDITOR UI_FORMS Import logic changes the current working directory
: R0 \( Y# W# i) s1992722 ALLEGRO_EDITOR UI_FORMS After netlist import process, the board file is changing its current path
' L) q& ?' H) y- m" G7 c8 H% |% u1697506 ALLEGRO_EDITOR UI_GENERAL Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-20166 q1 J# O7 \8 v' d# p
1702631 ALLEGRO_EDITOR UI_GENERAL Etch Length by Net report does not list correct net name for nets in a bus
& x' o# ]% b8 I! c1703105 ALLEGRO_EDITOR UI_GENERAL Bus net names are incorrect in reports when using the allegro_html_qt variable
* _- [ ?2 u3 K1770786 ALLEGRO_EDITOR UI_GENERAL Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-2016
; \4 v2 N& L: H0 g" Q2 o: I4 b1784938 ALLEGRO_EDITOR UI_GENERAL Etch Length by Net report does not show net names with angle brackets in release 17.2-2016
6 g! ^; g1 n0 l0 L1822557 ALLEGRO_EDITOR UI_GENERAL axlUIWCloseAll is not closing text window in release 17.2-20161 g$ X) K/ `( ~& S. ~. A
1836400 ALLEGRO_EDITOR UI_GENERAL Net names are truncated in HTML reports) `& D7 t4 T# ]
1869879 ALLEGRO_EDITOR UI_GENERAL Links not working in the Net loop report
% D4 {1 {# k8 N- Y; ]1895878 ALLEGRO_EDITOR UI_GENERAL axlUIWClose()/axlUIWCloseAll() functions do not work when allegro_html_qt setting is enabled.$ D i1 z$ e' K2 f( F
1912282 ALLEGRO_EDITOR UI_GENERAL PCB Editor exits with error message on editing objects
% a2 j3 C# C3 B2 u& d1913962 ALLEGRO_EDITOR UI_GENERAL PCB Editor toolbars change on choosing View - UI Settings - Save Settings and then restarting
" m; q- N" W; V. u- L' w6 q1933172 APD UI_GENERAL Cannot paste text into the command prompt without clicking when 'enable_command_window_history' is set
8 H- E: T& p* W1843712 CAPTURE NETGROUPS Signals shown only for first segment of NetGroup3 J( p8 W9 e0 i( [0 Z2 t
1917768 CAPTURE NEW_SYM_EDITO Missing package pin overview in Symbol editor
) \5 M' ~, ?( S9 M; y6 P1920088 CAPTURE NEW_SYM_EDITO Package view missing in the new Symbol Editor
; y( `2 f. q9 A1922196 CAPTURE NEW_SYM_EDITO Snap to grid issue in Symbol editor& W1 H- C) M L
1927268 CAPTURE NEW_SYM_EDITO View Package is grayed out in release 17.2-2016, hotfix 038 and later versions
0 |' [- }% k8 ^1928012 CAPTURE NEW_SYM_EDITO In new Symbol Editor, View - Package is grayed out
' |5 P1 A$ {; L- Z7 x& y. g4 _' ]1930865 CAPTURE NEW_SYM_EDITO View Package missing in hotfix 038
. s0 v/ Z7 A6 `4 h, m$ Y' j1938507 CAPTURE NEW_SYM_EDITO Issues with new Symbol Editor: Justification and spreadsheet usability
2 }4 a: [5 y( t% Y0 u, L1940869 CAPTURE NEW_SYM_EDITO Missing pins in 'Edit Pins of All Section' table view for 4k resolution but not in 2k resolution& R* j+ l' \6 o4 c
1940888 CAPTURE NEW_SYM_EDITO Copying pins from a part and pasting on different parts not working properly.
$ |* T5 @6 S+ Y z1 U! j1942994 CAPTURE NEW_SYM_EDITO Cut / Paste of object in New Part / Symbol editor always pastes on grid& @ m9 B4 ?9 ^$ j- A" T' {
1944396 CAPTURE NEW_SYM_EDITO JavaScript error while copying from 'Edit Pins of All Sections'5 f6 r& Y9 w5 N
1950224 CAPTURE NEW_SYM_EDITO Cyrillic alphabets are not displayed properly on Schematic.
5 h, D; q! j5 D1951369 CAPTURE NEW_SYM_EDITO Cancel closes Symbol Editor5 q ^. ^3 m" u }
1966785 CAPTURE NEW_SYM_EDITO Edit Part is grayed out
, E" ?( c5 ^4 N/ ?) c1973135 CAPTURE NEW_SYM_EDITO Issue with new Symbol Editor: cannot copy-paste pins
* _( ^5 H3 c* m5 T+ z' G1973344 CAPTURE NEW_SYM_EDITO JavaScript error on opening part from design; ]+ \ ]( f& A! ?
1974122 CAPTURE NEW_SYM_EDITO Cannot copy-paste all pin list on the new Symbol Editor
* e. p1 M1 M) A* o: u1983593 CAPTURE NEW_SYM_EDITO Script error on copying and pasting to property sheet
# Z6 X8 d; s: }* {' A2 j: F1929692 CAPTURE OPTIONS PACK_SHORT issues with Pin Numbers that contain letters/alphabets! G" E/ c: D5 g- v! {
1876939 CAPTURE OTHER Incorrect Capture renaming error (ORCAP-1310)
4 r$ N" [* D" g, `1916090 CAPTURE OTHER Incorrect error message when 'save as' fails due to long directory path
- A# o' T9 O1 Z3 }8 n; {1921927 CAPTURE OTHER Two functions are mapped to Shift + R in OrCAD Capture in hotfix 038 I# U2 a2 I/ x
1946453 CAPTURE OTHER Shift+R shortcut is assigned to two functions.
5 j: k/ K1 f3 h# {3 ]* ^. j( r1965456 CAPTURE OTHER Shortcut Shift + R is not opening the Independent Sources dialog box
4 h2 k3 u6 S3 @' K1968757 CAPTURE OTHER Close CIP is grayed when right-clicking on the tab in Capture.: w$ \' u) t% }2 _) T. Z
1938437 CAPTURE PART_EDITOR OrCAD Capture new Symbol Editor Pin Type missing in table
& C0 I$ W' q/ ~! x1 E1906757 CAPTURE SCHEMATICS Intersheet reference is overlapping with the offpage connector name4 Q8 U; a7 ~* g6 L( Z
1867016 CAPTURE SCHEMATIC_EDI Part placeholders not being positioned when moved% Y3 B. H. _& ^- d: o8 D/ v
1932837 CAPTURE SCHEMATIC_EDI Parameters graphics are not correctly positioned# o3 k3 \4 {4 Y7 _# |, Q3 L* [# ?
1949518 CAPTURE SCHEMATIC_EDI Getting error when comparing designs
' X/ L' C. _9 F! z; k+ t$ L6 ~2 W1967545 CAPTURE SCHEMATIC_EDI Only section A of heterogeneous part being placed and not sections B, C, or D3 S. e+ v, ~# U
1933919 CIS DBC_CFG_WIZAR New CIS Configuration .dbc file created in release 17.2-2016 shows release 16.3
: E6 z/ P$ \6 l" r; P( f+ Y1932550 CIS RELATIONAL_DB VIEW NAME in Relational Database configuration is not working as expected.
7 {, t( N p0 ^6 l. D1832524 CONCEPT_HDL CHECKPLUS Default checkplus rules show body height of 0 (sym_2 of the attached cell). This causes the cell to fail verification.
- s$ y7 X5 R* Y1912023 CONCEPT_HDL CHECKPLUS signalWidth predicate does not recognize SIG[1..0] as bus.( `! n1 z/ \8 ^' b5 k/ I4 W5 `! ^
1966120 CONCEPT_HDL COPY_PROJECT Copying release 17.2-2016 project results in message stating the project is of an older version( P* p, p7 X7 q2 }
1879425 CONCEPT_HDL CORE Adding signals with the right-click menu is not following the defined color scheme
. R& N+ q6 D: A2 h3 _7 ~4 d1890542 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1911) when running export physical with backannotation1 G7 ~) n! O% Y% W" d% Z% h1 h
1907684 CONCEPT_HDL CORE Moving symbol makes canvas unresponsive for a long time
) Q' v) \2 p- t8 R1920711 CONCEPT_HDL CORE Pin names changes when mirroring the swapped section.
8 ?# c' Y% W, F' A: k1931421 CONCEPT_HDL CORE On Linux, 'cpmaccess -read' returns incorrect value
! G! S, T( S N/ m& w1931782 CONCEPT_HDL CORE Setting DONT_FORCE_ORIGIN_ONGRID to ON does not work for sig_name
. A4 g1 B, C* t: U6 n( p' M1932433 CONCEPT_HDL CORE _movetogrid causes signal disconnection/ z5 R: U3 n( q n
1946993 CONCEPT_HDL CORE DE-HDL Part Manager fails to update parts on schematic if new KEY properties exist in PTF but not in schematic) k: w4 Q" l& `, X R
1947029 CONCEPT_HDL CORE Design Entry HDL Font Support not working for signal rename
; m4 m8 r7 n* m9 D1962865 CONCEPT_HDL CORE Schematic symbol creation with '-' as pin name not packaging# T% K4 v+ `% q7 g
1966805 CONCEPT_HDL CORE Issues with packaging design containing cells named with a leading underscore8 I( B* g6 N# [ I$ F$ c
1967760 CONCEPT_HDL CORE DE-HDL crashes on moving Net Group/Port in release 17.2-2016, hotfix 044- i, `% h* p: K8 G0 ~3 P; t
1968282 CONCEPT_HDL CORE DE-HDL Part Manager fails to update parts on schematic when new KEY properties exist in PTF and not in schematic3 s ^9 t8 @; e, u
1972815 CONCEPT_HDL CORE Part Manager not updating missing key attributes from the ptf file by using 'Update instances' option5 T& N' _# _9 l
1887790 CONCEPT_HDL CREFER CRefer links not working in selected cpm file% b6 |$ t- E" c
1898535 CONCEPT_HDL INTERFACE_DES Global Navigation window does not reflect removal of a net on page2 that is part of a netgroup on page11 a/ x. |1 `) L3 J
1888048 CONCEPT_HDL PDF Japanese characters are not output correctly to PDF on Linux.
! n; M$ X( Q& z* v1937505 CONCEPT_HDL PDF Missing intersection dot in schematic PDF- C7 ]9 Q: s' P! a( I5 X
1942486 CONSTRAINT_MGR CONCEPT_HDL CM crashes when you save after importing a TCF file
& \0 `- N" q7 i1983743 CONSTRAINT_MGR CONCEPT_HDL Region Class-Class members are being duplicated in CM in the current session2 M' o, U! M+ }3 r% L: F+ K. g
1906573 CONSTRAINT_MGR ECS_APPLY Database corrupt and DBDoctor reports illegal database pointer error
6 ?' u- D# ]7 J1913805 CONSTRAINT_MGR OTHER Setting environmental variable CM_PARTIAL_DCF in release 17.2-2016 causing crash3 X6 F1 P5 Q* ^: r0 ` q9 j
1914813 CONSTRAINT_MGR OTHER C++ Runtime error and non-recoverable crash in class-class worksheet
1 R) n9 V H5 Y7 z+ }1920142 CONSTRAINT_MGR OTHER Xnet names are not consistent in the design3 ~0 S# H& Q/ U! Y
1898549 CONSTRAINT_MGR SCHEM_FTB Importing netlist causing crash in release 17.2-2016, hotfix 036
3 M, @" G7 t" Y* ]& R9 i) R1814851 CONSTRAINT_MGR UI_FORMS Field solver /DRC check running forever
' Y0 L$ ^9 s* n# @1889862 CONSTRAINT_MGR UI_FORMS PCB Editor hangs while assigning net voltages in CM
4 H+ A) V% c1 y( ~) w1965470 CONSTRAINT_MGR UI_FORMS Constraint Manager GUI Issue in release 17.2-2016, hotfix 039: Font size small and rows/columns in shrink mode' L5 I1 M( W, S: ^3 ?' L0 Y7 S
1945406 ECW ADMINISTRATIO Tree view was not refreshed soon after changing the site permission.
$ H6 K8 {7 |, u, G1826848 ECW METRICS SPDWECW-551 and SPDWECW-553 should be warnings, not errors+ `' v* i0 n4 \; c% s2 c6 J
1933373 ECW PROJECT_MANAG ecwbatch does not accept password and does not ignore invalid users0 u3 [$ x& c7 T; K; h1 s |
1921502 F2B PACKAGERXL Errors on running Export Physical:SPCOPK-1138 and SPCOPK-1149
. S! |- R# A; W1929846 F2B PACKAGERXL PackagerXL is still creating the pstcmbc.dat file on a release 16.6 design uprevved to release 17.2-2016# c% E8 J. B0 ?2 p2 ^
1953780 F2B PACKAGERXL Updated subdesign package information not updated on the top-level design in the reuse flow8 c6 c1 L4 c9 e' a
1971738 F2B PACKAGERXL Deleting blank space from pstxnet.dat file crashing DE-HDL
& ^* W# V( i$ [: K J. u7 q1891002 INSTALLATION DOWNLOAD_MGR Issue with Download Manager (Change Preferences Option does not Work)
; Y. N! @; P% O+ L- b' A1972890 ORBITIO OTHER OrbitIO-APR failed to run if PCB design included$ o2 T4 u5 g/ B) f: J& v
1954262 PCB_LIBRARIAN CORE Footprint model check in fails with verification checks failed error
( ]* b# o5 M+ F) C3 @1943656 PCB_LIBRARIAN GRAPHICAL_EDI Symbol Editor is blank if .ascii file is newer than .css file
0 D! I- M7 L, ^& b2 z1897887 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Inconsistent symbol results when adding vector pins in Part Developer
z. K1 X U. y% A) o& B: J% t1898003 PCB_LIBRARIAN SYMBOL_EDITOR Issue with Page Border Symbol
$ }7 k, F8 _: }1842007 PSPICE LIBRARIES Change required in swit_reg.lib
/ j X8 t/ X) d9 i$ K9 X, m1906922 PSPICE LIBRARIES Mismatch in mapping of IC pins in model and PSpice template for analog device AD8138
7 T& b. R4 K/ g3 h1947586 PSPICE LIBRARIES Update the model AD8138/AD in ANLG_DEV.OLB
! _) h9 ` h( G/ D, q1 ]0 [1748470 PSPICE MATLAB PSpice displays an error when sending current in co-simulation
' r) u+ z5 Y3 {' u# J. g3 m1802455 PSPICE MATLAB Incorrect current direction for pins in SLPS flow
8 R. h0 p+ w) z$ d0 o+ b1852811 PSPICE MATLAB ORPSIM-2604 being reported in SLPS simulation
% R# X* Y \) z& g1858716 PSPICE MATLAB Co-Simulation fails if 'RC' is used as reference of resistor% ?6 Z9 ?4 a0 I8 P
1921641 PSPICE MODELEDITOR Model Editor in Client Server installation slow to invoke K) P0 _; v* r! m
1922160 PSPICE MODELING_APPS New Capture Associate Symbol GUI not reading libraries; ^2 H1 I7 d+ ]# c
1843698 PSPICE PROBE PSpice icons appear very small on a specific computer
6 c% d; n' b" E1773841 PSPICE SIMULATOR orSimSetup64 crashes when running the simulation for attached design3 j/ y7 y9 |& I2 g
1816316 PSPICE SIMULATOR Simulation stuck; however, the status bar is correctly updated during Pseudo Transient Analysis
" O+ @- E+ D3 q7 m6 O F: l" W1887119 SCM IMPORTS Cannot selectively update changes in VDD
- J" E+ k- ^- {8 u& @5 t5 v R" _1889362 SCM IMPORTS Cannot selectively update changes in Visual Design Differences- e( s0 N, _5 |* _* t
1958545 SCM SETUP Auto assign models does not work in SCM same way as in DE-HDL1 ^7 r$ q( K, Z- x
1988841 SIG_EXPLORER INTERACTIV SigXplorer stops responding or crashes in hotfix 047 when a design is saved
; l! z. c9 A6 j* I5 G1988943 SIG_EXPLORER INTERACTIV SigXplorer crashes on selecting Update Constraint Manager
9 ^! B6 i: }" F. w4 s% x1991375 SIG_EXPLORER INTERACTIV SigXplorer crashes when clicking Save
2 p* ^* F" w" R* u! t, i1993749 SIG_EXPLORER INTERACTIV SigXplorer crashes on saving topology! k* A2 \3 ^& G# V0 k& _
1969975 SIG_INTEGRITY GUI Model Browser edits model above the one that is selected8 C3 L/ m/ _* H2 |
1953184 SIP_LAYOUT IMPORT_DATA Sub Drawing not saving dashed lines
0 G3 y5 R: e3 u1913864 SIP_LAYOUT ORBITIO_IF SiP Layout design import results in wrong die rotation
. y* J* l# m) X# j" C8 _1880237 SIP_LAYOUT PADSTACK_EDIT Background Window comes to the forefront when closing the Padstack editor
1 ^4 Y7 ?8 Q4 L' H5 c& t' Z! e1972560 SIP_LAYOUT STREAM_IF GDS Export fidelity issue: inverted arcs3 X- X( |# o7 c: C
1920317 SIP_LAYOUT THIEVING Thieving pattern does not allow for OOPS operation% G( U; t- S% @) T" Z
1909075 SYSTEMSI DOC SystemSI PBA channel and circuit simulations do not respond if bit pattern is 1s or 0s
+ k. x# _5 ? d& T$ y0 W; Q1916101 SYSTEMSI DOC Lack of stimulus in file causes Serial Link Analysis to become unresponsive+ w; n6 W, p3 Y- l3 ~2 [* O
1919562 SYSTEMSI ENG_PBA SystemSI generates wrong timing bathtub curves in channel simulations for write and read6 [4 O: K+ j5 }3 W7 x
1964064 SYSTEMSI GUI_PBA Able to sweep AMI parameters in SSI-PBA
) Y- u8 b Q& R4 e2 O1971266 SYSTEMSI GUI_PBA MCP header shows only 49 ckt nodes instead of 52 for s52p S-parameter file
) j8 V/ h7 @: q6 D' j9 l f8 [1885625 SYSTEMSI GUI_SLA Manage AMI + DLL from Setup Analysis Window
$ {( _; \ G1 f1924382 SYSTEMSI GUI_SLA Data Rate field in SystemSI Stimulus property form is confusing for PAM4 operation0 y) Z! k7 s4 L. D" f& w, ^
1982341 SYSTEM_CAPTURE CANVAS_EDIT Signal rename does not maintain new signal name value
6 `9 e% B: q8 v* W6 u0 _. Z4 t1976857 SYSTEM_CAPTURE CONSTRAINT_MA System Capture-CM Match Group Creation is not updating correctly6 L. h/ a) B4 p
1929606 SYSTEM_CAPTURE DESIGN_CORRUP Opening design causes System Capture to crash4 ~4 o4 E9 l0 j& M: L; q, c$ h; ?) C- v/ }
1914697 SYSTEM_CAPTURE DRC Overlapping component DRC does not work
( Y d# Y) L D3 N1 \) o! S1973467 SYSTEM_CAPTURE IMPORT_PCB System Capture Import Physical shows many component and physical differences on a design that is synced up) s) y! k+ E% y) g7 D
1962603 SYSTEM_CAPTURE NAVLINKS Ability to not underline hyperlinks for Navigation Link values
6 [- _$ b: c% K8 W1967639 SYSTEM_CAPTURE PART_MANAGER Part Manager does not open in System Capture for part property value changes even after setting the cpm directive.
5 S( v' N% i5 C7 `1 Z+ I; d1964388 SYSTEM_CAPTURE SMART_PDF Some shapes are not visible in the smart PDF schematics
) d$ a6 p- b9 T( O+ S+ X1976832 SYSTEM_CAPTURE TDO Rolling Back local lower-block requires check-out of higher-level packaged & variant views( Y) e; v, C* ^
1976844 SYSTEM_CAPTURE TDO CM - TDO check-out dependencies are broken
3 \6 n- M. w; p7 P1 g4 |% ]1976859 SYSTEM_CAPTURE TDO Variant Editor in System Capture -TDO allows to delete a variant without checking out variants view$ t% g1 ^# e0 G/ R: F$ T
1839816 TDA CORE All the design objects are locked in the EDM dashboard after a DSFrame error
1 b1 V9 a E/ {) _5 `7 D4 J) i1889898 TDA CORE Cannot check in the top level of the project in TDO
8 m5 M9 r8 Y7 j3 W# Y+ W1892411 TDA CORE Unable to undo the block checkout if something fails6 {4 s( s3 v+ E% N" H+ s3 G
1877757 TDA DEHDL Refresh Hierarchy does not show latest TDO lock/unlock status in DE-HDL
* z" o" `; S* D5 j# u4 h5 `# g0 R* E3 ]( H7 H" g
8 p* l$ t, i; g' j, N* `0 _
Fixed CCRs: SPB 17.2 HF0474 C" v0 T/ R+ p, @* A
09-9-2018
2 g: O/ b1 }& s7 i4 k. C1 p- p# |) F========================================================================================================================================================( H& _8 @2 O" y1 c3 b2 d
CCRID Product ProductLevel2 Title+ o+ ]. p9 u5 n; c/ N
======================================================================================================================================================== ^+ ~% n* k6 o+ M
1969527 ADW LIBIMPORT Getting java.lang.NullPointerException error on bulk import in hotfix 0441 {; y# x y6 l+ S+ H! N
1976219 ALLEGRO_EDITOR DATABASE .SAV file not created although message states it is created# u" p. E: H `# P$ J
1968270 ALLEGRO_EDITOR DFM PCB Editor crashes when running DRC
! {( _/ W; m/ {5 d# Z1978421 ALLEGRO_EDITOR DRC_CONSTR False DRCs between via and its fillet shown after editing shape boundary; A$ x. K5 ^( n9 V( r% j6 ^( [
1966772 ALLEGRO_EDITOR PAD_EDITOR PCB Editor and DBDoctor crash on editing DRA file: Found bad pointer, run dbdoctor
$ j' a# N+ }8 j* O1 {5 B1973866 ALLEGRO_EDITOR SHAPE PCB Editor crashes when deleting a group
- d8 z f5 H A/ k1818779 ALLEGRO_EDITOR UI_FORMS Dialog box goes behind main window on clicking PCB Editor canvas( }3 j5 Z* e/ i' [8 n, V
1880175 ALLEGRO_EDITOR UI_GENERAL Multiple sessions of PCB Editor gets mixed up in Linux in release 17.2-2016
6 I- p4 `. F+ P5 K% r) ^' t1946027 ALLEGRO_EDITOR UI_GENERAL Arrow Keys in Canvas stop responding after changing the view.
# K/ t; c+ `& p2 E* y1967701 ALLEGRO_EDITOR UI_GENERAL Arrow Key panning does not work when third-party SKILL call is active
9 A- t6 I# @+ g x3 X' R- ]' k& D' }1967706 ALLEGRO_EDITOR UI_GENERAL Observe Special Characters when command is run% q7 e- u; M4 ~0 x2 |, t; h
1971183 ALLEGRO_EDITOR UI_GENERAL Focus is lost from command line when Save icon is used
* ]2 B9 l9 P* C7 Y1971186 ALLEGRO_EDITOR UI_GENERAL Focus from Command line is lost when using CTRL + N7 A) }$ e3 m" W& r
1971190 ALLEGRO_EDITOR UI_GENERAL Focus from Command line is lost when using CTRL + Alt: ` h, S( |# Z' `
1971200 ALLEGRO_EDITOR UI_GENERAL Focus is lost in comand line when you save using command save9 j+ n5 z |, a, r$ P. S
1961833 APD SHAPE Crash when changing dimension of existing via padstack in the design' ?, [ T* Z& _% B" U
1968256 ASDA EXPORT_PCB SDA crashes directly after Export to PCB
. n2 G4 z! w c; f7 l6 F. f1970284 ASDA EXPORT_PCB Placing part crashes SDA
+ A3 P: Q- j' D' T9 x/ T
% k( k! e3 \& p' B) }4 U$ n; T% H3 u+ F8 ~4 i& M) m+ H" B% ^. T& K
Fixed CCRs: SPB 17.2 HF046# X5 ~, b2 G9 ?, [( a( j
08-24-2018
% K1 h7 K! O8 _5 P# D5 _6 ]3 N% n3 u========================================================================================================================================================% L, q! N3 Z; M/ |* P y. X; ^' E
CCRID Product ProductLevel2 Title, U. M0 Y* p1 A& B
========================================================================================================================================================
/ s: Y% L8 E w" M- T( k4 ?* B1880800 ADW PART_BROWSER Server connection failure on a running SDA session.4 }9 p5 D; B: Q- V! h4 y
1880895 ADW PART_BROWSER NCB - components missing from the component browser
9 K! `' u( U/ w1 }2 J1962336 ALLEGRO_EDITOR INTERFACES Smart PDF shows both top and bottom probe layers for a film layer with only a single probe layer (top or bottom)
$ G/ D( x, q; N r5 _1955128 ALLEGRO_EDITOR MANUFACT Need to close PCB Editor to delete xsectionChart.log generated on placing a cross-section chart
1 |& A' i. ^) |0 d1969088 ALLEGRO_EDITOR SHAPE PCB Editor crashes on updating shapes to smooth
; H( v' @; }+ X1963828 ASDA DESIGN_EXPLOR Unwired schematic block movement with text is not correct8 N( ~7 ^4 B" n5 O8 D+ f" ^
1954426 ASDA OPEN_CLOSE_PR Double-clicking to paste a note crashes SDA& }3 c3 I8 d6 D! m! A0 _+ q
1965423 ASDA OPEN_CLOSE_PR Crash when working with notes in SDA. C G X8 R( |4 b
1960060 ASDA PART_MANAGER Original property differences not displayed in Part Manager on selecting a new part from CB and doing reset8 r, W) z+ T5 p
1960112 ASDA PART_MANAGER Part Manager incorrectly updating part property values, \; Y+ r% y& M9 l/ z
1955723 ASDA ROUTING Draw Multiple Bits misses bit 0 when in reverse order.
4 X4 O+ _6 M+ M6 |1952963 CONCEPT_HDL CORE Variant Editor takes a long time to load
& x3 P) E! D' S& n) V1962568 CONCEPT_HDL CORE Directive DEHDL_BROWSER_FILEPATH does not work8 c. W& H" @* X D: n* Y% v
1939192 PCB_LIBRARIAN SYMBOL_EDITOR pin_text size and location very different between DE-HDL and Symbol Editor resulting in text overlap% I# { j, i! w6 a
1952967 SCM OTHER Error while copying a release 17.2-2016 design: message says design created in release 16.3 or an earlier version$ L, g" z( q' C9 S
1948999 SPIF OTHER Some place_keepout shapes and antipads not exported
7 m% O5 [ [/ z9 M! E5 @7 e: z
/ _5 \% \+ {$ r! v; x/ e: d4 y
6 S! s9 v. i# O4 PFixed CCRs: SPB 17.2 HF045
- C8 |3 \' k3 @+ L& e3 }4 I- \0 _: z/ p08-10-2018. ^6 G6 G* |- \" y6 x# W
========================================================================================================================================================5 B6 g0 Q, G+ Q/ c! p
CCRID Product ProductLevel2 Title
; ^9 u0 E9 ?; B; j) @========================================================================================================================================================0 H# U8 x+ Y+ Z
1934956 ADW DBEDITOR Footprint missing from part in release 17.2-2016
* _) Y& E7 P g. A) F1945005 ADW DSN_MIGRATION Right side of Migration dialog box is cut off5 \. E+ d' K+ E9 a5 p
1933245 ADW FLOW_MGR 'Open last Project' button should open the last opened project
: l" Z" V5 W. O: t1953210 ADW LIBDISTRIBUTI Library Distribution is not distributing all symbols. No errors for the missing schematic models.
* k6 q- R7 O, J1953727 ADW LRM LRM missing two symbols when migrating from release 16.6 to 17.2-2016- f2 @- r$ e5 M2 w/ x1 n, h
1952923 ALLEGRO_EDITOR DATABASE PCB Editor crashes on trying to delete layer
2 d+ e6 X- D0 S2 t& H1957171 ALLEGRO_EDITOR DATABASE Pastemask offset not working when creating a symbol that requires two top-paste masks5 |( _5 x/ {; O0 M* N
1960059 ALLEGRO_EDITOR DATABASE Stackup definition causes custom script to crash
& X2 @" Q/ h3 q" P. ]1932864 ALLEGRO_EDITOR DFM Exporting DFM Constraints losing the association to design level+ j: c2 x! ~) b0 }$ u+ w7 A3 @
1957467 ALLEGRO_EDITOR EDIT_SHAPE Compose Shape copies lines to wrong subclass
9 S& A; X2 l2 Y! F0 y* `7 p, ~1938536 ALLEGRO_EDITOR GRAPHICS Multiple crashes on different boards after installing hotfix 040; i/ y* \% H5 a+ `7 _9 N, m
1954075 ALLEGRO_EDITOR SHAPE Dynamic Crosshatch shapes should be clipped inside RKI if RKI Autoclip is enabled* P( w! n; ^- ]+ ?
1957803 ALLEGRO_EDITOR SHAPE Wrong dynamic shape status3 D) s6 ^1 i: c2 x
1949923 ALLEGRO_EDITOR UI_GENERAL Focus lost from command window when any command is active) H" [2 j/ i& U& m
1963245 ALLEGRO_EDITOR UI_GENERAL Alias behaves as Funckey in release 17.2-2016, hotfix 044: J. G, a" T: |0 @
1892126 ALLEGRO_PROD_TOOLB CORE Clines disappear and then reappear suddenly on using Route - Shield Generator5 V j$ _! Y0 T& A* i8 ^" @
1931127 ALLEGRO_PROD_TOOLB CORE ZDRC not working for Xhatch Shape
- q4 Q3 E1 e4 r9 d, B( W7 v* V9 [1932563 ALLEGRO_PROD_TOOLB CORE allegro_legacy_board_outline environment variable not set in PCB Design Compare.
# m" H* j( W) x: i* y1929855 ALLEGRO_PROD_TOOLB OTHERS Outline not exported correctly for PCB design compare if Design_Outline and Cutout exist, ?1 o8 | d( E; v2 f4 H
1956494 APD DATABASE DBDoctor removes pads
7 A; D' X; l7 Z4 A( ^! |& e1956291 APD INTERACTIVE axlSpreadsheetSetStyleProp should accept 0 and 1 as Boolean values for protection style- d( U. ^. A; o' R. I Q
1960127 ASDA ARCHIVER Using the Tcl command 'archiveproject' crashes SDA
# b) H* B. ~: M: e0 D! d1953718 ASDA CONSTRAINT_MA SDA Import Pin Delay fails with extra columns, does not explain why5 N, x5 A A9 ~$ N7 ]
1924498 CAPTURE SCHEMATIC_EDI Cannot place part 'B' for heterogeneous part if 'Preferences - Miscellaneous - Auto References' not set- o9 \6 I4 T2 B& L
1927129 CAPTURE SCHEMATIC_EDI unable to place heterogeneous part section directly from place part window& y% w# ]! [% \" R4 }: M
1928255 CAPTURE SCHEMATIC_EDI Unable to place a specific section from Place Part5 c' q5 M5 b* j' P3 E
1945207 CAPTURE SCHEMATIC_EDI Part selection pull-down reverts to part '1|A' when placing heterogeneous part
5 G6 q/ P) j( d: d* K3 {" i1945661 CAPTURE SCHEMATIC_EDI Section drop-down in Place Part window is not working4 k8 M; {% F# N" `& U) N) Q
1958121 CAPTURE SCHEMATIC_EDI Preview and placement of sections of Heterogeneous parts is not correct in New Symbol Editor
5 x( G$ W ?" J- k# M1956535 CONCEPT_HDL CORE DE-HDL crashes on Import Pin Delay for a CSV file
4 I% {/ o( {: S) t2 q3 k' _; x1960922 CONCEPT_HDL CORE DE-HDL crashes on moving netgroup on Windows 10+ q* O2 ^2 n7 ]# a( L. D! _
1964016 CONCEPT_HDL CORE In DE-HDL moving around nets connected to Netgroups causes crash on Windows 10
H" ?. j1 b# {, |5 j' a9 b1907040 F2B PACKAGERXL Export Physical output board file name reverts to old when changing options# `4 ~+ H2 F t+ o# L5 u
1957862 ORBITIO ALLEGRO_SIP_I allegro2orbit failed to translate rounded rectangle padstack+ s0 U' h" V$ w' Q( e* n" M5 z
: n' y1 {7 W4 f; z# E
8 a& |% u0 a( _2 u, RFixed CCRs: SPB 17.2 HF044- ?* x- a7 n" g
07-27-20187 A7 S. o( X( D, U
========================================================================================================================================================
: Z& W/ c5 \: v( Q; m* x; ZCCRID Product ProductLevel2 Title& p- m$ V9 F; c; e
========================================================================================================================================================( \+ o$ O# x! }- a; `9 e4 [( p) c. h
1943727 ADW DBEDITOR EDM DBEditor: Cannot check in/out schematic model symbols with many linked parts
0 a9 O9 L0 \0 F/ x0 ^6 Z, r1800630 ADW FLOW_MGR Support spaces in design directory path on Windows4 w; }: }; V$ o( o7 d
1951052 ADW LRM LRM stops responding on project update and removes parts from design
3 X% M5 s4 l+ l# K% K1891428 ADW PART_MANAGER Resistor turns into a capacitor when placed. N3 `3 x9 H1 E$ p
1945194 ALLEGRO_EDITOR 3D_CANVAS 3D Viewer crashes when opening from board file.
% A2 H) x0 {& b' n0 ~- ]2 r) V. S1935558 ALLEGRO_EDITOR INTERFACES Exported STEP file missing components when viewed in free STEP viewer
4 `3 u6 \6 T1 z+ ~1 }: U% A1945640 ALLEGRO_EDITOR MULTI_USER Symphony client disconnects from server without any notification
- g$ x7 T! D, k4 ]; }1948454 ALLEGRO_EDITOR MULTI_USER Window DRC stops responding when run in Symphony
! [6 D$ m7 U( }! a) ]4 t1946619 ALLEGRO_EDITOR SHAPE Pin/via with suppressed pad on shape layer and thermal connection type of none should void to drill hole.
V) ?9 V4 F+ ^" K, B1946708 ALLEGRO_EDITOR SHAPE Same net hole to shape voiding is incorrect.2 \8 a G9 V5 o* U
1952213 ALLEGRO_EDITOR SHAPE Shape voiding from Thru Via when the via regular pad is not completely drilled out by Backdrill hole is not consistent
' n- V! V9 J. t; E1889433 ALLEGRO_EDITOR UI_GENERAL Command window shows result at the end of a command rather than showing dynamic updates3 B, @0 X1 ~0 x* {+ |
1933503 ALLEGRO_EDITOR UI_GENERAL Extra click required to enable command window7 I9 e& O! e, H; w+ j* a; x0 L
1943692 ALLEGRO_EDITOR UI_GENERAL Funckey commands are not working% u% d6 a' s6 s, X$ i+ K: p
1945914 ALLEGRO_EDITOR UI_GENERAL Mouse focus lost in the command console when doing an 'undo' from the toolbar icon) c. k9 U4 C4 n
1945920 ALLEGRO_EDITOR UI_GENERAL Focus lost from command window when the toolbar is used for any operation3 U- x. i% \' O" q L
1949922 ALLEGRO_EDITOR UI_GENERAL Focus lost from command window after save or even autosave; _+ d4 j# P5 B, |/ n4 \/ V+ \3 A
1947551 ALLEGRO_EDITOR WIREBOND PCB Editor crashes in wirebond edit mode( H4 K5 ~# o1 z! @7 f
1935722 ALLEGRO_PROD_TOOLB OTHERS Panelization: Cannot place parts after migrating design from release 16.6 to 17.2-2016# `, I: O% m4 U5 z K
1951511 APD REPORTS The result of Metal Usage Report is incorrect.
; z( }0 S) }* ^8 |/ a/ d s% U1952942 ASDA GRAPHICS Need metric (mm) support in grids in SDA
) Y* |9 b2 G7 Z$ W1948122 ASDA TDO If user ID has uppercase characters in teamassignmenttemplate.xml, TDO fails to join a project
- v, I9 a. m3 v8 w6 L. b5 R8 v7 ?1931199 CONCEPT_HDL COPY_PROJECT Stop hard coding Copy Project license inside EDM
) n- b6 @4 h: o6 M& ?/ S- _! f1938153 CONCEPT_HDL OTHER Component Browser stops responding on replacing and modifying components) G! _2 \- R3 x
1770601 CONCEPT_HDL PDF Wire Pattern set to two-dot chain line not shown in PDF
8 A4 B, S2 w+ t1791175 PCB_LIBRARIAN CORE Allow baseline of cells with pins at symbol origin: change error to warning, t% b1 M. X. G
1922238 PCB_LIBRARIAN CORE Unable to check in into EDM Server due to con2con error SPLBPD-323 - Origin on pin connection point1 {: ]9 n& @0 a* Z( Z$ x8 s& m
1936812 PCB_LIBRARIAN GRAPHICAL_EDI New Symbol Editor: Wrong text being updated when editing text after copy and paste$ ]6 g0 e, I2 M8 p" R8 E
1804159 PCB_LIBRARIAN SYMBOL_EDITOR Copy and paste of pins in new symbol editor: issues with pin name, rotation, and move% n2 W9 q/ C! _7 T( `: P/ {
1927422 PCB_LIBRARIAN SYMBOL_EDITOR Symbol outline not updated correctly in the new default graphic editor in Part Developer release 17.2-2016
% n; `* T2 j' A/ S1939272 PCB_LIBRARIAN SYMBOL_EDITOR Symbol Editor changes origin to bottom left, outline to invisible, shows rectangle with center rectangle at new origin2 K7 i" Q9 {" b& m: }/ a
1928076 RF_PCB DISCRETE_LIBX dlibx2iff does not work with managed libraries and library-level PTF: a% W9 H/ e- v8 P0 _
1929574 RF_PCB DISCRETE_LIBX Discrete Library to third-party Translator does not populate the Available Parts section correctly' `! m. w- x+ k
1850360 TDA CORE TDO crashes while changing the root design
+ S$ L9 J! j* M0 k5 g- g1934388 TDA SDA SDA TDO crashes on attempting to check in a 'New Block in Shared Area'% y4 u- _/ R7 M- D
' K' c. T# }, _- k3 ?7 ^" A
, T- R% i: S! J1 M$ D$ t5 h5 Y6 vFixed CCRs: SPB 17.2 HF043
+ S% T8 Z {7 a7 @# K. ?07-13-20186 h: j+ x0 F; a; U3 ^
========================================================================================================================================================
; X) b& d; o; ~4 |7 l: j9 ]1 [CCRID Product ProductLevel2 Title P9 M) R9 i7 h, w4 `8 m
========================================================================================================================================================
% K0 y" C6 y! T" ]( W1935813 ADW DBEDITOR Auto merging of DE-HDL and Capture Classifications is not working; r7 x. w3 c5 g
1935834 ADW DBEDITOR Some DE-HDL only classifications are removed during the CSV merge process of libimport) x$ [0 ]: c& I, y: H
1941570 ALLEGRO_EDITOR DATABASE PCB Editor crashes or stops responding on performing 'Info' or 'edit properties' on select pins$ \2 H7 C' n3 q/ }4 u
1942536 ALLEGRO_EDITOR DATABASE Allegro PCB Editor fails to create backdrill plunges in Zone area# \* o% A8 G* F. c
1925899 ALLEGRO_EDITOR DFM PCB Editor crashes when placing components in Hotfix 039
) W* n z% I, |, W+ |1 w1943113 ALLEGRO_EDITOR DFM Restore normal move/slide via performance when annular ring checking is enabled.5 x, ^/ O$ N; ~; \& C# H# s
1940939 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashed on running the Gloss - Line and via cleanup tool
3 ~4 l' x5 P/ k( e: J1937754 ALLEGRO_EDITOR GRAPHICS Text string disappears when selected during 'Edit - Text' if using PCB_CURSOR
* f/ f/ J! t+ E/ X+ A1937056 ALLEGRO_EDITOR INTERFACES Cannot import IDX acceptance of third-party change to PCB Editor
/ y9 y2 l4 \* G1 H7 L0 n# |1940197 ALLEGRO_EDITOR INTERFACES PCB Editor crashes when reading IDX file from third-party
; O6 ^8 i* _: c8 j! V; q1940232 ALLEGRO_EDITOR IN_DESIGN_ANA PCB Editor crashes when running Return path DRC) j5 m2 N8 \# g0 ~
1916921 ALLEGRO_EDITOR PLACEMENT Property Pin_Global_Fiducial not inherited from symbol into board
: y! S4 @& L) q8 ~1 q- j1862241 ALLEGRO_EDITOR REPORTS In 'Summary Drawing Report', the listed quantity for HDI vias is incorrect under Drilling Statistics! Y, G6 x$ H w( ~; s
1935448 ALLEGRO_EDITOR REPORTS Etch Detailed Length Report lists only one coordinate pair per trace
& ~ c* w! G) I( V. K d1948322 ALLEGRO_EDITOR SHAPE Allegro hangs when axlPolyOperation api is called! Z% x# S& e5 a2 k$ s
1795564 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, focus is lost from command window after right-click
; q9 w, [% I' G. h& E1919247 ALLEGRO_EDITOR UI_GENERAL Infinite cursor graphics issues on move: Cursor disappears and symbol image remains at old location till refresh
1 H1 ?4 P; O* _, A8 f1919256 ALLEGRO_EDITOR UI_GENERAL Infinite cursor graphics issue: Symbol disappears during rotate
+ y' o; L9 i- h6 O" y& o i1933526 ALLEGRO_EDITOR UI_GENERAL Panning is slow in PCB Editor in Hotfix 0388 C( m7 k( d; G- B2 `
1933530 ALLEGRO_EDITOR UI_GENERAL Strokes are slower to respond in release 17.2-2016
' }. o# B0 |: _9 ~2 o- R2 ]1933536 ALLEGRO_EDITOR UI_GENERAL Third-party dialog stops responding on running commands
# v; }' V { Z" o/ z1 I1782227 APD DIE_GENERATOR Ability to specify rectangular shapes in die text in
7 H2 K8 l% e. `2 P" y1933011 ASDA PART_MANAGER Parts changed in library with new pin names are not reported or updated by Part Manager
) k- a Z- i; U6 ]$ r1924529 CAPTURE NEW_SYM_EDITO Global colors for pin name and number and part body not allowed in release 17.2-2016, Hotfix 038/039
e/ e+ I2 J1 {& V9 Y% z5 f* ~1925846 CAPTURE NEW_SYM_EDITO Opening library or component with special characters in path throws JavaScript exception
. q2 ]" u2 `" T' D' R, h1928905 CAPTURE NEW_SYM_EDITO Pin name justification, length, and casing incorrect for generated parts in Hotfix 038
2 f s$ T7 l9 ^/ T1 ^1928965 CAPTURE NEW_SYM_EDITO Cannot move pins in Capture if Pin Name is missing
9 @# i a# G" {, m5 M1932149 CAPTURE NEW_SYM_EDITO JavaScript exception if path to part contains special characters in Hotfix 039) l5 h* g& f$ S. h: U+ v5 m
1936301 CAPTURE NEW_SYM_EDITO Cannot edit symbol in new symbol editor: Displays parsing error (SPSMI-1)
, v2 P* ^, K' h$ p+ q3 @% V1917172 CAPTURE PART_EDITOR Pin name rotating on schematic even when pin name rotate is off in symbol editor
. k n& \0 G' |# L9 S1924456 CAPTURE PART_EDITOR Color preferences for pin, pin name, and pin number do not apply in part editor but only in schematic7 b# ^1 y* }+ g; _, i
1928872 CAPTURE PART_EDITOR Pin name locations are wrong and each needs to be placed manually
% }( }" ?3 X* p6 m9 b. B1929562 CAPTURE PART_EDITOR Changing pin name while adding a pin not intuitive in Symbol Editor* c0 I- j% ?, S
1932732 CAPTURE PART_EDITOR Part Editor issue: Pin name selection box too long and text not justified in Hotfix 040
- Q1 ^3 j$ V- h2 \# s/ t% q! b/ Y1933523 CAPTURE PART_EDITOR Connection box does not appear after changing pin of a placed part in Hotfix 040 m5 a1 Z" _4 u0 T& Q- J
1936994 CAPTURE PART_EDITOR Error because of illegal characters in pin name and number and net name2 n: {, x# y8 c: h( O3 X
1943074 CAPTURE PART_EDITOR Pin names rotated in Part Editor not rotated when placed on page* N% O5 e# t# ?6 S0 G6 s
1943078 CAPTURE PART_EDITOR Pin name rotate not working.
; o: J% k$ n8 U! {1945055 CAPTURE PART_EDITOR Pin names not rotated in schematic
1 h. e( P) n2 I# O1925700 CAPTURE VIEWER Pin numbers and text not shown during Variant View mode anymore.7 Q' u/ @" `, e) N
1914437 CONSTRAINT_MGR CONCEPT_HDL Constraint Difference Report appears even though there is no difference in constraint." o8 C* R1 K9 A
1935152 CONSTRAINT_MGR CONCEPT_HDL Match Groups are not formed with the correct pin pairs
" X$ ^9 J. l" \2 s1940575 SIP_LAYOUT ORBITIO_IF Need new routing flow
! i! ^( y% Z2 ~7 S1923722 SIP_LAYOUT STREAM_IF Use one symbol for all instances of a Via Structure* u: \+ P- w0 ~
+ i& ?( |- f- X! @" r: N
& t3 u: s! g. ?7 U3 kFixed CCRs: SPB 17.2 HF0421 q0 \3 j! s/ A" Q
06-22-20186 Q$ C& h7 f& V B3 x- O
========================================================================================================================================================
. R# Y" A( c* L# h {* o3 y OCCRID Product ProductLevel2 Title1 x+ p3 o4 A y, L
========================================================================================================================================================
- u( p% `1 x* ]) h1922654 ALLEGRO_EDITOR ARTWORK Difference in board and Gerber display8 i' O1 |( g5 o: G! I
1932714 ALLEGRO_EDITOR COLOR Manufacturing subclass NCDRILL_FIGURE missing from Color Dialog when editing .dra file; l. h& _" T$ `( S, Q, a, k% S
1932316 ALLEGRO_EDITOR DFM DFM constraint reporting wrong DRC between backdrill via hole to shape clearance under copper spacing
4 k3 C3 b) b2 }6 f$ Y! Z1914334 ALLEGRO_EDITOR INTERFACES Design Compare does not import some netlists created using Export - Netlist with properties from PCB Editor+ | c1 r5 U* h1 m1 d
1910213 ALLEGRO_EDITOR MANUFACT OrCAD PCB Designer shows Backdrill Status in Check - Design Status
0 F- ]) i" [& ^9 P+ H6 A! |1933049 ALLEGRO_EDITOR MANUFACT NC Route seems to put all routed drills in the same .rou file regardless of what layer they are on./ J) r4 d* F0 L4 v$ F' i, u, M
1880576 ALLEGRO_EDITOR PLOTTING Extra lines appearing in plots that are mirrored
3 @( u" ^" T5 X1881031 ALLEGRO_EDITOR PLOTTING Plot Preview with the Mirror option in the Plot setup creates fancy lines on shapes
4 X; c' x; J0 K( k0 E r" t1908005 ALLEGRO_EDITOR PLOTTING Plotting with mirror options set results in strange lines on the plot( X" ]& k) ]0 ^/ \
1909530 ALLEGRO_EDITOR PLOTTING Use mirror function when plotting lines to design: b& T8 D- q0 ?+ l
1919405 ALLEGRO_EDITOR PLOTTING Printing with the mirror option results in arcs in Print Preview' U. B- s, c; D5 D. M' w$ [. x- |
1830419 ALLEGRO_EDITOR SCHEM_FTB Import Logic with 'Overwrite current constraints' deletes attributes from drawing
+ W5 v$ R v* E/ i; t. z4 ~1935253 ALLEGRO_EDITOR SHAPE Compose shape command causes tool to stop responding( _: t* ?) d7 z6 ?, ]6 A# A- H
1571600 ALLEGRO_EDITOR UI_GENERAL File - Capture Canvas Image missing in release 17.2-2016& c2 [8 _$ r& z4 Y" k' ~
1650403 ALLEGRO_EDITOR UI_GENERAL Include Capture Canvas Image command in Allegro PCB Editor release 17.2-2016' a# c* d% |+ c0 Z1 o7 { T: \
1710310 ALLEGRO_EDITOR UI_GENERAL 'Capture Canvas Image' command is absent from the file menu in PCB Editor in release 17.2-2016
8 A7 A: N6 y- ~1718407 ALLEGRO_EDITOR UI_GENERAL Reintroduce the Capture Canvas Image command: ^! x4 r5 \& s, N
1729699 ALLEGRO_EDITOR UI_GENERAL Capture Canvas Image is not present in release 17.2-2016
2 ~2 _1 @: Y9 h: Q K1753234 ALLEGRO_EDITOR UI_GENERAL Capture Canvas Image missing from the File menu
5 F+ \4 q4 z0 `0 z4 w5 x: o' u1754222 ALLEGRO_EDITOR UI_GENERAL Need command to capture view window as image in release 17.2-2016
1 U. Z# p# M9 s% U8 B1 }1794348 ALLEGRO_EDITOR UI_GENERAL Reintroduce Capture Canvas Image in PCB Editor in release 17.2-2016
6 W# {; ]. [, N8 Y1818610 ALLEGRO_EDITOR UI_GENERAL Restore the option to capture canvas image in PCB Editor in release 17.2-2016
4 K: |3 U, `8 s, e) D: H1844591 ALLEGRO_EDITOR UI_GENERAL Reintroduce 'Capture Canvas Image' in release 17.2-2016
$ ]) A; H( H( u: A3 c1869380 ALLEGRO_EDITOR UI_GENERAL File - Capture Canvas Image missing in release 17.2-2016
7 {, ]6 R3 P4 j2 K1889412 ALLEGRO_EDITOR UI_GENERAL Cross-probing between two boards in release 17.2-2016' w+ [* G+ }9 m b/ g
1922329 ALLEGRO_EDITOR UI_GENERAL Add the 'Capture Canvas Image' command in release 17.2-2016
; r# p3 u' n1 g$ b# j1932070 ALLEGRO_EDITOR UI_GENERAL File - Capture Canvas Image is missing in release 17.2-2016
' b+ {. y M* ]* h1885594 ASDA PACKAGER Export to PCB Layout exits without reporting error when Netrev fails- O: r, z( N1 m4 y, C
1931657 ASDA PACKAGER Export to PCB Editor does not work for a project
; T4 U1 k' u' g4 l1937757 ECW METRICS SDA metrics not getting collected5 t, A" ^5 l1 l* f: b' X7 Y+ x0 H
1934482 EMI SETUP EMControl function flow is not working correctly in release 17.2-2016
* i4 ^, p7 x S2 M1 B' K1931623 SIP_LAYOUT EDIT_ETCH Shapes are not updated and force update does not work. Y- U% G# c X& I' {( u y
# z+ b! S3 q# x1 ]
& r [6 p- C- J3 V+ E" D: s! mFixed CCRs: SPB 17.2 HF041* [1 @2 F! h& r& }
06-9-2018
) A- `- J( q; s3 X0 I7 B- J, e========================================================================================================================================================
' F# B% r# ^6 H cCCRID Product ProductLevel2 Title# s! L5 p& N- H2 x
========================================================================================================================================================
5 g2 i* i6 C) `( C- ?. t8 U/ |/ a1880083 ADW ADWSERVER ALM fails to connect and authenticate LDAP server2 h/ H0 z1 X" e+ G
1922218 ALLEGRO_EDITOR 3D_CANVAS PCB Editor stops responding when 3D Canvas is opened for a symbol# t: R+ A# X: J C0 }2 u4 l
1915838 ALLEGRO_EDITOR DFM Outline to non-signal geometry is not working for non-etch layers in design
3 n7 ~1 V* U! J$ }# x1925263 ALLEGRO_EDITOR DFM False minimum spoke count DRC
% `3 ^ W% \; z4 R1895486 ALLEGRO_EDITOR INTERFACES Importing IPF displays error regarding line being outside drawing extents (SPMHMF-409)) ^) E4 @* Z1 p2 `" _. {
1927266 ALLEGRO_EDITOR INTERFACES Miniaturization license required when using enterprise licenses
' X! j( i m$ L1 T- M7 |$ G1912186 ALLEGRO_EDITOR IN_DESIGN_ANA Coupling analysis on one net takes a long time) u s6 Y M" o3 f4 |* H- f
1916015 ALLEGRO_EDITOR NC Improve the message for reporting unsupported characters in the directory path while generating NC Drill data
( T5 o) R) }" a& G; F# x0 u1926072 ALLEGRO_EDITOR SHAPE Dynamic shape to route keepout not voiding correctly: b) H3 @) ]" S! X/ @3 b
1903202 ALLEGRO_EDITOR UI_GENERAL HTML report dialog does not handle relative links to files correctly
+ |0 q* L% X9 D' P( C2 @4 P$ d1880684 ALTM_TRANSLATOR CAPTURE Importing third-party schematic is not working in Capture. g% V7 a* U2 Z+ O% W2 t
1870218 ALTM_TRANSLATOR DE_HDL Unable to translate a third-party design to DE-HDL
5 T& K$ M+ j3 [/ C L c' m- t0 r: _1881208 ALTM_TRANSLATOR DE_HDL Third-party to DE-HDL translation: schematic symbols missing all pins
) @7 @& h2 K: b: \. H4 X/ {4 a1889909 ALTM_TRANSLATOR DE_HDL Third-party to DE-HDL and OrCAD Capture translator fails with error message or crash
$ W9 [1 Y0 ]$ m1924375 ASDA NEW_PROJECT SDA new project path truncated at ellipses
% C3 a8 n1 I E4 d3 ^6 h1900957 ASI_SI OTHER axlLicDefaultVersion() in SKILL console crashes PCB Editor in release 17.2-2016 and works in release 16.6 h$ U' A! p, m( i% @! r; ~ A" r& |
1918499 CAPTURE NEW_SYM_EDITO Text in new Part Editor is always left-justified and justification cannot be changed# g; i- z, u {; ^6 U& b
1921505 CAPTURE NEW_SYM_EDITO Error if property name starts with the less than character '<'" `9 _5 E; w6 `
1924273 CAPTURE NEW_SYM_EDITO Error if property name starts with the less than character '<'$ ~. q5 C9 |% O7 M1 D1 |
1924332 CAPTURE NEW_SYM_EDITO Capture reports an error when editing pin numbers where names contain the less than character '<' [* ]$ F1 V4 f6 I6 r
1934655 CAPTURE NEW_SYM_EDITO Properties populated in older release show up blank in new Symbol Editor
+ Z( O, l6 `: K/ H. F1855851 CAPTURE OTHER Crystal Reports not working in release 17.2-20169 I% I- M# H: g# L4 F
1918048 CAPTURE PART_EDITOR Unable to modify pin type and shapes for multiple pins simultaneously in new Part Editor. Q% c1 A# F& [
1919459 CAPTURE PART_EDITOR Part Editor background display color is not consistent when zoomed out/in
5 b. b4 m& {9 y) A, L1920078 CAPTURE PART_EDITOR Option needed for updating pin type of multiple pins in the 'Edit all pins' menu) `( l6 R; `3 j3 S5 T7 J
1922785 CAPTURE PART_EDITOR Cannot place pin array with zero in the suffix in Symbol Editor
& H4 x. X8 C( ^9 S1922831 CAPTURE PART_EDITOR Symbol Editor redraws when scrolling with non-default background and when zoomed out
# L" f. O4 ^, e7 f5 S& Q6 t7 ?1923772 CAPTURE PART_EDITOR Placing pin arrays results in error
7 V% {& N6 l' N: q/ D1888897 CAPTURE SCHEMATICS Capture slowly redraws schematic page+ S: t, m- o/ ]% x3 A
1910087 CONCEPT_HDL CORE DE-HDL crashes when adding Current Probe to a design
# P0 Y9 T; W+ I% b( |. }1 \7 D1930364 CONCEPT_HDL CORE SIGNAL_MODEL properties not deleted on importing release 16.6 DML design into release 17.2-2016 non-DML design
+ `' W. ]! X/ k* |/ H! H1920716 CONSTRAINT_MGR CONCEPT_HDL Issue with the passing of physical and spacing CSets between Design Entry HDL and PCB Editor
! k9 Y+ ~' R3 K9 |" `- M! \1902591 ECW OTHER Flow Manager reports a digital certificate error when launched with Pulse0 g4 ?1 U* S2 o, {
1926029 PCB_LIBRARIAN GRAPHICAL_EDI PDV Symbol Editor opens to a blank page in release 17.2-2016- D; M" T& m& m
1884694 PSPICE ENCRYPTION User-defined library encryption is not working as expected, t+ ` [* L$ d$ `/ @6 W
1927537 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes when running manufacturing checks on specific designs
* D- v {+ J+ ?1878733 SIP_LAYOUT CROSS_SECTION Layer Function and Manufacture fields in Cross-section Editor are grayed out for soldermask layers in SiP Layout: E( ]0 d6 s M' _2 f+ j' u& J4 N
1900628 SIP_LAYOUT CROSS_SECTION Board thickness in Cross-section Editor does not change even after soldermask layers are added, f/ ?7 J- v& N( r; a4 G6 O
% o$ {9 J; Y& `( [3 j5 _# l+ [) m7 _1 R8 J% H: z
Fixed CCRs: SPB 17.2 HF040
4 _* y$ q3 E# @% _1 V5 |, r05-27-2018
Y( S f H7 o========================================================================================================================================================$ ]5 V& x5 X4 J/ p, O6 D
CCRID Product ProductLevel2 Title% b* W' ?. L& D; s7 X
========================================================================================================================================================/ N3 i, R. L6 v3 y( u
1924541 ADW CONF Designer Server configuration cannot be completed1 g( ?9 \* o; |4 L6 W, `: ?6 T
1906973 ADW DBEDITOR Rename attribute fails to preserve values in affected parts
9 n+ Q3 ~1 t! y1718524 ADW FLOW_MGR FM: Find Projects does not find any projects when Project Path contains a period& c7 E3 w [3 |( R: c
1803310 ADW FLOW_MGR EDM Find Project no longer supports dot in the project path f2 t" C3 q% X6 g! b
1916898 ADW FLOW_MGR Flow Manager does not recognize projects with a dot in the path# Y) Y0 X5 U6 w, X* p8 e& E
1887669 ADW LIBDISTRIBUTI ptfgen displaying Java errors
]" S) m# }2 q7 T7 g: v3 x" w1897991 ADW LIBDISTRIBUTI ptfgen fails with error LIBDIST-1062 in library distribution.
+ D! ^# \7 M& Q" C2 i1915319 ADW LIBDISTRIBUTI ptfgen should rerun with the -rewrite2db option automatically! ?/ o% M+ _0 a# h: M& L3 m& m
1920309 ADW LIBDISTRIBUTI Java exceptions in the ptfgen log file
- O9 ?5 U: f. H1914706 ALLEGRO_EDITOR DFM False Mask to trace DRCs9 v! W6 v5 I7 s; W
1912290 ALLEGRO_EDITOR GRAPHICS Infinite PCB cursor: symbol move results in symbol trail and disappearance of cursor and symbol$ ^% {% d3 D* }5 ^! J3 U
1927425 ALLEGRO_EDITOR GRAPHICS Infinite PCB Cursor disappear while moving objects on layout4 X- u0 @% D5 z1 n2 o S1 C& y
1908867 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes in release 17.2-2016, Hotfix 036 and 0371 m: \( N/ D$ f9 P2 p
1906116 ALLEGRO_EDITOR IN_DESIGN_ANA Allegro Integrated Analysis and Checking: Coupling vision shows the influence of voltage net
# Q1 M* ]5 K* q1918161 ALLEGRO_EDITOR MULTI_USER Symphony crashing and clients disconnecting from server cannot leave session, error applying DBupdate
. f1 P3 G; P$ }1919467 ALLEGRO_EDITOR MULTI_USER Random crashes while routing design in Symphony5 I, {% y; o' u" H" E
1918702 ALLEGRO_EDITOR SHAPE Differential Pair vias not voided in a split plane* n6 b8 e4 ]0 `) o5 x3 \
1905109 ALLEGRO_EDITOR UI_GENERAL PCB Editor randomly stops responding in release 17.2-2016 in Linux
: p. b* C; \4 N0 v- O1882365 ASDA CANVAS_EDIT SDA - body changes but not properties when changing version of a symbol9 ^1 N: F( s Q, d& W
1900370 ASDA CANVAS_EDIT Version command in SDA should use placeholders from selected version
+ N0 B' V8 ]5 o3 G1901120 ASDA CANVAS_EDIT Choosing a different version of a placed component does not use the property placeholders as per the new symbol% ?3 ]. n: B% _2 F5 h$ u
1907497 ASDA GRAPHICS DNI Cross Mark much larger than Components6 B1 p% ]' k `7 }+ g, @# ^- P* ~
1895135 ASDA MISCELLANEOUS Design created in SDA has the cds.lib containing a pointer to worklib
, K/ n% t) |, ^ L9 S2 o j1895139 ASDA MISCELLANEOUS Irrelevant warning related to worklib when running checkplus on SDA design
' k& a4 G1 U/ ]. R9 n. g7 d1920753 CAPTURE LIBRARY JavaScript exception reported on opening part with name containing '\' in hotfix 038
( P4 u, c p; }+ a, F" P6 Q% n4 S1925848 CAPTURE LIBRARY New (QIR6) Symbol Editor has Script error / SR 600037969
6 B4 w; w! M3 h) k1916991 CAPTURE NEW_SYM_EDITO New part/symbol editor ignores grid color set in Preferences% s, `. F, a) X# \* s# t: T- c& [
1917090 CAPTURE NEW_SYM_EDITO New symbol editor goes into permanent pan mode on clicking the middle mouse button: J* T9 C! c' k6 \
1918041 CAPTURE NEW_SYM_EDITO Saves As for symbol in library from new symbol editor saving 0 byte files
+ f6 E) R+ r9 k: F' h8 `1918497 CAPTURE NEW_SYM_EDITO Moving multiple items using the arrow keys results in error in new part editor
& n9 {. L' E, \4 I+ G1918711 CAPTURE NEW_SYM_EDITO Unable to do a Save As from a Library part to change the name
# ?8 a, j4 j# c: e* |+ d/ s& `1920889 CAPTURE NEW_SYM_EDITO Unable to edit symbol with name containing '/'1 m% r, O& t" |! R
1922123 CAPTURE NEW_SYM_EDITO Save As for symbol in library from new symbol editor saving 0 byte files0 D9 @# N2 o* K4 N
1922276 CAPTURE NEW_SYM_EDITO Space between pin name and pin for names having bar- ~9 l& B9 K1 ]/ q! S& l5 x) e6 i
1922282 CAPTURE NEW_SYM_EDITO JavaScript exception on closing new part editor window using keyboard shortcuts
% n1 m q7 D8 b) A1923526 CAPTURE NEW_SYM_EDITO Unable to "Save As" in new symbol editor.% B+ D. c- n" e2 j2 X( h, Z4 |
1927262 CAPTURE NEW_SYM_EDITO The File > Save As command in version 17.2-s038 differs from earlier versions. a# c2 @& C3 |8 [. y
1919322 CAPTURE PART_EDITOR JavaScript exception on opening parts and creating new part using right-click
' {+ M2 X! P4 z' r: D1914183 CONSTRAINT_MGR XNET_DIFFPAIR ECSet fails to map in PCB Editor but maps fine in DE-HDL
u. ~# p9 N3 e9 `/ o: L3 c; p1908102 ECW DASHBOARD Some lines in Design Dashboard in Pulse are grayed out, _" D: `5 ~+ M. z0 x ]; K
1914812 F2B PACKAGERXL Hierarchical variable not evaluated
e3 y5 y* c& ^/ S% [8 J1639231 PSPICE ENVIRONMENT Remember last location in simulation settings
6 L+ F2 }3 L" Y! w9 ^3 o5 s* o1804391 PSPICE ENVIRONMENT Libraries with uppercase extension (.LIB) not retained if added using 'Add to Profile'1 C) p1 H, Q! x# w
1879915 PSPICE ENVIRONMENT Check points cannot be loaded from a directory with space in its name/ K( M) m% @+ n9 o, f: z# y
1695306 SIP_LAYOUT STREAM_IF SiP Layout - Stream out issue: Embedded or stacked components using pad reference in more than one layer
' @; [' M) K m& ? Y3 {7 m. t
% A9 W) U& P+ G8 g; u
6 y, P: n/ d& BFixed CCRs: SPB 17.2 HF039+ ~% D1 [2 w; x3 q/ e. S( N
05-11-2018
% x) `' G* {) N( q+ h h( z========================================================================================================================================================# G6 n8 ~( I1 u- c$ }8 O$ ?0 `
CCRID Product ProductLevel2 Title* N* ^5 F! j6 ?3 j4 b2 E1 N
========================================================================================================================================================: ~2 r0 Y7 f. d
1915149 ADV_PKG_ROUTER OTHER Auto-connect fails to initialize when rats are selected, but works with bundle0 d6 I: a+ c8 L9 x2 z' N6 g
1870109 ADW ADW_UPREV Most mandatory properties turned into optional properties following database uprev5 M* J2 s* }% T$ t% v/ ^
1758396 ADW CONF Server Memory setting in setting.ini is lost if server is re-configured using Conf
. l2 H# F4 D9 t) X% W7 c% X1911591 ADW FLOW_MGR Flow Manager does not start on high latency (> 25ms) networks: displays Java Content Disabled dialog
# y' K6 l% r: j: s' U2 s1887861 ADW LIBIMPORT Library Consolidation reports front2back issues but does not provide information about the issues.
0 ?& Z1 q7 y- E% _1778977 ADW REPORT_GENERA reportgen memory setting too high in release 17.2-2016 resulting in launch failure
4 g; A( ?9 f5 _$ `" _; S1900422 ADW REPORT_GENERA Save in reportgen does not save Preferred Part List entry into .rep file
' C6 l T- G" s4 X1 o" X+ {1903888 ADW REPORT_GENERA Report generator not outputting values as expected for PPL field
+ l/ c# O& L: P1916903 ADW REPORT_GENERA Reportgen -gui is not producing the expected result0 R! u$ P' s0 g! l9 _) Q6 X: A& i+ T
1902184 ALLEGRO_EDITOR DATABASE Add connect in package symbol crashes PCB Editor when using the 'clearance_view' variable
$ T$ V4 ?, b' z% Y( i7 S: W1914793 ALLEGRO_EDITOR DATABASE Updating shape crashes Allegro PCB Editor; m' t. u" ^- w, `- o# \8 G; Q
1905138 ALLEGRO_EDITOR DRC_CONSTR Max Via count DRC disappears on running DRC update. G! V* {* A& N' X
1848015 ALLEGRO_EDITOR MANUFACT Export Creo View cannot find the webpage on the PTC site
2 E/ u* P/ g* i( U+ c. Z# o1850553 ALLEGRO_EDITOR MANUFACT 'File - Export - Creo View' is not working
V8 W3 Y% k* d8 y2 t2 E1853960 ALLEGRO_EDITOR MANUFACT PTC Creo Interface link is broken: f% k0 _* e2 _$ Z; U
1862305 ALLEGRO_EDITOR MANUFACT PTC Creo interface link is not working
& P2 N. s$ E5 ?# ^# g1878682 ALLEGRO_EDITOR MULTI_USER Delay in Symphony server session when server is started from Allegro PCB Editor6 A. ~7 Z2 V2 g
1890108 ALLEGRO_EDITOR MULTI_USER Database rejections in Symphony
5 L5 N* g5 p; W1887331 ALLEGRO_EDITOR NC Milling (NC route) in Gerber tools is not the same as what it is in the board.
# d8 I3 r$ V2 ~3 B- h1898179 ALLEGRO_EDITOR RAVEL_CHECKS PCB High-Speed option required for high-speed rules when Venture license is selected
5 w, e! Y$ v# l8 `3 d9 V1461142 ALLEGRO_EDITOR SHAPE Pin with nearly-tangent via fails to generate void in dynamic shape, results in short.' {% h% Y5 C+ @; W6 g: s
1863467 ASDA CROSSPROBE Highlighting all parts in PCB Editor does not highlight all parts in SDA7 C7 |* R. g2 N* x4 [' p
1910974 ASDA CROSSPROBE Cross-probing between SDA and PCB Editor does not work" K6 I* g' K& v! T( K' n
1904440 CONCEPT_HDL CORE SPCOCD-577 error on migrating from release 16.6 to release 17.2-2016
& F! I C+ F- S: U# X \1909611 CONCEPT_HDL CORE DE-HDL stops responding on running '_movetogrid' and clicking 'No'
3 j6 M/ \8 h7 ?- m; @1808743 CONCEPT_HDL PDF Inconsistent display of Publish PDF hyperlinks
?2 r" r6 w" {6 g* n @1894868 CONCEPT_HDL PDF XREFs getting clipped in the Published PDF, O5 W8 r( j- Y7 K9 w
1911676 CONSTRAINT_MGR CONCEPT_HDL DE-HDL Constraint Manager crashes on selecting ECSet and then creating pin-pair option
0 |% k; t9 p7 x; k# B! X7 ^- G1913968 CONSTRAINT_MGR CONCEPT_HDL Match Group pin-pairs are not created on applying ECSet to differential pair
& x7 W* K7 f9 `, }1899638 CONSTRAINT_MGR XNET_DIFFPAIR Differential pair buffer models are extracted differently in release 17.2-2016 and release 16.6
0 W7 f2 v, z5 Y: P1914116 ORBITIO ALLEGRO_SIP_I Unable to import OrbitIO file to SiP Layout6 q$ F7 }, @8 a$ |0 A
1896487 PCB_LIBRARIAN GRAPHICAL_EDI Use lower-case characters for notes and pin text in New Symbol Editor
' Q/ c3 a- {9 e: I* E9 P1898008 PCB_LIBRARIAN SYMBOL_EDITOR Styling is not available for custom shape and pins.0 E( A, N& ^" h. ^7 `
1644787 PSPICE FRONTENDPLUGI PSpice Model Search window does not show complete library path
1 j8 n' w% V" ^* a1785939 PSPICE FRONTENDPLUGI PSpice Part Search library browser should display path of the library directories
) ]0 R3 S3 g/ t7 [+ M: Y& d1855867 PSPICE FRONTENDPLUGI PSpice Model Search window does not show complete library path
9 Y! c: v2 d' U% D; K5 I; Z1887016 PSPICE SIMULATOR Pseudotran should always be invoked first time in case autoconvergence is ON/ \4 [/ @) e- K0 ~( M* ?
1895752 SIG_INTEGRITY OTHER Layout Cross Section: Wrong Differential Impedance calculation (0 ohms) in RHEL Linux 7.1 or later versions
( f9 I; ^8 F* N" B9 g/ ?% C1895759 SIG_INTEGRITY OTHER Cross Section does not calculate correct differential pair impedance in Linux CENTOS 7 and gives 0 value
1 z% X& y; v4 G8 G" G6 Y4 ?2 Q9 G- S1909257 SIP_LAYOUT INTERACTIVE Error 'E- (SPMHGE-639): Copying component with bond wire is not allowed' when copying SMD symbols
; S( M1 V4 n! \! D* |4 T6 y f7 P1900970 SIP_LAYOUT SHAPE Shape does not void around SMD Pins and Vias inside pad3 x3 E: E2 L3 a9 `8 B C+ W+ s
1885496 SIP_LAYOUT SYMB_EDIT_APP Pin Numbering: different results for release 16.6 and 17.2-2016 for the same case.
! n6 L$ E7 [3 {4 A0 o. O2 m1907796 SIP_LAYOUT SYMB_EDIT_APP SKILL commands fail to change pin number in SiP Layout# ~0 A+ d" d7 t1 q5 U1 ?6 }2 a1 A
1887703 SIP_LAYOUT WIREBOND On trying to add wire bond to a die, SiP Layout crashes displaying a restart message5 ]$ |; p9 S/ h) a/ A. ~
1903081 SPECCTRA LICENSING PCB Router is failing in Linux 7.1 in release 17.2-2016
7 L! q8 Q& ?8 S, E% L7 \1721606 SPECCTRA ROUTE PCB Router stops responding on exit if opened in the stand-alone mode) |* y" s5 M, Q" X
1844366 SPECCTRA ROUTE Allegro PCB Router will not exit# g% J2 d& A# A
1873716 SPECCTRA ROUTE PCB Router does not close if opened from Allegro PCB Editor or in the stand-alone mode
. n; Z# i+ d* g" [8 }/ n' y+ F1907703 SPIF OTHER PCB Editor crashes on choosing 'File - Export - Router' in release 17.2-2016& Q5 c h% Z# h
1889059 VSDP DIEEXPORT Incorrect pin location if bump cell origin is not at lower left for rotation other than R0
% r) b' f Y3 N6 h/ o
z- ]9 f& d$ M5 P% N
# D0 p8 U: p2 VFixed CCRs: SPB 17.2 HF038
1 s: _; L0 o$ W5 }* f/ ~9 H04-27-2018
! F" i7 j( @) ^% A6 |" w========================================================================================================================================================
8 M) d6 h6 j2 x$ m, |, a) qCCRID Product ProductLevel2 Title% O# I& }$ ^1 ?: l# F8 o: M
========================================================================================================================================================9 u& d4 Z! ^6 [5 f
1861616 ADW TDO-SHAREPOIN Team Design Option requires Allegro_ECAD_Collab_Workbench license feature
- w/ D% f: A z7 H, f1784170 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Canvas does not show the flex zone thickness correctly
. Q8 _" a [8 V5 b0 W) k; x1801053 ALLEGRO_EDITOR 3D_CANVAS Moving component in 3D Canvas does not move the pads
3 I' y6 m1 ^8 k: \6 Q1805038 ALLEGRO_EDITOR 3D_CANVAS Soldermask and drill not refreshed when component is moved in 3D Canvas, or on the board with Canvas open" f& U. Y& K& c7 J
1808579 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas displays annular ring incorrectly) G/ M; Q. o& E/ o" B5 j
1816732 ALLEGRO_EDITOR 3D_CANVAS Mismatch in shape width between board and 3D Canvas
8 X$ V5 y/ p* x9 N$ u) t+ [' n1822778 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas does not display nets when selection is done through click drag
9 e% L/ `* p: z: X. H7 c1838129 ALLEGRO_EDITOR 3D_CANVAS User is not able to create a pastemask layer that is visible in 3D Canvas
- S/ f% p9 A3 A- ]0 t x7 e1 q1842911 ALLEGRO_EDITOR 3D_CANVAS Etch shapes not visible in the 3D Canvas when invoked from a symbol drawing& L4 b/ ?7 ~1 Y2 j1 T
1849380 ALLEGRO_EDITOR 3D_CANVAS Mirrored components placed in flex zones are not displayed in the 3D Canvas
: H6 e' g1 f, G( y8 w1851898 ALLEGRO_EDITOR 3D_CANVAS STL export from 3D Viewer scales it up by 100
+ D) `, t2 F# N3 s( N6 z1853378 ALLEGRO_EDITOR 3D_CANVAS The new interactive 3D Canvas has a display issue with the off-centered drills.6 e. [$ H4 ~2 Y2 A9 H0 g+ I
1859713 ALLEGRO_EDITOR 3D_CANVAS PLACE_BOUND shape with package_height_max and package_height_min set displayed incorrectly in 3D Canvas
( }( l9 c6 t( k/ R; |- J9 g/ \7 p1880073 ALLEGRO_EDITOR 3D_CANVAS Design Outline is not displayed correctly in 3D Canvas
) }( |6 W9 m4 G3 c& a$ A1880338 ALLEGRO_EDITOR 3D_CANVAS Step Model missing in interactive 3D canvas.7 M9 N3 |. y2 z! ?
1881889 ALLEGRO_EDITOR 3D_CANVAS Changing the color of STEP model in STEP Mapping Window does not display this color in 3D Canvas.
$ e+ v6 v7 @2 k8 d1889861 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas swaps padstack from Bottom to Top( e3 m$ R$ X/ g2 R% H1 _ D7 M
1830749 ALLEGRO_EDITOR ARTWORK Gerber 4x and 6x output do not fill the shape
; S% a. h- e9 O, D1848514 ALLEGRO_EDITOR COLOR axlVisibleDesign does not interact with wirebonds7 R) o& [$ T# l0 x' }$ J
1837388 ALLEGRO_EDITOR CROSS_SECTION Cannot add solder mask to the site layer mask file
8 m7 \9 w8 X O6 ~3 Q! z* h3 x1859797 ALLEGRO_EDITOR CROSS_SECTION The Report only option does not work when choosing Setup - Cross-section - Import - IPC2581
+ P' y6 s$ E* z; m( S1877858 ALLEGRO_EDITOR CROSS_SECTION Dynamic Pads Suppression option is not working correctly
0 D6 Z- }, I6 I! H. b1880093 ALLEGRO_EDITOR CROSS_SECTION Unused Pad Suppression options are not working correctly and are reset on opening cross-section
6 I7 ^- N6 n- t9 s1886283 ALLEGRO_EDITOR CROSS_SECTION Unable to turn on 'Dynamic Unused Pads Suppression'
1 y5 R+ [2 ]0 Z x- m$ Y1890959 ALLEGRO_EDITOR CROSS_SECTION Dynamic Pads Suppression option is not working correctly
; M; L- l8 F# |. D1900397 ALLEGRO_EDITOR CROSS_SECTION Dynamic Unused Pad Suppression option in Cross-section not working at one go.
8 b7 v; Y9 n: w" y% ~: f1905315 ALLEGRO_EDITOR CROSS_SECTION 'Dynamic Unused Pad Suppression' cannot be turned on." g& o7 [0 y7 [0 C
1861406 ALLEGRO_EDITOR DATABASE Refresh symbol for flex zone not mapping padstack layers correctly
( x0 x0 {$ j3 i/ E* H+ w, \% s1877132 ALLEGRO_EDITOR DATABASE Fail to open #Taaaaed17598.tmp file and save database. ]8 N5 j1 T5 c& `$ d* E
1883747 ALLEGRO_EDITOR DATABASE PCB Editor crashes on stackup modification
4 g: `+ o* a8 i2 p1860238 ALLEGRO_EDITOR DFM Applying a DFF constraint set closes PCB Editor instantly
% C4 f& |. {# f( i( V1 Y1872780 ALLEGRO_EDITOR DFM DFF false pin to via DRCs: Copper Spacing, SMD pin Pad to Thru Via pad5 }5 [" d! g2 H8 k
1823912 ALLEGRO_EDITOR DRC_CONSTR Thru pin to Thru pin DRC between Symbol Pin to Mechanical Hole (with NO regular pad)% d! S5 t2 L+ c
1828168 ALLEGRO_EDITOR DRC_CONSTR Upgrading from release 16.3 to 17.2-2016: Differences in spacing constraints
/ a0 [$ n& |# {1 n" | q7 }8 O% J1844780 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to Shape Air Gap value is reduced when updating shape
6 A6 b# q, v* d% H$ ~1845011 ALLEGRO_EDITOR DRC_CONSTR When upgrading from 16.6 to 17.2, Spacing constraints for shape to mechanical pin not being resolved properly: M; K# B1 \7 n9 g. G
1861548 ALLEGRO_EDITOR DRC_CONSTR Inconsistent Micro via to Micro via drill to drill overlap DRCs0 B1 j7 s# m6 v* U
1862281 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin/hole to Shape spacing too small: P+ ]$ N4 U; M& k. ^+ e2 D
1887145 ALLEGRO_EDITOR DRC_CONSTR Mechanical pin to conductor spacing setting is overriding constraint region in release 17.2-2016" m1 N* e2 z0 `9 o$ G* G
1893012 ALLEGRO_EDITOR DRC_CONSTR Shape voiding not taking the shape to hole spacing rules for NPTH- V! Z' r- O2 Y
1906840 ALLEGRO_EDITOR GRAPHICS Context menu stays when PCB Editor is minimized.
# W: X Y: j" I( K/ {2 O9 p9 ^. d1738624 ALLEGRO_EDITOR INTERACTIV 'Invalid Sector' error when saving psm file for symbol that has die pads, which are copied) s; Z0 U7 ]" K3 ~
1800741 ALLEGRO_EDITOR INTERACTIV Search in User Preferences Editor is giving incorrect results" F/ ~1 x8 t1 F0 x2 O/ c7 {
1812530 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes when opening a file that is in an unsupported format
6 _+ d# U- A& O' X: w- p1812570 ALLEGRO_EDITOR INTERACTIV PCB Editor hangs when an invalid pin number value is specified as the rotation point in the symbol preselect mode
( i3 F; _. T9 K2 ?' U1826819 ALLEGRO_EDITOR INTERACTIV 'Route - Resize/Respace - Align Vias' menu is not available
9 x8 h2 j+ \- f! ~8 w& T1842645 ALLEGRO_EDITOR INTERACTIV Via align command is missing from the menu path% s! L" u( c. f/ @
1845748 ALLEGRO_EDITOR INTERACTIV With 'Shape - Change Shape Type' enabled, changing visibility reverts the Shape Fill selection to dynamic copper.
: ?5 W# l. Q: u' t3 O1849700 ALLEGRO_EDITOR INTERACTIV Add the reason for generating DBFIX_PAD, to the dbdoctor.log.
- c" P" _ j8 ]. G1860934 ALLEGRO_EDITOR INTERACTIV Auto-Paste environment variable is not working as it should
7 n F% z: R0 J9 d; g* l. y a1 c: n' |1861928 ALLEGRO_EDITOR INTERACTIV Provide a Persistent snap pick option for Display - Measure0 Q1 [8 ]0 p' R) U
1864238 ALLEGRO_EDITOR INTERACTIV Shape place rectangle issue: Dimension of placed rectangle changes on cancelling action
( Q. T/ _3 `7 L% T$ o9 e" O6 X6 x1877026 ALLEGRO_EDITOR INTERACTIV Filled rectangles on ETCH/TOP and ETCH/BOTTOM are not getting copied
8 ?4 x# B+ e4 I V1881637 ALLEGRO_EDITOR INTERACTIV Radius of Shape changes when trying to place circle using Place Circle mode.( C" ?$ u/ \& p6 _( B" g; U3 @; |
1883032 ALLEGRO_EDITOR INTERACTIV Find by Query does not find all padstacks in a symbol drawing6 ?8 Q. ` \/ e' L& Y$ ]' N0 k
1855248 ALLEGRO_EDITOR INTERFACES The Technology Dependent Footprint command returns an error
& f) Z4 z. @1 F0 r2 U1885716 ALLEGRO_EDITOR INTERFACES Increase supported STEP model size to enable the use of models larger then 500MB
% n5 y' _8 V$ T* _1860835 ALLEGRO_EDITOR MANUFACT Display a message when backdrill_max_pth_stub is defined for vias or pins only
# A+ z9 R; j4 E8 P( `* U1869528 ALLEGRO_EDITOR MANUFACT Backdrill out of date when deleting Teardrop and Sliding cline with Teardrop, v& H* x6 d$ M3 o5 C3 m
1885672 ALLEGRO_EDITOR NC NC drill is creating false backdrills when repeat code is turned on in release 17.2-2016 |2 g7 F4 L" ?9 G/ u
1895084 ALLEGRO_EDITOR NC Padstacks with backdrill data trigger backdrill out-of-date even if the board is not set up for backdrilling; O( R9 H. M2 \3 e# s3 \* w8 d
1837514 ALLEGRO_EDITOR PAD_EDITOR Offset is not consistent for keepout and mask layers in padstack editor.9 D+ A" q" `! I& T a. Z, _
1842902 ALLEGRO_EDITOR PAD_EDITOR Scrolling through the .pad files in the Library Padstack Browser displays Error(SPMHA1-161)
4 j$ T2 t5 D. G# e; j+ s1846504 ALLEGRO_EDITOR PAD_EDITOR COVERLAY_TOP definition lost while opening and saving a 16.6 pad in 17.2 padstack editor
- Q" O W, l: ~" w# x0 ?/ Y. U2 T) b1879453 ALLEGRO_EDITOR PAD_EDITOR The 'Y' tolerance in the Padstack Editor does not update when changing the units of the padstack.
6 N- D5 w0 ^6 e; V2 G2 F* W' u, F5 M1805202 ALLEGRO_EDITOR PLACEMENT Place via array adds via on differential pairs incorrectly
& q9 T5 W! [( [$ P# z* s3 c9 i8 l1806675 ALLEGRO_EDITOR PLACEMENT Place - Manually - Quickview displays the Assembly Top details only
$ L% }+ g" V) |( C+ U; |0 L1835177 ALLEGRO_EDITOR PLACEMENT Can place symbol even after cancelling copy by choosing 'Oops' from pop-up% v3 J2 y# d; b5 O: r/ ]+ A
1846892 ALLEGRO_EDITOR PLOTTING PCB Editor Export PDF does not show lines correct for certain component
7 v8 L" ^1 H; Y5 E) r: m9 x. I2 ^1006328 ALLEGRO_EDITOR SHAPE Static shapes should void around corners as dynamic shapes do* `& F: L% E4 M I6 M- z1 V: g
1033326 ALLEGRO_EDITOR SHAPE Cannot compose lines to shape9 H2 }! d1 n6 n) ~2 ?- S' k, ` Y& q7 N
1045089 ALLEGRO_EDITOR SHAPE Dynamic shape voiding is inconsistent for solid and xhatch shape fill type
6 O- m- Z6 v/ j) q# `1069959 ALLEGRO_EDITOR SHAPE Compose shape crashes PCB Editor
- J) ^, a+ R! b( g* c! s3 j% }2 O2 x1085907 ALLEGRO_EDITOR SHAPE Pad does not get thermal connections to shape if outside of the shape outline by more than DRC spacing.
h1 K# c. A6 I9 L* j1143563 ALLEGRO_EDITOR SHAPE The pin void inline clearance does not seem to dynamically update the shape and requires a 'force update'.3 U( {3 Y: F$ B j9 `" ]
1243688 ALLEGRO_EDITOR SHAPE shape_rki_autoclip fails to clip shape to route keepin
5 d1 a( l8 u& i* ^# n" @6 B1269069 ALLEGRO_EDITOR SHAPE Shape void not working properly in release 16.5 hotfix 054
0 |7 r2 }5 H; X: _1 D9 G1327755 ALLEGRO_EDITOR SHAPE Need the ability to nest dynamic shapes on different nets partially or entirely) `. l6 S* j E4 J; U4 D
1417394 ALLEGRO_EDITOR SHAPE Shape not updating correctly+ T6 M1 I' Y) \, V& v- ~
1430742 ALLEGRO_EDITOR SHAPE When adding fillet to an irregular pad, the fillet might not be added or be strangely shaped9 x2 k: G" Y, i, N" M
1750760 ALLEGRO_EDITOR SHAPE Shape to Route Keepout DRC for a void that meets route keepout2 N, v7 f3 t. g2 d& q
1793898 ALLEGRO_EDITOR SHAPE Add teardrops fails to add anything with different settings1 V/ V/ {7 x4 ?
1811662 ALLEGRO_EDITOR SHAPE 'show measure' gives incorrect air gap value between two pins" x' _7 G" ~& |" X9 d
1820901 ALLEGRO_EDITOR SHAPE The pins on adjacent layers are voided as Rounded Rectangle instead of Rectangular as defined in padstacks% u, z/ H7 M, R# p
1829570 ALLEGRO_EDITOR SHAPE Display measure airgap value is very large
; D$ C8 Z) {0 i$ X1858696 ALLEGRO_EDITOR SHAPE The via to the edge of the board is not connecting to shape even with the PAD_SHAPE_TOUCH_CONNECTION property added- `! B# Y' @" l, S- S9 G
1873384 ALLEGRO_EDITOR SHAPE Boolean AND operation returning nil/ x6 x O" I; U; }2 T
1873860 ALLEGRO_EDITOR SHAPE Copper shape does not respect route keepout
% y% A/ S! H8 G' M# M R1889312 ALLEGRO_EDITOR SHAPE Shape voided for net vias on adding 'PAD_SHAPE_TOUCH_CONNECTIONS' when enabling via suppression
) i* L/ _1 }6 h4 d8 ~" k/ a" m1890702 ALLEGRO_EDITOR SHAPE Not able to add teardrop in release 17.2-2016
0 g J$ C" W& k t% k, E! l1892692 ALLEGRO_EDITOR SHAPE Thermal relief connections being added to static shapes present in the void inside Dynamic Shapes
$ o; f& _; q; K1893492 ALLEGRO_EDITOR SHAPE 'merge shapes' results in moved void
; q+ M& W0 F6 Q8 A1896543 ALLEGRO_EDITOR SHAPE Same net pin will not add thermal connection to shape if it is a rotated slot in the symdef
2 j) O. v4 V( P. j+ L' N! r, `1897645 ALLEGRO_EDITOR SKILL axlCNSGetSpacing() returns nil if active class is non-etch.! N8 i5 j/ i7 m2 @( [+ O
1822364 ALLEGRO_EDITOR UI_FORMS Design Parameters dialog disappears if prmed is called while show measure is active! d8 L% l& x5 T( j+ j6 \; L$ o9 R9 i8 B
1834395 ALLEGRO_EDITOR UI_FORMS Setup menu of OrCAD PCB Editor is missing the Anchor 3D View command
1 W# ~% N2 z3 l8 x; r' H) c1838941 ALLEGRO_EDITOR UI_FORMS Anchor 3D View command is not available in OrCAD PCB Editor Setup menu
4 X$ j1 `0 r! [1716433 ALLEGRO_EDITOR UI_GENERAL Alias keys do not work until mouse scroll key is activated. |4 Y: K8 }1 q8 j5 E7 C/ l
1721761 ALLEGRO_EDITOR UI_GENERAL During manual placement of symbols, hovering over symbols does not highlight them
1 v7 O8 a% X8 ^0 G) J6 ^' _1732915 ALLEGRO_EDITOR UI_GENERAL Alias does not work in release 17.2-2016 when switching windows
3 G! b7 @" Q6 }/ ~# `1 c# |& K1770723 ALLEGRO_EDITOR UI_GENERAL Funckey does not work if focus is not on canvas in release 17.2-20161 S2 o! K& z6 N6 x/ \: }
1793839 ALLEGRO_EDITOR UI_GENERAL Function Key does not work if a form is opened by a previous command7 s5 w+ M- h* g& H: G$ h" L
1813961 ALLEGRO_EDITOR UI_GENERAL Inconsistent file formats available when saving reports0 V) I* M7 t2 K4 v9 E& N
1816716 ALLEGRO_EDITOR UI_GENERAL Shortcut not working when using working layer with 'add connect'# M7 Q$ S8 }" X
1864321 ALLEGRO_EDITOR UI_GENERAL Funckeys not being registered after focus has moved to other window and back again in PCB Editor
" C' A/ r- {3 ~5 ]1865010 ALLEGRO_EDITOR UI_GENERAL PCB Editor does not get focus when clicking shortcut after switching from any other program or application0 h1 ~* ^2 ` ]3 Z3 }1 S
1868708 ALLEGRO_EDITOR UI_GENERAL Allegro PCB Editor, funckeys stop working intermittently in release 17.2-2016, hotfix 032
4 m+ e( S" w: m5 |1869745 ALLEGRO_EDITOR UI_GENERAL Allegro 3D Canvas window becomes active on pointing at minimized icon on taskbar, m' r2 U1 ?4 A5 e+ A* G
1869860 ALLEGRO_EDITOR UI_GENERAL Hotkeys no longer functional on switching from PCB Editor to another application and then back again
6 q: p; Y2 V% C/ u; `! z( c' v1870744 ALLEGRO_EDITOR UI_GENERAL Need html extension added to Save pull down menu.
* b* k: t8 z6 K1870996 ALLEGRO_EDITOR UI_GENERAL If you switch from one active window to other, hotkeys stop working
) u0 m# t: \5 P! l- j8 s* E1883507 ALLEGRO_EDITOR UI_GENERAL Hotkeys stop working after Allegro PCB Editor UI window is opened5 O/ W0 Z( B8 k1 Z/ D) n
1886981 ALLEGRO_EDITOR UI_GENERAL Focus lost from layout when switching between PCB Editor and Capture8 p* z3 u* O7 @2 p z$ e4 l' F$ D
1887519 ALLEGRO_EDITOR UI_GENERAL Release 17.2-2016, hotfix 034: Shortcuts defined using funckeys not working correctly
: ]0 z& J ~* J1887660 ALLEGRO_EDITOR UI_GENERAL Alias does not work in release 17.2-2016 when switching windows.
W4 Q+ Q% b8 l$ D9 I1891204 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes if SKILL form is closed using the Close icon ('X')
# Z# y+ V* _; i b1898059 ALLEGRO_EDITOR UI_GENERAL Funckey commands are not working consistently in release 17.2-2016 {0 |3 t7 g; X9 [
1902322 ALLEGRO_EDITOR UI_GENERAL Cannot use funckey commands when cross-probing1 Q, R* V+ n% }- G
1905906 ALLEGRO_EDITOR UI_GENERAL Issue with keys and focus when navigating between windows ]* Q% s* Z8 n7 t" X
1913768 ALLEGRO_EDITOR UI_GENERAL Uppercase funckey shortcuts do not work- y1 w8 T) X) F. {* z( r3 X- o m
1751586 APD OTHER axlGetMetalUsageForLayer() for etch returns value including pins and vias7 h- n! S$ Q" j( y. T6 P
1863241 APD SHAPE Fillet is left on the T-Point without Cline(center) connection.
c$ O. P8 \" V* |) e8 l( K1894438 APD STREAM_IF APD/SiP Layout: Export rounded features as circumscribed and not inscribed polygon in GDS
0 {- Y' I( a4 ^1812699 ASDA AUTOMATION Enhance the performance when extracting data from SDA, using TCL functions
0 }; d* X }5 b1863436 ASDA CANVAS_EDIT alignment guides are not displayed when placing or copy a part, only when moving. They are most needed during placement
, l( s$ {3 W* ^, X) O- m1863445 ASDA CANVAS_EDIT Dark theme blue text in docked CM needs to be of a different color: difficult to read
1 A. N) j5 i1 M& L1 x5 U9 V3 Y+ ^# b1802111 ASDA DARK_THEME Dark theme in SDA should also change the border line color and text color of grid references: they are still black
1 z D" r. _1 f! D0 Q. U& U: T `1869951 ASDA EXPORT_PCB File browser button in Export to PCB Layout flashes graphics of the window behind the form- u0 i9 d. o! _, }+ K0 E# q
1845831 ASDA FORMAT_OBJECT Width of the twisted pair of wire should automatically be set to 6, otherwise it is not drawn correctly
2 T& D& P, @8 P1879914 ASDA INTERNATIONAL Using French Keyboard cannot use the . (point) delimiter to set VOLTAGE property value
' d4 I! E1 h; g8 S7 |: v3 R1865753 ASDA MISCELLANEOUS Inconsistent and non-ideal behavior in SDA product choice dialog, small box, hard to check unlike the bottom box
a7 j1 @9 P/ [9 o- S8 g1863457 ASDA PACKAGER Unset all user-assigned references globally
% G' ^2 V* d. g9 @) h) s1889301 ASDA TDO SDA TDO Crashes when switching to/from Offline mode
6 l9 \1 c) @5 w8 w1 v1823203 ASDA VARIANT_MANAG Variant setting part to not present does not do anything
$ P$ B2 K n3 I; P1823992 ASDA VARIANT_MANAG Variant Editor fails to read netlist if a net is named NC' f0 ]% }4 n! l7 U* Z
1863451 ASDA VARIANT_MANAG variant mode can select multiple parts to add to variant but can't select multiple parts to hit reset( Y5 i) m _3 g0 _8 N
1863455 ASDA VARIANT_MANAG Cannot resize any panels in the Variant mode, S8 z6 {7 D' Q/ H, r! |/ r) X2 n
1874952 ASDA VARIANT_MANAG Letter I in the alternate part icons in variant spreadsheet should be white for readability
6 p, F% n; T; J2 k1878401 ASDA VARIANT_MANAG SDA Variant Display - DNI marker color switches between black and red
o9 _. f: z; w" w: R# J) o1877239 ASDA WORKSPACE SDA DRC window is hidden if undocked and minimized
/ u/ D( h* P+ m0 _) I* k1809605 CAPTURE LIBRARY Part has pins in the incorrect order in the Connectors library
+ D0 G0 H" @ h1638693 CAPTURE OTHER Capture Footprint Viewer not showing footprint.% S* \1 e6 A: E/ [% O! {/ o
1873612 CONCEPT_HDL COPY_PROJECT Copy project causes nets to be added to net groups and ports - fails to package due to mismatch
& Y# } z' S" b- O1779289 CONCEPT_HDL CORE Adding a component and wire and saving the design results in a 'Connectivity save failed' error" q! m' l B7 G+ |" s
1878719 CONCEPT_HDL CORE Cannot enable or apply block variants at the top-level in a hierarchical design.; d+ D8 y) i- m- y* C& w5 ~# M
1865480 CONCEPT_HDL OTHER 'partmgr -ptfMode shoppingCart' cannot output cell name with project ptf file into shoppingCart.xml/ K6 f5 t2 l. F, Q# Q6 w
1829966 CONSTRAINT_MGR CONCEPT_HDL DML independent flow: Export Physical audits missing signal models in release 17.2+ u, S; a# w, N* m' T3 \7 `" C9 v
1904458 CONSTRAINT_MGR ECS_APPLY 'Audit - ECSets' crashes DE-HDL in release 17.2-2016, Hotfix 037
' l+ k, ?2 s. N1 I/ x3 x7 [ y1798269 CONSTRAINT_MGR OTHER Script changes '-' in layer name to '_'+ ?- L! r* ~# }- g% W" L* z/ w, u- p( T
1835520 CONSTRAINT_MGR OTHER Cannot add members to netclass name with parenthesis
' m" ?" ^) X C1896638 CONSTRAINT_MGR OTHER Constraint Manager worksheets jump abruptly
! V& F1 M, i: x1801938 CONSTRAINT_MGR UI_FORMS Add To Netclass window: Focus not on ClassSelection
4 k, a: @6 K) h$ ~$ v3 P. b1854060 CONSTRAINT_MGR UI_FORMS Using the tab key in the Manufacturing workbook jumps a cell
+ ]: m9 D" V. X1881832 ECW ROLES_PERMISS Adding Users in SSO environment using PS is error prone* p4 [) G* t2 M
1864870 F2B BOM Incomplete BOM report generated
7 O5 Z+ z1 U U8 ?* N1846578 PCB_LIBRARIAN GRAPHICAL_EDI radio buttons and clickable buttons are hidden in the UI for verify rules
1 B2 x0 X0 }3 }$ B: U1 a1854080 PCB_LIBRARIAN METADATA con2con needs to support special characters in Primitive Name
6 n; f- A4 m' a! j* q$ d! b1796377 PCB_LIBRARIAN SYMBOL_EDITOR Unable to move pins using arrows when symbol is opened in Symbol Editor
) o1 ?! M) ?$ }1839692 PCB_LIBRARIAN SYMBOL_EDITOR Properties tab grayed out in Symbol preview window
' H6 I' S2 \) P- L" K' f1865657 PCB_LIBRARIAN SYMBOL_EDITOR Cannot change symbol properties using the General tab1 K6 p3 d& D2 A8 ^( L; Z
1906888 PCB_LIBRARIAN SYMBOL_EDITOR Properties button in Symbol Pins tab of the Symbols section is inactive.
5 N! Q; S# D( f' X: k1891248 PCB_LIBRARIAN SYMBOL_EDITOR Copy and mirror arc drawing object in the new Symbol Editor results in wrong arc on opening symbol in DE-HDL& Q$ J6 T6 ^7 f/ i9 U! ~, b- u
1908381 PDN_ANALYSIS PCB_STATICIRD Allegro PCB PDN Analysis crashes after performing analysis and saving result in release 17.2-2016
& D; l4 C9 I' g ^! I$ J# h1825087 PSPICE AA_OPT Graph view menu does not appear when we use 'Curve Fit' in Optimizer.1 Q8 P3 i( n$ q4 y. v
1808091 PSPICE ENVIRONMENT 'orSimSetup' crashes when 'Restart Simulation' is selected: K0 N" e" G3 b& r6 P8 P5 [$ N4 E
1811782 PSPICE ENVIRONMENT Setup Simulation Profile no longer enables Advanced Markers when appropriate( ]& _' G% D5 Z
1834147 PSPICE ENVIRONMENT PSpice Part Search library icons not displayed if product is installed in the Program Files folder in release 17.2-2016! _& X" q# s' B! V# H
1841992 PSPICE FRONTENDPLUGI Getting a blank Error dialog while adding a marker" z' z( D: D' K" C
1858574 PSPICE NETLISTER PSpice simulation: Some models cannot be used after upgrading to release 17.2-20169 T# S, P x3 y! P# n5 T
1865022 PSPICE NETLISTER The division operator is not recognized by PSpice in DEV expressions in release 17.2-2016* t4 z* |& }) k
1677119 PSPICE PROBE PSpice crashes when plotting simulation message summary0 J2 j, c* \) D2 f& j( T
1837046 PSPICE PROBE On Windows 10, PSpice crashes on clicking Yes to see message' O) u; e' h( ?) \$ J' e
1879387 PSPICE PROBE PSpice crashes when we choose to plot simulation message summary
+ s$ |5 ]6 }9 Q. o: F4 d/ q/ Q3 C1842231 PSPICE SIMULATOR Wrong results in PSpice Advanced Analysis for DC Sweep Analysis
1 f* N" T s0 x' p- T/ r& E1843446 PSPICE SIMULATOR Distribution type is not showing under Assign Tolerance window for transistor
8 t7 f- S. z: t% z1872630 RF_PCB ROUTING Transition taper length does not work in route- Add RF trace
" K& O Z/ I. b1872636 RF_PCB ROUTING Inherit Width parameter in Route -RF trace only uses width of one side
) f5 E- g& E* G2 O: {1872644 RF_PCB ROUTING Regression RF trace: change in trace width not retained while routing+ x j- ]+ c6 C: i/ e% d& f
1901201 SIP_LAYOUT EXTRACT extracta is not retaining custom layer names
0 L- w5 I! g7 w! p1813380 SIP_LAYOUT OTHER Layer Compare is not adding the required shapes- w3 p4 C- @5 b& Y: E8 g3 m
1852762 SIP_LAYOUT OTHER Error generated in Package Design Integrity Check when adding soldermask to my design
" ^. ]" }% a8 P* y. H2 n/ ~1886847 SIP_LAYOUT REPORTS Incorrect metal area in metal usage report0 p% E& [2 C- g1 v+ x* G4 T3 N0 o
1491315 SIP_LAYOUT SHAPE Dynamic shape filling exceeds the shape boundary on running 'create bounding shape' command
, h f- w# V5 C F$ {4 m1853989 SIP_LAYOUT SHAPE 'Shape - Select' and then' Move' from pop-up with ix 500 iy 0 moves shape diagonally0 ^& }* B; [) c1 ?+ d$ @5 a) ]
1868509 SPECCTRA PARSER Autorouter takes long time to invoke/ n' |+ U- U0 b8 w, F# O
1869317 SYSTEMSI ENG_PBA SystemSI PBA does not align correlation waveforms correctly on Linux platform
3 ? B* a5 M! Y/ Z8 Z
7 W+ f3 {7 F) p4 s! C
6 B9 M9 f" P2 N- O9 T" R( J" `Fixed CCRs: SPB 17.2 HF037
! V4 h) T* k9 a+ o, E3 P03-30-2018 p# _: a5 D' j, z
========================================================================================================================================================+ ]$ U6 l# J) g& o8 [% j% m
CCRID Product ProductLevel2 Title
: X' n! r; ~+ R4 r2 |========================================================================================================================================================
& [ c: l# r4 d: _8 _$ I6 U+ Z1886573 ALLEGRO_EDITOR IN_DESIGN_ANA Fail to launch Sigrity executable from release 17.2-2016# P% a3 A( ~" L5 N. z/ q
1891113 ALLEGRO_EDITOR NC Clubbing total backdrill layerwise data
9 t' n3 I# Q: x: A- n1886085 ALLEGRO_EDITOR SHAPE Line to Thru Via DRC is not displayed automatically
. L4 T. |7 e" N, ` D: Q: [: o1850888 ALLEGRO_PROD_TOOLB CORE Design Compare crashes immediately after execution/ W' Y8 R( W! x$ I1 i( i
1639079 ALTM_TRANSLATOR CAPTURE Title block issues with third-party design
/ R# s9 p+ w. |# H6 c% a$ o U3 y5 a1722577 ALTM_TRANSLATOR CAPTURE Third-party translator does not work in Capture in release 17.2-2016 if CDSROOT is not defined4 h q& k) V; O) Z
1744697 ALTM_TRANSLATOR CAPTURE Third-party translator crashes
% S, J8 M" y3 Z9 ]0 T7 X) O1820160 ALTM_TRANSLATOR CAPTURE Title block does not show ghost image when selecting it for placement
# u! X; i! }: a. d) K1628560 ALTM_TRANSLATOR PCB_EDITOR Third-party translation to PCB Editor not working properly0 d+ D) ?4 X* M, ] b! E
1836750 ALTM_TRANSLATOR PCB_EDITOR Third-party translator fails to translate a complete design3 f2 l/ c; u6 X) n$ y% }
1844423 ALTM_TRANSLATOR PCB_EDITOR Third-party translation takes a long time in release 17.2-2016
! h2 d$ D* b5 c& M% j6 o1849338 ALTM_TRANSLATOR PCB_EDITOR Third-party translated board not correct" G( @# S ~8 m1 `/ n; q( I" u7 K; Y8 t
1894607 CONCEPT_HDL CORE Closing CM during 'Save Hierarchy' crashes DE-HDL, i5 B; z: t* Y! k! V' \
1703351 CONSTRAINT_MGR CONCEPT_HDL SigXplorer shows invalid models instead of default models in extracted topology# V3 J: ]5 h3 O6 X
1868687 CONSTRAINT_MGR CONCEPT_HDL DML-independent flow: some pin-pairs missing for Differential Pair XNets when migrating 16.6 design to 17.2
3 g- I8 }. g" v) r" J1868747 CONSTRAINT_MGR CONCEPT_HDL Additional pin-pairs created on migrating design to release 17.2-2016 DML-Independent flow
C+ ?5 J* y k& ]/ W8 q8 o6 Q& I1887794 CONSTRAINT_MGR OTHER Ability to disable cross-section changes in F2B flow6 T: A/ H% v* i& H3 b6 L$ o
1859193 MODEL_EDITOR TRANSLATION DML provided by Model Integrity has a parsing error: curve must start at time zero& ~# Y) c [2 h
/ t2 e( i1 q6 g/ ~$ h9 N4 j& H
9 S8 s3 L! V% X/ [Fixed CCRs: SPB 17.2 HF036
2 \3 L6 y8 u2 b, i' V4 [03-16-2018
/ H+ p: o; c5 {+ W& R========================================================================================================================================================
3 Q9 a! V6 f: f2 l) N% t6 jCCRID Product ProductLevel2 Title
8 t' f S& W" ?& Y6 B4 R& J========================================================================================================================================================
1 ^, M$ x! l$ ]$ g" i) x% Z* u0 K1880209 ADW DBEDITOR DBEditor quick search is resetting the check boxes in the Attributes tab
! f* w0 v/ z- u4 d* {" |1 Q1880376 ADW DBEDITOR Allegro EDM Database Editor wildcard search functionality broken after installing hotfix 034.
( ^7 c: L Z) E5 R- y5 ~1 C1855444 ALLEGRO_EDITOR DATABASE PCB Editor crashes on creating MDD files after deleting subclasses" i* \5 @4 _: S& F# ^8 V
1863478 ALLEGRO_EDITOR DATABASE PCB Editor crashes on a specific machine when loading any .mdd file
t1 P, n, L1 K% P" W1875544 ALLEGRO_EDITOR SCHEM_FTB Constraints are getting removed
% S& P2 S- g, u v1719683 ALLEGRO_EDITOR UI_GENERAL Incorrect display when using infinite cursor.) i* A0 X" {* H; q$ m
1765989 ALLEGRO_EDITOR UI_GENERAL Selection window does not work correctly with infinite cursor option checked
# g: H: ^2 z, a7 p; [$ q1885667 ALLEGRO_EDITOR UI_GENERAL Infinite cursor is not working correctly4 o) C& E% I4 O8 Q
1873954 ASDA IMPORT_DEHDL_ SDA: Inconsistent pin number positions on part in an imported DE-HDL project6 f; x/ ~0 \0 U+ Y
1873883 ASDA NEW_PROJECT SDA: New project from DE-HDL creates blank Page 1
. S- k" n$ x" X% q' b9 m* Z0 a1852036 ASDA VARIANT_MANAG Design with variant cannot generate a variant BOM
9 \* l7 c" n7 n5 |3 ^& T4 y2 V5 e$ D1875549 CONCEPT_HDL CORE Incorrect PART_NUMBER/VALUE properties on schematic% I% {7 |' Q" M1 E+ b
1881848 CONCEPT_HDL OTHER License issue: Cannot open Allegro Design Authoring and unable to choose options and features7 w( S* H4 f& n" v: ~. a
1872189 CONSTRAINT_MGR CONCEPT_HDL Pin-pairs are created for incorrect members of differential pair after ECSet is applied
4 D3 g8 x# \7 j+ F1880235 CONSTRAINT_MGR UI_FORMS Ability to lock auto-generated Constraint Set in UI
* O7 g* P! ` w/ K Y1868711 CONSTRAINT_MGR XNET_DIFFPAIR Nets are dropped from XNets on the BRD file in the front-to-back flow+ h6 g( x; ]+ b; }* C
1879296 ECW PROJECT_MANAG Mode to remove Uprev Lock from locked webs in admin keys
: s( g) w9 v% W1881632 PSPICE SLPS PSpice creates 'psp_input.log' during co-simulation flow. ?' F3 B2 `6 |3 c' ~
1879302 SCM OTHER SCM crashes when global nets are changed in the Block Packaging Options dialog box; I8 R& r8 U9 Y: I2 q: N
1879580 TDA SHAREPOINT GetData error when opening a project in Design Data Management/ J7 y" g9 C/ a H9 a4 W. M1 E
3 G& ^, {: u9 [1 N7 h$ d
( Y4 M! D0 \0 G8 I6 R1 H. j0 k! {Fixed CCRs: SPB 17.2 HF035
5 s" p+ k5 q5 J! K1 B3 ` t03-02-2018
8 k/ t7 q0 U' P2 }: O- h) |7 z* P========================================================================================================================================================
3 X4 l& h: m$ @9 O' ~CCRID Product ProductLevel2 Title
5 y$ q" v n' x: W) N* r========================================================================================================================================================/ B" U9 j; A* c' s) L$ } A$ q$ F
1873547 ADW ADW_UPREV adw_uprev resulted in incomplete footprint XML
2 q: P6 h/ u6 D5 S: B1643895 ADW DBEDITOR Create Footprint model name is not working properly if footprint exists in local flatlib* }! ?% ]5 R$ p+ E! `! i4 E
1846400 ADW DBEDITOR 'Copy As' and 'Rename' STEP model options do not work) N' A- ~' @' r1 o4 e {
1868299 ADW FLOW_MGR Copy Project fails and makes Flow Manager unresponsive. u1 E$ n$ p' V/ n- M: X
1872796 ADW PART_BROWSER Part/Model Details Attributes are all empty when connected to the EDM DB `( U, T% |1 a6 w2 @ Q3 e
1877199 ALLEGRO_EDITOR DATABASE Purging backdrill adds bottom filmmask to vias when it is not defined in the padstack9 ^& P4 S2 I. c0 A- b" u7 e" Q
1877219 ALLEGRO_EDITOR DRC_CONSTR PCB Editor crashes on updating DRC
Q+ {( J! s& o y1875528 ALLEGRO_EDITOR GRAPHICS Subclasses disappear in partition
- I$ l5 r& f1 {6 s1 ?0 {1868364 ALLEGRO_EDITOR OTHER Translator for Layout to PCB Editor fails in release 17.2-2016 but works in 16.6
& A) F3 r4 ^) {9 P0 ^( ^# {1822989 ALLEGRO_EDITOR UI_GENERAL PCB Editor very slow when using infinite cursor
, i% ^- C( z5 M7 p( a7 i6 o) j4 ~1855275 ALLEGRO_EDITOR UI_GENERAL PCB Editor becomes slow if OpenGL is disabled
$ @' m# X. ^" |* S1868803 ALLEGRO_EDITOR UI_GENERAL Infinite cursor not working as expected- d1 i4 b* n- V% g
1869523 ALLEGRO_EDITOR UI_GENERAL PCB Editor hangs inconsistently on axlOpenDesign0 q7 k6 x! ?3 f" @! o) u" S
1871409 ALLEGRO_EDITOR UI_GENERAL ESC key does not function with Enable_command_window_history set' n; W8 v6 ^& g
1812306 ALLEGRO_PROD_TOOLB CORE Incorrect DIFF result of PCB Design Compare% ]) X- x% Q: \8 M: j: w6 k/ |7 h
1872772 ASDA MISCELLANEOUS SDA pulls a license for 'Allegro_performance'
2 ]- u3 b; R; M1877070 CAPTURE OTHER Capture redraws icons1 h3 F( Z! D* j
1863624 CONCEPT_HDL CONSTRAINT_MG XNet names are changed in the designs migrated to release 17.2-20164 e4 j# C/ O( q
1866290 CONCEPT_HDL CORE variant editor/DE-DHL crashed when changing a component property/ v1 D9 y* ^1 a8 d, X& ?# J
1858139 CONCEPT_HDL OTHER Slow graphic response in Windows10: Icons redraw
_0 A9 z3 M$ x& X4 v1872703 CONCEPT_HDL OTHER Icon and toolbar in DE-HDL keeps on refreshing for every command% ^0 n: _. Y# ]3 J/ U( w! i9 n+ U. Q/ t
1873949 CONCEPT_HDL OTHER DE-HDL user interface refreshes frequently Y: ]( M: I. L2 u. C& @2 Q
1871542 CONSTRAINT_MGR INTERACTIV Extracting object with 'Referenced ECSet' does not inherit T-points from the applied ECSet+ ], X2 P" u, g% x( [' G3 R# n
1868812 CONSTRAINT_MGR UI_FORMS Cannot Save Log File from CM ECSet Audit.& o6 }' G) ~# D; b: P+ R/ P% Z' P
1878574 ECW PROJECT_MANAG Duplicate entries are created in SharePoint users list while creating project on SSO setup! n* _7 Z' X4 D' M
1878619 ECW PROJECT_MANAG Too many mails generated on doing create project
A# }5 B5 a+ X3 d/ I% O0 v8 n1862772 ECW TDO-SHAREPOIN Logical BOM file name not displayed in Changed Files of Pulse Activity Log.
$ i2 ], e, @% V3 U& f- m1 J: P/ B5 v1860641 INSTALLATION DOWNLOAD_MGR Download Manager remembers credential settings! a0 A9 M) E+ D3 ?3 V4 B1 X: k: X2 R
1867195 INSTALLATION DOWNLOAD_MGR Download manager crash+ e" F# J) E& T' O, G/ F- `
1872187 SIP_LAYOUT DRC_CONSTRAIN Sliding a cline removes DRC markers but updating DRC shows more DRC markers4 B4 @8 ~5 z9 _' F; Z7 L' ~1 R
7 f3 B' v# p' E. J e, n0 i
s1 b ~! O! P5 y
Fixed CCRs: SPB 17.2 HF034
' p. v2 \$ X9 t3 b02-11-2018, S1 g( B: [+ N* g0 F
========================================================================================================================================================, K! `" W. H: G! D
CCRID Product ProductLevel2 Title
% K: o9 F+ [- U5 w========================================================================================================================================================
4 j7 @1 K, R7 x1863981 ADW ADW_UPREV adw_uprev is taking a long time after installing hotfix 031
" x0 i( @6 c9 g+ S1868186 ADW DBEDITOR Configured LDAP authentication giving error on launching DBeditor after ISR31 installation1 b! \% I& l( Z! x! o" N
1861524 ADW LIBDISTRIBUTI Library distribution is checking for obsolete classifications every time it is run hence taking more time
3 c- [/ @! X. {4 Y: |. L( ~: Q* E1842998 ADW LIB_FLOW Footprint model check-in fails with verification checks failed error
% C e! [) e- g& K; m( R1863047 ALLEGRO_EDITOR DATABASE The layer added above the TOP layer in SiP Layout cannot be deleted from database.
3 Z9 x$ p2 y3 ]1852799 ALLEGRO_EDITOR DFM Refresh symbols crashing inside constraint re-enablement code
* E3 R) u" m* d$ v/ n1865732 ALLEGRO_EDITOR DFM The Thru via hole to Pad check in Annular Ring should check only the Finished hole size instead of backdrill diameter
6 X E1 W, O6 c2 @- s1 A( X; `1862977 ALLEGRO_EDITOR DRC_CONSTR Differential pair phase tolerance DRCs introduced in release 17.2-2016 DML-independent flow
8 @5 Y5 p: T& L- n" W$ I$ O1864460 ALLEGRO_EDITOR EXTRACT Running Extracta from outside using command window writes layer name for top/bottom layers incorrectly for SiP designs
O q! \) x! g6 P1859208 ALLEGRO_EDITOR GRAPHICS Pop-up menu remains on desktop when PCB Editor is minimized5 q' k) R# c* G F' X3 S
1866422 ALLEGRO_EDITOR MANUFACT Backdrill update taking a long time4 B, z5 j" B( J
1867148 ALLEGRO_EDITOR MANUFACT Backdrill update taking longer time to process.
2 W$ ~; m! i9 h& p' q1872127 ALLEGRO_EDITOR MANUFACT Backdrill performance issues - Additional fixes required for S034
8 t; W1 R6 E4 h1866577 ALLEGRO_EDITOR SHAPE Board becomes unresponsive on Shape Update or Slide Trace: `/ b5 V" u$ s- i2 \; M
1867590 ALLEGRO_EDITOR SHAPE The Shape to Pad clearance on multi drill oblong padstacks is not working correctly9 f) o; P# T) A( l" @7 c
1871902 ALLEGRO_EDITOR SHAPE Void issue during rotation of symbol with multi-drill padstack from hotfix S032
# Q; z" Y) Q/ |1 m% `' s1866778 ALLEGRO_EDITOR UI_GENERAL Unsupported prototype 'Enable_command_window_history' is not allowing text edits using arrow keys
! t/ R1 Q2 @' E7 G1865757 ASDA DESIGN_CORRUP SDA hangs when trying to save design or copy page or circuitry! m# z8 a: D% W/ B$ M' J
1865872 ASDA DESIGN_CORRUP Corrupt design crashes on editing.
' f+ {" V& u. E: l1867039 ASDA DESIGN_CORRUP Design corruption issues, j% c `7 g- e9 z( P% Q
1831263 CAPTURE OTHER Toolbar refresh is very slow on windows 10 after installing latest windows patch
$ Q# R8 W w3 ?+ Q1843595 CAPTURE OTHER Icon refresh is very slow on Windows 10 Professional after installing Hotfix 0296 M/ B5 W) G# m6 x
1845003 CAPTURE OTHER Application slow to respond after running for a long time
5 t7 h1 G* X! @; e& S( e, q4 U1847062 CAPTURE OTHER Starting OrCAD Capture redraws the toolbar icons many times.
% R# Z% m% R# w" M; v' ^4 d1850816 CAPTURE OTHER Capture redraws toolbar very slowly and repeatedly) Q1 }6 w. S7 {6 ]; S
1851346 CAPTURE OTHER Capture CIS redraws toolbars repeatedly- u; K- E+ i. k# K- H
1851354 CAPTURE OTHER Capture slows down in Hotfix 30 as tools icons are repeatedly redrawn very slowly
) }, c. S X: D9 R1851883 CAPTURE OTHER Toolbar content refresh is very slow8 ]: ~4 w! n; [: g5 p" Z! M- _
1852819 CAPTURE OTHER Capture refreshes toolbar again and again, Y! i u& G4 O/ V6 J s
1853395 CAPTURE OTHER Release 17.2-2016: Capture is refreshing toolbar icons many times at startup with latest hotfix& i3 D! N0 o, X* v) C8 \& l
1853972 CAPTURE OTHER Capture starts and redraws toolbar very slowly! F1 f3 B' l6 u
1854735 CAPTURE OTHER Capture toolbar reloads multiple times U# W1 ~$ b8 w& T1 B
1855850 CAPTURE OTHER Toolbar content refresh is very slow
5 O3 L' Z+ q' z ^6 E& f0 u7 L7 B9 S1857523 CAPTURE OTHER Toolbar icons refresh multiple times and very slowly in release 17.2-2016/ G6 T: I9 N8 Y( n" u) m
1859219 CAPTURE OTHER Toolbar is refreshed multiple times while starting Capture CIS. B: G) [4 H: M" t! n
1859626 CAPTURE OTHER OrCAD Capture does not work with the latest Windows 10 update3 o8 ~$ R: x; R, h4 o2 z3 Q
1863341 CAPTURE OTHER Toolbar icon refresh is very slow
4 l- _, F q% k" o9 l0 T) Z1865661 CAPTURE OTHER Release 17.2-2016, hotfix 032: Capture extremely slow on Windows 10
d7 s/ o" p K* r* p, V1867009 CAPTURE OTHER Slow graphics with Design Entry CIS on Windows 10.8 b) _( O; K, G8 Q. m5 k
1869160 CAPTURE OTHER OrCAD Capture poor performance (toolbar related)* e3 k" [; r- R* m. F
1869692 CAPTURE OTHER Redrawing of toolbars on Windows 10& ]1 [$ ~2 A& [, K- O* M
1870310 CAPTURE OTHER Allegro Design Entry CIS redraw issue* s+ A9 X6 s! g% Y6 U7 e
1870367 CAPTURE OTHER OrCAD Capture Slow Redraw& S; r" _6 w" S$ W
1871382 CAPTURE OTHER Schematic will not open and toolbars refreshed repeatedly
# K+ g( X0 ^4 `9 H" x8 C1872427 CAPTURE OTHER OrCAD Capture freeze on Windows 10
1 }* z& ~* s' ~, {3 T+ F1862679 CONCEPT_HDL COMP_BROWSER Unable to input property value to search in Part Information Manager- v( H5 J/ n" p& P' Y3 K9 m
1865039 CONCEPT_HDL CORE 'Save Hierarchy' of a release 16.6 design opened in release 17.2-2016 results in unexpected part changes
% o6 V6 [$ Y0 N9 i8 R1866544 CONCEPT_HDL CORE XNET_PINS added to migrate Design as DML Independentflow does not get saved in the CSA files
& Y# b: _* z! `" B1849363 SIG_INTEGRITY SIMULATION Differential impedance calculation shows ZERO when changing dielectric constant& L; e% ]; R! B' _# e. u9 c
1854195 SIP_LAYOUT UI_GENERAL After setting 'enable_command_window_history' in QIR5/Hotfix 031, Edit - Text no longer functions
) D9 d) }; G5 X4 L @3 L, D% C. s9 _2 x6 L
1 g! E* m% b- @9 T6 |$ ?
Fixed CCRs: SPB 17.2 HF033, v% e! R# V" |/ k
01-25-2018
3 Y- M) P. S. I- ]) G========================================================================================================================================================
6 }9 P: s! q) Z! HCCRID Product ProductLevel2 Title
, O+ l: D P- f' X1 ~/ P4 d$ Q: ^ w========================================================================================================================================================, P9 G) R& `& i
1828672 ADW ADWSERVER LDAP connection error while trying to log in to DBeditor' O/ z/ j8 y* V
1840699 ADW DBEDITOR Unable to release footprint model due to older version being linked to a DE-HDL Block Model
8 N9 F7 C) U$ F$ }& D/ m1852402 ALLEGRO_EDITOR DATABASE Cutouts are not converted correctly when opening release 16.6 board in release 17.2-20160 [" `: S, c0 S: \/ Z3 I
1855223 ALLEGRO_EDITOR DATABASE Release 16.6. BoardOutline not fully converted to release 17.2-2016 Cutout Layer
7 f9 K q) m$ C$ X: q6 F1855252 ALLEGRO_EDITOR DATABASE Unable to open a previously saved release 17.2-2016 database
( x! p5 P0 ~. K6 o& ?1863025 ALLEGRO_EDITOR DRC_CONSTR Shape voiding to Via pad with backdrill keepout is oversizing the Dynamic shape void by the backdrill keepout
" Z# r4 _% x; p% T _; g. n1854087 ALLEGRO_EDITOR EDIT_ETCH Sliding arc crashes PCB Editor4 D. k# y" t& M& F
1840667 ALLEGRO_EDITOR INTERACTIV Choosing 'Change Text block to' from pop-up displays message 'E- (SPMHGE-150): Text font is not defined'$ c4 f4 f6 H/ A: u6 t
1849133 ALLEGRO_EDITOR INTERACTIV On choosing 'Change Text block to' on text , 'Text font is not defined' message appears
5 n" H; d' W9 n% d9 A+ m8 I1854695 ALLEGRO_EDITOR MANUFACT PCB Editor crashes while performing nc_route( `; N9 @; Y0 F( Y% k1 n8 X
1854634 ALLEGRO_EDITOR NC NC Drill file is generated with half the number of Drill Holes on enabling 'Optimize drill head travel'0 j5 R7 \0 _+ b, ]0 j
1856773 ALLEGRO_EDITOR NC Issue with Optimize Drill head travel in hotfix 031: Missing drill holes
$ } e8 \# I9 W1860876 ALLEGRO_EDITOR NC NC route critical difference between hotfix 031 and 022: No slots found warning
* f/ i3 h' l% z; M. P; @1758671 ALLEGRO_EDITOR OTHER Export parameters takes long time to export and some times the process hangs
9 W1 o" w/ K$ U0 x1040989 ALLEGRO_EDITOR SHAPE PCB Editor crashes while editing board outline
+ B+ h4 h$ _7 Z$ x) \1328385 ALLEGRO_EDITOR SHAPE Check for missing thermal reliefs when shapes overlap
- L) @1 ~ t( w. V$ ~: w1366376 ALLEGRO_EDITOR SHAPE Thermal created for Xhatch shape overlapping another shape, but not created when solid shapes overlap: I5 }- j6 ]4 U# U) h
1716436 ALLEGRO_EDITOR SHAPE Acute angle trim should not violate DRC.3 d, r6 U2 o, j4 ^0 W9 ]& \
1822377 ALLEGRO_EDITOR SHAPE Setting shape parameter Acute angle trim control to Full round produces unwanted shape to keepout DRCs _, c) M; c* A
1826436 ALLEGRO_EDITOR SHAPE Same net shape to hole spacing not voiding shape for cline of different net moved close to vias of same net shapes3 M) H' i/ ^# A$ i" O
1834510 ALLEGRO_EDITOR SHAPE Same Net Shape to Via Spacing does not always clear correctly% y6 u O" D% Z, g. y) }1 h
1850716 ALLEGRO_EDITOR SHAPE 'DiffPair combined void for vias added with Return Path option' does not work with fillet and pad suppression& C$ B5 c. d! f! b+ m* F5 w
1852814 ALLEGRO_EDITOR SHAPE Thermal reliefs are not created after placing modules.$ d$ }' W% H) v- t
1853453 ALLEGRO_EDITOR SHAPE Route keepout clipping of cross-hatched shapes needs to be corrected% O$ D# a9 q6 V9 M& @7 c
1859391 ALLEGRO_EDITOR SHAPE Shapes are not using 'minimum aperture for gap width' for voiding after back drill update.* a- H1 k5 U0 x8 f
1859410 ALLEGRO_EDITOR SHAPE Shape to Teardrop is not using same net spacing rules
& U* N2 t9 ~4 d5 S& J8 Q1 d4 T. c1825397 ALLEGRO_EDITOR UI_FORMS Option panel disappears in release 17.2-20167 k! x6 b2 }: R7 G
1854070 ALLEGRO_EDITOR UI_GENERAL enable_command_window_history prevents many aliases and commands from working correctly
{ y& t5 E8 k; G& m7 i1855180 ALLEGRO_EDITOR UI_GENERAL Comma and dot do not work in funckey if 'enable_command_window_history' is set
. ^/ c5 W) W" L5 ^+ S" w7 {2 R1860003 ALLEGRO_EDITOR UI_GENERAL Icons and features missing or behaving differently in release 17.2-2016, Hotfix 031, B$ F7 v+ ~3 H
1861278 ALLEGRO_EDITOR UI_GENERAL Icons and menus missing in PCB Editor in release 17.2-2016, Hotfix 0317 U3 { V( Y" ] y- P2 H
1862292 ALLEGRO_EDITOR UI_GENERAL Layout Pins icon missing in toolbar in Symbol Editor since Hotfix 031
0 Q+ c5 |8 H1 x L1793284 ALLEGRO_PROD_TOOLB CORE Limit View (V1R, V2R, COM) for OUTLINE layer.
* r7 a- a) w1 _1712701 ALTM_TRANSLATOR CAPTURE Third-party translator shows error for missing operand, f8 j0 X% E2 ]0 z, H% ^
1802182 ALTM_TRANSLATOR CAPTURE Imported schematic has connectivity loss
5 d2 D+ C' p& n! e/ I1802462 ALTM_TRANSLATOR CAPTURE Hierarchical ports placed incorrectly for imported third-party design
% ~1 b( d6 Y8 ?) `1823935 ALTM_TRANSLATOR CAPTURE Translating third-party schematics with hierarchical pages from Design Entry CIS2 B2 v# w9 F. Q5 }! _: ~( M
1830570 ALTM_TRANSLATOR CAPTURE Third-party to Capture translation is translating only one page out of 32
. Z: D0 m4 F; c! f! g! z1839627 ALTM_TRANSLATOR CAPTURE Third-party translator is not importing complete schematic
: O9 t# v2 Q- a6 {, h L. p1846965 ALTM_TRANSLATOR CAPTURE Cannot translate third-party schematic B2 f0 s9 b% s$ k- d
1816767 ALTM_TRANSLATOR DE_HDL Error when translating third-party schematic to DE-HDL- e; U( _6 i7 M. H
1845601 ALTM_TRANSLATOR PCB_EDITOR Cannot operate third-party PCB translation in release 17.2-2016 Allegro Venture PCB Designer license
) y: ~( b9 F$ P9 ^, a7 }1841060 APD DIE_GENERATOR Cannot 'die text out' from SiP Layout or Allegro Package Designer
Z% ]+ u& u" J! _# t- I1793232 APD SHAPE When fillet/taper not connected to a pin, voiding process incorrectly applies shape clearance values6 J; ]/ i! s& H/ X% }
1846541 APD SHAPE shape degassing does not obey void to shape boundary C3 [0 x# o: j& ~; C' |
1863446 ASDA CONSTRAINT_MA A space in the name of a spacing or physical constraint results in the incorrect constraint set name, O% w7 ?7 ]& b' H7 _. z" T- K
1859678 ASDA VARIANT_MANAG SDA - When hovering over all three buttons, under Preferred Parts in the Variant info it says (Do not install)
2 u4 b) `( H- L1 E! E; X1815839 CONCEPT_HDL CORE Allegro Design Entry HDL crashes when entering Location data manually
% j, D5 {$ n& ^1 b& b# v9 C1841857 CONCEPT_HDL CORE Unable to modify Components in non-windows mode
1 q6 A7 x9 x1 r: E" Z1852096 CONCEPT_HDL CORE Creating a block using top-down approach does not generate the CSB file
+ M J+ E! ?. ~9 T. g1857390 CONCEPT_HDL CORE DE-HDL crashes on moving symbol4 T! X; t9 \4 _' l
1789070 CONCEPT_HDL OTHER Having folder 'allegro' in cpm root directory gives error while launching layout editor from Project Manager {; W V0 q9 R
1862484 CONSTRAINT_MGR CONCEPT_HDL Extracting an ECSet in SigXP is missing a t-point
5 g9 s1 t' l# z- A$ N1863045 CONSTRAINT_MGR CONCEPT_HDL Pin pairs deleted for a few differential pairs after upreving the design to release 17.2-20169 e. S E6 ?, j& y1 w
1863054 CONSTRAINT_MGR CONCEPT_HDL Differential Pairs are treated as invalid objects on upreved design( j# f3 y& `' l n0 }: X
1863094 CONSTRAINT_MGR CONCEPT_HDL Pin-Pairs are shown duplicated in the topology for the extracted object (Diff Pair)2 _$ a) I' {' M% a
1831998 CONSTRAINT_MGR OTHER 'Tools - Options' settings not saved on closing Constraint Manager
6 A5 A2 w! o- S9 v/ \2 P1855324 CONSTRAINT_MGR OTHER Enable the option 'Expand Hierarchy' in 'Find and Replace' dialog, by default+ v% F$ U# p' a! c* l
1860847 CONSTRAINT_MGR OTHER 'Include Routed interconnect' option once enabled, should remain enabled for that board file
' w; |0 h- J6 n9 j2 N2 W2 d9 Y1843359 EAGLE_TRANSLATOR PCB_EDITOR While importing third-party PCB, many footprints do not convert, even though the log file says footprint created1 I* Z9 I' f3 ]$ f7 t) y, ^2 e9 o6 g* x
1839978 SCM REPORTS dsreportgen unable to output reference designator from a lower-level hierarchical block if it has a single component3 w+ F! z/ d. Z/ c1 Z
1850013 SIP_LAYOUT OTHER Environment variable 'icp_disable_cte_auto_update' needs grammatical change. F6 e1 f9 V- V! K% \/ \' c
1833742 SIP_LAYOUT PADSTACK_EDIT When creating Die to Die Via using Generate Padstacks, resultant pad stack has wrong Layers8 T- @+ y$ D' f* f
1619098 SIP_LAYOUT SHAPE Acute angle of shape in design' [' E, f: b2 E. I% R u
1728628 SIP_LAYOUT SHAPE Auto-void in dynamic shape does not disappear if object is removed( B3 I% J, K4 Q: G* e, a
1854592 SIP_LAYOUT VIA_STRUCTURE Create via structure returns an error0 J' u5 X" k; N# A) g7 A6 ]4 ~& ?& t
; I4 b d$ t9 B2 s" _0 J
h' Y* y: V: c- y, |Fixed CCRs: SPB 17.2 HF032" F% m5 _6 N! A1 @: p5 p
01-13-2018
4 t( Y: p5 |( U( w. }4 t" _* d) I: ^======================================================================================================================================================== Q9 V" Q$ g2 G7 U- r) c. ~
CCRID Product ProductLevel2 Title
! w9 C) h6 ^, H6 F5 V========================================================================================================================================================
' m9 u1 K F7 f% \! {3 q1846603 ADW FLOW_MGR Copy project GUI not displaying correct design name after changing the project folder name* b4 _. i+ V+ v+ N# w( Z0 J
1831152 ALLEGRO_EDITOR 3D_CANVAS New 3D viewer canvas is blank; |1 M3 D0 ]) B: a1 @# w- b
1805870 ALLEGRO_EDITOR COLOR Color file with dot (.) in the filename is not recognized for setting color from the Visibility tab
! ~/ v( `0 S: G1 a" \/ H6 f* @) `) {1843126 ALLEGRO_EDITOR DATABASE DBDoctor UI is taking very long+ V9 S# n7 Y) O2 y+ o, O
1857588 ALLEGRO_EDITOR DFM Design for Fabrication - Aspect Ratio is not taking correct drill hole size5 e, Q- B& p4 F: m2 R6 x# h Q
1844313 ALLEGRO_EDITOR INTERFACES STEP output viewed in third-party tool has parts sunken into the secondary side1 K$ C- l% g% `; Y6 k2 N4 d
1801301 ALLEGRO_EDITOR MANUFACT Export IPC 2581 fails if VOLTAGE property is attached to the nets on each side of a RF component
0 v8 b5 k; ^. g- D1850078 ALLEGRO_EDITOR MANUFACT Choosing 'Manufacture - Artwork' crashes tool: q5 L8 d( }; b, s
1844049 ALLEGRO_EDITOR MODULES Module deletion not removing related component information.6 e4 j; p# ~+ `% W' [
1849665 ALLEGRO_EDITOR MULTI_USER Shape rejected by muserver# T: Z0 D" {+ Q& ?
1782831 ALLEGRO_EDITOR RAVEL_CHECKS RAVEL file does not load when it is located on a network with a UNC path specified5 ?& v) J. B* E' Q4 t
1830442 ALLEGRO_EDITOR SCHEM_FTB Fail to import technology file with message for failure to read the configuration file
8 C5 I- q1 h5 |& |1837391 ALLEGRO_EDITOR SCHEM_FTB Capture Property cannot rewrite or update constraints in PCB Editor& H4 L+ j: j1 d3 E
1840643 ALLEGRO_EDITOR SCHEM_FTB Export physical does not work after modifying PCB cross section5 y8 D# y4 I# e" @+ e% {6 w; P1 ?' i; ^
1718165 ALLEGRO_EDITOR SHAPE Drill hole cannot be voided by shape
* q3 P1 o* H% ?1 M# v4 l" n4 g1753245 ALLEGRO_EDITOR SHAPE Update Shape retracts more than the shape to shape spacing. n: N" I/ B4 I9 e
1827366 ALLEGRO_EDITOR SHAPE out of date shape is not flagged as out of date
, Z$ x) L" A- r h4 ~4 D( L( a1828208 ALLEGRO_EDITOR SHAPE Shape remains out of date, but status shows otherwise
* H8 B& V* C/ w& e5 N4 W1832098 ALLEGRO_EDITOR SHAPE Skip via shorts to plane at few places even after the necessary keep-outs are assigned to the via pad-stack.* G" a9 x) [' n* c; K6 ?
1834281 ALLEGRO_EDITOR SHAPE DBDoctor creates a large number of DRCs, R; e$ h- j; `! l
1842121 ALLEGRO_EDITOR SHAPE Unable to clear the Drill Hole to Shape Spacing DRC as Pin is not able void to the shape correctly.0 C1 h; p0 Q* `/ h9 f
1846010 ALLEGRO_EDITOR SHAPE Changing MCAD hole to copper spacing in Analysis Modes - Design does not make shapes out-of-date% i+ n, t: @/ U, }) b
1839119 ALLEGRO_EDITOR UI_GENERAL On some machines, PCB Editor hangs when launched with a script that uses SKILL to open a design
/ D9 Z0 u6 r& y3 d8 U3 L1828794 APD SHAPE Setting Shape Fill Xhatch Cells option to HIGH, crashes the application0 c* b$ n3 l: g6 \+ F T7 |
1840748 CAPTURE PROJECT_MANAG Capture crashes on opening or creating designs8 |8 S3 ^1 F% @$ i0 F+ A
1785298 CONCEPT_HDL CORE Incorrect object access during variant load
+ t ]) r' b+ m! {7 g0 a+ {: }8 |1832119 CONCEPT_HDL CORE Save Hierarchy shows ERROR(SPCOCN-2010) messages but design packages without error
7 B1 G% C- F9 |7 b- b1 k" Q1833036 CONCEPT_HDL CORE nconcepthdl crashes with a core dump when running an external script2 U o q {- M6 [
1841545 CONCEPT_HDL CORE NO_XNET_CONNECTION properties added to two-pin filters after upreving to release 17.2-2016# T( D: x! a. P1 d
1842289 CONCEPT_HDL CORE Opening a schematic in release 17.2-2016 causes the .dcf file to be overwritten$ z0 f6 S- r; C5 T4 N
1841543 CONCEPT_HDL OTHER DE-HDL crashes when changing a net name/page name/bit bus after installing release 17.2-2016, Hotfix 029
! l; e$ h/ F) x; V1843791 CONCEPT_HDL OTHER Table of contents listing does not update for some hierarchy blocks at the top level1 \ c. W& [" D& o1 x' P% h
1850709 CONCEPT_HDL OTHER DE-HDL crashes on editing text on canvas in release 17.2-2016, Hotfix 030; y& `$ {5 p, w" q0 L% Q0 e
1853377 CONCEPT_HDL OTHER DE-HDL crashes on trying to edit bus tap value on Windows 10.
5 T# g, b" V! A. r. a2 M0 y1857213 CONCEPT_HDL OTHER DE-HDL crashes when changing Power Property
: E. d' d3 H5 W# o% i x" W1857214 CONCEPT_HDL OTHER In release 17.2-2016, DE-HDL crashes on using 'Change' for a $LOCATION text value on Windows 104 v) X6 [) ?8 r1 h- T" y8 D- y9 y: [4 Z
1821982 CONCEPT_HDL PDF Pin number shown in PDF published from DE-HDL: k; K- Y8 c! k& \1 q2 z5 E: h
1848615 CONCEPT_HDL PDF PDF Publisher shows incorrect pin text values for parts* R1 q' m# Q3 u. p$ N1 K+ \
1845996 CONSTRAINT_MGR CONCEPT_HDL Confusing error message regarding 'Auto XNets Off Mode' vs 'DML Enabled'
$ I) w1 I# q3 e7 M, j8 m# t1854190 CONSTRAINT_MGR CONCEPT_HDL 'Audit - Electrical CSets' hangs Constraint Manager after the design is upreved to release 17.2-2016
& Q d, [# t5 w4 u5 ?1854868 CONSTRAINT_MGR CONCEPT_HDL Match Group getting deleted after upreving the design to 17.2 and removing the signal_models
; l, t0 b" X) U1854872 CONSTRAINT_MGR CONCEPT_HDL Additional Pin-Pairs getting created on the DiffPair after upreving to 17.2
7 j% S9 `- t& { T6 ~) W( t, f1822624 CONSTRAINT_MGR ECS_APPLY Cannot copy PCB net schedule from a net to other nets) ?, N& l; ]7 Y: V. l+ _% O8 K. ~
1854883 CONSTRAINT_MGR ECS_APPLY Match group showing 0 length for pin pairs in design upreved from release 16.6 to 17.2-20166 g* V5 ]$ O2 S: H' Y% s' M
1855893 CONSTRAINT_MGR OTHER SigXplorer extraction crashes PCB Editor
" h; F9 U i; @* i5 M# T$ ?5 K" L1855917 CONSTRAINT_MGR OTHER SigXplorer extraction does not extract constraints unless the worksheet is opened once in CM
4 ^4 n" k- I2 J9 x1855350 CONSTRAINT_MGR UI_FORMS Constraint Manager significantly slower in release 17.2-2016, Hotfix 031- l# y! I$ _: ?7 x
1855860 EAGLE_TRANSLATOR PCB_EDITOR Cannot invoke a CAD translator in PCB Editor- l, A$ s m! b" d. l0 u) K
1857745 EAGLE_TRANSLATOR PCB_EDITOR A CAD translator does not invoke in PCB Editor
8 o& t) V# R4 J& K9 p$ a& [/ f, B1859005 EAGLE_TRANSLATOR PCB_EDITOR Eagle translator is not invoking at all
& k# l' G& |; r; V% l9 w) t) }& D6 v( O1843091 F2B DESIGNVARI Variant Editor allows mismatched JEDEC_TYPEs in release 17.2-2016+ `4 R* ]' E( P; U
1719059 FSP DE-HDL_SCHEMA Termination resistors on buses not being drawn efficiently
1 M, z6 Q, l4 ?# V- @! d1823419 FSP GUI Net Name Template not visible in Change Net Name in Windows 10
, V! v, p. e, H$ X5 { R3 C! X. d7 b1480035 ORBITIO ALLEGRO_SIP_I Die symbols are mirrored when imported back to SiP Layout' t) u/ ]4 M9 M x3 c
1853331 PCB_LIBRARIAN SETUP CPM file not updated from PCB Librarian setup+ J% K! n" _4 B' B! `" w, v
1841308 PCB_LIBRARIAN SYMBOL_EDITOR Symbol not updated in Library View
9 P, Q& z, Z: B6 c8 g1831269 SCM OTHER Blank properties of associated components are being filled with NULL( \4 `! L: |5 [3 S; T* s: j) |
1719057 SCM SCHGEN Pins off grid for voltage nets
( a: _8 _9 B6 O" y% c: N) i4 z1719060 SCM SCHGEN Pull-ups and pull-downs showing upside down in view
) X+ V% u0 o/ w- | m1732687 SCM SCHGEN Schematic generation deletes IO ports; says it's placing them on last page, but never places them* L6 N( N! V& K6 {7 G$ y
1855932 SIG_EXPLORER OTHER For non-DML designs, SigXplorer defaulting to mils when PCB Editor design units and CM constraints are in mm* `% j d9 T$ P- e7 u) p: ^
1824035 SIP_LAYOUT WLP SiP Layout DRC GUI not reading Tcl blocks in PVS DRC rule deck; H8 V, Y/ G( F& u4 P) V
8 N: {& R) S0 U/ l/ d
/ e! m2 Z: O( L* s/ K' IFixed CCRs: SPB 17.2 HF031/ \6 X# r3 [4 P
12-8-2017
5 Q! Z8 k4 C Y7 e1 o2 e========================================================================================================================================================/ G# _- N; e$ z2 v& G+ ]
CCRID Product ProductLevel2 Title f, R, Y+ [: u
========================================================================================================================================================
! n% Y- E5 V$ y! G+ f1746108 ADW DBADMIN Adding and then saving a custom rule set in rule manager results in corrupt rules.xml
* T! B- o/ r( J( `9 k1609983 ADW DBEDITOR dbeditor should automatically change mechanical kit names to uppercase
" i# C; B" c- h. T! o7 V1807139 ADW DBEDITOR Cannot add new properties, though the new properties were shown in dbeditor( R; R, A- H/ u) d9 k( G
1807410 ADW LIB_FLOW Checked-in parts not available in database
& D: Z# r/ t8 R+ Y {) H1797408 ADW TDA TDO crashes without displaying exception during check-in
/ K7 R0 I1 s6 C& o8 U* v; m9 R9 T, B1804500 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas fails to show all placebounds of a .dra, K) K& Y; u+ M
1810758 ALLEGRO_EDITOR 3D_CANVAS 3D Viewer represents symbol incorrectly in hotfix 025 but as expected in hotfix 024* x0 R% [9 c& w3 Q; [; J; `
1795567 ALLEGRO_EDITOR EDIT_ETCH Route menu has same hot key for 'Connect' and 'Convert Fanout'' s; A: p) C$ n
1796525 ALLEGRO_EDITOR EDIT_ETCH AiPT is not pushing dynamic shape to add bumps to resolve dynamic phase DRC c8 b' ~# c) ]! h$ l5 x* S- z8 R
1818170 ALLEGRO_EDITOR EDIT_ETCH Fanout with Outward Via direction is shorting few pins4 B! B6 {3 L" Y+ Q/ E' s
1712658 ALLEGRO_EDITOR INTERACTIV Add connect: Pin remains highlighted even after choosing 'Done'
+ i" e Q2 x" c1 N2 i( A' r' E1727193 ALLEGRO_EDITOR INTERACTIV Logic - Part List truncates device names to 64 characters though database allows longer names/ u$ F6 F D5 n$ N6 j7 u
1775484 ALLEGRO_EDITOR INTERACTIV Choosing Next with persistent snap in Show Measure disables persistent snap* M; G4 m1 I/ }; U& x; g
1711860 ALLEGRO_EDITOR MULTI_USER Multi-user lock cannot be cancelled: R( d: W6 `: _2 y
1812448 ALLEGRO_EDITOR NC Crash when canceling NC Parameters dialog G$ u9 c. b# ?% X5 M( S' o
1792987 ALLEGRO_EDITOR PAD_EDITOR Pad Designer does not recognize flash names longer than 31 characters
' k% w8 n: ?: C! n( Q2 I1810958 ALLEGRO_EDITOR PAD_EDITOR Padstacks with offset holes$ j# F+ r" E8 L8 n6 _
787024 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in regions2 |+ ~5 z U: w% E# U3 v
793232 ALLEGRO_EDITOR SHAPE Line to Shape spacing rule outside region affects shape void in region6 d; V1 P% [0 W. J5 x6 ?
797245 ALLEGRO_EDITOR SHAPE Line to Shape Spacing with Region not followed
0 C5 V0 q; D& ^( Z8 P865822 ALLEGRO_EDITOR SHAPE The autovoid functionality should use the true line-to-shape spacing value- V1 p. ^4 D7 {# B( p2 m
912051 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in regions
3 d5 G! T9 B/ ~+ w$ D965714 ALLEGRO_EDITOR SHAPE Region constraints are not working correctly on dynamic shapes8 Z( L" S. J3 ~. i
968342 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region is taking conservative value and not the actual spacing value( r; U7 H* K4 [0 z, M
974734 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
2 C5 R: L: m1 p. X @* s0 u1 t& w1073908 ALLEGRO_EDITOR SHAPE Allow line to shape spacing in Region
" e4 g1 r9 s) j; K1154787 ALLEGRO_EDITOR SHAPE Region constraints not applied correctly to dynamic shapes
$ K1 A6 k. R8 C& r) x) n, V: L1171283 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
' ` o8 x& H( H: g6 E( E- [1181767 ALLEGRO_EDITOR SHAPE Allow override on line to shape spacing in Constraint Region
* f, t/ z+ J9 P6 t1183792 ALLEGRO_EDITOR SHAPE Allow override on line to shape spacing in Constraint Region
2 R3 N: g4 |; H' @2 Y; n1186210 ALLEGRO_EDITOR SHAPE Line to shape spacing constraint does not follow the Constraint Region value# _( m/ u' A' r1 @, J
1192312 ALLEGRO_EDITOR SHAPE Region constraints are not working correctly.; k- B9 P$ G4 Y; {
1387021 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in Regions
0 x/ F5 J/ ?4 U1447891 ALLEGRO_EDITOR SHAPE Resolved constraint and actual air gap differ5 _( R K: c. G& G* A+ Y' [
1465383 ALLEGRO_EDITOR SHAPE Line to shape spacing constraint does not follow the Constraint Region
0 B% ]& |' f2 f) n" v |3 F s+ \' V1583144 ALLEGRO_EDITOR SHAPE Line to shape spacing inside the constraint region does not follow region rules
( l$ `- r+ V- h' c$ f& A0 v1591320 ALLEGRO_EDITOR SHAPE Resolve shape to pin constraint in constraint region8 T# j+ ^- E! {9 v3 U: Z9 B; O
1627305 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value0 x+ N& y* v3 g# |
1694552 ALLEGRO_EDITOR SHAPE Constraint region not working correctly' Y4 O' C! D) S& h( v* D
1764474 ALLEGRO_EDITOR SHAPE Line to Shape Spacing for Region should be used inside region instead of conservative value
" M+ q8 y. ~! ~1775119 ALLEGRO_EDITOR SHAPE Shape voiding is not following constraint rules for dynamic shapes in a constraint region
- @" j X4 o( V3 f" F1784916 ALLEGRO_EDITOR SHAPE Shapes are not voiding to other shapes against DRC settings, creating random DRCs.
4 y7 e, K! h8 ]& e' F% A1793179 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
* G. X* _+ Q4 ]8 N7 q- G- j& P9 ^1803365 ALLEGRO_EDITOR SHAPE Region shape to shape constraints take precedence when shapes have multiple constraints
* v( M; j. ?0 C+ R0 y0 W1800530 ALLEGRO_EDITOR UI_FORMS 3D Anchor menu missing when using new style OrCAD PCB Editor menu
6 w* K+ i! b# @6 t- Y1813604 ALLEGRO_EDITOR UI_FORMS 3D Anchor View is not available on OrCAD PCB Editor menu.
% B* A! i8 c6 d0 @* Y2 k2 [1784710 ALLEGRO_EDITOR UI_GENERAL During Place Replicate and saving file with same name, the warning pop-up window does not show on top/ j& g A4 S) q) _ I$ `7 A4 x7 L
1784728 ALLEGRO_EDITOR UI_GENERAL During Place Replicate and saving file with same name, the warning pop-up window does not show on top
1 K; B. u; t5 U: [7 x. M1721853 ASDA CANVAS_EDIT Movement of components results in shorts and inconsistent routing
: X$ @* C! Z. }1802120 ASDA CONTEXT_MENUS Ports are selected though filter is set to Components
- o# ?. }5 x$ N1 J1 F1803832 ASDA MISCELLANEOUS Browse and select new libraries without editing cds.lib& C0 g2 l( ~( o0 s E9 [- A M- T/ y
1804643 ASDA TABLE Exception when pasting table data from third-party tool in SDA/ B" _# a' q3 {8 O
1794004 CAPTURE LIBRARY Diode pin numbers different in Capture in release 16.6 and 17.2-2016; J6 x+ v0 r2 M' }' H4 B. g; ~7 [
1735506 CAPTURE OTHER File menu is missing in Capture7 D. g" R% l, r2 [6 x6 _
1766663 CAPTURE SCHEMATICS Capture crashes during part placement
$ ^ J* v4 Y" N6 h% i) p* k& E Z1762181 CAPTURE SCHEMATIC_EDI Crash on 'Push Occ. Prop into Instance'
2 M, ]5 [6 d* R: y/ ~1786762 CAPTURE SCHEMATIC_EDI 'Remove Occurrence Properties' and 'Push Occ. Prop into Instance' corrupt database m( k7 W3 Z, v! y) E& X0 ^
1759424 CIS PART_MANAGER Unable to save the link database part from part manager" b; ?, s0 h' N
1802670 CONCEPT_HDL CORE Variant commands take 6 to 10 hours to run on a block
% I! E1 S% S8 J) Q0 }1816798 CONSTRAINT_MGR CONCEPT_HDL CM API ACNS_DESIGN returns the design name in mixed case) j( N% T: H' X
1812656 CONSTRAINT_MGR DATABASE Constraint Value specified at the DEFAULT PCSet/SCSet is not shown in bold blue* o0 K$ r; [) b) t" ^. f
1635766 CONSTRAINT_MGR UI_FORMS Worksheet views are not changed as per input* h h. Q; | L( C6 g
1700505 ECW PART_LIST_MAN Shopping Cart Quantity is not read or not displayed in Pulse, }3 W/ c1 R( P7 \
1797371 ECW PROJECT_MANAG Clicking on another project sometimes takes you to the default project instead of the project you click on6 T4 [9 A: K8 w# v2 `8 E9 n/ G
1843526 INSTALLATION TRIAL Trial installer should not check disk space in update licensing mode
& ]6 O/ s* H! z5 o; w: g+ ]* ^1762148 PCB_LIBRARIAN SETUP Part Developer: Text not readable in Setup form
0 g! Z2 v* E! A; R1770760 PCB_LIBRARIAN SYMBOL_EDITOR Symbol Editor does not remember the last size of the window$ ~" T$ a4 b* s& u9 c
1773604 PCB_LIBRARIAN SYMBOL_EDITOR Option to switch between the new and legacy Symbol Editors
' s$ T/ n/ F6 M1800354 PCB_LIBRARIAN SYMBOL_EDITOR Resistor has too many lines and looks wrong in new symbol editor4 X$ O- h% h( u& @4 z: W
1813346 PCB_LIBRARIAN SYMBOL_EDITOR Resistor looks different with multiple diagonal lines in new Symbol Editor but looks normal in DE-HDL
3 n4 | _; j0 B& V7 [* N" q1815279 PCB_LIBRARIAN SYMBOL_EDITOR Unable to change Grid Settings from Lines to Dots
2 j# t" e3 \$ s, _1738603 PSPICE DIG_SIMULATOR Release 17.2-2016 PSpice digital model: Delay defined by PINDLY is not taken into account
: Z( g1 b: m6 N0 e6 w; W1802905 PSPICE ENCRYPTION Incorrect option shown in PSpiceENC syntax in usage detail
$ e. a: O2 z7 T( N* L1765345 PSPICE ENVIRONMENT Custom distributions are not added to the dropdown5 i. k: l0 J* Q
1784856 PSPICE ENVIRONMENT PSpice ignoring directory changes for Save check point in simulation setup session
( v2 ]/ z7 Q0 h0 a W0 n1817805 PSPICE ENVIRONMENT Incorrect result for PSpice 'Start saving data after'
6 k9 }% l5 X5 | p, D( k1784507 PSPICE FRONTENDPLUGI Spelling of 'Definition' in PSpice Part Search is not correct% D' @: Z, e% M: m3 P+ G) l
1801790 PSPICE LIBRARIES SAC model giving errors8 |0 [ W. s5 _/ L& Z5 R$ E; `$ q
1738776 PSPICE SIMULATOR PSpice simulation stops before TSTOP
% O9 u! _& A. ?& q0 g1795950 PSPICE SIMULATOR Simulation cannot be completed in release 17.2-2016 but is completed in release 16.6 Y4 c1 P9 a7 P; H( e8 q8 A& d
1803407 PSPICE SIMULATOR Getting convergence error on a model
# w4 c8 w1 }, Z( m% a+ C$ l1814759 PSPICE SLPS .INC file is not working with SLPS
4 Y* D# `# [: P$ k2 \1 Z. N1715859 SIP_LAYOUT ETCH_BACK Etchback mask not overlapping each other; creating floating metal. J4 C/ ^' Z% z$ M7 {0 j) I
1729523 SIP_LAYOUT INTERACTIVE When creating a bond finger solder mask the results do not match the required settings
. ~+ {/ E* d( `- A1800069 SIP_LAYOUT INTERACTIVE Corrupt dra/psm symbol, but the reason is unclear
/ T) Q3 ^, M+ r' a5 O% M1756620 SIP_LAYOUT SHAPE Performance issue when moving vias.1 Z( ^. U. U) G8 i2 U6 Y
1782928 SIP_LAYOUT SHAPE Shape merging (logical operation) shows error though measuring shows elements are correctly spaced
% V3 k5 d' ?% c; p1816454 SIP_LAYOUT THIEVING Thieving: need thieving as a specific data type in CM to better control the filling pattern8 e3 c8 D9 Z' Q) d/ j: N
1728026 TDA CORE Check-in should not require all child objects to be checked in specially if they are not checked-out# }8 J: w3 b! s" @& k. I
1823976 TDA SHAREPOINT Connection to server terminates when joining a project
3 u }. X& x0 h* M& ~" l! `$ S2 U `1 B8 v
. j% o2 P8 Z* Q5 S* o z. J
Fixed CCRs: SPB 17.2 HF030
6 F% J3 ~, E1 t4 E+ P6 C; Z& W11-17-2017
$ g( T1 G$ `$ m. r) @========================================================================================================================================================
" l( r- U% H$ x) \% g w* ^+ z, SCCRID Product ProductLevel2 Title
6 o0 j1 x' `3 Y# f- O3 t# s" P9 e g========================================================================================================================================================0 S |" e: P+ c5 h r
1821774 ADW DBEDITOR MPN is tagged Pending Purge after deletion and lib_dist/ D# X; N; p2 l7 j" b/ _& q
1829549 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase DRC marker displayed at the design origin; t3 D4 h( n4 l2 }. N
1690998 ALLEGRO_EDITOR INTERFACES Runtime error when running PDF Publisher
/ u& |/ q6 X. X. o% n, p1805203 ALLEGRO_EDITOR INTERFACES Runtime error when exporting smart PDF on a large board with all film layers selected
$ W1 f% r( a! ]' N1811698 ALLEGRO_EDITOR INTERFACES Runtime error while exporting PDF$ A+ u3 q Z/ {8 Q
1823818 ALLEGRO_EDITOR INTERFACES Cannot map some step models0 W) h4 h; @) V( e! u0 u, H
1750654 ALLEGRO_EDITOR MANUFACT Cut marks cannot be generated on cut outline.
. X! s) F! I: w; K& S1828293 ALLEGRO_EDITOR NC Incorrect status returned for backdrill
3 u: T7 Z; J4 a7 _" A1825401 ALLEGRO_EDITOR PADS_IN In PADS library translation, pads_lib_in fails to create Placebound_Top as a shape
6 g9 J, N. ^% W8 y$ i3 }; l a1825427 ALLEGRO_EDITOR PADS_IN Symbol drawing files (.dra) created after PADS Library translation are not getting renamed to their decals9 m% k; y( T1 j% f5 D
1825460 ALLEGRO_EDITOR PADS_IN Pins are moved from their correct locations during PADS Library Translation8 |& ~5 g/ Z! |) T$ T
1831200 ALLEGRO_EDITOR PLOTTING Incorrect PDF output for traces) A$ ^- ?3 V( U. H
1321314 ALLEGRO_EDITOR SHAPE Force update of dynamic shape generates thermal tie that causes net to short
" R9 M: i9 Y1 A3 [% O1647585 ALLEGRO_EDITOR SHAPE Void around holes is not circular but of the shape of the bounding box q2 g8 G8 h* A, W6 ^
1830676 ALLEGRO_EDITOR SHAPE XHatch Shape not voiding properly1 o7 y2 S+ D% k% s
1821286 ALLEGRO_EDITOR SKILL Using axlSetParam to set static shape clearance parameter crashes PCB Editor( y# H- B5 K$ y, G& j: A! v
1804662 ASDA DARK_THEME Dark Theme: Change color of selected cells in Rename signals dialog so user can see they are selected
8 H7 Q" k: ]8 L3 {$ g5 `0 y, H1817486 ASDA NEW_PROJECT Need to save a project with a new name, 'copyprojectas' does not seem to work
! F: i P6 \+ W+ o/ T: J+ a9 P! X1826023 ASDA NEW_PROJECT SDA requires user to go into project settings window twice to add a library! K9 k" ~ d: P* A; n6 ?9 N. }
1830632 ASDA SCRIPTING SDA crashes when you type 'find -types' in the Tcl command window
+ r8 Z$ C" u- B* {7 b: z, h" e+ E1798864 ASDA VARIANT_MANAG Retain default part visibility when substituting preferred part for variant
- l F4 k$ @% I% e$ k1 {1798865 ASDA VARIANT_MANAG Value attribute of variant is off while printing though on for default and view
' h& x0 m5 @- P0 }4 L* P2 v1798866 ASDA VARIANT_MANAG Variant Printing: Pin numbers printed though set to off on default part# N) B# r( h2 S( @( @9 }, d% l, N4 q
1831836 ASDA VARIANT_MANAG Cannot delete existing variants in design
6 A0 y, m/ f) J1821120 CONCEPT_HDL CORE SIGNAL_MODEL attached to a component is not displayed on the canvas in the Attributes form
3 H; ~ _# x7 T% D9 `# r7 A1824714 CONCEPT_HDL CORE Display issue: Page border disappears when running the command _movetogrid
+ Y/ L' o, ~# A, t: T( C1822587 CONCEPT_HDL CREFER CRefer crashes on a hierarchical design using split blocks
; Q% v% m; ~1 r7 V; p; }$ J1825461 CONSTRAINT_MGR CONCEPT_HDL Uprevving to release 17.2-2016 adds NO_XNET_CONNECTIONS on components having custom models
F4 L. v' j Y1825968 CONSTRAINT_MGR DATABASE cmxlGetObjects returns all the aliased nets and the physical net that goes to the netlist
/ E0 _' J& K0 r) L0 J5 H7 _5 v1819622 CONSTRAINT_MGR XNET_DIFFPAIR Discrete with NO_XNET_CONNECTION removed from topology when extracted with Routed Interconnect, C% e/ h* l5 Z: f2 ]1 c% N
1829762 ECW PROJECT_MANAG Pulse log in: Multiple processes triggered, generating many zip file packets and corrupting many of the packets
8 N2 K& s8 l8 U+ f1810296 F2B BOM BOM includes status column, nothing should ever be forced on a users BOM output
/ M: M5 X; T6 z) `1 R. [& ]1824593 F2B PACKAGERXL PXL crashes and removes the pxl.log file from the Packaged directory; r& c( |, E8 j8 A
1832005 F2B PACKAGERXL Message stating 'PXL has stopped working' when packaging design: U1 z- P/ _) c. [( A
1822912 RF_PCB AUTO_PLACE rf_autoplace fails for RF component containing variable7 _* Y5 I' N/ ?7 L
1803731 SIP_LAYOUT DXF_IF DXF export from 'Component Geometry/Pin_Number' subclass not working in release 17.2-2016% T4 B; y4 I0 ^$ T. n. D# }
1825478 SIP_LAYOUT SHAPE When running the Shape Islands report it is listing all the Fillets as Islands& {& Z, D. N1 T; m9 D( F$ J
2 J& {# o* I8 h) \, D
g A$ d- ~! l0 t8 KFixed CCRs: SPB 17.2 HF029
2 X. n0 }4 j' Y" F11-3-2017- f3 p' E. F+ T u- y5 ]
========================================================================================================================================================, G" F7 e4 V0 Z0 O$ q
CCRID Product ProductLevel2 Title3 l: F5 R) h$ l# J1 |4 e
========================================================================================================================================================7 s2 @' G. M% i# Q. ~9 u: H. i
1814597 ADW DBEDITOR Associate part classification is very slow in release 17.2-2016 of Allegro EDM
3 w4 A% S- A4 q. a- n1733482 ADW FLOW_MGR After installing QIR3, Flow Manager prompts with Java Help question
1 T# _! W$ O( e, L1814789 ADW PART_BROWSER PTF shows data in old component browser but not new component browser
/ j2 i0 J2 w0 k# I1808620 ALLEGRO_EDITOR DFM Missing graphics in new drc browser.
! L W( O! F1 Q4 B9 s# L9 K1814558 ALLEGRO_EDITOR DFM Silkscreen checks do not work if silkscreen is defined as mask in cross section8 w% x& C1 m0 v4 D- B" j
1807996 ALLEGRO_EDITOR EDIT_ETCH Route Clearance View is not using the correct spacing constraint when nets are partially routed in a region, M8 t% ]3 [0 Q, F* _, J
1747929 ALLEGRO_EDITOR INTERFACES Cannot import logo/bmp on a .dra file, C5 O$ q; I* D+ z: [+ Z$ ?
1820142 ALLEGRO_EDITOR INTERFACES pdf_out command not supporting UNC paths for the output pdf file
* @7 ?7 \; [6 S8 B1671865 ALLEGRO_EDITOR MANUFACT Exceeding 20 characters in Artwork Control Form - General Parameters - Prefix displays 'Illegal Character(s)' error, T3 O( r/ B% K8 J, I
1710032 ALLEGRO_EDITOR MANUFACT Adding Artwork prefix gives error for illegal characters
0 H2 k2 d- G4 s) R* v1714911 ALLEGRO_EDITOR MANUFACT ERROR: 'illegal character(s) present in name or value' while adding prefix in Artwork Control Form, s$ r: E9 y, s9 a' e
1813950 ALLEGRO_EDITOR MANUFACT In the drill chart, the titles 'tolerance_drill' and 'tolerance_travel' seem to be reversed4 L6 @: h3 e* g* F S0 N
1820970 ALLEGRO_EDITOR MANUFACT IDX_EXCLUDE and BOM_IGNORE excluding objects from IDX export, H* H3 T; ^/ m: L- S6 |" r/ U1 r' w
1822045 ALLEGRO_EDITOR PARTITION Shape fillet becomes static shape and loses fillet attribute after importing partition. o/ s# _- S( q6 |$ L G x0 ?
1776181 ALLEGRO_EDITOR SHAPE Placing via arrays around a differential pair places vias only for one net" N+ t+ z v7 m! s, O& h8 v- \
1817283 ALLEGRO_EDITOR SHAPE Allegro PCB Editor Show Measure Air Gap shows a very large number
3 s0 E& C% w. t1 |( q1815595 APD DRC_CONSTRAIN Differential pair spacing constraint not propagating to physical cset nets0 s! r. Z4 H0 j4 E
1785116 APD SHAPE Big size die performance issue, p* ?( X' ]( Z8 b( l2 x; r, Z
1811134 APD STREAM_IF GDS stream out with 2000 precision has sharp edges along shapes.
: G, E" c+ q3 Z% q1811882 APD VIA_STRUCTURE High-speed via structure refresh fails e3 q/ T+ o5 L. K' f8 i
1814878 ASDA DARK_THEME Part Manager: Difficult to read black text on black background
9 u# u+ `: Q" O' P! z& O) S1814889 ASDA DARK_THEME Change 'updating route in progress' message color: a bright orange bar in dark theme is difficult to read
' b7 Q2 u# U! z% p. r1817355 ASDA PAGE_MANAGEME Double-clicking a library in project preferences library does not move the library but changes appearance
( G6 u) U( g; m( E1817964 ASDA SHORTCUTS User Preferences shortcut misspelled
. D5 }( q2 r% z" p1820247 CONCEPT_HDL CORE DE-HDL crashes while saving a design
/ V7 R1 L3 R* F3 \* v8 q1823187 CONCEPT_HDL CORE DEHDL allows editing of the locked component's refdes using change text editor
7 z' S8 t6 c4 N3 m. Y7 H$ g1824052 CONCEPT_HDL CORE Trying to edit on a group containing a LOCK component, deletes the packaging data on the schematic
/ L1 K6 b" R! w2 h5 B1813987 CONSTRAINT_MGR OTHER PCB Editor crashes when Constraint Manager is closed7 a P5 w$ k& d7 x0 N6 {) A
1821129 CONSTRAINT_MGR XNET_DIFFPAIR Uprev to release 17.2-2016 adds unwanted NO_XNET_CONNECTION property to discrete symbols
" ~ I/ p: m3 W( C0 W1814725 PSPICE PROBE PSpice Measurements crashes PSpice for a digital simulation
) {! F5 p6 i$ h/ u$ r1808672 SIP_LAYOUT INTERACTIVE create bounding shape command options: 'Min Area' and 'Sync with shape layer'0 l5 J6 O5 g2 h3 H
1817458 SIP_LAYOUT MANUFACTURING Error in DXF conversion after updating SiP Layout from Hotfix 066 to 082 in release 16.6
" U* V2 j6 d, i. P
2 M- c4 f v6 A) \- Q
# B# E2 I1 A/ ^6 z$ `5 l4 [Fixed CCRs: SPB 17.2 HF028* J1 `( p& {4 [ N$ R' K3 r1 z/ a
10-14-2017' B: `4 {( X; s
========================================================================================================================================================
; ?" p& q/ l+ `; R# NCCRID Product ProductLevel2 Title
! T3 G) m5 K( F1 a7 ~========================================================================================================================================================" D5 M8 m/ t" O# T% f( C F" U* c
1773530 ADW FLOW_MGR DE-HDL hangs on importing components from another design or copying and pasting components within a design
* A2 V' u8 ^1 g$ S! T/ J1790584 ADW FLOW_MGR SKILL code for comparing two PCB Editor .brd files does not work in EDM in release 17.2-2016
( k* C) [$ Z l; G3 i$ B1794116 ADW FLOW_MGR LRM fails to run on project& O Y$ w6 V; J+ H+ I2 ]+ O P
1811532 ADW FLOW_MGR The message for missing tools.jar should not appear in adwcopyproject.log
" I: O3 R& T, s* L& o1812109 ADW LRM Library revision manager displays errors while re-importing updated sub-blocks* Y3 Q' w: C$ h4 b/ n: q9 Y, N
1771851 ADW PCBCACHE Problem in packaging upreved imported block
. m6 a3 K2 Z4 W$ p1814785 ALLEGRO_EDITOR 3D_CANVAS PCB Editor crashes when a bend is created and then viewed in 3D Viewer
4 O. A: A# x, |% i: W( t1800131 ALLEGRO_EDITOR DATABASE allegro_downrev_library utility fails on Windows 10- W- o- f. e0 E# A7 O2 q
1814607 ALLEGRO_EDITOR DFM DFM check for soldermask does not include Package Geometry/ Soldermask if the soldermask is part of stackup& N7 q. `& v+ W
1813996 ALLEGRO_EDITOR EDIT_ETCH Add Connect crashes PCB Editor if clearance view is set to channel/ f2 v# a8 O: m, O- H/ v
1810832 ALLEGRO_EDITOR SCHEM_FTB Error while doing Export Physical from DE-HDL to PCB Editor
* a9 B7 c w0 C. c- u& U9 e, {1811785 ALLEGRO_EDITOR SCHEM_FTB Import > Logic > Import Directory does not resolve the relative path to the packaged folder) x6 H5 y8 e/ O2 B8 W/ s
1814166 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version of database
+ F/ M: _ F: }" _( i1817891 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version6 w7 ^! Z3 |( O) [7 A4 a4 X/ D
1818954 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version of database; I; Z8 V/ `' z1 I7 [% P
1812808 ALLEGRO_EDITOR SHAPE Artwork is different from PCB board' X( d! L/ ]6 |
1814836 ALLEGRO_EDITOR SKILL Doing zcopy Xhatch pattern crashes PCB Editor in release 17.2-2016
) u) L6 p/ B0 r) E8 v1772218 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding on Show Element# a, W! F+ N* T2 x x0 t& c4 B
1778353 ALLEGRO_EDITOR UI_GENERAL Intermittent PCB Editor crashes on loading IDX in release 17.2-2016 Hotfix 020$ W& ?8 ]$ q+ Y& c- D; x* r
1818077 ALLEGRO_EDITOR UI_GENERAL axlViewFileCreate disappears behind window or is blank
+ p2 I! C6 Z) { a3 D1807423 ASDA NEW_PROJECT SDA CPM file has erroneous date( x0 V: Y! u! P2 o
1809597 CONCEPT_HDL CORE Problem auditing SI model in Allegro Design Entry HDL from Hotfix 025 onward, no problem in Hotfix 0246 q* [8 u8 E3 L$ F% g
1810322 CONCEPT_HDL CORE Unable to package design if OK_NET_ONE_PIN property is set
7 a$ C7 {4 o4 k' P1813436 CONCEPT_HDL CORE Read-only block import issue in same session: displays error message SPCOCD-553
0 I, q5 N6 M, ]' U+ t1813912 CONCEPT_HDL CORE The response in DE-HDL is sometimes extremely slow/ j' q7 A: h7 e' v
1812506 CONCEPT_HDL INTERFACE_DES Error messages during packaging followed by a success message though there are errors in design
* i( K2 W& A5 l/ Q1808677 CONSTRAINT_MGR CONCEPT_HDL Auto-generation of differential pair finds several instances of the same net1 v0 R3 u/ i, n: _% _5 \& i
1808898 CONSTRAINT_MGR CONCEPT_HDL Unable to resolve the ECSet mapping errors if the topology has pin of PINUSE POWER & GROUND
3 J2 S* A( I5 m& Y4 N" W* K1810320 CONSTRAINT_MGR CONCEPT_HDL DE-HDL - Constraint Manager: Cannot add group to net class if a net in group is a member of the net class
- T8 e& h# R6 w9 A) i5 p$ x2 X2 A* }1812459 CONSTRAINT_MGR CONCEPT_HDL Auto-generation of differential pairs has issues
S; M0 X( _3 Q. t1796234 CONSTRAINT_MGR OTHER PCB Editor crashes on query (ALLOW_ON_ETCH_SUBCLASS) without data type defined
$ \, L/ N' p4 h3 E( v& v1811692 CONSTRAINT_MGR OTHER Constraint Manager: Set Topology Constraints - Rel Prop Delay - Pins is empty in release 17.2-2016 Hotfix 026
0 n% [) t/ R, P% m' f1816311 CONSTRAINT_MGR XNET_DIFFPAIR Extracting a differential pair into SigXplorer crashes DE-HDL; `* [- ^- A) G) [: N( ^7 j8 t
1807593 ORBITIO ALLEGRO_SIP_I Die symbol shifts when importing die from OrbitIO to SiP Layout
# V4 Z5 }: i7 O) M7 g% N1800763 PSPICE SLPS Error while running co-simulation in MATLAB for PSpice-SLPS demo designs
; f# h/ k3 N9 d
/ u+ l% ~3 j, y! {- o E* M* f9 ~% C! ]0 e- R: ~- N
Fixed CCRs: SPB 17.2 HF027* A# a% ~4 q7 ]
09-29-2017
7 m. ^5 G7 y; J" |- ^========================================================================================================================================================* }' j7 R/ q; F: l( }9 }7 o
CCRID Product ProductLevel2 Title8 d8 @( c' d. o. W, P! N
======================================================================================================================================================== m, P0 A$ o" r, G4 P# A. \
1795353 ADW FLOW_MGR Tool unable to find project in windows_project.txt
, v$ q- c& K. P( ?8 t& C4 o1810386 ADW FLOW_MGR Error regarding not finding project in 'windows_project.txt'
% M P; p x' x* K Q4 |+ O: t' b& I1743732 ADW LIBDISTRIBUTI adwserver -install does not give error if it cannot connect to server." L" O* K' S; N G" `3 |- K3 v
1804378 ALLEGRO_EDITOR 3D_CANVAS Bend area issues in 3D Viewer9 l- b+ |/ r/ F$ j! x$ }! M0 e
1795312 ALLEGRO_EDITOR DATABASE Cannot unlock symbols as status is changed to View on opening design
: \- y$ e# i) }8 k1803262 ALLEGRO_EDITOR DATABASE Donut pad With DYN_THERMAL_CON set to FULL_CONTACT has connectivity issues
# J- x6 [; T, _0 D `- A5 O2 \1802183 ALLEGRO_EDITOR DFM Using mouse wheel to scroll error information in DRC Browser changes font size' R3 D y1 x# C
1797222 ALLEGRO_EDITOR DRC_CONSTR Updating DRC results in error 'SPMHDB-403'8 M0 _7 Z/ s7 m
1792163 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on moving components- N, R" [* n( x' Z% I. y
1806640 ALLEGRO_EDITOR INTERFACES Step Mapping not working in release 17.2-2016 Hotfix 025
0 n# p3 r7 g( N3 d9 e1807278 ALLEGRO_EDITOR INTERFACES Running 'step_export_product_asm.exe' displays 'vcruntime140.dll' missing error$ E7 X8 H' Q( s6 R/ K
1807286 ALLEGRO_EDITOR INTERFACES The facet file (.xml) for the STEP model 'modelname.step' cannot be found.! f( o5 E. V. {- i4 {7 y
1808006 ALLEGRO_EDITOR INTERFACES Facet file for step model cannot be found
; j; h2 A# |7 c+ ?6 d0 Y# {" h1704335 ALLEGRO_EDITOR MANUFACT Documentation Editor shows an error about backdrill while no backdrill was used in the design1 y" v$ s) N) e( q* K- K
1800115 ALLEGRO_EDITOR MANUFACT IPC2581 Export giving error that backdrill is out of date even though no backdrill is defined in the design
. p8 S# N, v }% z& M: l1799444 ALLEGRO_EDITOR PLACEMENT Via Array - Boundary placement fails with error) t& X1 S1 F" n7 G5 C- K
1725242 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape5 _- {% T# i. D, {- v! a
1804129 ALLEGRO_EDITOR SHAPE XHatch Shape not voiding properly$ b1 B/ S% U D6 f2 z( r2 Z
1805238 ALLEGRO_EDITOR SHAPE PCB Editor crashes while importing netlist& J1 s& [1 r, C( [0 a
1803542 ALLEGRO_EDITOR SKILL Using axlPadstackEdit to change drill size causes via net to change in release 17.2-2016 Hotfix 025" Z) Y) b1 M6 R& L
1800774 APD STREAM_IF Only one pad in GDSII when running 'stream out' with the Flatten Geometry option
& C' G! R. Y' x1804196 APD STREAM_IF Component is mirrored by X-axis instead of Y-axis on enabling mirror geometry
: p( a% c2 l" }& D5 [& a1803375 ASDA IMPORT_BLOCK Import HDL Block fails with message regarding Xnet states and DML independence
8 j0 J& q4 k2 i6 a% [" `+ @/ _1807423 ASDA NEW_PROJECT SDA CPM file has erroneous date
6 ~0 H7 G- f5 J5 r+ `. D1789400 CAPTURE SCHEMATIC_EDI Capture schematic opens unannotated pages on search
% y; R1 Y6 o( [6 O1801573 CONCEPT_HDL CONSTRAINT_MG Upreving release 16.6 design to 17.2-2016 adds NO_XNET_CONNECTION to some components9 V( q7 ?' b+ _! s& M9 R+ p
1810586 CONCEPT_HDL CONSTRAINT_MG DE-HDL crashes when transferring XNET properties to similar components in a read-only block0 _$ G4 U- ]9 O5 m( Q* N
1794169 CONCEPT_HDL CORE _automodel command crashes DE-HDL if PACK_IGNORE is set
4 B8 ^; M T1 @6 M7 u0 L; J, f1798672 CONCEPT_HDL CORE Dashes in design name creates an extra design folder in worklib after upreving to release 17.2-2016
: i& ]/ D; @0 O+ J$ O1802258 CONCEPT_HDL CORE Locking unlocked components results in a warning (SPCOCN-3403)
% w, q0 N$ d- X$ v1803019 CONCEPT_HDL CORE DE-HDL crashes on backannotation8 @8 E3 d: v& }2 x) Q1 T5 I2 K5 _
1803615 CONCEPT_HDL CORE After running 'Mark for Variant', the block cannot be changed to blue% H! T o. g) I, Z X* m ]9 ]
1804029 CONCEPT_HDL CORE Visibility issues when using the LOCK functionality0 h" D. S$ x8 U8 O( f
1806352 CONCEPT_HDL CORE Group Mirror is causing design corruption.
. L' Z5 e/ B+ z5 W( E1806978 CONCEPT_HDL CORE Cannot mirror a group of objects- K2 f; h5 ?( C8 o8 K0 f
1810387 CONCEPT_HDL CORE Mirroring groups causes erratic display and may corrupt database if project is saved
: P& i4 R( n+ Y1 U" y m$ W1812811 CONCEPT_HDL CORE Schematic group mirror not working. _4 @, t! q* ]$ G5 z
1810401 CONCEPT_HDL INFRA Add Signal Name: Cannot select suggested net name0 {$ \ ]4 t- m; f
1787409 CONCEPT_HDL PDF Minus character at the end of netname causes unexpected string concatenation during PDF Publish
- ?3 Z! x8 r% O& J% v& C' p1800931 CONSTRAINT_MGR OTHER Even after removing NO_XNET_CONNECTION on parallel termination, topology extracted has duplicate capacitors- \2 A( y. j8 j5 B
1790106 CONSTRAINT_MGR SCM Cannot find the constraints file (0) in the schematic project4 c" ~. S8 f4 ]+ A
1787117 CONSTRAINT_MGR UI_FORMS Creating bundle in Constraint Manager crashes PCB Editor8 o* j* n) I1 p- }
1797384 ECW METRICS Pop-up metrics value tool tip is translucent, making values hard/impossible to read( a( w. c% Q9 u$ ^$ p# J
1803226 ECW METRICS Pop-up metrics value tool tip is translucent, making values hard/impossible to read8 y% @; d1 x7 J" m8 B1 j) A1 }; Q
1664059 ORBITIO ALLEGRO_SIP_I Incorrect connectivity after .brd import5 ]; X- z# E8 T4 x7 p* I
1799338 SIP_LAYOUT DRC_CONSTRAIN Multi-threaded DRC fails with internal memory error even after setting shape_cache_size
& s! A+ |) F1 d' i" B- h1799499 SIP_LAYOUT DRC_CONSTRAIN Multi-thread DRC fails
/ m* d3 i; P/ C6 K0 p* Y `1806585 SIP_LAYOUT DRC_CONSTRAIN Multi-threaded DRC update aborted: internal memory resource depleted
5 L0 u5 Z0 W2 M8 D6 s7 q1809804 SIP_LAYOUT DRC_CONSTRAIN Error message while updating DRCs in release 17.2-2016 Hotfix 026 regarding shape_cache_size
" g1 c# S5 q1 P- v! V- I7 c! D1788770 XTRACTIM ENG Translated bump / ball conductivity is wrong (PowerDC and XtractIM)9 X/ h* t& e. s8 X9 y3 o
4 G8 O+ s, \+ N6 `0 |6 b: p2 V5 W- D
Fixed CCRs: SPB 17.2 HF026
$ z0 a8 g2 B4 [* V* Y! h9 G09-15-2017! ?* n' V4 }8 C- ~/ M1 B, C9 k% q
========================================================================================================================================================
* s! W1 r- Q. l/ Z' y aCCRID Product ProductLevel2 Title( N& o* P7 t( @3 `3 b
========================================================================================================================================================7 x+ X8 t( \% u7 a$ `
1765398 ADW DATAEXCHANGE Duplicate MPNs are created when updating MPN classification properties with data exchange
, K; g1 b4 C: }. J1780147 ADW DBEDITOR 'Associate Footprint from Tree' does not log the information5 N2 D( o+ |, m
1790134 ALLEGRO_EDITOR DATABASE Correct spelling in Layer Function definition
. O& }# t1 R% d, m# u; ^' L1792345 ALLEGRO_EDITOR DATABASE Pastemask is added to bottom layer on backdrilled pins
% t' k% K' T& u' P7 d0 E( L1792930 ALLEGRO_EDITOR DATABASE Uprev required for all libraries and padstacks to use release 16.6 DRA in release 17.2-2016! D9 D0 a0 u) t* V
1781203 ALLEGRO_EDITOR DFA DFA Spreadsheet Editor not starting from Windows Start menu
0 k! e& X' l/ W! \5 Q1797422 ALLEGRO_EDITOR DFA DFA Spreadsheet Editor not starting from Windows Start menu
% [0 I/ w8 z9 b+ Q, K1770694 ALLEGRO_EDITOR INTERFACES Incremental IDX does not place unplaced components2 N- @6 }' G' C$ w6 X3 v: `
1776791 ALLEGRO_EDITOR INTERFACES STEP file not displayed in PCB Editor for mapping
5 C5 a9 F/ c; I% Y) }1783515 ALLEGRO_EDITOR INTERFACES PCB Editor reading step model incorrectly5 j2 b* q' c& T; B( j% g3 B
1781485 ALLEGRO_EDITOR MANUFACT Setting ipc2581attrpath results in error 'E- ipc2581attrpath: Variable not defined'
9 ?7 x* l @: s0 }1772713 ALLEGRO_EDITOR MULTI_USER Allegro Symphony Server rejects group moves: |7 t" j# x; r' n& j3 @6 p" a, @9 A0 e
1789853 ALLEGRO_EDITOR MULTI_USER Symphony Server rejects updates and hangs frequently
q5 u7 t, Z, S6 v0 `1 `5 I1725591 ALLEGRO_EDITOR OTHER File - Export PDF crashes on the design attached
, F$ U/ y- m" m" Q; Q1736324 ALLEGRO_EDITOR OTHER Export - PDF fails to export PDF
W$ V. S% e z0 X4 B$ f1794071 ALLEGRO_EDITOR PLACEMENT The placement of component is very slow and takes around 3 to 5 minutes per component.1 T2 p& z7 o6 r/ M4 ]
1496199 ALLEGRO_EDITOR SHAPE Overlapping route keepouts result in a broken shape., @6 C/ `$ A, q6 |6 b$ b4 b
1760146 ALLEGRO_EDITOR SHAPE Void offset in Artwork but not in board for a particular instance only
* a( O) o* e: Y4 w/ V, ^1770372 ALLEGRO_EDITOR SHAPE Overlapping shapes merged in artwork shifts void causing a manufacturing short
$ A* B* }8 i. v- t' o7 T! X1 t% l1793419 ALLEGRO_EDITOR SHAPE Unexpected shape void in artwork in release 16.60 h! J& A( P5 ~) g* d. l
1796666 ALLEGRO_EDITOR SHAPE DRCs for out-of-date shape while placing single via! u! g# Q2 t4 q3 [' s! x9 V
1786386 APD EXPORT_DATA Exported dra and pad files do not have right stackup3 C5 H$ M3 u. S. G. U
1765673 APD SHAPE Shape in Cu1 and Cu3 cannot void correctly G& T$ I6 K' t$ w# Q
1782418 APD SHAPE Artwork is showing unnecessary horizontal lines
( {5 Q n$ Q% o. D' _* d1778366 CONCEPT_HDL CHECKPLUS CheckPlus not printing logic design name( k2 [; Z" D4 r! z
1723855 CONCEPT_HDL CORE Cannot use Rename Signal for unnamed wire segment if the wire has a branch to the same instance/ y4 T$ a$ z" A0 t* `
1755174 CONCEPT_HDL CORE Unable to create XNETs on the read-only blocks1 v1 S ^( I, f6 `$ r+ Y
1765533 CONCEPT_HDL CORE Strokes are slow to respond in release 17.2-2016
7 h7 l3 Q! P6 m) l1780253 CONCEPT_HDL CORE In Windows mode, with copy command still active and symbol on cursor, DE-HDL stops responding on pressing Delete key
. \% f" }" s8 Z" m9 D3 V+ N4 t1785069 CONCEPT_HDL CORE Warning box for SPCOCN-2251 needs to be resized and the text formatted correctly
; P, V' q* S$ Y0 w8 `1786030 CONCEPT_HDL CORE Packager fails in release 16.6 but runs successfully in release 17.2-2016
6 i) P! [, F7 Y, u. | [1788077 CONCEPT_HDL CORE Creating new window (new tab) in DE-HDL resets view of original window
& a3 S# W$ |* E# s9 l1788591 CONCEPT_HDL CORE Wrong pin number displayed after running packager
, ~9 i, h4 y3 I6 W0 a1776774 CONCEPT_HDL CREFER CRefer crashes without error entry in log file; W$ N, e9 h4 U% H
1328320 CONCEPT_HDL PDF Cannot select/search sig_name in published PDF
. W$ f( F1 y$ ^, c1787409 CONCEPT_HDL PDF Minus character at the end of netname causes unexpected string concatenation during PDF Publish4 A" k( |, o2 C: D0 L8 n
1758122 CONSTRAINT_MGR ANALYSIS Extracted topology for a differential pair is missing a pin-to-pin connection in the top file6 T+ y' i7 O! T$ V! v7 V! J
1786161 CONSTRAINT_MGR CONCEPT_HDL Random crashes in release 17.2-2016 while working on the schematic editor along with Constraint Manager9 V1 {0 K" \' m4 Q
1788877 CONSTRAINT_MGR DATABASE Constraint Manager API cmxlImportFile looks for sub-string during replace mode and not explicit names
$ x2 D, z6 O( d" a1 B* R1800263 CONSTRAINT_MGR OTHER DE-HDL and CM crash when deleting regions
# z& c* B% @; _1 E8 f1792000 CONSTRAINT_MGR UI_FORMS Data type of constraint not shown in GUI0 S7 y/ L# B3 ]; Y/ }
1744828 FSP CAPTURE_SCHEM Button appears during 'Generate OrCAD Schematics'4 G6 u+ s3 w9 t9 }# ?
1747568 ORBITIO OTHER Import of .oio file in SiP Layout takes a long time) O6 U% G8 g+ h7 D `# o0 D+ G
1765229 PSPICE AA_FLOW Not able to run PSpice MC after setting Assign Tolerance
, r- h8 o! T! U3 Y9 @1770174 PSPICE MISC Issues with DMI Template Code Generator
+ q' T* ]4 ]# R2 y& Z2 U8 K( x7 a! R+ B
2 ~, y- }* w V- E) W# Q
Fixed CCRs: SPB 17.2 HF025
* ^, C# \& Y8 H: F) m08-25-2017
0 P" M9 V* R( y, T" S& Q========================================================================================================================================================' d( u9 A& z7 I% g( d4 t1 U
CCRID Product ProductLevel2 Title
. @7 y2 g& E- Q! [6 U+ E+ l========================================================================================================================================================
2 p+ b5 r5 ~2 }+ ]0 m, d. Z1258913 ADW ADWSERVER Copy project message: Unable to locate tools.jar% y! ?+ a. F2 k, f- \
1760866 ADW ADWSERVER Metrics dashboard in Allegro EDM Configuration Manager does not show updated SPB 17.2 hotfix
/ i s# R" b4 q# F0 k# W9 P, S' z* P5 t/ _1055946 ADW ADW_UPREV Set PTF_SUBTYPE SEARCHABLE to false and default value to exclamation mark
* r4 l" E" v' n! @9 @* D1508163 ADW COMPONENT_BRO Manufacturers Part tab disappears on clicking anything other than the part number in the left tree
- y) h- x" t& B/ f: z% p1774164 ADW COMPONENT_BRO In release 17.2-2016 Hotfix 22, DE-HDL crashes on using Generate View
; S8 k$ Z" Y0 [" b; R1345018 ADW DBEDITOR Database Editor does not catch empty mandatory properties if no changes are made to the part1 P) E; l5 e5 X
1586858 ADW DBEDITOR 'Access Denied' Error while opening Datasheet Model using Launch Viewer in Database Editor- _: P+ e0 }9 l
1754185 ADW DBEDITOR Max Height value in DBEditor is different from PCB Editor- S0 h0 x' c: R/ M, X
1719260 ADW FLOW_MGR Configuration error on a fresh install of EDM in release 17.2-2016 Hotfix 0141 c4 N" X. ]( t7 _; m7 L
1743730 ADW LIBDISTRIBUTI .lis file error in install_model while using MLR.) {+ V& D# B* U: l
1757178 ADW LIBIMPORT back-end libimport failed, crash and existing flashmodel not found
* ~% M7 h E# G' T1 d1648609 ADW SRM PCB Editor stops responding when launched with -s option in release 16.6-2015 Hotfix 078) g% y, O8 y# j6 Z. i
1731152 ADW TDA TDO coredumps after a new object has been checked in as minor and deleted.3 x/ N; Y+ w( f: [6 V9 c8 P
1766998 ADW TDA TDO-ASA: Cannot enable the project for team design until a component is added to the new ASA/SCM design. @* @; T9 {+ @ v, p) e
1695240 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D View of a package symbol not showing the correct mapped STEP file attached to the package symbol$ v3 |" F7 Z8 z& H$ D
1698148 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Viewer crashes on Windows 10
$ F2 j. y# L5 J" S1 ^& t& n: A/ d1 H1738655 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas crashes on Windows 10
) I1 p* I4 r& p. H- V1750001 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D Canvas crashes on selecting in symbol view
- J! q! m( i3 Q( G( A& P& M+ S1751796 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas shows component placed at wrong layer for Embedded components
( P3 y) \6 c- X; Q1768775 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D canvas closes when Update Symbol is done and cannot be re-invoked/ ]3 L# S1 N+ ?
1695025 ALLEGRO_EDITOR ARTWORK Artwork film show shorts.
; ]9 l; L9 i4 R" j1 ]5 C1708674 ALLEGRO_EDITOR COLOR Dehighlight all should disable the check boxes in the color dialog/nets9 J9 y6 A% _- v
1735522 ALLEGRO_EDITOR COLOR In release 17.2-2016, PCB Editor crashes when not being able to write the CVSettings.xml file.
, a! V' l% c' [( ?1 V" Y% w1764475 ALLEGRO_EDITOR COLOR Allegro PCB Editor hangs when selecting OK on the Color Dialog form
+ K8 \& G' D0 i" N3 _1718438 ALLEGRO_EDITOR CROSS_SECTION User interface is inconsistent for the Mask Layer Subclass site file editor.
: j0 g6 h3 X$ c% \ ] m% b1765387 ALLEGRO_EDITOR CROSS_SECTION Cross Section Editor does not retain or remove layers added/removed from Setup-->Subclasses
: P- o0 ^; Y+ m4 C2 l1714910 ALLEGRO_EDITOR DATABASE PCB Editor crashes with blank allegro.jrl file when a release 16.6 board is opened in release 17.2-2016 Hotfix 0131 E- t1 E5 w: l3 s! N% a+ n, J
1769534 ALLEGRO_EDITOR DATABASE DBDoctor unable to delete invalid subclass
; k% k. `1 n. v% h: q1 j/ k1775705 ALLEGRO_EDITOR DATABASE Updating stackup in PCB Editor does not change backdrill status to 'Out-of-Date backdrills'
0 M+ a( x- z0 i: a) q3 y+ A1778608 ALLEGRO_EDITOR DATABASE Rigid Flex design: Components with pads defined on the TOP and BOTTOM layers are not placed on the correct layer
9 X, z, s1 S1 [9 h4 J6 |) p1778644 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes while trying to place dimensions
3 P t7 ]# |2 c3 `1 |* O' C1698695 ALLEGRO_EDITOR DRC_CONSTR Line to Mech-Pin DRC not displayed
4 c4 z- d1 g+ `4 ]5 S1705214 ALLEGRO_EDITOR DRC_CONSTR Shape to drill DRCs not getting void and 'cns_show' does not report constraint value* @' p% p6 S+ w4 h' c$ n8 ]
1722841 ALLEGRO_EDITOR DRC_CONSTR Inconsistent soldermask to soldermask DRCs on vias as compared to board geometry/soldermask' t/ \8 S4 W: B: I! P
1736116 ALLEGRO_EDITOR DRC_CONSTR Shape Voiding and DRC error on layer with no hole or pad definition
9 |9 s! s% S9 O9 X) {1744248 ALLEGRO_EDITOR DRC_CONSTR Release 16.6 to 17.2-2016 DML Independent Flow does not resolve differential pair pin pairs Correctly
0 U) A4 d; t$ @" _, N# t. N& Q1776848 ALLEGRO_EDITOR DRC_CONSTR Negative plane island DRC reported in release 17.2-2016 Hotfix 23
* E( z4 l. i8 \- [; |; O+ x1730806 ALLEGRO_EDITOR EDIT_ETCH Element 'vias_allowed' is not valid for content model adding high speed via structures9 L$ u: d) q: A' x
1745332 ALLEGRO_EDITOR EDIT_ETCH In release 17.2-2016, PCB Editor crashes when starting Add ZigZag Pattern
, c+ F# b( h: q& y8 _1765555 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes during contour routing
. @4 o' q- ^. Q7 `1644401 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes on running the z-copy command
- p c! s. Z& f3 v1657621 ALLEGRO_EDITOR INTERACTIV Copy cline and via cause redundant vias- t/ U. T! S, m: D. t5 [- g' w
1688556 ALLEGRO_EDITOR INTERACTIV Limitations with editpad boundary
7 @, [/ [/ @3 [# \) A: ]! i7 X1704901 ALLEGRO_EDITOR INTERACTIV Changes cannot be done when 'Design outline' is selected
) t6 h; X, C" P' P& }* J! p, V1 ^- V( o: H1710731 ALLEGRO_EDITOR INTERACTIV The Edit > Change command does not select or change the text on a block& m" G# Z" E% {2 s# Z* h$ O2 n
1714855 ALLEGRO_EDITOR INTERACTIV Placing two objects on the Design_Outline subclass causes PCB Editor to crash
: j5 Y5 n4 x2 s: U# Q, n5 ]3 R$ t1725736 ALLEGRO_EDITOR INTERACTIV Edit>Change cannot change silkscreen line to a different class, but works in preselect mode
; v! z1 s4 V/ e1728004 ALLEGRO_EDITOR INTERACTIV Text cannot be edited if the Design_Outline subclass is in the selection box
6 O' F) T+ j4 y' e1728794 ALLEGRO_EDITOR INTERACTIV The Oops command and the Esc key do not work when moving components in the Temp Group mode7 r% i* z5 w0 d& K+ V# n |9 V
1738070 ALLEGRO_EDITOR INTERACTIV Copying shape after Shape Operations results in error 'E- (SPMHDB-72): Current active shape must be filled first'4 U! L: t4 S7 y2 |3 j) N
1750696 ALLEGRO_EDITOR INTERACTIV Add notch angle option fails to update if changed while add notch command is active.1 O p8 U3 Q% @! a# G& a6 {
1755240 ALLEGRO_EDITOR INTERACTIV Copy via does not work
T8 E- \: B; C, }# x, B3 r4 ^1777416 ALLEGRO_EDITOR INTERACTIV Running shape operations results in database corruption3 I2 n( C* F* N& |, X
1715835 ALLEGRO_EDITOR INTERFACES When IDX is imported in PCB Editor, all the shapes are created on package keepout on all subclasses2 A7 k0 B1 l" z! h
1744111 ALLEGRO_EDITOR INTERFACES Pads rotating 90 degree when exporting DXF file from Allegro PCB Editor% E$ M( a' z" y1 y* w; f/ e
1736045 ALLEGRO_EDITOR MENTOR Third-party import crashes PCB Editor with error stating that .SAV file will be created' |8 S; M$ n5 }. j+ I
1751914 ALLEGRO_EDITOR MULTI_USER Find Filter options get disabled while creating symbols/ H4 G5 I' w4 I! b p+ _( {2 t
1770811 ALLEGRO_EDITOR MULTI_USER In release 17.2-2016, axlTriggerSet('exit 'routine) causes a crash while exiting
. c/ Y. C/ n7 N# u; l# E1736545 ALLEGRO_EDITOR OTHER Spelling mistake in description of no_dynamic_zoom variable in user preferences Editor
9 w; _8 H1 q9 X" e. x/ E. k. R1761610 ALLEGRO_EDITOR OTHER Dynamic shape is not voiding as expected.1 C# ]1 n# b, ~5 U; _1 b' m
1702535 ALLEGRO_EDITOR PAD_EDITOR After modifying a padstack in Pad_Editor, the Update to Design function fails to update the dra file; n5 k& P4 K! i, i
1713461 ALLEGRO_EDITOR PAD_EDITOR Padstack editor default geometry not working when cell is preselected" X. R, C, Z/ O
1715702 ALLEGRO_EDITOR PAD_EDITOR Donut shape is lost on cutting the pad shape of the donut pad( X* w: v* L3 o' l
1720300 ALLEGRO_EDITOR PAD_EDITOR Multi-drill staggered pattern: Different hole placement for first and second rows for releases 16.6 and 17.2-2016
; Y# G- \. m8 Y/ s: P( T# p1724896 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor shows flash symbol for regular pad on selecting 'Shape Symbol' h/ d o: ]& E$ y6 ~0 S
1714839 ALLEGRO_EDITOR PLACEMENT Selecting an alternate symbol (alt_symbol) in a group, in the Placement Edit mode, removes the symbol from the group
}. \6 `3 i% S$ D6 T0 a$ e, k& ]1781502 ALLEGRO_EDITOR PLACEMENT Quickplace by room crashes Allegro PCB Editor
8 r. v! c0 k+ D- q) |0 U* @, t1699690 ALLEGRO_EDITOR SCHEM_FTB 'view_pcb directive' no longer working as expected. J% l) m, K$ _+ J( U
1758796 ALLEGRO_EDITOR SCHEM_FTB PCB Editor launched from Project Manager does not read the relative paths specified in the view_pcb directive/ N1 L' E, g/ W; o. G' Z
1761101 ALLEGRO_EDITOR SCHEM_FTB On saving a board after import logic in PCB Editor, the file is saved in the cpm location and not in the physical folder6 h) E% g8 v' P5 X) b: |
1761394 ALLEGRO_EDITOR SCHEM_FTB Working directory for PCB Editor changes after import logic2 ^+ T5 F" n- H& ~0 b. q1 d
1714922 ALLEGRO_EDITOR SCRIPTS Running script in the non-graphic mode runs the tool graphically2 G5 G1 w3 N! e g) h
1726550 ALLEGRO_EDITOR SHAPE Shape failed to connect to pin% m3 H; a5 N- T8 H/ L
1754945 ALLEGRO_EDITOR SHAPE In release 17.2-2016, Delete islands fails to add DYN_DELETED_ISLAND to voids on Windows 10 systems2 l: s! ~5 r: z! ~
1766280 ALLEGRO_EDITOR SHAPE SPMHGE-300 Polygon operation failed because of an internal error
6 r# k4 `* ^: C2 a1768307 ALLEGRO_EDITOR TECHFILE Properties defined in the technology files are not being imported in a new design
# L l4 _/ F- m1 Y# Y7 n0 ]1771584 ALLEGRO_EDITOR TECHFILE The tech file import command does not update user-defined property immediately2 B- t. i, E: H3 s5 Z4 d8 d
1730104 ALLEGRO_EDITOR UI_FORMS Change description of Title bar option variables in User Preferences: d2 H( g5 }% h: x. ]( `
1749272 ALLEGRO_EDITOR UI_FORMS etchlen_ignore_pinvia variable needs to be updated
1 i# p2 O6 C/ J! L1649254 ALLEGRO_EDITOR UI_GENERAL Using wildcard to open padstack file generates error SPMHA1-161 in Padstack Editor in release 17.2-2016
/ A8 L: X9 i. M1 h) t* n/ D1685985 ALLEGRO_EDITOR UI_GENERAL Funckey not working for Display - Measure& x# M8 Q5 H3 d8 G4 [7 l
1687073 ALLEGRO_EDITOR UI_GENERAL Show Measure command shifts focus to Search field in result window after selecting first element; M% l0 @$ c5 p _) X
1699272 ALLEGRO_EDITOR UI_GENERAL File Viewer not displaying HTML files correctly when 'allegro_html_qt' is enabled
7 a" }# G5 J o) n1711321 ALLEGRO_EDITOR UI_GENERAL Database settings do not change on changing color settings using the SKILL function axlDBDisplayControl()
4 x* B3 _* f. V7 q) m3 p1728468 ALLEGRO_EDITOR UI_GENERAL The Show Element window takes the focus away from the PCB Editor window g% b8 l6 |( u' @9 L
1733690 ALLEGRO_EDITOR UI_GENERAL Performance issues in Visibility dialog if called repeatedly in release 17.2-2016, Hotfix 0175 h8 m" v. C' k: H J+ S, W
1734176 ALLEGRO_EDITOR UI_GENERAL Unable to sort padstacks to open in the padstack editor using wildcards( u8 P9 n8 O) R2 i- s) X1 F
1735733 ALLEGRO_EDITOR UI_GENERAL RAVEL checks slower in release 17.2-2016, Hotfix 0179 K( b! H" _( Z! ?8 d6 R& _
1737545 ALLEGRO_EDITOR UI_GENERAL axlVisibleSet is slower in release 17.2-2016
* H+ ]7 x5 n& E4 C7 o1744655 ALLEGRO_EDITOR UI_GENERAL SKILL code with axlVisibleSet slower in release 17.2-2016 compared to 16.6 A" [% q! M: L; J T6 a
1759380 ALLEGRO_EDITOR UI_GENERAL axlLayerPriority API changes layer visibility and colors' ~* e# W. a1 v, ^
1775071 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, dialog boxes are not displayed in the right order on using SKILL4 D& W3 j i7 x4 `4 k) V' ?/ l
1708554 APD GRAPHICS MCM shape lines are almost short and different with DXF and Gerber files6 R7 U1 g Z8 L& W
1678824 APD SHAPE Updating dynamic shape fails to void all elements on layer L2.3 W0 U) ]$ @$ N6 s' [
1742335 ASDA COMPONENT_BRO Libraries missing from new Component Browser4 ^- n, }$ z8 C3 y6 a7 p0 }
1779777 ASDA CONNECTIVITY_ SDA: Net name and physical net name are different
) p2 d9 k+ G- v, [9 A. r1721919 ASDA CROSSPROBE Cross-probing a net from the .brd file highlights the entire bus in the schematic# u2 Y+ J/ _$ a2 y8 u
1714313 ASDA EDIT_OPERATIO Filter does not work correctly in the Change RefDes form
# t0 w8 ~$ I0 G0 Q4 b0 n, [" m3 i1730809 ASDA FORMAT_OBJECT Image transparency slider does not update the number in the combo box correctly
6 r' }" R) c! }- F" E1747397 ASDA GRAPHICS Pop-up DRC descriptions are too small and cannot be read0 K3 d0 ^. O8 h7 E: L( ?; i
1640061 ASDA HIERARCHY Incorrect message received when invalid characters are specified for subdesign suffix
3 z5 a; ]: B1 Y* p' _, C1723535 ASDA MISCELLANEOUS Clicking in the Command window should place the cursor at the last line to avoid editing previously run commands
5 g9 w9 b" U3 s( ?0 c4 H4 O3 h1699936 ASDA PAGE_MANAGEME Page gaps created while moving pages
, [2 ~ G( w3 z0 G/ g, s7 C1737180 ASDA VARIANT_MANAG Deleted variants are removed from the variant.lst file but displayed in SDA5 s- X/ m% r& D- U. _/ b
1763247 ASDA VARIANT_MANAG Changes in Variant Editor are not reflected on the schematic page.
7 W* T6 y, [. Q0 I" o1 a, e$ j1733971 CAPTURE CONNECTIVITY Auto connect to bus not working in the attached design
/ h0 w; K( S8 O& S' x, y' @* T1236010 CAPTURE DATABASE Capture is very slow in processing designs. Q B7 [5 }. H2 V1 `1 B
1518560 CAPTURE DATABASE Large schematics are slow to respond: m$ P! w# ^1 t! O) k+ c6 ]
1705592 CAPTURE DATABASE Capture hangs when switching between schematics that contain nested netgroups/ T9 c6 {: r" Y' V
1770687 CAPTURE GENERAL In release 17.2-2016 Hotfix 021 and 022, selecting Help - Learning PSpice throws Java Script error X. o; M! M( F J5 U3 P, I3 B
1692435 CAPTURE HELP Version Info Window is empty
. \2 g; z6 ~( O5 }- [1767374 CAPTURE NETLIST_ALLEG Capture crashes on canceling the netlisting process
- }7 K) q, I0 c* H+ y: b5 V1719613 CAPTURE OTHER Moving a wire in OrCAD Capture CIS or Allegro Design Entry CIS results in design crash
# `, V) m$ m% m# n9 F$ t8 n1746663 CAPTURE OTHER Capture slows down significantly in release 17.2-2016 Hotfix 017 and 018! L/ w0 n* i9 p8 F
1709179 CAPTURE PROPERTY_EDIT Unable to delete unwanted properties associated with Ground and VCC nets.
w1 A; s) b b! r$ @1714121 CAPTURE SCHEMATIC_EDI Mirroring and moving a symbol resets the position of a newly added pin property
/ x: g7 o5 K, q5 B" E5 g1 P1729861 CIS OTHER The 'Refresh Part Types' icon is alternated with 'Refresh Symbols From Libs' icon
: o" l' [, y$ Q; P- U3 _8 [/ ~! N1333600 CONCEPT_HDL COMP_BROWSER Sort the sections numerically in Part Information Manager
* R, [: s% |' X* c5 H( I! L1758761 CONCEPT_HDL COMP_BROWSER Incorrect Version showing in Component Browser in 17.2& b* o; M& t( C6 N7 ^
1769591 CONCEPT_HDL COMP_BROWSER Modify Component / Project Information Manager (PIM), parts take longer to load in EDM# a! q: e. ~5 `; J& y
1479711 CONCEPT_HDL CORE Mirroring symbols causes alignment issues2 R9 @; ~& L5 a% j$ o% `
1696208 CONCEPT_HDL CORE Display issue with the grid visibility after a save hierarchy
5 V C2 }7 }; X. S @1698802 CONCEPT_HDL CORE Pin number overlap with the pin stub when the component is mirrored.3 W2 W3 A1 D X5 {' b7 b
1708917 CONCEPT_HDL CORE nconcepthdl crashes on a design with a core dump
! q+ k! N' b$ I% Z2 f1744815 CONCEPT_HDL CORE Deleting a page crashes DE-HDL: P1 n( u7 ?5 i- d, j4 l: U
1751863 CONCEPT_HDL CORE 'Move' does not move body but only properties of selected part: a" Y$ \- n" c, ?
1763556 CONCEPT_HDL CORE Component Alignment and other graphical feature not working in Windows 10
% S7 ?' f! r# ~( R1725121 CONSTRAINT_MGR CONCEPT_HDL Audit report of ECSets reflects some gaps in certain columns' i/ s: m( G. Z) W: t
1758740 CONSTRAINT_MGR CONCEPT_HDL Extracted topology does not populate the gather control used in the ECSet7 _# n# x5 @' H) B i# Z$ S. Z ~/ h
1759580 CONSTRAINT_MGR CONCEPT_HDL Class to Class assignments are incorrectly displayed in the 'CSet Assignment Matrix'
; u4 B( X! v7 o8 z$ |( C1759590 CONSTRAINT_MGR CONCEPT_HDL Unable to create bookmarks in Constraint Manager+ e) O% A$ D4 O x& p' W) K0 T
1764597 CONSTRAINT_MGR CONCEPT_HDL Copying constraints from a SKILL-defined CSet copies the automation flag/attribute ('A' in UI), as well.3 ^+ ~) g0 R. |# J
1771427 CONSTRAINT_MGR CONCEPT_HDL Decimal units specified in the precision settings are not applied correctly
1 b# G6 V- z1 o) T0 j% V1700402 CONSTRAINT_MGR DATABASE Parallelism violation DRC not reported until cline is moved
2 g$ u6 G A$ `5 q) ?. _1700370 CONSTRAINT_MGR OTHER Constraint Manager: Expanded nodes collapse on restart
0 o5 p# T0 a+ F1 D- i# P1735636 CONSTRAINT_MGR OTHER Inductors are extracted as resistors in the topology1 f# l. i* N. |. L$ N/ ~
1776917 CONSTRAINT_MGR OTHER Creating advanced formula causes the tool to crash
" G( j' K1 F v' ~; s! i% G2 x7 g1762979 CONSTRAINT_MGR TECHFILE Constraint Manager does not retain values after importing tech file
6 m. z7 M2 V4 d7 W0 v+ `; _1699275 CONSTRAINT_MGR UI_FORMS Constraint Manager: Dialog boxes opened from the File – Import menu show files and folders in incorrect order, N$ q9 u5 o* ?
1699312 CONSTRAINT_MGR UI_FORMS Typing *.* in the File name field does not display all the files in the Import Constraints dialog box) Q4 x0 G7 E) d, N, I
1742134 CONSTRAINT_MGR UI_FORMS Editing a cell from any of the constraint set in Constraint manager is filling other cells that should not be selected
9 M+ \! h0 d: g$ s( w6 P" a) L. q1755576 CONSTRAINT_MGR UI_FORMS Constraint Manager: Physical CSet filter not working correctly! d \1 B% v- S/ P2 {
1775333 ECW DASHBOARD Activity Log is not accessible to ECAD_Integrators if they are not part of the project team
5 `0 Z1 y2 \8 H: u) t1749220 ECW OTHER Remove 'Role' column from Users web parts
7 L! E. a9 D: p/ V# M% c1716527 ECW TDO-SHAREPOIN Allegro Pulse: Mismatch between metrics with components on schematic and components in layout- P# _5 |/ \# Y3 n
1724195 FSP SYMBOL_EDITOR Device pins are not correctly aligned after being moved in Schematic Symbol Editor F: T6 ]' S8 u- |* j# A
1725479 INSTALLATION DOWNLOAD_MGR Download Manager error prompts user to close downloadmanager.exe/ Q# P0 L* o4 x' d. d
1738952 PCB_LIBRARIAN SYMBOL_EDITOR Pin table must allow for Copy/Paste of Rows0 ]; I8 W$ |- T: i a
1638740 PSPICE FRONTENDPLUGI Set minimum height for the search field in PSpice Part Search
# D+ b \; A$ N3 N" n$ V+ n1699822 PSPICE FRONTENDPLUGI Set minimum height for the search field in PSpice Part Search8 p2 P% P8 f( [8 f8 n+ H
1652265 PSPICE MODELING_APPS Cannot place PWL source from PSpice Modeling App% {- M; |% L2 M+ r( R' j: ]9 O
1685967 PSPICE MODELING_APPS Getting error when trying to place PWL source from PSpice Modeling App
) o; N i, d! L2 k" Q3 ^1716313 PSPICE MODELING_APPS PSpice PWL Sources not working correctly in release 17.2-2016 Hotfix 014
# g" o: T3 @/ \" I0 o' W! a* A1738747 PSPICE MODELING_APPS Inconsistent file type for PWL part in modeling application and source library" W( p4 M" o1 p5 w) \
1762202 PSPICE MODELING_APPS PSpice modelling app Tcl issues3 |% r m: C5 B7 u ~( k" F8 t
1736605 PSPICE SIMMODELS BSIM4.6 model parameters incorrectly handled by simulator
+ l0 n+ `* E/ T- E1442623 PSPICE SIMULATOR Bias points are nor correct in attached circuit
& L6 v( P" O3 D- T+ I+ ~; L! o% T1618815 PSPICE SIMULATOR Bias Point calculation appears incomplete% e/ r% q/ R" u1 c; r
1723039 PSPICE SIMULATOR PSpice crashes when curly braces are specified for the ETABLE parts
5 o. f7 _4 }* i/ S' N8 t T% ~1782353 SIG_INTEGRITY SIGWAVE SigWave crashes when opening .sww file in release 17.2-2016 Hotfix 023* r" d2 ]( U' K9 r i, A
1745940 SIP_LAYOUT DATABASE Cutting a part of a tapered cline does not remove the connectivity on the dangling cline! X0 e4 N+ E4 L; b/ y T( d& T# |# D
1780072 SIP_LAYOUT DIE_ABSTRACT_ Export->Die Abstract File causes a crash
/ B; i- H& u8 ?" ?. Y0 a- E, t1736396 SIP_LAYOUT SYMB_EDIT_APP 'No such child' error message when deleting pins in symed
. J4 l, s3 N% t& Z2 B1769728 TDA CORE Default policy file needs to be fixed
3 S1 Z1 v/ h8 v l5 w1735682 XTRACTIM GUI XtractIM translation is incorrect: adds anti-pads: @! V) L$ I, }$ C% h3 `
5 H5 [' j' q) X4 I& Y6 _
6 Y9 g- q. `3 f) [. zFixed CCRs: SPB 17.2 HF024: b* `' C4 ]4 ^- u! ~
07-28-2017
6 B7 h1 O6 K1 A7 N$ k# R========================================================================================================================================================! o4 D0 x/ f E" k! B' \
CCRID Product ProductLevel2 Title
2 Q! ]" P% w( R/ c3 t========================================================================================================================================================
8 [9 v! C: G4 c) j9 z$ ?1762143 ADW COMPONENT_BRO Part placed using the 'Add' button does not populate 'PART_NAME' property& z& q6 i* T; n1 G: u4 P
1765790 ADW PART_BROWSER Fail to extract component part number and footprint information
* |% e) Y1 ^0 k Z3 `1757719 ADW TDA TDO and Windchilll Work Group Manager out of sync at times
, K6 S4 H9 L* W2 H- N1760607 ALLEGRO_EDITOR DATABASE Value for number of decimal places changes in Pad Designer in release 17.2-2016
5 C+ m5 M; f8 v9 @6 d( ^+ K1775160 ALLEGRO_EDITOR DFA Loading DFA spreadsheet crashes PCB Editor in release 17.2-2016
% U$ k6 N! x/ b1765984 ALLEGRO_EDITOR OTHER Cannot view System Info6 J# H: e/ N/ c8 o# A. s) r
1729350 ALLEGRO_EDITOR REPORTS Net loop is not listed in report2 }) S& s$ s5 x# D; m
1725242 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
* F# o- g) s$ c1754402 ALLEGRO_EDITOR SHAPE Illegal arc radius error (SPMHA1-85)
$ V- L' m6 X3 K, s1762888 ALLEGRO_EDITOR SHAPE Border line missing for some crosshatch (xhatch) shape voids; [7 c! F) i' b4 m+ o9 }# V2 t5 c
1769188 ALLEGRO_EDITOR SHOW_ELEM 'Show Element' with the 'Groups' option used on certain modules crashes PCB Editor
4 K4 |8 D2 B% E( y1767690 ALLEGRO_EDITOR TESTPREP PCB Editor crashes when running automatic Testprep& i! U/ Q; u2 E- F4 F! W- k7 y* B
1737337 ALLEGRO_EDITOR UI_FORMS Pinned Show Element window closes when opening new design in release 17.2-2016
! \2 h4 O2 ?; ~ p0 \- V/ g1736642 ALLEGRO_PROD_TOOLB INTEGRATION Cannot change accuracy to 4 for 'Change Width' in Productivity Toolbox
( Z( S$ ^; L0 ]# X3 L) _$ h1685216 ALTM_TRANSLATOR CAPTURE Third-party translator placing symbols off grid
/ [: ^0 ~1 t. ^( z0 t1738679 ALTM_TRANSLATOR CAPTURE Connectivity loss in imported schematic
1 N6 A: n, J/ _9 C) A; Z1738705 ALTM_TRANSLATOR CAPTURE Connectivity loss in imported schematic
* P+ X9 b: G% J% ~9 w% C0 d1748583 ALTM_TRANSLATOR CAPTURE Crash on importing design using third-party translator& |5 K: u% U, |; R; U
1679310 ALTM_TRANSLATOR PCB_EDITOR Third-party translator should fix off-centered connections! Z3 ]* m: x! N* t" R5 k4 q- b
1686845 ALTM_TRANSLATOR PCB_EDITOR Third-party translator does not place parts after successful translation
; S2 V0 Z: r4 ^& e! B$ g# d1723141 ALTM_TRANSLATOR PCB_EDITOR Placement outlines are rotated in third-party translator
: R0 k4 H0 Y' r! c0 J1723164 ALTM_TRANSLATOR PCB_EDITOR Third-party translator creates board with missing data: vias, traces, and so on
( y9 U. u. z: D1723190 ALTM_TRANSLATOR PCB_EDITOR Third-party translator changes design origin2 {$ e. W/ s* h) |5 | G" B- T$ i
1750496 ALTM_TRANSLATOR PCB_EDITOR Third-party board with arc tracks not correctly converted to arc clines" O4 \* ]( X) `
1769624 APD DATABASE Attempted symbol delete crashes APD; s# z% O: Y3 @+ y7 `6 n
1727206 APD SHAPE Merging two shapes results in an incorrect shape$ K F5 y! s. U4 T& G; K( S' q
1707756 ASDA VARIANT_MANAG Scrolling in Create Variant closes tool
1 H0 H% d4 j4 L2 @& H1753699 CM RELEASE installDebugger() does not work in release 17.2-2016 as SKILL kit is not installed
2 ]6 J" B+ u) F( R5 I3 ^1741534 CONCEPT_HDL CORE DE-HDL freezes when selecting a net that contains many connections
6 U- k0 ~6 ^3 S2 M" B1 X1752687 CONCEPT_HDL CORE The move command changes the connectivity of the schematic
8 U4 t# ~' V* F4 J1763525 CONCEPT_HDL CORE Genview crashes when generating split symbols
0 ?, S* J, n' ^/ M2 I/ Z+ {1766797 CONCEPT_HDL CORE Schematic not refreshed after using the clear xnet overrides feature
& {' f0 C0 i% x. ?- E u. p1770852 F2B PACKAGERXL ERROR(SPCOPK-1138): A hard location was found on instances of different physical part types
9 V8 n4 S M( P! A4 z: g1754473 FSP DE-HDL_SCHEMA Provide an option to generate symbols with custom attributes2 K* R0 f, f" {! L
1748106 FSP OTHER Create protocol from existing protocol error message needs clarity
$ O) p+ R6 B6 |7 |7 g1 H1724201 FSP SYMBOL_EDITOR Unable to change 'Pin Direction' in symbol editor
( @3 n1 U% e* R% b a1772429 ORBITIO ALLEGRO_SIP_I Import - OrbitIO: Translator cannot create bundle in PCB Editor' w* F) P3 {/ q( r. Y& [) E9 F3 A
1725759 SIG_INTEGRITY OTHER PCB shape/plane capacitance
2 {* u; M' v' ^0 S; n1760924 SIP_LAYOUT DIE_STACK_EDI Package height of die .dra file reset to 110um when placed
3 [5 T1 { Q9 G. r6 J, L( t1764385 SIP_LAYOUT MODULES Embedded components are unplaced in created modules (.mdd)
( G7 b7 s7 k. B6 l; T P% B( Y1733679 SIP_LAYOUT OTHER 'metal density scan' does not use select window
' i& }; v" E, L& ^6 D8 c7 a, R0 Y1763707 SIP_LAYOUT OTHER SiP Layout exits with error message in release 17.2-2016) L! W" C; `( k i
1763515 SIP_RF DIEEXPORT Virtuoso writes incorrect width for 45 degree path segments in XDA file6 v A$ _3 E4 A1 S* V- ~& q0 f
1772397 TDA DEHDL DE-HDL crashes if license is not available for team design/ @, L( i. R- J3 \9 m" U3 R( T
# ?* M2 [; f9 N! v% r# ]$ m
! [2 }4 P7 c. B- X4 _$ fFixed CCRs: SPB 17.2 HF023
, r3 E) F3 @4 l) W) ]& a, b07-7-20176 p M% e: y- R9 k2 \$ c- q* v
========================================================================================================================================================
' s0 f1 L: c' \" Y" V1 JCCRID Product ProductLevel2 Title
& }( d& G) j/ g5 ` R========================================================================================================================================================. H2 X: l% x: P3 F: Q( ^
1703281 ADW ADW_UPREV Design_init needs to support the -cb command7 }5 Y! `" C9 u8 R* w' F2 E" x1 A
1762238 ADW COMPONENT_BRO DEHDL crashes without reason" Q* B6 E" j6 F+ r4 E* A2 d' ]
1759467 ADW DBEDITOR DBEditor does not recognize that 1.10 is a higher version than 1.9
( s5 O, P$ r/ H1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager
8 Y6 z0 a( T' h1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager
4 U5 b( I9 o( \& }' Y1757443 ADW LIBDISTRIBUTI Blank PHYS_DES_PREFIX in PTF file2 J: u2 [9 ^( i7 w' Z$ x: M3 L
1752126 ADW LRM cache not getting updated with std models when moving from 16.6 to 17.2% {1 ^5 F& j% k1 S% P! }
1754444 ADW LRM Update Standard library in LRM causes an error, "Cannot proceed with update as don't have permission to delete."
$ w: @# \6 o+ w, h0 t( h1715861 ADW SRM symbolrevchk.par has incorrect variable name for SRM to ignore the tool version+ [+ J. U7 m$ R! u. j/ j
1628403 ADW TDO-SHAREPOIN Objects remain checked-out after multiple failed 'check in hierarchy' attempts
7 Y- u3 w- q$ W8 j1759250 ALLEGRO_EDITOR DATABASE Flex-rigid placement does not move bottom pads to nearest layer
- x0 z. w( P2 q( H9 m& N1762782 ALLEGRO_EDITOR DATABASE PCB Editor crashes when creating artwork
# t0 o# h, g% x1 c% w7 U6 D1746665 ALLEGRO_EDITOR DFA Cannot scroll in DFA Constraints Dialog if the DFA constraint file is read only
$ y8 r* r# m+ u8 O' O! ?+ w( _. `1750084 ALLEGRO_EDITOR DFA DFA spreadsheet disappears from the DFA library if hyphen is present in the name
- N- G, S7 G1 l: [4 U+ O: M+ h- W1697155 ALLEGRO_EDITOR GRAPHICS Position and size of Show Element and Measurement windows not saved in PCB Editor
8 @) Y$ v% Y0 B9 u; E- ?& c Y1734282 ALLEGRO_EDITOR GRAPHICS Placement of reports and pop-ups not retained in PCB Editor& i5 G2 V# X& _' K1 Q6 g) V, d4 E
1740863 ALLEGRO_EDITOR GRAPHICS Show Element and Measure windows do not retain position
- N4 D/ d; ~& B, }; Q# Z' h1749687 ALLEGRO_EDITOR GRAPHICS Position and size of Show Element and Measure windows are not saved in PCB Editor in release 17.2-2016
- q i; e9 s0 Y+ n6 w- m1764124 ALLEGRO_EDITOR SCRIPTS Replaying recorded script file crashes PCB Editor
3 H5 b) E" {' m) K0 q9 F5 v1762888 ALLEGRO_EDITOR SHAPE Border line missing for some crosshatch (xhatch) shape voids
1 e' J$ K* E* g1763619 ALLEGRO_EDITOR SKILL Incorrect text block name when extracting text parameters using SKILL
) R, a8 _+ j( P( z9 d% ^5 k! U1685826 ALLEGRO_EDITOR UI_GENERAL Reports when opened from Status Form disappear behind PCB Editor canvas when clicking on canvas
1 q" E+ u! E0 d. b1 U1733552 ALLEGRO_EDITOR UI_GENERAL Although F1 is defined as an alias for another command, pressing F1 opens help
: W% `0 N1 H" |: D1735098 ALLEGRO_EDITOR UI_GENERAL axlUIYesNo displays garbled text when customized for Chinese in release 17.2-2016
- x4 S( Z1 R4 @* }$ W+ e+ ]: J1753430 ALLEGRO_EDITOR UI_GENERAL 'Tools - Quick Reports' opens only one report at a time5 T% @ b7 ?& w9 {/ `
1754283 ALLEGRO_EDITOR UI_GENERAL Call multiple reports from a function key
" o6 H9 U- x7 @1 q- n2 l" o" Q1742822 APD STREAM_IF Component pins are not mirrored properly when mirror geometry option is checked and component is mirrored at 90/270* w* g* a/ J2 ^6 S/ A. g
1762284 ASDA COPY_PASTE Copying testpoint crashes tool and eventually the operating system" w* x q1 R) k
1655057 CONCEPT_HDL COMP_BROWSER ADW Part Manager and Component Modify hangs) `; ~% I) ]/ Q/ T M. Z
1689740 CONCEPT_HDL COMP_BROWSER Bad response time using Dehdl component browser
1 C' z# o& {0 O+ {0 v9 v+ g2 F1735332 CONCEPT_HDL COMP_BROWSER Sort in mathematical order Symbol list in Component Browser
$ u( R! F8 j* [4 \) C1739197 CONCEPT_HDL COMP_BROWSER Part Information Manager can`t sorted symbol version& I4 S6 g- @6 k* k6 d3 t
1764605 CONCEPT_HDL CORE Signal added from the console should be 'Left Aligned' instead of 'Center Aligned'5 f9 Z6 B" q0 V) m1 U+ k y
1761706 CONSTRAINT_MGR CONCEPT_HDL cmDiffUtility has a typo in the usage statement7 `$ N s: ?5 M
1758426 ECW DASHBOARD Behavior of 'Apply Label' for Dynamic and Status labels should be same in TDO and DE Webpart
6 S \/ j3 ~9 B! U$ F1 [- \8 Z% a1764096 ECW PROJECT_MANAG Renaming project using the ETD window randomly hangs the edit window, refreshing bring backs the page0 L; b" T0 z6 q7 m+ _5 h8 o
1764070 ECW TDO-SHAREPOIN Join Project: Multiple entries shown for workspace/project with multi-hierarchical structure
* ~1 m) D8 L8 Y* |, Q3 o1754473 FSP DE-HDL_SCHEMA Provide an option to generate symbols with custom attributes* R7 a7 r5 E6 s# B9 a) G
1724124 FSP DESIGN_EXPLOR Provide Tcl command to filter data in Design Connectivity Window4 j+ \9 ^# S9 `; }: }# Y" r
1726548 FSP OTHER Unable to open FPGA system planner if username/log file path has Cyrillic letters% d6 z6 ?8 M8 h0 ]4 C8 h
1719133 SCM SCHGEN Voltage symbol not getting placed for some of the voltage nets
. w1 q9 S5 Q( g' Q1 \1680989 SIP_LAYOUT ARTWORK Artwork film set-up: Match Display including invisible layer: M; P, v! {2 |4 b* t7 M. r5 A$ I
1732218 SIP_LAYOUT DEGASSING Shape will not degas as needed - not all voids degassed5 {# D. c' u3 p
1763280 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout does not recognize width of segment when importing .xda! S. E" Q' q: V4 I
1762992 SIP_LAYOUT OTHER Saving a design after adding a solder mask layer in the cross-section crashes tool
/ Y4 G: \% B& M6 L" g
6 H& _8 E4 v0 u6 u- _% e5 c3 B' M: ^3 v
Fixed CCRs: SPB 17.2 HF022
# _- f9 Y; ], ?' M4 m06-16-2017
" E" ^" F- g7 ^8 F' W/ F/ ~5 ?========================================================================================================================================================
$ q. M+ m1 e" |# Q4 \CCRID Product ProductLevel2 Title+ a3 m2 P4 T- F* m
========================================================================================================================================================
/ [# E g( R! j* J1755789 ADW DBEDITOR Checking in HSS Block returns 'Failed to create archive'
! o/ p a& o' T1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager
& J& E' E* g8 U3 x! e1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager" Z# ~: W+ z% z9 |
1744081 ADW FLOW_MGR Error regarding configuration file when trying to open Workflow Manager
2 ~" T: ~( A/ r, u+ _! D/ Z1756727 ADW LIBIMPORT EDM Library Import fails with java exceptions when merging classifications: n6 @: T/ {1 m
1743763 ADW SRM Find filter is grayed out when Allegro PCB Editor is opened from EDM Flow Manager- Z# D7 c: a+ ^3 g3 B' r* x2 u
1748399 ALLEGRO_EDITOR DATABASE In release 17.2-2016, end caps not visible for certain clines in PCB Editor
" Z( ?. v0 d' j9 W( E! P3 o1748522 ALLEGRO_EDITOR INTERACTIV A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it; j' o' p# _& Z1 |1 N
1734983 ALLEGRO_EDITOR INTERFACES Secondary step model does not stay mapped after drawing is reopened/ C0 g0 N' G4 C" F
1753704 ALLEGRO_EDITOR REFRESH Refreshing symbols crashes PCB Editor; g$ N) Z: `4 b7 m3 M( P8 x0 y! Z% c
1493721 ALLEGRO_EDITOR SHAPE Voids on negative planes are not adhering to constraints
6 H: `/ C( b8 a7 J5 p+ y& `* _3 a1711242 ALLEGRO_EDITOR SHAPE Route keep out leads to partly unfilled shapes with gaps
! H6 ?0 @5 ^5 ~) ]/ i" u5 s p" O1726865 ALLEGRO_EDITOR UI_GENERAL Pop-up Mirror command does not mirror at cursor position9 v4 `, E" H$ V' X
1752987 ALLEGRO_EDITOR UI_GENERAL axlUIViewFileCreate zoom to xy location not working while in user created form.
. I8 Z" B0 A1 w' W$ u' S1755638 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run( U% X P/ D+ o" u M: D. K
1719792 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC hangs or crashes PCB Editor+ \" i" e6 L1 f
1624869 ALTM_TRANSLATOR CAPTURE A structure file is required to translate a third-party schematic to OrCAD Capture" p Z; Q/ o' U
1707416 ALTM_TRANSLATOR CAPTURE Missing components and pins in the OrCAD Capture schematic translated from a third-party tool
3 }8 O' ~) x8 h* F0 {1708825 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate the schematic
/ n4 m8 w+ W9 Y/ W1719200 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate all the pages of a schematic( m4 n' N) A7 ~' ]* F' K Y
1546070 ALTM_TRANSLATOR CORE Third-party to DE-HDL schematic translation fails
2 Z/ `& i' b7 V! M ?1700508 ALTM_TRANSLATOR CORE Third-party PCB translator does not work in release 17.2-2016
9 h8 @; @: a8 a d+ n* A1699340 ALTM_TRANSLATOR DE_HDL Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor0 Y5 V, x& s! x$ f1 x
1630379 ALTM_TRANSLATOR PCB_EDITOR Third-party translator is not importing clines and vias; O4 l! r1 X7 N
1708615 ALTM_TRANSLATOR PCB_EDITOR All items of third-party PCB not imported in release 17.2-2016
! H# g2 I4 z- M, f/ S: h1758296 APD DXF_IF DXF OUT: Rounded rectangle pads mirrored incorrectly, n6 _" P# t# W6 \
1756040 APD IMPORT_DATA The 'die text in' command ignores values after the decimal point* f. A6 m) w* M3 ]
1727206 APD SHAPE Merging two shapes results in an incorrect shape4 D$ Y7 l" {. U0 Y4 f2 F
1753682 CONCEPT_HDL CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL$ A3 E. l- `% ?- k8 ?% N% s2 Y
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic
. e( g# ^2 ]- A* @; f7 x/ o7 j1747559 CONCEPT_HDL CORE Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)
8 h) ?/ ^1 Z! E9 X; S. P; x2 w1749644 CONCEPT_HDL CORE In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes" Y- v/ r' Q/ ^1 }
1746910 CONCEPT_HDL GLOBALCHANGE Global Component Change unable to identify part data when using schematic pick option
* L, H" U- i% i6 T$ w( W1743572 FLOWS PROJMGR Project Manager displays incorrect values in Project Setting2 c& O: ?# [$ u- d: J
1724124 FSP DESIGN_EXPLOR Provide TCL command to filter design connectivity window
1 |* y0 N' Q5 ]; B) Q* k1719105 FSP GUI Tabular sorting not working in FPGA System Planner
2 ]- l! X# j. D6 {! I" w q1755750 PCB_LIBRARIAN GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor
6 U) G- z. _1 L2 J; T0 J1722993 PCB_LIBRARIAN IMPORT_CSV Part Developer crashes while importing part information stored in a .csv file# K, U$ p @/ [* a
1758856 SIP_LAYOUT 3D_VIEWER Correct the spelling error in the 3D Viewer Design Configuration window+ A! G0 x6 _" A: [0 f [
1755179 SIP_LAYOUT ARTWORK PCB Editor crashes when creating Gerber files& j& j3 U7 T" t9 v3 P) r, Q
1743511 SIP_LAYOUT MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check
$ O; m& O6 T3 g) [
$ Z, B! j/ }' T2 ~( A7 N7 ?" j0 s& X
Fixed CCRs: SPB 17.2 HF021
( t- F1 }/ \/ a" g06-3-2017 ?' y1 V' G* c0 s) I4 d
========================================================================================================================================================
9 z8 M2 @. J" \8 Q! ?; j2 yCCRID Product ProductLevel2 Title0 ]. Q& K( A# {# |) T* q
========================================================================================================================================================
% M$ W7 I" ?2 [. j: x+ d1401318 ADW DBEDITOR Bulk Edit - Previously modified cells do not turn blue when selected/ l$ O9 b' g2 [& e6 D
1621446 ADW DBEDITOR Bulk Edit - sorting highlights incorrect cells to mark them as changed* {- a6 @7 q$ g1 r' ^
1743997 ADW LIB_FLOW Match file for standard models is incorrect" S# x0 A, u$ k
1746052 ALLEGRO_EDITOR DATABASE PCB Editor crashes when applying no drc property
+ K9 ~ S ?% j) _& o1736067 ALLEGRO_EDITOR DRC_CONSTR Interlayer checks not reporting DRCs between cline and mask layer. p! {8 s. m8 P! n5 F5 d5 v
1738587 ALLEGRO_EDITOR EDIT_ETCH Line width changing on slide for ETCH - Conductor (Not on a NET)
3 G4 q0 e1 e6 @+ \- q1745277 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using the slide command# V( i% n8 Z! e' H* r7 X
1747942 ALLEGRO_EDITOR EXTRACT Fabmaster Out does not export arc in pad_shape& j) ]7 W% I T; q' f
1737202 ALLEGRO_EDITOR GRAPHICS Setting the variable display_raster_ops# p" z K3 U5 ~+ Y5 q2 ~2 {9 n
1744042 ALLEGRO_EDITOR GRAPHICS Unused pad suppression is not working on few nets! I ]+ V% H2 O) {5 i
1703848 ALLEGRO_EDITOR INTERFACES IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty; }5 A% K2 q, I
1743899 ALLEGRO_EDITOR MANUFACT Glossing dangling vias crashes PCB Editor/ d+ q# J9 q7 J$ `* K; G9 z# k( i2 H
1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor9 e; V- Q- S: k0 k( b
1748520 ALLEGRO_EDITOR OTHER TDP fails to load on an empty database
7 z: l9 O# v3 t5 t F3 ]1748581 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when changing default pad geometry" ?! b/ @: D- C
1751469 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes/freezes when browsing for a shape symbol
& H6 j, M0 K$ U# u9 B# r1 a) `1725948 ALLEGRO_EDITOR SHAPE Shape differences after conversion from release 16.6 to release 17.2-2016
/ _- U; @/ A, d: O/ `! m( }1729306 ALLEGRO_EDITOR SHAPE Seting shape_rki_autoclip variable causes no void to be generated
9 P1 W$ v2 I& a4 k# |1698876 ALLEGRO_EDITOR UI_GENERAL Tabs are large and text is compressed in release 17.2-20162 M' D0 r1 Z. x* C2 i4 O6 x
1698883 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors
M3 k$ L8 @; ^6 m6 a9 |1707933 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not locating menu as per x_location
" d+ o4 q) W$ f7 Z1741460 ALLEGRO_EDITOR UI_GENERAL Right-click, context menu options grayed in some cases after choosing Edit - Copy
) @& u- W) C3 j4 L% L1747588 ALLEGRO_EDITOR UI_GENERAL Interacting with PCB Editor by sending messages is not working7 d: B' A5 P# q0 O8 G }3 a
1747488 APD EDIT_ETCH Route connect is improperly affecting existing routes in locked high speed via structures
% G. {, A$ L+ s6 V, k8 a# N3 q1750182 APD STREAM_IF The stream out settings are not saved
7 H! k2 w4 _6 c. }& |1752067 ASI_SI GUI Links to differential waveforms do not work in Sigrity SI report ]+ K" ]$ \/ |. M* e
1752131 CONCEPT_HDL COMP_BROWSER Symbol view in part manager doesn't match the symbol version
# t v& |; F( `' J ?# @1754116 CONCEPT_HDL COMP_BROWSER Default Symbol selected is n°2 instead of n°1 in component Browser
5 {4 M. \7 \) X2 V$ d& `1754949 CONCEPT_HDL COMP_BROWSER Part Information Manager displays preview window with the wrong symbol and missing footprint0 k4 j( b4 i3 n
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic2 z, G( s i+ H+ b# y
1750916 CONCEPT_HDL CORE DE-HDL crashes when trying to uprev a project in release 17.2-2016
. `. p: N8 z+ G! K" }( ~1711487 CONCEPT_HDL INFRA Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design0 e, M$ L+ E1 b: d
1746915 CONSTRAINT_MGR CONCEPT_HDL Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow5 J" d8 s, _8 X. v! [! e
1743523 CONSTRAINT_MGR DATABASE Suppress warning pop-ups from the constraint automation script
: _! M3 s% ]' Q: y/ b- E/ b" O. R1746941 CONSTRAINT_MGR UI_FORMS 'Go to Source' from DRC tab is not working in release 17.2-2016
; o) z. F( o5 o+ q, c( r+ [ r1753010 ECW METRICS Metrics not getting collected due to old license in use h& Q; M( T/ T( M) ^" k4 x
1713052 FSP GUI Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance) m( p) J1 l8 |. Q
1719099 FSP GUI Net naming wrong after building block; k+ h/ S* V$ v& e) p( g7 @
1719105 FSP GUI Tabular sorting not working in FPGA System Planner' j( t7 J; L7 `$ A5 P5 @" q7 T
1720479 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems
; r3 m/ V* N+ e" i* v: s$ M/ Q. P1723411 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems
+ M# M9 v- g( m' t1746628 PSPICE ENVIRONMENT PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016
) o/ r' G; F+ ^3 c# o( s1745976 SIG_INTEGRITY GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing5 `% I" M: B% Z
1690820 SIP_LAYOUT PLATING_BAR Cannot add fillets to pads with plating bars in release 17.2-2016( j, F! ]( G9 H* K! _( R
1725042 SIP_LAYOUT PLATING_BAR Creating a plating bar removes dynamic fillets
: m# f4 F8 u& c! }+ e! X1747534 SIP_LAYOUT SHAPE Moving fiducial crashes SiP Layout+ l' x r. }& y6 `* b* C8 ~/ D
% B4 ?8 S& {- W1 ]" ?5 w3 l5 ^0 O
7 A3 [* \* k! o6 k) JFixed CCRs: SPB 17.2 HF020
1 T* d0 s: a6 G* n' f05-21-2017
' s+ M4 d3 R# `5 q) A========================================================================================================================================================0 @! k. y! U+ Y5 k( h& ]" V+ \+ d
CCRID Product ProductLevel2 Title' f& F0 @& c+ Q- T" x1 d+ G7 ^& _
========================================================================================================================================================
( h& X" G3 I- p0 O" v) j" Y0 c1737443 ADW DBEDITOR Revising the schematic model classification for one category causes all parts in the library to be revised
- ?! p" y6 f5 X- K6 n, _. y% E/ q1734123 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas crashes Allegro PCB Designer in 17.2 S0160 b# Z& o( ]3 `: E) c
1742084 ALLEGRO_EDITOR DATABASE Running DB Doctor on DRA files with custom pad shapes resets some of the custom padstack shapes in release 17.2
' A+ Q' r( S; r. l0 R8 M1739397 ALLEGRO_EDITOR INTERACTIV In release 17.2, running the SKILL function axlImportXmlDBRecords causes Allegro PCB Editor to crash5 }, g4 E, |2 }9 r) W3 ^
1724588 ALLEGRO_EDITOR MANUFACT Backdrill Route keepout suppressing existing Route Keepouts
- ~" o0 K$ @, L- z2 V+ U$ x; e1740036 ALLEGRO_EDITOR MANUFACT Generating the cross-section chart does not provide information about the overall board thickness
" y% w! S ^) [* l7 s# P) N4 g1743726 ALLEGRO_EDITOR OTHER IDF file export: In release 17.2, only one design outline is exported as against multiple board outlines in release 16.6* _' m, ^- o6 w+ y5 K
1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor
4 K$ R, }! l7 ^: t* r: J- T1729350 ALLEGRO_EDITOR REPORTS Net loop report is not working.4 j) t, o! `: f! d( C
1713014 ALLEGRO_EDITOR SHAPE Incorrect behavior of donut shaped pads at certain rotations! b- g/ x& u& p6 c ]
1739870 ALLEGRO_EDITOR SHAPE The artwork is different from the PCB in release 17.2 Hotfix 171 ^2 r6 ?' N: j* m
1698869 ALLEGRO_EDITOR SKILL PCB Editor crashes when trying to open another .brd file after running SRM on first .brd file
4 O Z; ^; M8 X( A1739307 ALLEGRO_EDITOR SKILL axlCNSDFAExport fails after first run
: b& {8 _+ E. t' C: n3 S/ F1743385 ALLEGRO_EDITOR SKILL SKILL APIs for STEP model mapping are not available in release 17.2 Hotfix 17 or 18
0 j5 R' ^( C) Q% u2 ]* C1685826 ALLEGRO_EDITOR UI_GENERAL Reports when opened from Status Form disappear behind PCB Editor canvas when clicking on canvas1 h7 P( u( V7 U! L- ^
1687797 ALLEGRO_EDITOR UI_GENERAL Cannot open two HTML windows, one after the other, while using SKILL function
# |8 W. d) Y6 e, ]- z1 V1696229 ALLEGRO_EDITOR UI_GENERAL Setting the 'allegro_html' environment variable in User Preferences Editor overwrites existing popup text windows6 ?' ~: C. ?4 X5 w) p- A4 D
1708636 ALLEGRO_EDITOR UI_GENERAL In SPB 17.2 release, keyboard focus automatically shifts to the newly opened dialog box- w! R# {2 t7 p6 D
1711367 ALLEGRO_EDITOR UI_GENERAL Launching two report windows using SKILL is not working in 17.2
1 E1 Y# O' q4 J Y! Q5 R1742856 ALLEGRO_EDITOR UI_GENERAL Allegro PCB Editor crashes if Project Manager is open for a design in release 17.2 Hotfix 18
. K/ p% \8 B `5 t$ {* W" v1 o3 T B e1729519 APD SHAPE shape degassing does not generate all voids to cover entire shape
" h, x6 @* x+ \0 h% U$ P1711375 CONCEPT_HDL CORE Copy-paste of schematic between two instances of DE-HDL is not working as expected+ P# O" ~+ b, a: n4 w
1737230 CONCEPT_HDL CORE On the Linux platform, copying of schematic objects does not work between designs of releases 16.6 and 17.2: R& U3 [: I7 m: {) `# p
1741375 CONCEPT_HDL CORE Inconsistent behavior of the Move command when moving a symbol6 n0 v5 A; Q9 }, o: O) p
1743992 CONCEPT_HDL CORE Inconsistent behavior of the Move command when moving a symbol# ?1 N4 P- {4 U8 P0 |$ B
1736093 CONSTRAINT_MGR CONCEPT_HDL Incorrect topology extraction and mapping errors related to MUX parts
+ R8 x5 y8 w2 c; I2 Y5 D( W2 N1743518 CONSTRAINT_MGR CONCEPT_HDL Lag observed in expanding and collapsing the net classes in Constraint Manager( f9 y2 d8 _/ t: U2 z( x1 Q
1730159 FSP ALLEGRO_INTEG FSP diff engine does not read PF Thevenin connections in FSP
# q# X4 Z S$ y0 y/ j, U1664070 ORBITIO ALLEGRO_SIP_I Display pads of SMD components on correct layer
: c+ {$ l1 N* U' O0 f1709319 ORBITIO USABILITY OrbitIO issues an error about Device template while importing brd with Bundles
0 ~' }5 z( M; }6 G1741150 PSPICE ENVIRONMENT Need a way to prevent the 'pspSimSetting.js' file from being overwritten by a hotfix installation in 17.29 m7 l1 E# e; v& e: t9 F3 o
1735354 PSPICE SIMULATOR Access to custom nom.lib is not working as expected* A: ]$ J7 c$ Z& Z {) ~* K
1716523 SIP_LAYOUT COLOR Tool crashes on using the PageUp, PageDown, and Tab keys in the Color dialog box.
% T. j3 ^4 q" M- j3 R3 m/ v# T2 G; F& X( z% G/ }" a* }' ?
% C+ H% O7 _: e1 N$ iFixed CCRs: SPB 17.2 HF019* }( P; x! i9 \/ b1 Q
05-6-2017
# J, B7 Z4 F6 h========================================================================================================================================================. b3 `6 T: ]7 v. m
CCRID Product ProductLevel2 Title
3 V- I5 v# x9 _3 f* x4 f: m% \========================================================================================================================================================
# y# S$ q+ J Q; o0 q7 w1701785 ADW ADWSERVER Getting 'Unable to locate tools.jar' error while using 'Copy Projects'
: R, b6 S$ \1 ?$ t! y/ i, F% d7 `: K; s1706782 ADW ADW_UPREV Design uprev failed with error 'ERROR (FM-107): Failed to run adw_uprev'
* ?- s. a: ? Q4 J1508159 ADW FLOW_MGR Flow Manager 'Open Last Project' option points to a deleted project' y- f. Q) |& ^
1690903 ADW FLOW_MGR Flow Manager library project list empty after 'Remove From List'
- `% ~2 O, u# M1705224 ADW LIBDISTRIBUTI Cannot migrate Library Footprint Models having subdirectory to release 17.2-2016
$ W# ~% l% D k3 A" {1672037 ALLEGRO_EDITOR EDIT_ETCH Add ZigZag Pattern crashes PCB Editor
9 l+ e* G, c; O! ]2 q2 G1695711 ALLEGRO_EDITOR EDIT_ETCH In release 17.2-2016, Fiber Weave Effect - Add ZigZag Pattern crashes in Windows 10
& w2 y$ q3 C0 }0 l- ?5 q1706522 ALLEGRO_EDITOR INTERFACES DFX import displays error message '*Error* eval: undefined function - cloneID' but imports outline
- c5 ]3 }7 b& G; b5 y1716336 ALLEGRO_EDITOR INTERFACES DXF file is not correctly imported into PCB Editor
: N% ?6 B0 S) y( ^/ t4 n( u1720290 ALLEGRO_EDITOR INTERFACES Incorrect rotation of padstack after dxf import) M0 H" o V! d9 \ a
1724683 ALLEGRO_EDITOR INTERFACES DXF OUT: incorrect Rounded/Chamfered rectangle pad rotation
6 ? l( t0 i7 m- {, _1732587 ALLEGRO_EDITOR INTERFACES Format/content of ipc356 files exported in release 17.2-2016 different from release 16.6$ Y! w7 [8 I: _, Q; q8 }
1737516 ALLEGRO_EDITOR INTERFACES IDX Import works differently for placed and unplaced parts, X7 Q( g C/ p0 v- x; w
1715152 ALLEGRO_EDITOR SCRIPTS Clicking Layout in Project Manager fails to load PCB Editor and gives message 'Word too long', t+ ~- H. u# A: T; m4 X
940699 ALLEGRO_EDITOR SHAPE Update shape to smooth fails to void a few clines.
# q! ?- S- R6 ?, Q1706581 ALLEGRO_EDITOR SHAPE Dynamic shape void clearance errors with vias* w) {/ x8 C3 D* D% i- N7 r8 Y0 }# r
1638300 ALLEGRO_EDITOR UI_GENERAL Version information set in $cdsversion truncated on title bar for some tools/ x6 j3 D0 d7 b9 q g3 h8 j/ G
1697732 CONCEPT_HDL CORE Pasting a signal name results in warning (SPCOCN-922) if the wire is too close to the edge of the page border* e( i$ V) H4 V. T4 n9 v
1729510 CONCEPT_HDL CORE Changing the name of a split block adds pages that are part of the page gaps
& y) ]$ X3 l8 n& o3 O X6 B( y1721065 CONSTRAINT_MGR CONCEPT_HDL Physical import errors on changing plane to conductor in stack-up9 o; y- e. V* \; U& _5 p g9 q5 v
1734875 CONSTRAINT_MGR OTHER 'Create Spacing CSet' crashes tool from existing CSet context and grayed out in design context
1 M) Z( k i7 \8 S1473104 ECW PART_LIST_MAN Pulse does not filter capacitor values correctly1 [* f1 \1 H4 h
1736580 PCB_LIBRARIAN SYMBOL_EDITOR Grids are not displayed correctly in Symbol Editor
; j; J2 ]3 {+ f1 B1738955 PCB_LIBRARIAN SYMBOL_EDITOR Need ability to edit Symbol Properties
( S! j# J% M* i* @, H* N, w" \1735215 PSPICE FRONTENDPLUGI PSpice part search customization CDN_PSPICE_ODBC_SRC environment variable is not working
/ q2 l3 D( \) c* P/ Q8 `. u9 E1733198 PSPICE PROBE Probe crashes when exporting trace expressions with multiple plots to CSV files: |6 K" N1 {, s( [
1737060 SIG_INTEGRITY SIGNOISE signoise fails for the AllegroSigrity_HS_Base_Suite option in release 17.2-2016 and release 16.6-2015
# \4 K Q/ ?% H# t/ d, l+ N1707443 SIP_LAYOUT WIREBOND Moving bondfingers violates spacing constraint/ ~! N) {% z" W& c
# `- \8 X# C- S9 y8 L: X
, E( g& P9 E& d) \! x; _6 }( k1 `Fixed CCRs: SPB 17.2 HF018
4 C+ ?8 O7 i3 P; r04-23-2017: J8 ^. u) R8 f9 i( `
========================================================================================================================================================
/ e |% y5 ?# lCCRID Product ProductLevel2 Title
. c1 U) H: L1 [; l) x: Z========================================================================================================================================================
$ w" J' M' w1 _7 o1721773 ADW ADW_UPREV adw_uprev updates all versions in history log to the new version. Should only insert note about uprev.
4 y& e# Q; S! h) K1 X, t. q3 o, \7 M1684346 ADW LIBDISTRIBUTI lib_dist_client fails for new release 17.2-2016 design server
* W. R: e+ l; }$ ~3 F1696632 ADW LIBDISTRIBUTI lib_dist_client fails on release 17.2 Designer Server having release 16.6 Master Server0 @- _" v# n! k: W/ U0 y
1705224 ADW LIBDISTRIBUTI Cannot migrate Library Footprint Models having subdirectory to release 17.2-2016
0 d7 G& ?4 k9 P8 O+ c2 h1721017 ADW LIBDISTRIBUTI adwserver -install fails intermittently during Master Library Server or MLR distribution
) F' q: ^, `& G% g* v1711373 ALLEGRO_EDITOR COLOR Cannot interact with Allegro PCB Editor when Color dialog is open
$ X* D- H; p- m1 m( W4 B5 ~9 f1710772 ALLEGRO_EDITOR DATABASE Mirror command not working on zones
$ l5 I: L8 D, q% T% q% J/ l- }1725621 ALLEGRO_EDITOR DATABASE PCB Editor crashes when moving a group of components or clines! B" s, w. ^4 @, p1 u
1699796 ALLEGRO_EDITOR EDIT_ETCH AiDT fails and reports there are no timing constraints even when propagation delay is set1 t% c# D w7 r1 t8 x1 f
1726483 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashing when converting corners to arcs: ~# v6 t4 `9 H- ^: ^) Y0 E, }; I
1726678 ALLEGRO_EDITOR INTERFACES IDX copper layer export does not export all pin pads7 V- ?" [4 W& V7 p
1691036 ALLEGRO_EDITOR MANUFACT Fillet not centered on trace
6 J! T' n1 p& T5 V* S1732304 ALLEGRO_EDITOR MANUFACT Countersink does not have drill figure on NCCOUNTERDRILL-1 subclass
# y' S* s8 z8 w O1719564 ALLEGRO_EDITOR OTHER Cannot open PDF published in release 17.2-2016 in third-party software
' W/ o) [) X- a! Y1723065 ALLEGRO_EDITOR OTHER PDF out does not print the outline correctly
6 E/ d+ c# A% l9 }' t2 Q- R5 V+ B1729247 ALLEGRO_EDITOR OTHER Cannot delete shape on Route Keepout layer& V% b% u+ B/ c7 o% j0 D) b$ F
1722747 ALLEGRO_EDITOR PAD_EDITOR Option to enable 'Connect by Touch' in Pad Editor
: O7 J/ p b# I4 y8 a% L% A1731643 ALLEGRO_EDITOR PAD_EDITOR Changes to secondary drill are not saved on padstack update# I& l1 e# s$ Q8 u j( E. c5 ]
1727303 ALLEGRO_EDITOR REPORTS The 'Shape Dynamic State' report has changed to 'Shape Dynamic Status' in release 17.2-2016
/ r/ R+ G2 b2 W" d$ P1 o1695879 ALLEGRO_EDITOR SHAPE Dynamic shape priority error creates shorts.* k- G: l1 J0 E6 @4 |
1713014 ALLEGRO_EDITOR SHAPE Incorrect behavior of donut shaped pads at certain rotations
* ^" K! O: d: Y1 e @1588769 ALLEGRO_EDITOR UI_GENERAL Alt+key shortcuts are not available in release 17.2
' c' g1 W }$ Q$ K0 W1602563 ALLEGRO_EDITOR UI_GENERAL Shortcuts to menu items not working in release 17.22 H* I! R. U% a
1603776 ALLEGRO_EDITOR UI_GENERAL Alt key not working with menu commands/ ~. C( _% A1 ?# F' ^: H [9 X4 r
1611516 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts have no response* H% s, L; N, ~& M
1647271 ALLEGRO_EDITOR UI_GENERAL Preselection is not working for docked Find window
h/ P, f9 ~: ~) U m9 @8 l$ l, A1650044 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts are not working properly in release 17.2; H1 Y: ^( |/ \$ @" q( l
1651912 ALLEGRO_EDITOR UI_GENERAL Inconsistent response when using the Alt key
: G- i6 b0 S+ P9 M1 }( y' P1679964 ALLEGRO_EDITOR UI_GENERAL Many dialog boxes are blurred in Allegro PCB Editor
0 G9 W" C, @1 q b7 e c1692416 ALLEGRO_EDITOR UI_GENERAL Underscores in menu commands denoting shortcuts are missing in release 17.2
& S; x2 y5 |/ H# H: W: `4 [1693055 ALLEGRO_EDITOR UI_GENERAL Reports with html links end with an extra > at the end: @2 R* V) |! v6 \
1693968 ALLEGRO_EDITOR UI_GENERAL Batch process that uses SKILL is taking too long to process files and generate reports& N$ B* @+ S4 }5 v/ L3 w
1698840 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016 Waive DRC report, selected coordinates of a Waived DRC remain blue6 T: B/ U8 v$ A. F( U* {
1703065 ALLEGRO_EDITOR UI_GENERAL Menu shortcuts do not work as expected
; |, G0 _4 G& X1707547 ALLEGRO_EDITOR UI_GENERAL Release 17.2: The Alt key function is not working in PCB Editor
' v; O* b7 k+ l) a2 D# o1709280 ALLEGRO_EDITOR UI_GENERAL Alt+Function key not working in release 17.2.
4 X/ U/ O* Q* m, |% d1711203 ALLEGRO_EDITOR UI_GENERAL Color does not change for selected coordinates in reports and Show Element1 W7 y% t+ P! W- _7 R1 s$ x
1711724 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, custom interactive menus stop responding when invoking another custom command
" s& [1 p& i! G+ z& o# M" B: \1715613 ALLEGRO_EDITOR UI_GENERAL With undocked Options window there is a mix up of entered text and funckey/ ~: p; w6 v& _! [
1719301 ALLEGRO_EDITOR UI_GENERAL Selected coordinates do not change color in reports and Show Element
6 d' T- j5 M* P7 H1724197 ALLEGRO_EDITOR UI_GENERAL Short cuts and hot keys not working in PCB Editor in release 17.2-2016
* {' K# O3 V" [. Z5 z1728724 ALLEGRO_EDITOR UI_GENERAL Funckey is not working in release 17.2-2016
, g$ Q! a+ `% A0 }1673703 ALLEGRO_PROD_TOOLB OTHERS Design compare not reporting the Top and Bottom layer differences
) x' n: V# J# B& G6 ^) Q1704474 ALLEGRO_PROD_TOOLB OTHERS When using Productivity Toolkit - PCB Design Compare, 'Override undefined width' is incorrectly applied- |7 h2 M1 R3 A% u1 y% D
1571035 ALTM_TRANSLATOR CAPTURE Circles in third-party schematics not getting translated into Capture
5 q3 {. m; k+ {3 N* u: M1588911 ALTM_TRANSLATOR CAPTURE Capture crashes when translating, project and libraries are empty' B( [7 Q- z0 j
1589394 ALTM_TRANSLATOR CAPTURE Schematic getting shifted off the page after translation
- P6 |" n: h$ i3 z3 @1631294 ALTM_TRANSLATOR CAPTURE Errors while translating third-party design when original design is in metric units
6 K, ]* N5 b4 s2 t. W. ?, N! J( L1663176 ALTM_TRANSLATOR CAPTURE Only first sheet of design getting translated from third-party schematic into Capture
4 _/ t1 @6 P6 S1 m9 s+ m% B8 R0 Q1694363 ALTM_TRANSLATOR CAPTURE Capture is unable to translate third-party designs
6 C0 |2 B. i8 _1 A7 {7 D1539739 ALTM_TRANSLATOR CORE Capture crashes on importing a third-party project E Y) X1 n2 B7 L/ e
1542860 ALTM_TRANSLATOR CORE Capture crashes on clicking Translate after selecting a third-party design
0 o: i* k, B$ E& G1551642 ALTM_TRANSLATOR CORE Unable to import third-party schematics into Capture
# R! y' b& ^& D( S1 H% C" ^1 S1572929 ALTM_TRANSLATOR CORE Footprint names getting altered during translation$ ~ g% G8 ]0 u9 c3 ?# A" a
1568436 ALTM_TRANSLATOR PCB_EDITOR Unable to translate third-party layout data into PCB Editor* T3 i7 k# s4 z# Q! `, G+ @
1629256 ALTM_TRANSLATOR PCB_EDITOR Getting empty symbol and devices folders when importing into PCB Editor L! Q1 m+ w7 A( a; M H
1664120 ALTM_TRANSLATOR PCB_EDITOR Import from third-party to PCB Editor is not translating data correctly! Y+ D: N% b; q+ e& [
1701537 ALTM_TRANSLATOR PCB_EDITOR Import does not complete and reports errors
4 r5 g4 r- W. r2 B5 {1698706 APD DIE_GENERATOR When using Compose Symbol from Geometry, circle from DXF cannot generate to pin. ?2 H4 Z4 a2 T4 c2 v/ ?
1714528 APD DIE_GENERATOR Getting 'illegal pad pointer' warning when creating die from geometry) |/ G# ?$ P; z; M; [" Z
1714532 APD DIE_GENERATOR Compose Die from Geometry creates incorrect pad shapes3 O a3 G' i' _9 G! C. Y" z E
1734310 APD MULTI_USER Symphony server mode malfunctions when die layer present.
' p0 p7 [+ w# ^. @- h$ m1 h1725506 APD SHAPE In release 17.2-2016 Hotfix 015, void is not generated in Artwork for BC7 layer causing short; O: w3 a- H/ c
1724395 APD WIREBOND Running axlBondWireDelete returns error message
# ] \# B' P, ]5 ]1726609 ASDA CANVAS_EDIT Paste should not be allowed in the Current Refdes column of the Change Refdes form
% D& l8 Q9 e$ T. Q1719754 CONCEPT_HDL ARCHIVER Path stored in the compressed file starts from /home instead of the current working directory, ]. Z$ U/ e5 S0 J
1726570 CONCEPT_HDL CHECKPLUS Checkplus crashes on Windows 10
2 M2 ^) P9 C7 |( w3 V1697977 CONCEPT_HDL CONSTRAINT_MG Differential pair disappears when it is packaged
$ v1 E- X+ Q# v9 q* |, N1679575 CONCEPT_HDL CORE Page numbers are duplicated in Hierarchy Viewer when editing page names% b; M" w/ p/ p4 b
1697732 CONCEPT_HDL CORE Pasting a signal name results in warning (SPCOCN-922) if the wire is too close to the edge of the page border" A1 d; b2 Z/ ~ c3 ~+ K P) \
1711564 CONCEPT_HDL CREFER CRefer crashes while processing a hierarchical design containing subdesigns' H0 c( v' m- n
1730736 CONCEPT_HDL OTHER Crash on generating BOM from design; T& K/ e* H0 V' \
1608350 CONSTRAINT_MGR CONCEPT_HDL Name of buffer model is not passed from Constraint Manager of DE-HDL to SigXplorer4 m0 E* h5 W; H: A/ T0 ^6 G T
1715803 CONSTRAINT_MGR CONCEPT_HDL Extract a net from constraint manager to SigXplorer, the models assigned are not displayed in SigXplorer9 y& F" P0 B2 |
1718073 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors on an upreved design in release 17.2: Pins in XNet and CSet do not match4 b9 a' e( n2 N
1720886 CONSTRAINT_MGR CONCEPT_HDL SigXplorer does not extract assigned model from the schematic& T& E) w# X2 \" i! \9 e/ Y
1718514 CONSTRAINT_MGR ECS_APPLY Extracted topology does not use the PINUSE overrides specified on the canvas5 y9 p" Q$ g0 m% z) L3 w
1722306 GRE CORE Boards with Total Etch Length constraint only should not include z-axis when budgeting pin pairs K0 @- W" ]1 Q- z! H& G0 B! Q Z
1710049 PSPICE SIMULATOR Functions are not taking parameters in correct order+ i& T* s( [( H% w* R
1693021 SIG_INTEGRITY OTHER PINUSE is not updated correctly at model assignment with specific steps" [* c; ?# Q8 R- M' c
1730854 SIP_LAYOUT SYMB_EDIT_APP Cannot delete all the die pin from a symbol using the Symbol Edit application mode
: W( w2 w2 s7 Q+ Z5 n% E
$ q7 E9 o5 T# r- `0 Z
! @/ C2 m; Y3 k3 eFixed CCRs: SPB 17.2 HF017
$ K. n, q$ F$ \04-13-2017
+ |7 p5 _& E4 O: v========================================================================================================================================================3 k4 v3 o, ~+ S
CCRID Product ProductLevel2 Title
0 [; A+ ]6 w4 f========================================================================================================================================================5 ]# W9 M4 w' M) V$ A# }- K; p. z
1732877 ALLEGRO_EDITOR SKILL The 'axlXSectionGet' function fails in release 17.2 Hotfix 016
6 w) t7 d# a) \: A
% C- O+ a' S" r0 c" h6 s e; l& D ]7 V- l3 A
Fixed CCRs: SPB 17.2 HF016
: a( c ]* r+ N1 r5 L& m04-6-2017
. u6 U& S6 B) Q======================================================================================================================================================== c+ C% y0 E3 c
CCRID Product ProductLevel2 Title
4 J1 |9 d; s& p+ Z========================================================================================================================================================! _) Q2 O7 x/ S) H
1673128 ADW COMPONENT_BRO Directive is saved in project CPM6 d# r6 R+ F2 R" b
1673510 ADW COMPONENT_BRO Lifecycle status color column is not sorted correctly in Component Browser search results( }7 c" g9 K0 ^8 v5 h
1604734 ADW DATABASE Parts displaying non-key properties and values in the Component Browser in ADW- l) t0 ?) x, Z; o8 O. v1 B
1142957 ADW DSN_FLOW No Help available for schematic design verification! w! r; R) _1 r; y2 q' D% _- l! v
1609186 ADW DSN_MIGRATION ADW Design Migration utility should handle ADW board reference projects and manage atdm.ini9 n( b0 i' d; `/ ^& Q0 q
1591757 ADW GENERIC_UI Running 'Create Test Schematic' in ADW Flow Manager results in Error SPCOCN-1736/ a# T" [0 E( P; }
1588111 ADW LIBIMPORT Library Import fails with Java errors while processing .csv files
; R7 h. A6 F3 U- P- w6 Z1642367 ALLEGRO_EDITOR 3D_CANVAS Component height is not correct in new 3D Viewer* T* D% W1 u9 }2 q
1642668 ALLEGRO_EDITOR 3D_CANVAS The new 3D canvas does not show STEP model of the drawing (.dra)* h' J- j7 V, a/ _* Z9 [. x1 P* _
1653247 ALLEGRO_EDITOR 3D_CANVAS New interactive 3D Viewer shows wrong placement/ d# V8 n. b4 c1 M9 m6 M9 q: S
1658275 ALLEGRO_EDITOR 3D_CANVAS Components on the bottom side are shifted in the new 3D view+ B4 l8 N9 m% x$ E( w" v
1639244 ALLEGRO_EDITOR ARTWORK When importing an artwork, a sub-folder is created with the value of the ads_sdart environment variable
, W3 x6 l- x3 R: L9 w" f4 B# M! u I1658173 ALLEGRO_EDITOR ARTWORK ARTWORK: Value of Scale factor for output.- B& \) s, ~& Q% T: `: R
1661760 ALLEGRO_EDITOR ARTWORK Import artwork to Design Outline layer does not give error in Allegro prompt.6 |4 A% G- X; n+ d. @4 _8 V. T6 I
1667778 ALLEGRO_EDITOR COLOR Add option to set FORM mini dehl_retain_color to NO
: y) A3 \; }: |& D7 R7 W1669462 ALLEGRO_EDITOR COLOR Changes made to the Visibility tab are not reflected in the Color Dialog window
8 _& [- ]5 k& s! t3 c9 }1 y9 v. ]1641265 ALLEGRO_EDITOR CROSS_SECTION The differential impedance value for a layer is not getting updated
Y( ?1 C7 Z, a- p5 \7 b8 j1648149 ALLEGRO_EDITOR CROSS_SECTION Getting warning when calculating impedance in mixed stackup
: F. P2 |; g7 c+ o" \1671441 ALLEGRO_EDITOR CROSS_SECTION Enhancement request for cross section dialog box2 R- x- x9 X' E0 d$ X* q) ~* g' v
1673320 ALLEGRO_EDITOR CROSS_SECTION Diff impedance calculation fails
0 D/ _9 D, z! G T- |1690021 ALLEGRO_EDITOR CROSS_SECTION How to keep settings of expanded/compressed columns in the Xsection, P8 i; O! ?2 v8 U8 S, |
1703831 ALLEGRO_EDITOR CROSS_SECTION Calculation of Diff Z0 fails in flex designs
) _* A) h: y2 ^1 e- h1711484 ALLEGRO_EDITOR CROSS_SECTION ShowAll Column does not retain its status/ |6 [3 n4 N5 B: r% K
1672841 ALLEGRO_EDITOR DATABASE ERROR(SPMHDB-153): Table corrupt; current/maximum mismatch" K' A8 W& |) x) C; l3 g
1673613 ALLEGRO_EDITOR DATABASE COVERLAY_TOP not present in the Non-conductor section of Color Dialog window5 V# N* A, Y- u0 q
1688123 ALLEGRO_EDITOR DATABASE Drill Plating Issue: d% l, Z8 N: n- h4 t
1701995 ALLEGRO_EDITOR DATABASE When upreving a 16.6 brd to release 17.2, lines drawn on OUTLINE are translated to CUTOUT and not DESIGN_OUTLINE1 X/ n) f* A4 ]
1710772 ALLEGRO_EDITOR DATABASE Mirror command not working on zones h% X4 d M& j9 b9 a& }' j: h0 l
1713335 ALLEGRO_EDITOR DATABASE Defining Adjacent_layer_keepout_above and/or Adjacent_layer_keepout_below and then saving the .dra file giving error2 {! C7 I2 z" W- N+ C8 z; N3 Q
1693289 ALLEGRO_EDITOR DFA File - Save As script does not save the DFA file
& t3 y4 {1 ?0 o; w; s# N1644004 ALLEGRO_EDITOR DRC_CONSTR Unreported DRCs from dynamic copper to line and dynamic copper to SMT pin* n* s) E8 b% Q) v, k
1651425 ALLEGRO_EDITOR DRC_CONSTR The .brd file crashes when moving text controlled with minimum metal to metal constraints5 _ H8 v% r# |/ A
1663494 ALLEGRO_EDITOR DRC_CONSTR Reported Mechanical Pin to conductor spacing DRC constraint value is incorrect leading to false DRCs
# R. Y* k3 ?! N; H0 ^! D4 Q4 _1 P1687049 ALLEGRO_EDITOR EDIT_ETCH Create a Via Structure disconnects nets
% `- A8 N/ {( h) M6 y4 I1704296 ALLEGRO_EDITOR EDIT_ETCH Asymmetrical fanout created for BGA Quadrant style
, P" J+ I/ D, U6 @3 v1686873 ALLEGRO_EDITOR EDIT_SHAPE Merge static shapes deletes both the shapes selected.
* R1 I4 ^" w& t: D. K2 w8 _3 u) N1629925 ALLEGRO_EDITOR GRAPHICS Errors reported and no layout data drawn in PCB Editor in release 17.2 Hotfix 003 on Ubuntu 14.04+ y1 Y( Z0 g4 d" N }
1628895 ALLEGRO_EDITOR INTERACTIV Shape Edit mode: An error message is required when attempting to edit a Shape with the FIXED property
. U8 r/ p S; l5 H6 o1666379 ALLEGRO_EDITOR INTERACTIV Place replicate is not working on the attached test case
) l/ N: s# y8 K. y+ c5 U1668282 ALLEGRO_EDITOR INTERACTIV Grid display incorrect for repeated grids
1 q/ H! o3 f8 j' z+ s1 Y X1675531 ALLEGRO_EDITOR INTERACTIV Design Entry CIS: Cross Probing with PCB Editor and Constraint Manager is not working
" }+ G6 A' p! y4 f1694470 ALLEGRO_EDITOR INTERACTIV Update description of variable padstack_nowarning_display
" i, X' v) @* R1696855 ALLEGRO_EDITOR INTERACTIV Mixed grid setting is not displayed correctly on Define Grid screen.8 T/ m2 U! e% T8 j7 ?: R2 F! y
1698192 ALLEGRO_EDITOR INTERACTIV Deleting and replacing a component causing database corruption in Hotfix 0093 _7 R/ E" j1 m: q2 Z7 v X
1703671 ALLEGRO_EDITOR INTERACTIV An error occurs when defining grids with zero increment value
6 G& a( ?% p4 A0 j1703812 ALLEGRO_EDITOR INTERACTIV Crash during move when using the 'snap pick to' option set to symbol origin1 C ]# b- y- S% i4 c8 r! r
1719276 ALLEGRO_EDITOR INTERACTIV Setting variable grid for 'All Etch' displays an error in the Define Grid form
1 E2 ^/ o4 N( U1 W1663422 ALLEGRO_EDITOR INTERFACES Shape loses group membership after importing through sub-drawing
) I; C3 V2 Z, ~: h1637959 ALLEGRO_EDITOR MANUFACT Thieving uses different clearance values around the route keepin.
; l% |" v( G: B Y$ c1716431 ALLEGRO_EDITOR MANUFACT Test points generation stops due to an error
/ E) V' {( ]. M5 h. `/ i- @1641994 ALLEGRO_EDITOR OTHER DB Doctor: Incorrect spelling of 'eliminated' in the log file messages6 L% g: J$ l6 j
1660496 ALLEGRO_EDITOR OTHER SiP Layout crashes when trying to generate abstract level view by using export chips and connectivity
: _$ X* F) O: g# b0 w' e% t1685464 ALLEGRO_EDITOR OTHER The 'alias ~S save' command is not recognized when set in the local env file3 n: Z. Z3 X. N* ?$ [ _
1696486 ALLEGRO_EDITOR OTHER STEP export results vary between releases 16.6 and 17.2
; p' i( g( B: g' k( S1706623 ALLEGRO_EDITOR OTHER axlBackdrillGet crashes for invalid argument( Y) e. y* X6 Y J9 J
1586957 ALLEGRO_EDITOR PAD_EDITOR In Pad Editor, selecting a pad geometry is not showing up in the Design Layers tab
$ P8 `8 B! U0 v0 x- [1610984 ALLEGRO_EDITOR PAD_EDITOR Geometry set in tabs not read, only initial value set in Start page is used# r$ u& {$ c& T6 H) X
1614015 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor in release 17.2 does not auto fill geometry in design layers
3 m# h0 z7 Y. A# n) p1636012 ALLEGRO_EDITOR PAD_EDITOR Keepout should not be allowed if antipad is not defined for outer layers) w! t* k1 o K( |5 U3 z
1641973 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor: Path to the previously opened .pad file is not seeded in the File - Open dialog on a fresh launch" r3 { }0 R# u! m* ]4 V
1642789 ALLEGRO_EDITOR PAD_EDITOR In release 17.2, 'Units' and 'Decimal Places' in Padstack Editor are not updated as per the .pad file
% ^; E# ?4 S* T: ?& }6 x1646914 ALLEGRO_EDITOR PAD_EDITOR The 'Save' button is grayed out in Padstack Editor# s$ P7 [+ h, E' I* k- o
1657553 ALLEGRO_EDITOR PAD_EDITOR No possibility to specify Padstack Editor default library path at invocation. g, z" N$ t: V9 J) c- _1 ~* T, p
1657609 ALLEGRO_EDITOR PAD_EDITOR Changing Tolerance field in Padstack Editor does not activate the Save button1 Y0 f; P" f2 _+ U7 q9 }
1662225 ALLEGRO_EDITOR PAD_EDITOR Padstack editor dialog message doesn't match available options2 Q) h1 } ]" r6 C( B9 v V
1667062 ALLEGRO_EDITOR PAD_EDITOR Padstack editor does not retain the decimal places from the previous session' H- Q+ H' Y' R8 {9 R
1672774 ALLEGRO_EDITOR PAD_EDITOR Pad Editor graphics appear to show offset incorrectly# S( _6 @& k& w$ q1 C
1674157 ALLEGRO_EDITOR PAD_EDITOR Update Symbols does not update Pad Type Information) q/ a( n+ q( b! A4 D" Q' g* w
1675438 ALLEGRO_EDITOR PAD_EDITOR Drill hole size warning for the SMD pad
+ I- v* t7 `9 J, [. f3 D, T1684376 ALLEGRO_EDITOR PAD_EDITOR Pad Editor issues with settings, such as decimal places, layers, and so on3 t1 v- D; j: ?8 r% _6 K
1690376 ALLEGRO_EDITOR PAD_EDITOR Variable padstack_nowarning_display fails to suppress warnings
) e. l9 n) C$ A. E, B. G& _1694649 ALLEGRO_EDITOR PAD_EDITOR Change Cancel button to No in warning generated when updating padstacks in design layout
' t1 ?- Q2 k" @( l$ g939242 ALLEGRO_EDITOR PLACEMENT Cross probing between Capture and PCB Editor is inconsistent
- ^+ ^5 z% P& ]7 k) H1103945 ALLEGRO_EDITOR PLACEMENT Place Replicate Create does not include the etch connected to pin R! y* }6 V& ?6 X0 a" ^
1233019 ALLEGRO_EDITOR PLACEMENT Allow cross probe object selection apart from highlighting during place replicate$ I+ A. w& w, L
1643078 ALLEGRO_EDITOR PLACEMENT PCB Editor flags an error message when a module is placed at a specific angle
% v0 I8 i: S2 H( v/ _+ _1696932 ALLEGRO_EDITOR PLACEMENT Inconsistency with Snap pick to when selecting Segment Midpoint
3 E0 V$ F& [* Y+ t( r1654500 ALLEGRO_EDITOR REPORTS In release 17.2 Hotfix 006, display of Netin (back anno.) report fails when variable ads_sdreport is set7 S) ^. Z# Y- _. P6 x6 f N% f
1643992 ALLEGRO_EDITOR SCHEM_FTB Export Physical fails with the 'netrev.exe has stopped working' error: y% v- y0 N9 g: ]2 r' T9 H6 b$ B
1653400 ALLEGRO_EDITOR SHAPE Dynamic shape does not void a via.
5 l" e# x( ]/ Q. @& W1668262 ALLEGRO_EDITOR SHAPE dynamic shape does not void custom route keepout with arc3 V8 z) X# v( D. ?
1682569 ALLEGRO_EDITOR SHAPE Variable 'dv_squarecorners' not working correctly.
! E; V0 e0 i( R! z$ Q% `1696240 ALLEGRO_EDITOR SHAPE SKILL error when merging polygons
8 |: A. q2 \6 a' L1709968 ALLEGRO_EDITOR SHAPE In release 17.2, DB Doctor reports error in shape when no error was reported in release 16.6 for the same shape8 D! G, [" X+ \) B. w" b% I
1632505 ALLEGRO_EDITOR SKILL In release 17.2 Hotfix 004, PCB Editor crashes after SRM update and save# l" t; H; K6 |$ b3 C s, i
1651701 ALLEGRO_EDITOR SKILL Cannot set the etch factor value in the cross-section using the axlXSectionModify() SKILL command
0 M" B, u- ~- Q1 f1658419 ALLEGRO_EDITOR SKILL PCB Editor crashes after running SRM
0 P3 }0 k( `5 j+ k$ \1658948 ALLEGRO_EDITOR SKILL axlIsLayerNegative() is not working in release 17.2; a" x, \) o# K8 w; L
1670956 ALLEGRO_EDITOR SKILL axlIsLayerNegative() always returns nil6 i7 i7 t& Z9 [9 }% M
1687239 ALLEGRO_EDITOR SKILL Problem with SKILL function axlCNSGetPhysical - incorrect parse string
7 `; j. u, q9 e. K4 G r9 g# Y1692345 ALLEGRO_EDITOR SKILL The axlGetParm documentation example for deleting an artwork record is incorrect.
) N0 C- Y6 U# g3 @) S9 m' Y1707878 ALLEGRO_EDITOR SKILL Object rat_t does not work with axlDBPinPairLength.
8 ]9 W/ s& n6 x0 a1598061 ALLEGRO_EDITOR UI_GENERAL Adjust menus to allow side by side view; k6 E, q7 H' ?2 {% d! g, Q$ `
1599901 ALLEGRO_EDITOR UI_GENERAL Color Dialog box is not updating according to visibility tab.
$ d, G( P2 v6 e1602563 ALLEGRO_EDITOR UI_GENERAL Shortcuts to menu items not working in release 17.2) |7 v0 e& x# C! Y* T0 X! O, F# [
1603776 ALLEGRO_EDITOR UI_GENERAL Alt key not working with menu commands
; t7 N" D) [0 z1611516 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts have no response4 ?; c+ z9 S$ `4 t9 M3 K
1614763 ALLEGRO_EDITOR UI_GENERAL Cannot scroll to the bottom of an undocked command window in PCB Editor( d G0 w4 @. n/ @8 A# y! R9 \9 f
1619873 ALLEGRO_EDITOR UI_GENERAL Command Window scrollbar does not reach its end
( C1 S7 Z9 i- ^* ?" p/ v8 x1624617 ALLEGRO_EDITOR UI_GENERAL Dialog box title under Setup > Outlines > Design Outline... Design is misspelled as "Desgin"; Y% g' I0 A% ], M9 _
1631646 ALLEGRO_EDITOR UI_GENERAL Visibility pane not retaining the correct layer view5 e5 p) b, f% _! M9 ?
1637062 ALLEGRO_EDITOR UI_GENERAL The last line of the floating command window in release 17.2 is hidden behind the command window frame
$ x- l. P7 ?2 D+ T+ d, V6 j1642645 ALLEGRO_EDITOR UI_GENERAL Cannot scroll to the bottom of an undocked command window in PCB Editor
7 _% ]. i3 O2 }5 L5 A! v; E1645335 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes in Hotfixes 004 and 005 if ODE and Allegro Manufacturing options are installed
8 s5 F- [. }+ |$ w+ w1647520 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes after installing release 17.2 Hotfix 005
% A% o p4 V( R* W& X+ i* R1647541 ALLEGRO_EDITOR UI_GENERAL Release 17.2 Hotfix 005: PCB Editor crashes immediately after launch
$ R# B" J, W# c x/ S- L2 p1650044 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts are not working properly in release 17.2' D5 s: l+ I' w* U) g# \9 |
1651912 ALLEGRO_EDITOR UI_GENERAL Inconsistent response when using the Alt key
. o5 K; b* J7 g1652423 ALLEGRO_EDITOR UI_GENERAL Using the F1 key does not display the help document
7 T D9 I9 s; Z$ _4 O5 p2 w* Y1654600 ALLEGRO_EDITOR UI_GENERAL Spelling Mistake in "Design Outline" dialog box, Setup->Outlines->Design Outline, misspelled as "Desgin"
) E9 j7 t+ \/ \% z6 c* j+ y- g. B1654777 ALLEGRO_EDITOR UI_GENERAL Reports UI does not work properly when writing a report file.$ C c5 \+ O, l9 c {& D9 R M7 U
1655500 ALLEGRO_EDITOR UI_GENERAL Visibility selection ignored after color change
9 v @: O- g& U- m1655514 ALLEGRO_EDITOR UI_GENERAL Artwork Film is available in the View section only after you restart PCB Editor
9 u* G" a; f; u- A6 {1663819 ALLEGRO_EDITOR UI_GENERAL In release 17.2, SKILL function, axlOpenDesign(), does not work as expected$ R# l: K- @' m2 y
1671334 ALLEGRO_EDITOR UI_GENERAL Design outline is not shown in 'World View' window8 i8 p- @/ a2 I# |, _
1672148 ALLEGRO_EDITOR UI_GENERAL Add option in release 17.2 to change the placement of the Find, Visibility, and Options tabs similar to earlier release
& S8 J) x5 S' j( Q8 J) E# A1679418 ALLEGRO_EDITOR UI_GENERAL On choosing Edit - Move, the 'Symbol pin #' box is obfuscated
# n. d' n& ]- m1679761 ALLEGRO_EDITOR UI_GENERAL Choosing Edit - Spin hides 'Symbol pin #' partially% M0 [, x9 X1 ?$ ~3 ~1 r
1686887 ALLEGRO_EDITOR UI_GENERAL Hyper Text no longer selects coordinates for easy copy
) u* v& ?* s. ?) v) Q6 a/ k) E1687286 ALLEGRO_EDITOR UI_GENERAL In 17.2 Hotfix 009, the Static Phase meter shows up in the middle of the screen instead of the lower-right corner/ k8 m# P) u3 G& Y) P* F( ^4 w
1692416 ALLEGRO_EDITOR UI_GENERAL Underscores in menu commands denoting shortcuts are missing in release 17.2" g) z; ~: E, l' j
1693968 ALLEGRO_EDITOR UI_GENERAL Batch process that uses SKILL is taking too long to process files and generate reports1 N% G+ _) u; |) ^3 m
1702420 ALLEGRO_EDITOR UI_GENERAL Unable to maximize reports viewer in 17.2
0 z- E+ p/ \% W* ?1703065 ALLEGRO_EDITOR UI_GENERAL Menu shortcuts do not work as expected7 M( u- j* A2 F/ K$ j7 G% `
1703107 ALLEGRO_EDITOR UI_GENERAL Scripting using regional settings for decimal separator
$ q/ S2 g- B1 {1707547 ALLEGRO_EDITOR UI_GENERAL Release 17.2: The Alt key function is not working in PCB Editor
" A$ g' f4 g! m7 \) g% I/ F1709280 ALLEGRO_EDITOR UI_GENERAL Alt+Function key not working in release 17.2.
3 m) K# _% p; ]/ U( z7 L& n( n1639896 ALLEGRO_PROD_TOOLB CORE MFG collector does not move files to subdirectories
( s- L* p3 s3 m( ?3 s8 b& X0 I1608804 ALTM_TRANSLATOR DE_HDL Translation issues in symbols with multiple physical pins mapping to a single logical function
" P4 G$ {' r2 o. S* j! r( J m" z1658525 ALTM_TRANSLATOR DE_HDL Invalid characters in pin names5 [! k+ E% y$ o6 u! S' _) S* G
1658536 ALTM_TRANSLATOR DE_HDL All cell names should be generated in lowercase letters# t5 h( p% m5 {1 D
1609962 ALTM_TRANSLATOR PCB_EDITOR Errors reported during design translation3 V! [9 J: p, m( x* S
1661562 APD DRC_CONSTRAIN The wrong space calculation on finger to trace7 f& _! Y" M U) x9 O4 h8 k# q
1682398 APD SHAPE Deleting islands causes out of date shapes3 R3 R$ d5 V7 p+ {
1638112 ASDA CANVAS_EDIT Unable to rename multiple selected buses using the 'Assign Name' command
5 B N: A. {7 l+ }( R- `0 {4 E1645571 ASDA CANVAS_EDIT Various routing inconsistencies with synonym bodies on the canvas
8 Z3 r1 `- p6 _( m9 N# D; x1656336 ASDA CANVAS_EDIT Presence of illegal characters in the net name removes the entire net name1 S0 n6 Q" f9 m* \( ]* h4 U
1667176 ASDA CANVAS_EDIT Unable to add the port symbol in a specific scenario
+ h4 z/ n3 {4 _* D n3 G7 u1641473 ASDA CONSTRAINT_MA Importing a tech file into SDA makes the tool unresponsive1 z+ u. D) w, m' f' u
1661350 ASDA CONSTRAINT_MA Unable to create physical & spacing class from the docked CM
2 {$ }) M2 f( \( o1645557 ASDA IMPORT_DEHDL_ Importing a DE-HDL design into SDA adds the COMMENT_BODY attribute to nets
9 ?- E3 [. c2 w9 v' d9 w1652753 ASDA MISCELLANEOUS Tcl command window should display correct casing for autocompleted command, y6 d5 F3 v2 P
1654973 ASDA MISCELLANEOUS If there is a casing mismatch in the Tcl command name, correct command is not picked from the list
! e& c3 m% T6 E9 s1652718 ASDA PAGE_MANAGEME Page numbering on the page border does not update correctly when pages are moved, added, deleted
& {; I1 ]1 ]1 k& u+ k) p1699454 ASDA TABLE In the table object, cursor skips a cell on the first use of the TAB key" I7 z# ?; G. l: v
1702702 ASDA TABLE Copy-pasting table objects to a new page fills the headers and rows in black
, g3 x( r2 f; Q/ Q7 l1668877 CAPTURE ANNOTATE Using Ctrl+drag does not preserve the reference designator value
5 w2 f( ] b& Z- G7 B9 N+ M1665454 CAPTURE NETGROUPS Incremental copy for alias does not work anymore.
: D' l. ~6 W% m: O" q1634598 CAPTURE OTHER The ‘OrCAD_Capture_CIS_option’ license not released even after selecting another product option
6 Q6 n# i }, W' S0 I1636090 CAPTURE OTHER Capture crashes after switching from release 17.2 Hotfix 003 to 004 due to some Tcl files
" T, q$ a8 `& G# ~1650029 CAPTURE OTHER Crash while archiving a newly created PSpice project without adding simulation profile
: _2 X) M" p, ]7 g; o) k( f4 M1659602 CAPTURE OTHER Saving CIS BOM via TCL command window# r( V6 j8 s# M! Z, w5 S
1678715 CAPTURE OTHER Capture.ini [WebResourcesMenu] is not working in release 17.2
! _0 b7 g* k1 }+ O8 U5 n1619449 CAPTURE PROJECT_MANAG Search not working in a PSpice project
) O2 o! W, x, L2 t! l m( u+ r8 p' s1670133 CAPTURE PROJECT_MANAG Start Page showing wrong Software Version* h! F! B+ ^! D1 j7 [, N* D
1670766 CAPTURE PROJECT_MANAG autoreference does not work properly
- M9 P" D8 Z" a9 U1 u1676095 CAPTURE PROJECT_MANAG (SID:22758) OrCAD Capture Start Page reporting wrong hotfix installed5 r7 b' F' @# Y+ l
1658315 CAPTURE TCL_INTERFACE Inserting text with double quotes is not working as expected in PDF created from Capture. R- v& k/ z- c/ z2 X
1642601 CIS OTHER Design Entry CIS: SQL server password is required each time the tool is launched8 G1 _$ L F! m0 _
1712279 CONCEPT_HDL CONSTRAINT_MG Differential pairs are dropped from Net Classes when upreved to release 17.2-2016& g. F6 w. r9 [- X; A9 |# Q
1665449 CONCEPT_HDL COPY_PROJECT Copy project fails with error COPYPROJ-77
% l* \4 Z7 Z' x1661778 CONCEPT_HDL CORE Advanced Find will not find pins with the SIG_NAME property attached
+ ~0 g$ l' b; u1666084 CONCEPT_HDL CORE All user-defined properties are not listed in the Customize columns in Variant Editor% z, z+ s( ]" _& Q& B3 \9 F B
1667043 CONCEPT_HDL CORE Incorrect information in cpm.log file
. D; q# f6 H+ I" t7 \0 v5 R/ H3 @' Z1670659 CONCEPT_HDL CORE SIGNAME text off grid when pasting copy using ctrl+v.
+ Z$ X @) u2 ]6 `& r1697732 CONCEPT_HDL CORE Warning (SPCOCN-922): The object is being placed towards the left edge of the schematic. Ensure that the objects are pla1 e! M7 z# O. @. c8 w* t
1697955 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net
$ X E/ B% C4 f1711635 CONCEPT_HDL CORE The arrow keys do not work as expected in Windows mode' k; O6 f0 B7 q& Z+ V' f! i+ O
1713091 CONCEPT_HDL CORE Difference in the behavior of 'Add Signal Name' in DE-HDL between releases 16.6 and 17.2
$ T0 V1 w5 }% W* L$ X- }. U3 S1708820 CONCEPT_HDL OTHER In a board cache flow, component bodies are missing when importing another board cached flow project.$ s$ ~( @( Y, o. q) |% @: d& q
1639928 CONSTRAINT_MGR CONCEPT_HDL The '-filterFile' argument is not recognized when cmDiffUtility is run as a command line operation9 @! V% a" `! M m1 H }2 c
1657048 CONSTRAINT_MGR CONCEPT_HDL Unable to navigate through the search results in the CM Reports
+ [/ E& R5 A c Q1718073 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors on an upreved design in release 17.2: Pins in XNet and CSet do not match
4 e4 u' Q7 w7 a: W, T) p1717336 CONSTRAINT_MGR DATABASE Netclass members change during logic import; it's a toggle switch# b, Z' J }( m( H: t' S; D
1718514 CONSTRAINT_MGR ECS_APPLY Extracted topology does not use the PINUSE overrides specified on the canvas
( c+ W' \4 u. z+ U8 h" a; l% v1682885 CONSTRAINT_MGR INTERACTIV Constraint Manager worksheet switching does not work correctly in Linux
7 G: o4 K! S6 E, e. b3 v; f2 T1669523 CONSTRAINT_MGR OTHER Select is disabled in Constraint Manager when a command is active in PCB Editor
9 f) y! z7 t* G# I* `* d+ m1670802 CONSTRAINT_MGR OTHER Selecting a list of nets using the shift key does not work in Spacing and Physical domain9 K3 o3 h) N+ t: ^& X2 W
1670922 CONSTRAINT_MGR OTHER Title of the Layer Remove window is Constraint Manager
% l s! F3 g" L w; v1 ^ P! W' |1678235 CONSTRAINT_MGR OTHER Select option grayed out in Constraint Manager if a command is active in PCB Editor1 p$ N2 b% O/ g/ ?
1680917 CONSTRAINT_MGR OTHER In release 17.2, nets cannot be selected in Constraint Manager when a PCB Editor command is active1 o& ]# }/ H; K7 t1 K# h3 e
1691125 CONSTRAINT_MGR OTHER Highlight command no longer selects the net in CM
V8 i6 {+ Z! O1 X. h: A6 {1703791 CONSTRAINT_MGR OTHER Cross highlighting and assigning color to nets between PCB Editor and CM does not work9 @: O4 w% H; h! O
1649603 CONSTRAINT_MGR UI_FORMS Expand and Collapse commands do not work when multiple objects are selected, I3 z3 N9 e, y) X& S5 ^ A
1654931 CONSTRAINT_MGR UI_FORMS Expand, collapse only works on one of the multiple selected objects.' H, d, m Y* X
1668794 CONSTRAINT_MGR UI_FORMS Incorrect via name shown when filtering via list
$ i; H) x, q5 d3 T1678305 CONSTRAINT_MGR UI_FORMS Unable to use the CM worksheet customization (wcfx) from the CDS_SITE area
6 W9 d" C$ ~4 x; ]3 b1 ?) ?, p; c1679909 CONSTRAINT_MGR UI_FORMS Incorrect layer order getting saved when defining BB vias in Constraint Manager PCSet$ o7 c' n: l( Z( i
1691906 CONSTRAINT_MGR UI_FORMS Display Issue: When you use the filters, the horizontal scroll bars are duplicated- i" ?( T! w0 j0 C" \
1677893 ECW INTEGRATION Integrations list update is not working as per scheduled time
X3 Z9 G% o. T8 C% ]0 J# i I1652707 ECW METRICS Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart2 X1 f% Z: a' a6 X7 Q8 T
1654512 ECW METRICS Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart
% h% L" j d- [3 P# T c1668953 ECW METRICS IE11 Swedish only: Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart
G6 I$ [# ?' j* |1677443 ECW METRICS Queued up metric packets on Pulse server are not processed if there are any packets related to a deleted project' q* S1 a2 N" j! Y* H- y W
1663676 F2B PACKAGERXL Physical net name (PNN) errors in the log file
$ s6 Z5 m+ c3 W- D0 u* q1669583 GRE DETAIL AiDT always fails push when there is a connect shape attached to the cline being tuned3 H6 F) ^: q% A* g- M
1686350 INSTALLATION SPB InstallDiagnose fails to repair some errors
+ }6 H0 o, e* t( |, b1672369 PCB_LIBRARIAN EXPLORER Cannot create a New library build in Library Explorer.
% T( f& E5 |7 h* q( k% t- ?9 r. O1631034 PSPICE ENVIRONMENT When simulating the design in release 17.2, Capture crashes but works with release 16.6
2 J$ y- e/ u6 \1648284 PSPICE ENVIRONMENT PSpice project crashes when a design is opened in release 17.2( S( T; V& n K' F
1663336 PSPICE MODELEDITOR Ibis translation not supporting paths with spaces
2 c- a" Q' M3 n& ^1 j2 i1679376 SIG_EXPLORER OTHER Topology created in OrCAD PCB SI license cannot be reopened with the same license$ q4 Y9 m6 F6 c3 Y# V3 h5 `
1666484 SIP_LAYOUT CROSS_SECTION On converting a design from release 16.6 to release 17.2, a Dielectric thickness of ‘0.2032’ is added to another layer.
! ?" m% V6 L( ~( p1687988 SIP_LAYOUT DIE_GENERATOR 'compose die from geometry' does not retain the user-defined padstack name9 b5 v- ]) O8 K; }; ?- \
1715016 SIP_LAYOUT DIE_GENERATOR Using Die Text-In wizard to replace a die reconnects wire bonds to the wrong die in stack-up
" [% V7 ?8 ?* x' E$ Y# @1620601 SIP_LAYOUT MANUFACTURING Need the ability to create LINES with round end caps in the same way as the LINES appear in the database D6 G/ }2 s9 o+ T
1705963 SIP_LAYOUT PADSTACK_EDIT Pad Designer: "None" changing spontaneously into "Circle 0.000" in a pad stack definition and unable to save
' ]/ l `5 R) {& h1713767 SIP_LAYOUT REPORTS Reports in release 17.2 for the Verilog Port Name are adding incorrect data that was not found in release 16.6
2 b! }* J( Q- n$ k1696218 SIP_LAYOUT SKILL SiP Layout crashes on reassigning nets
# D3 Y4 C2 F# }0 J( }1695885 SIP_LAYOUT UI_GENERAL Visibility Tab check box: unchecked "All" disables access to "Shp" check box( x9 ?/ Y* `$ ^ ~, e
1639838 SIP_RF DIEEXPORT Enhance the error message, SIP-1507, to include that overlapping pins within tolerance are included during die export' E }3 N7 c/ W3 W; y% F
1653894 SIP_RF DIEEXPORT Redundant error message for die export, when view name is other than "layout"
5 t. ]; `4 z1 [1681332 SIP_RF OTHER Running die export causes Virtuoso to crash
4 \4 u: s6 X9 J0 s5 L1 n# U1679336 SPECCTRA LICENSING Min/Max Propagation Delay cannot be routed by PCB Router using OrCAD PCB Designer Professional3 [7 n1 j& C8 B" {- Y8 ?
w/ x6 R6 j+ y3 g; B
& J3 V n# x. Q1 Y G" b
Fixed CCRs: SPB 17.2 HF015
- L: \# k3 _3 B; j5 S03-16-20172 t' C/ P4 J% v5 i
========================================================================================================================================================
% ?+ I& O+ M+ `* _! D; @1 Y: rCCRID Product ProductLevel2 Title+ t2 Y0 p- }' n( b
========================================================================================================================================================
; l8 d ]0 c5 |& x4 J1653366 ALLEGRO_EDITOR INTERFACES Unable to attach step model to symbol# W5 A8 ~- V, Z. f$ B A& Q2 P* y
1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model
% G8 s/ e' F! h% Y1 K5 H1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function4 c; w& N3 c6 x( a. t, k
1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file
& m0 |1 |+ t5 I- ^- t1 @) `* v1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting Padstack Editor results in incorrectly scaled forms* j# x9 G8 J, p4 m1 n/ d+ [
1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design
: Q1 i8 B p, R8 K+ _1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees
; _ v8 B' U! g4 H- b1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.( l8 C u9 C$ S9 p5 [
1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
+ r- ?$ i# `! [# D1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor; o" {7 [4 X. X2 U; Z, b$ H
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not3 D) ]8 \, {2 }9 P
1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used; _5 l1 c* f/ R+ }
1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places0 e$ x# O$ @6 c$ t: X' N
1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value
) l, @' c9 _: r1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
, A$ j+ B6 |5 x- G5 X1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad7 h8 f% h) G# Q' f h# X8 {" S. m$ k
1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout. ?( C4 |( }5 x+ C4 [6 D
1698697 CONCEPT_HDL COPY_PROJECT Copy project corrupts the .dcf file
$ |. _ ~" H+ b1 E! B( [. ~1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 0849 J. V6 }2 k# H8 J$ Y8 W& J' F
1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position
- E! T# w& A; n6 l1 F* X9 _1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net
0 M8 i8 F" _5 k* s9 ?1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer
; W9 `6 n' g; z: }& n& A+ e) i$ ^1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation
h6 b N( _8 w1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
. s. Q% D7 O: `) P4 U9 A1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode% w: s6 [5 a$ [, W# G, M; m3 u# C
% z1 X' }& Y5 S5 e* H' ?
, r* N4 }6 Q& P# VFixed CCRs: SPB 17.2 HF0149 c' C! G* y9 m- p
03-4-2017; \# h1 x1 w+ }# ]5 w, V' f
========================================================================================================================================================9 B, p+ l9 Y, |1 d" s# X Y
CCRID Product ProductLevel2 Title
' f( l/ K& |/ w7 J1 Q+ P! U========================================================================================================================================================' X) y$ v" x3 O" @3 [1 X8 `
1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships
k( \/ B- o9 [1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity
' S4 S! b: m+ p$ k1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-268
$ I" F q! l5 x0 l1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data
3 h& i& e4 Y/ w4 p1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data
3 |4 t3 q3 f p5 M1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors- k0 m' Y% `* t$ r, Z1 p3 {
1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.$ r1 w4 \( T$ u' j' O" J& O# y
1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted& X: C8 X! g6 A$ s) F2 H
1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location
1 z; P6 h) t/ p* U' Y, p- I1685995 ALLEGRO_EDITOR SKILL All film sequence numbers are returned as 0 when using the SKILL function axlGetParam
/ s* e+ `' |4 I1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately3 O! E }: L1 \2 x( T) Q
1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.60 t9 @2 Z H7 D4 ~( w
1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one
k& Z% u6 _: g+ S4 o* K+ [1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled
0 s! C* p: i$ ~9 ~1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved
- \, z% g$ E2 X( m1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components
' l- }# h- i" {& N, j A1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers2 B7 h! G4 X( V& l1 R$ U d7 i
1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase
8 w- t5 m! ]' m0 F. M8 e5 h. F) x1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement! p/ A. E$ u4 ?
1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message
- j5 G7 y3 P( D2 _! u1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011& `* F: J8 i+ F; S
1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2( S! {$ P3 k" f5 g
1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers
, L9 f! b/ o4 w: W$ L1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016" y+ d( Q6 _7 \! s8 u5 G% J$ x
1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design
* ^9 ?; ^# w. E8 ^& T' S5 N) m, V1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors
, |! v. f2 M7 @7 W1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters
( c7 L* q+ \: C1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP) ^9 o+ H3 k! V7 V( @3 @
1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'
$ O; o/ j! a( V1705265 INSTALLATION DOWNLOAD_MGR Problem installing OrCAD Library Builder from Download Manager) X9 V# T" s8 Y, z& Y, r2 X
1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script* ]/ x& _& R- ^! Q5 R% V
d1 F! ]$ S# t& k! E; H; y. }
$ z* T$ T' M3 w! D O
Fixed CCRs: SPB 17.2 HF0139 z7 g: T% y, J" E
02-17-2017
/ ^, E$ E+ {1 G6 A: G6 K* l========================================================================================================================================================& W( s9 E" V' I/ {& z1 d
CCRID Product ProductLevel2 Title. m3 I7 ]+ Q) V; l. \& D
========================================================================================================================================================& ~4 G, \* v0 Y
1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm w: a/ [$ }& N/ Y. c! ~* l# u
1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer: v& q B, Z/ @- u1 l9 R0 c! q
1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
8 l! @/ D6 O% J2 P4 [ Y5 }1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated& g. U* x% v' L0 X+ ~- N* E1 x! v
1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated$ Q6 e5 H5 E2 y, ?# g8 d
1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board
' B! Q/ n# T5 x2 E0 ] x( \1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor8 j o7 F. Z7 i1 L% r3 m
1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol! \* x7 d6 @* x I6 W
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
, i) C, a' R4 O# q, X& U1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components
+ k, y( b6 `1 O' E1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components
0 x! j) E( G: k; Q5 W, q1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets) K" A& i$ S/ N8 v- u" E
1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets+ {$ q& ]+ R4 H( q* }9 d( e
1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF8 z0 j5 Z4 ?6 y
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement
* P3 B5 O9 f) L0 T- t1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.9 y) {/ H& V ^2 T
1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file
4 P( b- p7 U# y0 V% C1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.
7 j/ E* b3 t+ n6 Y4 T1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker( n0 r7 g9 h& ? E, N. q
1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates
7 O9 X( J5 n! N( f9 y- }! J/ B1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes. L6 L4 P0 h+ H$ f- [" ~% _, N
1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side., `/ ]* k3 n8 o
* W. V& B+ V8 ~' P& j6 _/ u& v
; }% O& a) x1 p) ~- t8 F
Fixed CCRs: SPB 17.2 HF012
' Y+ L3 x" L% T* m- ]1 u K02-3-2017% ]3 o# W; N( D/ F
===================================================================================================================================
1 \+ _; b% U$ ~+ n% A. n- jCCRID PRODUCT PRODUCTLEVEL2 TITLE
' p. F) f9 \! v" E) }3 Z9 J===================================================================================================================================5 t' E5 O0 I5 T1 d
1659641 ADW FLOW_MGR Documentation Editor does not invoke when a .brd file is opened from EDM Flow Manager
$ B9 ]8 G* B4 o7 \1 L; m6 W1661632 CONCEPT_HDL OTHER Page skipped in DE-HDL when navigating using the Page Up and Page Down keys
+ c: C. n, G# t4 w. T1668325 ALLEGRO_EDITOR SHAPE Updating shapes to smooth creates erratic voids.
3 H( X7 o2 ~$ C& z5 Y( H1670082 CONSTRAINT_MGR ANALYSIS Inconsistency in Constraint Analysis Modes - Electrical in OrCAD PCB Designer Professional 17.2
5 J1 q* U4 s- j& o1674231 ECW METRICS Re-upload for local metric packets that failed on first attempt is not working when Pulse server name contains dots
6 ~) K5 {% r7 Q$ j( S# k! y, S1674338 APD SHAPE Shape is not clearing slivers that are smaller than the 'Minimum aperture for gap width' of '18 um'
9 g8 f( s1 v K y1675677 ADW DBEDITOR DBeditor Issue-Searching by using the Properties method
f2 v" }* W& p( `* g& B1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers v5 q0 I8 f0 |; S+ {0 ?, \
1679351 ALLEGRO_EDITOR REPORTS Missing Fillets Report is not showing missing fillets on the bottom layer6 H& B$ G6 Y0 B% X2 m- M
1681002 ALLEGRO_EDITOR OTHER 17.2 STEP output fails to produce an output similar to 16.68 ^& K9 v1 t0 B
1682287 ALLEGRO_EDITOR EDIT_ETCH Auto-interactive Delay tune (AiDT) rips lines that have been routed
7 S" ~3 n* Y Z6 M9 i/ t1 A1682900 ALLEGRO_EDITOR PLACEMENT Moving a symbol by snapping to segment vertex with 17.2 Hotfix 009 crashes PCB Editor B7 d+ R7 ~: ]( W; M
1684117 CONCEPT_HDL CONSTRAINT_MGR Property deleted from Constraint Manager is not getting updated in the DE-HDL canvas$ ?7 q% D: ~5 _" R2 | ]; e: @! ~$ a
1686803 ALLEGRO_EDITOR INTERFACES PCB Editor crashes if the 'ipc2581_group_drills' variable is set.( G6 v0 r; r/ C- _' r5 V
1687816 ALLEGRO_EDITOR PLOTTING Export PDF Vector text option does not work
$ k" z* {2 C5 K% k# c1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.
& w& l* d1 J% ]# w! h! }& `, i7 V1689881 ALLEGRO_EDITOR DFA Record and replay script for loading DFA spreadsheet not working( x) o9 f8 j3 D& [$ q
1690958 ALLEGRO_EDITOR SKILL SKILL command axlDBDelLock is not working as explained in the documentation! O9 \; R; l; y9 q
1692166 APD DATABASE DB Doctor returns 'ERROR(SPMHDB-252): A corrupt database pointer was detected' for a specific design
" f$ [* p" l2 R4 @$ S5 r& h1693431 ALLEGRO_EDITOR SKILL Running axlXSectionModify and axlXSectionSet results in warnings and corrupts multi-zone cross-section
6 b' r5 k3 J8 d! a1693719 ALLEGRO_EDITOR MANUFACT Incorrect suppressed holes information in the drill file created" K4 _7 v f3 \5 D/ `
1693846 ALLEGRO_EDITOR MANUFACT PCB Editor crashes when running the gloss command* G! S/ Z& x9 J
1694151 CONCEPT_HDL CORE Rename Signal for unnamed net added the sig_name at the incorrect position with small text size.
^ Q" r3 e. t; |; e1694867 ALLEGRO_EDITOR SHAPE Void is deleted by the shape merge command
: w2 G L5 s2 _8 i1695131 ALLEGRO_EDITOR SKILL PCB Editor crashes when using the axlSpreadsheetDefineCell SKILL function. F( u5 o! p) x5 _
& V3 O0 e' Y$ E
& I9 s/ K2 r/ h$ G* \5 f
Fixed CCRs: SPB 17.2 HF0115 M. J2 ?% z% g- }
01-20-20171 u0 B- E; ~: _3 B3 T
===================================================================================================================================
' Q% N7 S( x0 Y$ i, A; j* Y, KCCRID PRODUCT PRODUCTLEVEL2 TITLE- ], X+ I1 i4 F
===================================================================================================================================
4 v( |# P: l0 ]" Q( f6 O1 o! O1618986 CONCEPT_HDL CORE Information required about the DONT_FORCE_ORIGIN_ONGRID directive3 t* N( F% O/ K+ y3 {5 c- s- \. X
1629696 PSPICE PROBE After successfully exporting traces to csv, PSpice crashes on a subsequent attempt to export traces
' d, a/ z, E1 O$ o& [: I- W9 l1667213 CAPTURE NETLIST_ALLEGRO Tools - Create Netlist stops responding on Windows105 i% _) l2 G% ^0 G) `! u
1667599 APD OTHER Wire Bond operations taking longer than expected to complete! W$ q% D$ r( X$ [# f
1667678 MODEL_EDITOR PARSE Signal model assignment creates ESpice models that do not pass Model Integrity checks
. l: d. t" z4 N$ V! O( {+ t1670120 ALLEGRO_EDITOR UI_GENERAL In 17.2, the Static Phase meter shows up in the middle of the screen instead of the lower right corner
7 A j0 o' y# _6 e( p1670927 ALLEGRO_EDITOR DRAFTING Using zcopy to create a Route Keepin results in database errors
* e5 c9 ~% r+ }+ R& ^1675359 ALLEGRO_EDITOR ARTWORK Subclass ETCH/WIRE is added to artwork definition though the visibility of 'ALL Layers' is turned off
9 `; \8 ?0 X5 i1675619 ALLEGRO_EDITOR MANUFACT Differences observed in IPC-D-356A between releases 16.6 and 17.2! b4 I1 s8 ~! X; F) }( \2 ` j1 p9 \, ]
1676161 ADW FLOW_MGR Opening a project in SPB 17.2 flags the 'Operation load JNI code failed' error% ^" E8 x" O( E
1677405 CONCEPT_HDL OTHER When moving a wire with a dot, the dot is not removed directly! Q: B' x8 w5 h
1678061 PSPICE SLPS Simulating an SLPS co-simulation with a Fixed-step solver with a value smaller than 1E-4 results in a crash3 u: v( i. `( Y4 |/ F
1679347 PSPICE SLPS SLPS crashes when co-simulating without opening OrCAD Capture or PSpice
* \3 Z+ w% Z2 Z1680113 ALLEGRO_EDITOR SHAPE Irregular void created on dynamic shapes! f* D8 s8 _/ O" m3 Q+ |+ n& _: G, J% ]
1680802 ALLEGRO_EDITOR DATABASE A 16.3 database locked with disabled export of design data should be view only in 16.6
5 x4 i+ ^( T1 e- R- S; ]$ N1681129 ALLEGRO_EDITOR DATABASE Match Groups in the DE-HDL design are not getting transferred to the board file
7 @! F5 V! p. x' c0 v' {1681514 ALLEGRO_EDITOR UI_GENERAL Opening the Dynamic Shapes State report hangs PCB Editor in 17.2 Hotfix 009. X C1 P9 [4 T
1681727 CAPTURE NETGROUPS In 17.2, Capture crashes when closing a design that has assigned Netgroups
( z2 W& u3 X' `& _* X& W, z1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version8 e$ r! m! Z9 O+ r& q. n
1682447 CONSTRAINT_MGR CONCEPT_HDL Extraction issue on differential pairs in the given design
6 z6 ~7 S) \$ e) A5 r+ o1682454 CONSTRAINT_MGR CONCEPT_HDL Design with NO_XNET_CONNECTION property on parts is exported to PCB Editor; many other components get the property4 C* ]% @6 Z6 k8 G! w: p
1682469 CONSTRAINT_MGR CONCEPT_HDL Creating a CSet from an existing CSet leads to invalid CSet names in Constraint Manager connected to DE-HDL
5 t8 |: p q8 C* p7 Q8 W+ m8 R1683919 ECW TDO-SHAREPOINT Site Minder integration for login from TDA not working after SSL certificate update
+ A( }' ~ ?2 [4 c7 Y1684111 ALLEGRO_EDITOR SHAPE Dynamic Shape not voiding overlapped static shape) j& D1 c# g# G: h; b% ~$ |, Z2 T6 J" E
1684508 ALLEGRO_EDITOR AUTOVOID Allegro PCB Editor stops responding when deleting a via
6 y- e4 r% d' q& [( V4 V8 ]1685540 ALLEGRO_EDITOR OTHER If text is attached to an object, the object is also printed in the PDF+ t- I3 C2 x& Y3 a) M; Q
1685810 ALLEGRO_EDITOR PAD_EDITOR In 17.2, Padstack Editor does not save adjacent layer information for BOTTOM pads( \) ^+ v( O6 t; Z) @6 \8 b
1685986 ALLEGRO_EDITOR PADS_IN PADS Translator-generated output shows incorrect unit for the soldermask oversize option( \3 B0 e& q0 t- [) m
1686127 ALLEGRO_EDITOR SHAPE The void of shape missed in artwork.
* k4 f. F( w6 t, ~, ~- U% w/ `& r1686791 ALLEGRO_EDITOR OTHER Searchable property unavailable on bottom layer pins in the generated PDF9 ~. e& ?, d& j; b
: }3 I L- T+ d: N, } C
?0 E, {) y( K$ ], |/ r, j
Fixed CCRs: SPB 17.2 HF0109 {4 F/ m0 m. D" U, {
01-6-2017
3 b, ~# T, H6 [% C* F, o6 c===================================================================================================================================6 ~: n3 J8 g* R3 b- M" G
CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ ?5 T- o9 j- P9 v$ N( u; X===================================================================================================================================8 |. C0 L4 y2 ?# ^$ ?1 _) k
1524700 F2B DESIGNVARI Variant file cannot be loaded
& M+ I6 _/ |6 ?1597787 CONCEPT_HDL MARKERS Save As in Marker dialog causes DE-HDL to crash% C6 @9 b1 K5 u2 u I z, o$ W3 B
1599843 CONCEPT_HDL INTERFACE_DESIGN Moving NG causes extra elements added to it to move- B% O* c( ?0 X6 z9 X
1620017 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053) when $PART_NUMBER property for components has a value
% N/ W/ e& p2 k ~. B# J/ O1632977 CONCEPT_HDL INTERFACE_DESIGN Connectivity error when moving NG members
3 `( Q# [, r2 o0 a) x# s1635941 ALLEGRO_EDITOR INTERFACES Shape created by IPC 2581 for negative film is not same as the shape on board7 Y+ U+ K5 J% k; Y' i
1656357 CONCEPT_HDL CORE Pasting a signal name across pages causes the name to overlap with the wire segment. G+ B, {7 ~, A: l( B& l% K
1657346 CONCEPT_HDL PDF Wire Pattern set to two-dot chain line in a schematic appears as a solid line in the PDF output
9 G( Q4 F* H6 e3 o5 F: ?1 h k1658048 ALLEGRO_EDITOR COLOR color_lastgroup is not working in SPB 17.2
* |& e$ A- r- [6 m; M! c1658874 CONCEPT_HDL CORE 'Insert (n) Pages' command does not work when the CONFIRM_WRITE directive is ON
* R! K" _7 a" Q- V8 y1659030 RF_PCB LIBRARY Offset is not calculated from the center if using negative values for input pins when placing MSOP symbols
: P. ?. s6 \/ N1659097 CONCEPT_HDL CORE Mouse stroke fails to be enabled on startup with left mouse button (LMB)
4 |( e0 ~( F: J" R8 S2 w9 m+ I1659532 CONCEPT_HDL CORE About Import Design command with the CONFIRM_WRITE directive: s4 @- t& v: Y: W" {
1659929 CONSTRAINT_MGR UI_FORMS Using wildcards in filename for Import Constraints does not work in 17.2
% }5 \4 v* {% i( s1660200 ALLEGRO_EDITOR UI_GENERAL Move by Sym Pin # edit box is obfuscated
7 Z8 l% u$ \' z" C7 W, p& a1662821 ALLEGRO_EDITOR OTHER Cross section chart does not show stack vias in 17.2: e# p6 s: G$ o% l, [$ s
1663641 CONCEPT_HDL COPY_PROJECT File - Copy Project in Project Manager creates two designs if there are dashes in the design name5 x9 U: J/ |/ S
1665652 ALLEGRO_EDITOR SHAPE Critical fillet and shape issues in 17.2! I! k6 J [1 _
1665918 CONCEPT_HDL CHECKPLUS Error (100) Program Internal Error 'Create_flat_node' with checkplus run
0 d/ V- L- e+ [# F9 b1667056 ASI_PI GUI Power Feasibility Editor does not list capacitors connected to selected nets/parts3 h! c3 B* Z2 y; [5 ]1 j
1668137 ALLEGRO_EDITOR SCRIPTS PCB Editor crashing when running Script Replay
8 B# L3 W* D0 m; h8 y1669651 CONCEPT_HDL CREFER CreferHDL values are invisible
! O( P: K) t* U( A& O8 E1669707 CONCEPT_HDL CORE Pin numbers not visible on the canvas after replacing a part with the same symbol but a different part property3 m( \$ u& v. \- y/ K
1670339 ALLEGRO_EDITOR OTHER Small shapes defined on the mechanical symbol Board Geometry - Outline are not converted to the Cutout subclass.$ u7 m* \5 l5 y( ?
1670564 ALLEGRO_EDITOR MANUFACT Exported Gerber file cannot be imported in brd. I3 M- H0 S* p* y
1670687 ALLEGRO_EDITOR NC nclegend.log reports missing columns which are present in the NC Legend
. H( y$ s e: T$ p8 I1670811 PSPICE AA_MC AA MC Plot settings options
1 Q8 ]% d8 p/ ~9 `8 p" V1671428 ALLEGRO_EDITOR UI_FORMS Display origin checkbox position changes in Step Mapping dialog# L* |& V. K7 R! x) {0 i
1671728 CONCEPT_HDL CORE Option requested to reload preferred_projects.txt without re-opening DE-HDL
! K$ V8 g, R& V. p1671901 ALLEGRO_EDITOR UI_GENERAL Toolbar and menus are locked or greyed out8 c, x4 j$ F" ]1 Z
1672477 ALLEGRO_EDITOR DRC_CONSTR DRC generated by Dynamic fillets; K7 Q& W$ r, B; M
1673499 ALLEGRO_EDITOR DATABASE Drill table title issues of backdrill designs in 17.2
; r4 O/ u1 d/ c' f R1673681 ALLEGRO_EDITOR UI_GENERAL F1 for Help not working in PCB Editor 17.2
/ @2 t: `) X" [8 l) m" R% [ W! H+ `! m+ A1675499 ALLEGRO_EDITOR DATABASE Running the Gloss command causes PCB Editor to crash...
- _, ?& z. r7 b1676480 ALLEGRO_EDITOR MANUFACT Creating Variant Assy_Bot Drawing showing Variant Assy Top Drawing- _/ B) L5 F3 k- c; I
1677431 ALLEGRO_EDITOR DATABASE Get ERROR(SPMHA1-141): Invalid sector row. Contact cadence customer support when opening DRA File
( E `! Q( X# L: M% i3 a. k1677651 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crash on design after successful packaging2 m' O6 b6 ]7 E3 J8 k. Y
1677672 CONCEPT_HDL CORE Whitespaces in URL links are not resolved correctly on Linux with Firefox
9 _/ W: Q* s1 r" |+ |$ j1680837 ALLEGRO_EDITOR SHAPE Updating the shape makes the shape disconnect from Thru pins of same net: @! Q: p5 r! g* R# j. R5 l
1681059 ALLEGRO_EDITOR SHAPE Shape Voiding using DV_SQUARECORNERS environmental variable does not always produce voids with square corners.
. G! G) ~& n! R% U k9 Q8 i% j1682312 SIG_INTEGRITY LICENSING Allegro Sigrity SI/PI Product Choices window is blank after installing 17.2-s009 hotfix
8 |- I5 L3 v' i# G1 i- R; Q ]' B. g" O1 t B) O" O' Z: ?
" {. p) v& i' W4 Z. Y& {/ BFixed CCRs: SPB 17.2 HF009
) D2 ?: Z+ v0 C+ V- ~12-8-2016
0 O7 K! B: G# I D===================================================================================================================================+ e- D: C; G8 L$ Q$ F/ ]
CCRID PRODUCT PRODUCTLEVEL2 TITLE$ ]8 B* e- M- f: e$ _8 ~
===================================================================================================================================
1 B* _ U4 ^2 n1212577 PSPICE MODELEDITOR IBIS translation fails without any information in log file! R6 k- i8 v [- Z. \0 H
1311687 PSPICE MODELEDITOR Timeout error while translating IBIS model, x5 Z1 k: O" T, W/ S
1327174 PSPICE MODELEDITOR Log file should list error details during IBIS Translation: t/ ?& N) _- t; ?/ L; E% ?6 j- b
1499665 ALLEGRO_EDITOR INTERACTIV Offset Move depends on move setting.
" M/ {6 {' G3 P9 q. z1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation# t0 s+ A4 \9 G8 N$ \' ^2 B9 D
1565795 ALLEGRO_EDITOR UI_GENERAL Search does not work in the Defined Variables window# O0 d1 J) g; V! [+ j$ f/ g9 _
1568817 ALLEGRO_EDITOR UI_GENERAL Padstack editor not accepting comma as decimal separator with system locale set as LANG ru_RU.UTF-8
2 @! z; f) M; x2 m% E$ ~9 V1569272 ALLEGRO_EDITOR PLACEMENT Get the error message 'E- (SPMHDB-394): Placement cannot be completed ... 'after creating Place Replicate circuit
) G' E# K2 X8 c2 G7 P1577379 CONCEPT_HDL CORE Packager-XL gives different results when run from DE-HDL and ADW Flow Manager
1 s7 f3 N l0 u; L1578523 ALLEGRO_EDITOR PAD_EDITOR Library Padstack Browser does not refresh preview( x4 t% T- M5 E1 p2 _
1578533 ALLEGRO_EDITOR PAD_EDITOR New Padstack Editor does not automatically update the geometry
7 N; t7 q; ^" C1581129 CONSTRAINT_MGR UI_FORMS Unable to dock the Electrical worksheet in Constraint Manager6 M0 G# [# f. F$ e4 M9 ?! M
1582103 ALLEGRO_EDITOR PADS_IN PADS Library Import creates additional filled shape not present in source data
) b$ w# i$ U5 g" f5 z1591027 ADW LIBDISTRIBUTION Library Distribution redistributes previously distributed models
9 [: B" O, P3 `1 I, b( i! ^! ?) N1592026 CIS VIEW_DATABASE_PA View database part does not work from schematic pages of an externally referenced design4 e9 z4 e) O$ T
1593389 CAPTURE GEN_BOM Include files in Tools - BOM not working' c3 b# j' E* u- \
1593404 SIP_LAYOUT EDIT_ETCH Slide command moves via toward the object9 e' z6 U6 Z0 ?# E- V) G
1595872 CIS PART_MANAGER Capture CIS Part Manager PCB Footprint update case-sensitivity issue, @" R- u E8 m
1596955 ALLEGRO_EDITOR EDIT_ETCH Scribble mode is not working as per expectation.0 c& d5 x x# x% F
1600936 ALLEGRO_EDITOR INTERACTIV Pin DataTips differ between 16.6 and 17.2
" s, b4 a$ q8 L! m, T1605961 ALLEGRO_EDITOR COLOR Wildcards not working in the Filter Nets field of the Color Dialog window
( f. W7 C0 S) F: Y! O9 ^7 I* |1606392 ALLEGRO_EDITOR PLACEMENT Filmmask not shown when component is attached to cursor7 _" o- d" h O2 ]0 E
1607016 ADW TDA TDO crashes after LRM update during check-in hierarchy
7 ]0 C* _/ s5 G1608059 CONCEPT_HDL CREFER Removing crefs from top-level design also removes .csb files from lower-level blocks
/ A' k( o2 \, v! ^1608278 CAPTURE OTHER Crystal Reports: User is prompted for ODBC password to create a BOM report
6 f" F* B, J$ Y- m' Y. d5 f- y1610377 CAPTURE PROPERTY_EDITOR Discrepancies between the NET_SPACING_TYPE property (or any other property) text and the actual property
" c6 P8 ^. s) K! Q) Q: J Q1610456 ALLEGRO_EDITOR DATABASE Strip design and selecting user defined subclasses results in database corruption.
# Q3 j& D. e9 `1612793 CONCEPT_HDL OTHER Pattern-based auto-distribution of split symbols not working if there are spaces before commas
2 M! R/ \( ~; K$ Q2 s1613442 CONCEPT_HDL CORE Signal names are not horizontally centered when the wires are added using different methods( r, E, J6 H2 \/ q1 Z
1613559 ASDA IMPORT_DEHDL_SHE custom variables from the BOM Tables are not getting imported9 ?5 B5 M" o$ \, S
1614093 CONCEPT_HDL CORE Import Design window has artificial 64 char limit for path - prevents access to some locations5 ^+ _/ \$ ^, _. ~* C9 q
1614372 CONCEPT_HDL EDIF300 OFFPAGE symbol is exported as PageBorder in EDIF300 schematic0 b# h+ T4 |5 H
1615075 APD LOGIC Netlist-In wizard fails to import the net names, but gives a successful completion Info message
/ l2 G" F2 a Y) O; X! R7 X1616131 ALLEGRO_EDITOR PLACEMENT While placing a module, the Mirror command in the right-click pop-up menu is not working
. k ?" \0 |- l$ K3 e1617377 ALLEGRO_EDITOR UI_GENERAL Visibility pane does not retain the correct layer view8 T+ ]- U$ T3 n) I0 v
1617404 ALLEGRO_EDITOR UI_GENERAL axlUIMenuChange does not work as expected in 17.2
, ^! n' P7 D' d3 p1619412 ALLEGRO_EDITOR INTERACTIV Script to create new padstacks from existing padstack is putting in wrong values for a regular pad
2 h; c ]. u0 M: n1621842 ALLEGRO_EDITOR PLACEMENT mechanical symbol without placebound will not place in QuickPlace* I* V: e( \& F3 _4 g: M
1621874 ASDA PRINT Print - Save as PDF uses the default printer options only
+ E( `+ J; u. P, U1621887 ALLEGRO_EDITOR INTERACTIV Getting a 'Could not satisfy the snap condition' message when using the Snap pick to option
2 ?1 v; g. x6 e4 ]" D1622680 ALLEGRO_EDITOR PADS_IN Import PADS fails with the 'ERROR: *NET* section found. Translation of netlist is not allowed.' message' d- t0 A) g& O4 w* \1 `! J0 c t( g! f
1623832 ADW COMPONENT_BROWSE Incorrect part placement on schematic in Design Entry HDL 16.6-S073% Y* ?; n. H; V1 F" U! q
1624813 CAPTURE GENERAL The Value property is always left aligned when placing a symbol on the schematic
( b k, g/ G( d5 Q8 M V' b% X! m1624953 ALLEGRO_EDITOR UI_GENERAL Custom views in 17.2 do not return to original$ _% U# L# g* l; D8 k; {& s: T
1625000 ASDA CANVAS_EDIT File - Save Project does not provide any indication of saving or progress bar' e" D, A( @# p4 z
1625163 CONSTRAINT_MGR OTHER There is no status for the analyze command in the Constraint Manager in 17.2
9 T0 M8 F$ R& `* ?1626647 PSPICE ENVIRONMENT Capture crashes when loading a design with two hyphens in sim profile name. v4 O) M8 }/ J( Z5 ?4 m0 e; z) Y
1628357 CONSTRAINT_MGR OTHER Constraint Manager shows differences if exporting and importing constraints on the same board.
/ y3 c& W6 [/ }1628409 ALLEGRO_EDITOR PAD_EDITOR Pad Stack Editor does not remember last used directory( P9 k6 h: R' q# p# a/ H" J
1631443 CONCEPT_HDL ERCDX ERC reports warning due to lower-case value of some properties in chips.prt; N! z0 t$ |1 O# U! ^
1632195 SCM OTHER 'No known page border found' error in cref.log
$ @' ] c& U1 L' c4 V8 h8 A- g* z- K2 ~1632365 CONSTRAINT_MGR OTHER Select command is disabled in the right-click pop-up menu from Constraint Manager in SPB 17.2$ o1 h( Q& w3 r% f: L E# d
1632462 ALLEGRO_EDITOR 3D_CANVAS 3D View (new) and PCB Editor crash when checking collisions
2 i x9 u# ^5 B7 |1632590 ALLEGRO_EDITOR 3D_CANVAS PCB Editor crashes when 3D View is open and more 16.6 boards are opened! y' N% L" v0 Q% f0 N/ t3 B( ?1 c5 [
1633433 CONSTRAINT_MGR UI_FORMS Expand - Collapse feature for multiple objects not working correctly
$ ` Q) p% o: d! C0 ? e1633454 ADW TDA TDO crashes if DAO throws an exception
; l! u- |2 m- [1633526 PSPICE AA_PPLOT Spaces in Simulation Profile cause error in Parametric Plotter
/ b' l+ @ S1 f0 Q( Z f# [- c$ }1633608 ALLEGRO_EDITOR COLOR 'Retain objects custom color' should not enabled as default.( }; c2 @% a4 E; f$ E9 x* Z% I
1636216 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas (Unsupported prototype) is not mapping step model when assigned to device8 ~+ D# C' m. B/ T5 L g% B
1636899 ALLEGRO_EDITOR 3D_CANVAS The new 3D Viewer is not taking the Package Height set on the PLACE_BOUND layer into account when displaying it.; f- ^- c: Y5 j. q) V! g! T
1638185 CAPTURE DATABASE Opening CIS database locks all part libraries none of which are open8 E9 ~$ q! f9 L; Z+ ~
1639409 ASDA CANVAS_EDIT Handling of MAKE_BASE property from DE-HDL designs imported into SDA' X3 }4 N. @1 }: H4 s# u0 G
1639541 CONSTRAINT_MGR OTHER PCB Editor 17.2 crashes when making changes in Constraint Manager
% c4 K& r: O$ W2 h1639613 APD STREAM_IF The stream out command has created sharp angles in the GDSII output file1 T* |; h5 ?1 d4 I& u
1640061 ASDA HIERARCHY Incorrect message received when invalid characters are specified for subdesign suffix
) k+ ^8 @* O: G! l1641118 F2B DESIGNVARI Some DNI parts are not identified in the variant view due to the BLOCK/ f$ h: u/ k0 ?* M
1641410 ASDA CONSTRAINT_MANAG No errors or issues reported when incorrect topology is applied to a net or an Xnet& K- n" h: U0 n6 m% f9 r
1642891 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes randomly while working on Constraint Manager
+ T( h/ g6 W6 V6 m+ P1643003 CAPTURE PROJECT_MANAGER Start page shows latest as S004 after installing S005
: {: j- a) s- T" S1643532 ALLEGRO_EDITOR OTHER Strip design command fails to delete symbol text in the attached design
$ s2 ]. ?; [, `1645529 ASDA CONSTRAINT_MANAG Unable to delete the diff pair from the nets
# b6 Q, v/ e7 S% k. b8 N) r4 L1645639 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes when the XNET_PINS property value has a trailing comma character+ H6 D6 k6 O9 c3 L
1646354 CONSTRAINT_MGR CONCEPT_HDL Cannot select Design Instance/Block Filter from the View menu in Constraint Manager
; W) c7 {+ }) G. c5 A5 D( ^1646612 PCB_LIBRARIAN CORE Generate Symbol option crashes Part Developer' ^+ S6 N5 K @& r# x% R R4 v6 I
1646932 ALLEGRO_EDITOR MANUFACT Manufacture - Auto Rename Refdes keeps defaulting to Use Default Grid even if another is chosen
. g/ i- S% X% h1647190 APD REPORTS 'Sorted by Bond Finger' report shows incorrect wire bond connection
: ?' n! V0 Q, | [; e1647673 ASDA EXPORT_PCB Two Physical folders are seen after installation of QIR
5 A9 I5 e, R( X5 ^ J1647729 ALLEGRO_EDITOR SKILL axlFillet returns t when fillet is not added.
# y/ l2 z+ H0 P1647779 CONSTRAINT_MGR OTHER 'Software Version' in the cmDiffUtility viewer does not show the correct version
( _) P+ ~% E5 l! _# x1647843 ALLEGRO_EDITOR ARTWORK Misleading information in command window when artwork import fails4 X/ ]6 B# P) i4 @
1648575 CAPTURE OTHER Suppress warning setting must be written in capture.ini file8 a; S" m) ?& k
1649060 CONSTRAINT_MGR CONCEPT_HDL Rename dcfx to dcf process results in error in log file and dcf not updated4 y* T1 ?. t$ Q. `
1650106 ALLEGRO_EDITOR 3D_CANVAS 3D canvas rotates mirrored components in unmirrored angle3 i! ]) z1 ?' t6 w- z1 ~
1650238 SIP_LAYOUT WIREBOND When performing 'Adjust Min DRC', the reference bond finger should not move.
# G" U+ |( z3 j1 {3 D" r* K9 ^) h9 ?1650734 APD SHAPE Shape on L1 does not flood properly
' e! @$ z0 _* C9 q1 p. V& z1650793 CONSTRAINT_MGR CONCEPT_HDL Conflict of XNET_PINS definition between the chips and the SIGNAL_MODEL is not handled correctly
$ |1 h3 l3 S' N1650801 ALLEGRO_EDITOR SCHEM_FTB Running Export Physical with Update PCB enabled in Project Manager crashes netrev.exe9 U6 E) u2 I( q. {4 }$ N) H! p
1651011 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D viewer shows mechanical symbol mirrored: i+ J- Z! o& V! g, ]
1651063 ALLEGRO_EDITOR CROSS_SECTION Cross-section preview is incorrect9 A1 s2 q* k0 f
1651066 ALLEGRO_EDITOR DATABASE Pins not connecting even after running the Tools - Derive Connectivity command9 |9 L2 S) x9 K- P& A
1651700 ALLEGRO_EDITOR SKILL Running axlXSectionModify() on a layer removes the value of the material; C# m3 X$ i' G# ?) j
1651925 ALLEGRO_EDITOR ARTWORK Searching for a macro in the artwork data file: Count for the macro does not match the actual count in the output! C; A. @* L, b) K
1652230 CONCEPT_HDL CORE The master.tag and vlog004u.sir files are not created in the entity directory on saving symbols& S4 I W# Q8 j4 o
1653080 CONCEPT_HDL ERCDX Difference in results from SPB16.6 in 'erc.rpt' when logic_data is renamed as worklib in SPB17.2 on RHEL6.5) ^" ]* m( C2 G' F
1653422 ADW LIBIMPORT Classifications not linked to a Part Number or Cell Model are removed during Library Import6 S! s8 \/ Q' ^' d& n
1653526 ALLEGRO_EDITOR DATABASE Via padstack keepout is not displayed on the canvas when pads suppression is enabled.
; S% A/ U# N6 z+ g" Y1653951 ALLEGRO_EDITOR CROSS_SECTION Cross Section Editor changes lost despite selecting No to the 'All changes will be lost ...' message9 x' j8 a5 g- R6 P9 @7 D3 F9 h
1656224 ADW FLOW_MGR Copy Project wizard no longer allows dashes in the 'Name of new project folder' field
( o6 I$ E* E- C: ]1656581 ALLEGRO_EDITOR OTHER PDF generated for layer with shape shows undesired voids if film is mirrored and Filled Shape is not selected
" Z4 \ q, \7 {- `6 _' d1656608 APD REPORTS Incorrect calculation in the metal usage report
; `. v. ~" c, J( W1 b7 M1656726 CONCEPT_HDL CORE Interface command always disabled in the Wire menu% e& ^. L0 b& I0 l; M
1656841 CONSTRAINT_MGR UI_FORMS Incorrect layer information is displayed in the Edit Via List dialog when a filter is applied0 X! N& T% x4 d2 l" K1 @9 l
1657220 ALLEGRO_EDITOR SKILL axlXSectionGet() returns Primary list of layers and not All stackups* F# b; \7 D7 t9 O+ c9 R
1657257 SIP_LAYOUT EXTRACT When using extracta, custom layer names not getting retained
/ L- w, c% l7 A" U0 a1658440 ALLEGRO_EDITOR PAD_EDITOR The location of a drill in the .pad file is different from the .dra file
% o. |" g6 W" o& M ]2 r4 B1 h- l: L& W) p1658445 CONSTRAINT_MGR CONCEPT_HDL When DCF file is converted to ASCII, no further updates are allowed.3 s6 F; `( @9 [" y* W
1659473 SIP_LAYOUT WIREBOND When moving wirebonds they are jumping instead of sliding
5 ]% U; f. c9 ]1 k \( t5 w1659498 ALLEGRO_EDITOR INTERACTIV Unable to turn off line on Etch Wire for Jumpers
+ l1 j3 X: l( z1 w5 d/ C6 y1659644 CONCEPT_HDL OTHER Predefined nets are not listed if 16.6 design is being opened in 17.2# T7 v9 B; L; L2 F3 P* @
1660475 CONSTRAINT_MGR UI_FORMS The CTRL+V shortcut is not working in the Export Constraints window in Constraint Manager 17.2
& f1 t. ~3 O a0 O6 B1660492 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes when using multiple desktops on Windows 10* N- v5 v7 s- z1 ?4 \' Z
1661133 CONSTRAINT_MGR ANALYSIS PCB Editor crashes if comma is used in the Value field for Analysis Mode% i* V! i6 r1 i' d
1661307 CONSTRAINT_MGR CONCEPT_HDL Prevent creation of diff pairs on VOLTAGE nets
" P/ a) E7 H5 S. ^9 ~+ Q2 z1661357 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when using Route - Connect
1 _4 C. U/ j% V L2 V H1661874 ASDA DESIGN_CORRUPTIO Unable to delete the ZERO part from the schematic page
' [! L1 z) S6 s+ b! a0 B0 A9 z5 ^1662799 ADW SRM Mechanical symbols are not being displayed in the Mechanical tab of Symbol Rollback Manager
$ H0 h F7 |2 q3 p8 w1664797 SIG_INTEGRITY GUI Unnecessary coupled interconnect models were generated during View Waveform.
7 a+ Y, `/ T% V8 ?1664858 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes during Auto Interactive trunk route.' u4 q2 \/ \% v' t$ l" A
1664911 ALLEGRO_EDITOR OTHER PCB Editor freezes after DRC Update is performed
: A$ a* r/ ` [0 A1666329 CONSTRAINT_MGR OTHER SCM Import Physical process crashes cmfeedback
. B3 i$ w7 C# U2 X# l& z7 z' x1666551 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option separates imported artwork to different XY locations
1 f R6 M: R+ R% T1 E* s1666723 ECW TDO-SHAREPOINT TDO login is not working with Site Minder because of incorrect characters in the Site Minder login form HTML0 n$ V! F( y* I7 P. i4 u
1667068 ALLEGRO_EDITOR SHAPE Update shape removing the shape voiding
! J- T3 T$ z+ ]5 G* I4 M( Y1669828 F2B DESIGNVARI Variant Editor crashes on Windows 10 T540 P laptops but works fine on Windows 10 desktops7 R& t; B3 W; X$ D+ `# I# v% ]
1670221 ALLEGRO_EDITOR DATABASE Non-recoverable corruption error is reported when saving the board after adding a layer9 x: Z2 F0 b0 D: I5 P0 x
1672134 ALLEGRO_EDITOR ZONES TDP needs FIXED component override- q9 d; L: E, p; l
3 j7 ]6 A0 e; ]9 x
# X9 i9 ~. @# T: C6 I
Fixed CCRs: SPB 17.2 HF008
+ v9 N( m" ~- I% s10-29-2016& n! h* R1 `$ W# g+ v; j
===================================================================================================================================
) o/ L5 @, Q7 h. X' F3 f! J# nCCRID PRODUCT PRODUCTLEVEL2 TITLE* L$ C N, B9 U$ A8 x& X' K
===================================================================================================================================
+ B. g( b2 n3 D& _; Q1644406 ALLEGRO_EDITOR SHAPE Alternate symbol placement results in illegal parent identifier error
4 E" z \) `/ H4 q+ n: e1647098 SIP_LAYOUT OTHER SiP crashes on symbol copy and rotate
. V% z8 d4 e; |/ Z1647154 APD OTHER Disconnected Clines not working* `; J: l4 Z. I7 y5 {
1648817 GRE IFP_INTERACTIVE Allegro PCB Editor stops responding on adding netgroups to a nested netgroup4 c6 C4 h! x+ |' o4 c8 H- c& M
1649829 CONCEPT_HDL CORE A delay is observed before the sub menus of the File and Tools menus appear3 Y9 J+ B( x( g8 T
1652930 ALLEGRO_EDITOR OTHER Command-line version of switchversion not working/ u) [( `% H7 l( b+ z' l
1653109 ASDA DESIGN_CORRUPTIO SDA not pulling latest library information for part
, b# K( h& C+ Y0 {. n1 L b5 g1655377 FLOWS PROJMGR Project Manager crashes on Windows 10
5 g5 R& j1 b( z/ l# g4 o" H) V; l8 |+ U4 U
& ^ w+ q7 V1 Q, SFixed CCRs: SPB 17.2 HF0070 K) q# z8 P3 U" P
10-20-2016, ~5 |& c" o: B2 ]; F5 u6 K3 @
===================================================================================================================================" w% {& R. l' }% q4 i
CCRID PRODUCT PRODUCTLEVEL2 TITLE; k4 A7 B/ {( e- k0 p
===================================================================================================================================' b+ c; e9 ^4 r; v
1582276 CONCEPT_HDL CORE Need the ability to delete an image placed on the DE-HDL canvas+ w/ {! R- R& E+ T7 n, x* O
1594101 CONCEPT_HDL CORE No error or warning issued on specifying an incorrect unit for voltage% c* P( X# j$ Y) f, a
1611293 ALLEGRO_EDITOR UI_GENERAL If the Command window is floating, it cuts off text from the bottom half of the last line.- O. n8 L' Y2 a! L
1611652 ALLEGRO_EDITOR UI_GENERAL New artwork film not appearing in the drop-down list for Visibility Tab
4 E4 \3 M1 }- |6 H8 o. F0 o6 j1618205 ALLEGRO_EDITOR UI_GENERAL New Artwork film added is not updated in Visibility - View3 \+ r: x$ |, b; J- F
1631114 CONSTRAINT_MGR OTHER SKILL functions axlCnsPurgeAll and axlCNSDelete delete spacing constraint sets but not deleting names( y, J" E2 j" \/ M& }
1633726 ALLEGRO_EDITOR UI_GENERAL Visibility tab not dynamically updating the view list when artwork film changes
+ {- X( X. o; j1 s; m1636404 CONSTRAINT_MGR CONCEPT_HDL In 17.2 QIR1, DE-HDL Constraint Manager allows users to enter invalid voltage units
! M7 H1 w: R+ x3 | g, V0 T+ L1636864 ALLEGRO_EDITOR UI_GENERAL Domain Selection for Visibility does not work with Hotfix 004 unless you save and reopen the board file/ L) r+ V6 y0 _- }5 w; H5 j
1638251 ALLEGRO_EDITOR DATABASE Unplated hole changed to plated hole after uprev from 16.6 to 17.2 version
% _+ d7 r7 G3 z3 V! D/ `; X" O) G1639483 ALLEGRO_EDITOR EDIT_ETCH Manually routing discrete components with incorrect constraints causes PCB Editor to crash
9 j: P4 {: y. `( w0 ]" W; i1641435 SIP_LAYOUT IMPORT_DATA Need SiP Stream mapping layer count to match Virtuoso stream layer mapping count' K" a' C2 r X0 t
1641483 SIP_LAYOUT WIREBOND SiP Layout - Modify the wirebond report generation for Start and End height when using a DISCRETE class footprint
6 _, T2 D! c2 ~, {' Z1644131 F2B PACKAGERXL Option needed to package a DE-HDL design with ptf errors into a board file+ D ]0 I0 s& q
1644807 CONSTRAINT_MGR ANALYSIS Unable to set electrical constraints modes with the OrCAD PCB Designer Professional licenses7 |0 i; f6 e2 C6 p$ x2 t' Z9 f
1646228 ALLEGRO_EDITOR UI_GENERAL Running the axlUIMenuInsert command to add a submenu after running the axlUIMenuFind command crashes the tool$ u' H/ O) f1 {' ~1 O7 Q* N/ `
1647402 PSPICE PROBE Unable to print on Windows 10 as no plots are displayed in the Probe window+ Z+ \4 t, m7 W1 _
1648183 ALLEGRO_EDITOR INTERFACES Allegro STEP Export: Using the 'step_3D_copper' variable, pads not exported in the same plane as traces and shapes
: N' j% i$ ^4 Z6 \0 K# [1649222 APD ASSY_RULE_CHECK Allegro Package Designer stops responding on running the Acute Angle Metal DRC
. p+ I. Z q0 D# [* ^* H4 A5 _' a" n
9 o# L$ M, N/ c
( E( f, j# K( ]6 Z; ^" Z/ S: _Fixed CCRs: SPB 17.2 HF006/ u- r( {* Z) ?3 v l% M* }2 N+ F
10-7-2016
8 B2 t: y7 e+ ] n4 j===================================================================================================================================
$ c4 |& ]. T0 `* y( U( d8 _9 V3 LCCRID PRODUCT PRODUCTLEVEL2 TITLE; K" T' ~1 ]" c- ?; R3 }0 e% R6 I
===================================================================================================================================9 o! a/ r8 }3 W' `; e* I+ \
1585203 ADW DBEDITOR Optimize check-in of footprints with multiple padstacks
, H3 m Q& y$ X0 i V. Y8 P1607954 ALLEGRO_EDITOR SHAPE Dynamic Shape not updating correctly
- V! ^) D- \8 X9 r( z% h1618173 ADW SRM SRM does not automatically run when a .brd file is opened from EDM Flow Manager in 17.2 Hotfix 003$ m1 n8 Y( n$ j- ^8 Q
1618832 ADW SRM SRM marks parts as updated even when they are not updated* u. }7 w3 B; y
1623823 SIP_LAYOUT WIREBOND NO_WIREBOND property is ignored by Add/Edit Non-Standard- ]1 j5 {1 m" {. v0 [
1626001 ALLEGRO_EDITOR SHAPE Shape to route keepout DRCs reported for dynamic shapes in the attached design2 _" F& O' p8 ~( r
1626546 SIG_INTEGRITY FIELD_SOLVERS Extra RL elements in via spice circuit model generated by Via Model Generator
, K, a' {) [0 Q7 k! @' C! [1631792 SCM OTHER The NC net has re-attached itself to another net, RIGHT_LEFT_N, in the design6 H- t; a. ]( {' a& X
1632223 ADW LRM Checking in a hierarchy causes a crash
, _8 H* M0 \3 ~0 U, M' x6 a1632844 F2B DESIGNVARI Part is simultaneously defined as Pref and DNI in Variant Editor with no error
8 T1 a4 B6 O) s1633647 ALLEGRO_EDITOR MANUFACT Variant issue: Create Assembly Drawing command not creating filled shapes for keying pegs in attached design
4 \4 h1 K8 h+ i* ~! Z" b6 A, m1633707 ALLEGRO_EDITOR DATABASE Cannot remove Route_Keepout associated with a pin
1 t& O) k) N( t6 e. }1634392 PCB_LIBRARIAN OTHER Launching Library Explorer without -proj option crashes the tool! [* Q7 W' s; s4 J6 s2 |
1635049 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes when trying to create layer set from Constraint Manager
3 [$ Y3 s+ z9 g# E1635593 ORBITIO ALLEGRO_SIP_IF Importing .sip file reports undefined argument error while processing shapes( r' l" \7 f4 ^& p7 O$ i& G
1635858 ALLEGRO_EDITOR ARTWORK Get 'WARNING: Null REGULAR-PAD specified for padstack' messages in log file when generating artwork for all layers
5 ?6 U/ @1 w. ]" K1 L5 Q5 H' `2 ]1636097 ALLEGRO_EDITOR ZONES Technology Dependent Packaging footprints not updating in the design
6 h4 a* E& Q/ c& m3 e8 f1636185 ALLEGRO_EDITOR ZONES Import Placement not placing TDP footprints in zone" u8 S# x$ J+ u/ z
1636867 CONSTRAINT_MGR OTHER Millimeters shown as mils in the Analysis Modes dialog box7 v7 e4 h2 A8 E `2 f
1638094 SIP_LAYOUT OTHER Cross Section Editor not seeing updated information
! E8 E1 G( j+ A: h& m1639845 ALLEGRO_EDITOR INTERFACES Step file not generated when board is exported to a folder with special characters in name
! x) \; I% w2 h( m' k4 _1640611 APD SKILL Launching XtractIM from SiP Layout with the attached design crashes both SiP Layout and XtractIM
( z# H+ t, W3 ?0 |$ c% Z5 K1641339 ALLEGRO_EDITOR INTERFACES DXF_IN does not show all the subclasses available in the design
' Y0 J5 P6 o( U1641879 XTRACTIM GUI XtractIM crashes on extracting a SiP design if 'SI Ignore' is selected for a die stack layer in Cross Section Editor
2 ^* Z5 r, a9 ]/ m6 o+ ^1642012 CONCEPT_HDL CONSTRAINT_MGR Schematic-defined net groups without any members cannot be deleted in Constraint Manager
; k& h' [* ?0 ~% |- G( r, S1642015 CONCEPT_HDL CORE Pin exists on block but no corresponding port exists in the underlying schematic9 h: d; E% R8 X: A8 ]
1642597 ALLEGRO_EDITOR OTHER Importing .tdp file: Footprints not included in the .tdp file are updated in the design
4 f" y2 l; F. K N9 R3 A3 a! _, d1643557 SIP_LAYOUT DIE_GENERATOR Die Text files will not update the design) s4 L% u6 P$ _9 ^# D" d
1646086 ASDA IMPORT_BLOCK Importing a DE-HDL design into SDA results in error 'IMPSHT-42 Alias cannot be created'! K' F* M2 t/ |1 \* c( L9 O
1647580 ASDA IMPORT_PCB SDA-File Import from PCB Editor has duplicated RefDes on schematic.3 v3 E7 R0 Z. D6 c6 }$ h
8 s5 [( A1 E; t8 z0 I
, z9 p0 H+ U7 \Fixed CCRs: SPB 17.2 HF0055 s- d, ?- x& H# f* t0 R
09-10-2016
8 s4 M: a" y, x# c- j5 C5 [! w' n; p: X; k===================================================================================================================================9 ^& B/ h0 F/ b5 X
CCRID PRODUCT PRODUCTLEVEL2 TITLE
: X h# ]4 b; ~! W& S- u1 X" F===================================================================================================================================4 `- U" u4 c, F
1496199 ALLEGRO_EDITOR SHAPE Overlapping route keepouts result in a broken shape
9 k9 X% J, S6 c, L5 {0 s6 T9 \- w1519972 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase DRC at incorrect location- N2 |8 T+ ?1 {" b, ?' R* J: B
1521940 ALLEGRO_EDITOR DRC_CONSTR PCB Editor not recognizing the correct pin pairs of the differential pair* T! d' g1 D, u0 U3 O" _
1536713 ALLEGRO_EDITOR INTERFACES File - Viewlog still checks for brd2odb.log file4 h% x* K( l [ k' ]4 u7 m
1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once
) C% v! c7 k1 X' [1586846 RF_PCB PLACEMENT Get an error while manually placing RFCOMPIB part
" y* Y2 E( E1 S8 H- e$ c1588769 ALLEGRO_EDITOR UI_GENERAL ALT+key shortcuts are not available in 17.2
, ~& |4 S* P) ^' W1589396 ALLEGRO_EDITOR UI_GENERAL Need option in 17.2 to change the placement of the Find, Visibility, and Options tabs
4 W' I8 l# y t0 _1593258 ALLEGRO_EDITOR OTHER Adding German letters to database diary deletes all the entries
2 Y% g8 J* N1 @' q( v: h1597413 SIG_EXPLORER SIMULATION SigXplorer crashes when simulating with a via that was added to the canvas
' |. x2 V9 d) t) e: h9 {1599680 ALLEGRO_MFG_OP ALLEGRO_INTEG Documentation Editor crashes on opening a specific database
. B, I- B" u' \* ~1606682 ECW ADMINISTRATION ECWBackup and ECWRestore fail when data is 1GB or more, Q( v! {" w; B2 q) ^2 k
1607250 ALLEGRO_EDITOR DATABASE A board file created in release 16.5 crashes when opened in 16.6 Hotfix 696 v1 e* T3 Q4 a2 [+ R4 `3 Y
1607565 ALLEGRO_EDITOR SYMBOL Default values are not consistently converted when adding pins after changing units.
5 @! I4 N' O0 ~6 _6 F; d1607956 ALLEGRO_EDITOR OTHER Unable to generate the model index file from the command line using mkdeviceindex
/ y. j, v" g7 e1 y' e9 r1609794 ALLEGRO_EDITOR UI_GENERAL PCB Editor: Shortcut keys to menus are not available in 17.2+ w0 N M2 p$ _% b7 D
1609817 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes on opening project; F7 C" ~$ G4 k7 [1 z) H* y
1611446 ALLEGRO_EDITOR SHAPE Inconsistent break in shape when creating voids in a design in 16.6 Hotfix 69$ j! H; S" r5 {! H! b6 o* j/ p
1613512 ORBITIO ALLEGRO_SIP_IF Unable to read the OrbitIO database file (.oio) in SiP Layout
- |" Z5 D# |! u( n2 x) q1619610 ORBITIO ALLEGRO_SIP_IF Some mechanical pins appear rotated by 90 degrees when imported
( d0 _' U# ]% v/ _( e8 N( i. V1620814 ALLEGRO_EDITOR PARTITION Etch and Via are not imported with the partition9 H$ t h) `7 e: I i3 N" i2 j% k4 K3 O
1621390 GRE CORE Design Crashes during the Spatial Planning phase$ P$ A, a5 x. W
1623112 ALLEGRO_EDITOR OTHER SPB17.2 switch release is unable to identify 16.6 release when 16.6 is installed in All-Users mode
# W0 L* P5 r) G1623113 ASI_SI GUI Aggressor waveforms are not displayed in waveform viewer after crosstalk simulation( m3 V6 E" z- l, i* `' a/ T
1623231 CONCEPT_HDL CORE Unable to make the Attributes form part of the standard display in DE-HDL' g/ m8 ~3 `" ?; J2 C
1623666 APD OTHER Incorrect vector pin syntax appears in the chips file written using 'RF Module - Export chips & connectivity'
9 q( [; L" R, M: o! P1623888 CONSTRAINT_MGR CONCEPT_HDL Ambiguous and inaccurate mapping errors reported when an ECSet is applied to a differential pair object( o2 u s' V+ m, m" Z2 R) X
1623904 ALLEGRO_EDITOR SCHEM_FTB Logic import fails, but no error mentioned in the netrev.lst file
. J! I9 t7 y/ _1623935 ALLEGRO_EDITOR SKILL On running the SKILL function, axlSectionModify, Shield and Etch Factor are not updated
3 @( t( v" F! I1625610 ALLEGRO_EDITOR SHAPE Modifying a shape boundary leads to other shapes losing their voids7 v+ Z5 N. [7 {/ g6 D7 a4 _
1626716 ALLEGRO_EDITOR UI_FORMS Z-Copy menu is not available with OrCAD PCB designer Professional license. ~# O7 ~8 D. g, K
1628403 ADW TDO-SHAREPOINT Objects remain checked out after multiple failed 'check-in hierarchy' attempts
" k+ ^. k3 ?1 A' E( R1630458 ORBITIO ALLEGRO_SIP_IF Import OrbitIO Database file (.oio) in SiP: Bill of Materials report does not include standard dies
" Z" b. r/ ?0 W# @1632504 CONCEPT_HDL CORE DE-HDL core dumps during Save Hierarchy on Linux
2 M" f, t' F7 ?3 J1633581 ALLEGRO_EDITOR PLACEMENT On mirroring a part, the cursor moves to the origin of the board
, s; S% s9 G8 [) `! ~" q: x1633601 ALLEGRO_EDITOR PLACEMENT Place - Via Arrays - Boundary command: Via arrangement pattern deteriorated in Hotfix 0042 f7 b1 o3 J! r' V8 N
( v- p4 W& G+ x7 `8 Z
: s G$ a4 A( [* WFixed CCRs: SPB 17.2 HF004; I: r; ` E6 f2 l2 I# y
08-14-2016
# a4 d8 j6 @# G% r" b===================================================================================================================================
/ q6 {8 [- X \) iCCRID PRODUCT PRODUCTLEVEL2 TITLE
\/ S# J7 l! |) ]===================================================================================================================================
$ ~: x) N6 C9 W3 z908816 CAPTURE SCHEMATIC_EDITOR Few graphical operations are active even when a page has been locked
: B; J/ i1 e6 N$ q% ?0 V1213923 ADW LIBIMPORT Cannot delete parts in the Library Import project (XML)" L) ]! f' \$ B8 `9 }! D. Y8 s
1250476 PCB_LIBRARIAN LIBUTIL con2con does not check for PACK_TYPE value set to question mark
4 M) d9 M5 P8 Y" D6 |4 M s1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value( Q6 ^3 O! Q$ `, u; w1 Q* I
1322242 ALLEGRO_EDITOR INTERFACE_DESIGN Using Add Connect with the Replace Etch option causes PCB Editor to slow down for certain constraint nets1 U2 G8 o5 `$ y( W$ U# g
1326716 ADW DOCUMENTATION Dataexchange documentation correction needed( l0 T' y, a, e/ ^5 u9 d- r% z
1356948 APD DEGASSING When using the Degassing tool on shapes the size of the file becomes very large
/ @! z$ u& j' r. f( ?1376510 ADW DBEDITOR DX output ERROR after Property Display Ordering of Part Classification. _8 k6 I8 E; x- U3 P5 m
1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file; W/ Z3 l7 z5 E0 D2 ~) S0 c
1410485 CAPTURE SCHEMATIC_EDITOR The 'Autowire - Connect to Bus' menu command and the 'W' keyboard shortcut are enabled on a locked design) u9 i6 A( S/ s8 H8 J' {, E4 {. V8 ^
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only: \! i5 _- N) v) h
1413287 ADW LIBIMPORT Library Import converts all Attributes to uppercase when reading CSV
3 f& _# g% V" \; U1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
3 }' i2 f' p3 {1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
, [7 U0 G& a% S- u7 q% g1430251 ALLEGRO_EDITOR PLACEMENT Quickplace placing symbols outside of a polygon shaped room+ d/ A+ d9 l) D+ \ C# d8 S
1440509 ALLEGRO_EDITOR PLOTTING Ratsnest does not follow the RefDes position when plotting the BOTTOM layer with the Mirror option
7 X- Q: X% W( v, [5 d; i1441086 PCB_LIBRARIAN OTHER Changes made to a package with sizable pins generated from the 'sym1' view are not saved2 e( \$ s8 h6 k0 e
1443339 PCB_LIBRARIAN PTF_EDITOR ALT_SYMBOLS syntax in PTF file not checked
8 g! a3 `5 N# e1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC- C* @; v8 ]7 l- \
1451766 CONCEPT_HDL COMP_BROWSER License error message should indicate which license is required9 u" J0 S: f, n, t2 \
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set; {3 r# j# c0 k" O$ d4 |
1457138 CONCEPT_HDL CONSTRAINT_MGR devices.dml: difference in content generated by _automodel add command and Constraint Manager launch
& D$ @. [" ~2 l1458439 F2B PACKAGERXL The Packager pstprop.dat file reports false conflicts in net properties8 f; T9 U! d2 }8 L; w. D
1464865 CONSTRAINT_MGR ANALYSIS For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM
@4 ~% o$ O" e4 W1 M+ F q5 J$ [1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools' M2 x2 N* v. e& j- R
1467826 CONCEPT_HDL PDF PublishPDF from console window creates a long PDF filename
0 P: Z1 L2 }8 b# e4 e2 n1470106 ALLEGRO_EDITOR MANUFACT silkscreen program cuts auto-silkscreen lines excessively
( J+ B S$ t. j9 G1471287 CONCEPT_HDL CONSTRAINT_MGR Pages imported from other designs with different units should inherit the source constraint units0 N: W$ f- P. C
1472046 ALLEGRO_EDITOR OTHER Gloss routine, 'Via Eliminate' - 'Eliminate Unused Stacked Vias' is not removing unused microvias from the stack
$ a* C( P2 R8 Y) v/ ]7 `2 a: `* X1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region3 T7 _: n" F$ g5 \! e( Q0 c6 `% E
1472444 ADW ADWSERVER Multiple errors in adwserver.out after SPB054/ADW47) N: q: u4 Z& V# S: L
1473056 ALLEGRO_EDITOR ARTWORK Gerber export has additional phantom data not on design2 k8 `, A2 h4 A1 ]6 j' w
1473900 CONCEPT_HDL CORE DE-HDL stops responding when a hierarchical block with variants defined inside the reuse block is enabled
G# y. d4 _) g/ y5 J4 d1474020 ADW DBEDITOR Unable to modify schematic classification when a part is checked out previously by another librarian
! k8 Q4 q7 e _9 D5 Q- C1474066 ADW DBEDITOR Bulk edit performance lags when parts included have a large number of properties
' x3 K% H6 A2 k3 {" o1474764 ALLEGRO_EDITOR PLACEMENT In Hotfix 56, the 'place replicate create' command does not produce desired results if a fanout is marked
, q0 E% u1 J2 g, X' C3 |1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.
- f2 F" k3 o' I( i; U% F5 d7 Y1475650 ALLEGRO_EDITOR OTHER Using Outlines - Room Outline gives WARNING (axlRemoveNet): No match for subclass name - 'BOARD GEOMETRY/__EPB_SCRATCH_'
. o6 M, C! `: ~( q; s* ~/ r3 v1476528 ORBITIO ALLEGRO_SIP_IF While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown1 t* t1 o8 W. e! E
1476920 CONCEPT_HDL OTHER Genview consistently fails in some indeterminant manner.
1 C/ q2 E+ N( u1477369 CONCEPT_HDL INTERFACE_DESIGN A significant number of problems are reported when running genview with port groups
" |$ w( t* D/ s8 N6 m8 q, c i1478111 F2B DESIGNVARI Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release( n' l6 \6 l- [. [/ b7 a0 x
1478200 GRE IFP_INTERACTIVE PCB Editor displays the 'Low on Available Memory' error when updating shapes and then crashes
+ A1 Z2 K* a7 g6 [9 p6 C0 o* x1478680 CONCEPT_HDL CORE Unable to move components in a schematic using the arrow keys) E" U P G, F- r' _
1479135 F2B PACKAGERXL Hierarchical design reports conflicts when signal names change through the hierarchy2 X+ i- \0 n s# D# Q1 r
1479153 CONCEPT_HDL CORE File - Save Hierarchy flags an error and does not update subdesign xcon5 c7 ?" K' e: _, q/ k8 @" J; V
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy- k! ?3 e$ M. _, L8 I
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
$ K) L2 M9 t3 J- A% d% f7 ]1479569 PCB_LIBRARIAN OTHER hlibftb fails with error SPCOPK-1053. Q, P5 G6 g3 @. ^3 H9 M/ N3 `
1479785 ORBITIO ALLEGRO_SIP_IF BRD file is not loaded in OrbitIO' w' Z! {7 e# y- L0 H
1480005 ADW DBEDITOR The DBEditor or DBAdmin GUIs do not allow the same characters in Property as LibImport CSV Files
$ _; y6 {- l7 I+ w1480367 SIG_INTEGRITY OTHER Differential pair extraction SKILL error5 X# p2 h. e, y/ x% M, v+ X
1480499 ALLEGRO_EDITOR PARTITION Cannot delete partition
5 O* y) C% M4 I1482544 ADW DBADMIN Hierarchical Preferred Parts List (PPL) is not functioning correctly
( I, E* ~7 j5 @# ]! R1483136 ADW COMPONENT_BROWSE Error flagged when searching a property value with parenthesis or comma in Component Browser in the ADW mode
4 B: d8 N0 v3 S2 N( V9 V1483617 ALLEGRO_EDITOR DATABASE Delete islands command crashes database with filled rectangles; V& P8 w, H7 n* m1 f# n
1484100 SIP_LAYOUT INTERACTIVE SiP crashes when copying and rotating a symbol
. n! s0 N, A Q2 I1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
# P$ c$ K" T) [' q1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
, i+ Z' E0 a, d1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file6 l; b: A. [: a/ g( b7 W
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project
/ Y0 v5 s- r: N* y1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.8 ]' D3 c: P* i! f, k+ Y( I7 K7 L
1486378 ALLEGRO_EDITOR PARTITION Unable to delete orphan partition as it is not listed in workflow manager., [! C! {4 O$ I% D- q' i
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems2 A3 [' y5 b; E8 L5 L5 S% d8 E: t
1487125 ADW COMPONENT_BROWSE Results not displayed in Component Browser for parts with no associated manufacturer parts% t: o y! y2 q/ S, S, C) j
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior: @' E% D! B+ L6 U2 {& u
1487496 ADW DATAEXCHANGE DX changes checkout ownership when override action is set to remove existing relationships- @! V# ]& V. L' z5 F3 C
1487656 ADW LIBIMPORT Pre-analyzing a project reports false warnings
4 i9 x2 F! J) m; g1487733 CONSTRAINT_MGR OTHER Export Physical takes more than two hours to update PCB Editor board
) Y9 Q9 S$ I, I1488753 CONCEPT_HDL CORE Import sheets in a design with no change in models: CM_VALIDATION_ON_SAVE variable is triggered5 M: M5 Y" U% A
1488758 CONCEPT_HDL CONSTRAINT_MGR Disable Constraint Manager launch if CM_VALIDATION_ON_SAVE is set and the database goes out of sync$ g. m/ o8 _5 m& a
1490299 SCM OTHER Allegro System Architect does not update revision properly- J1 s/ t! p8 `! p7 i+ ?7 w1 _, U6 {
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer
Q# P- c# w+ g- V- Q0 o; }: A( i1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
- \. T( f$ E; X Y1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working5 V& W" C# o" `( h4 w
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)6 x( m5 d+ h0 K+ L
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong- Y/ a; V: F1 c) t" N
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit
, Z9 t/ v/ X0 X: R1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO crashes on importing MCM3 w6 ]" [' |6 |% r0 U9 s2 e/ p
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL0 [; H2 W5 y- A9 O2 F
1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs
/ ~' R8 f2 b! E. \0 l# T1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size
$ H% f9 q/ N* V* M* R* O1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root* P' @5 c; S! h1 |/ M# w
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file
0 J( p7 W- ?: X# ?) v0 Z1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60$ c- b' T [& p, I' S" A+ Q$ \
1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
9 G" u+ h( h$ J) M; x6 B1500725 CONSTRAINT_MGR CONCEPT_HDL Unable to clear pstprop.dat file conflicts& h: c" G7 T8 \0 u+ N) `6 b
1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant9 @' n+ Z: a) t" R9 d7 M6 Q9 {
1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out# Q& N; n( z* G& \ |, Q o$ ^
1501294 ADW COMPONENT_BROWSE Some tabs missing after the migration to ADW ISR 053 with SPB ISR 060
7 ]) Q- `$ d. S. `' ] ]1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
A+ u8 J$ d2 w/ S0 F1502282 ADW CONF Configuration Manager: Clicking 'Set up or Manage Company & Site' gives an unclear message
# }$ t0 b* m( I% x2 Y1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings
' m/ y; b: [8 b1 D1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized, Z8 ^* O2 W5 [. W( }- ~
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
r2 R1 ` Q) t' _( X5 O1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin2 g! \7 o6 \0 u- r2 ?2 f
1506654 CONCEPT_HDL INTERFACE_DESIGN On moving, Netgroups break
* z% r a/ g/ l% w' Y* D# Y1507497 ADW COMPONENT_BROWSE Switching rows in Component Browser does not change the graphics of the symbol
6 w- x6 |* b* {. l" Z# {- a1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork
8 P. |% T1 W, f7 x" u0 L1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
$ b( X* ^ ]0 w# W1510570 ADW DATABASE ERROR: Cannot check in block model because the part with instance id used in the model is not available in the database
4 f/ N" R/ V8 G1 K* Z1511180 ADW DBEDITOR Database Editor: Incorrect message about a schematic mode displays when associating a footprint to a part number5 z( z2 j, a4 J8 j4 t- f. c8 t
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6; A. x2 t t4 p
1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance2 c% f$ \% r( {- i
1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.
$ g _! D4 t K1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working5 m3 D% b; S! K( w
1513085 CONCEPT_HDL CORE NC symbols in the schematic are being renamed to NC_1 in pstxnet.dat and are routed as one net in Allegro PCB Editor
4 I7 }! a o- X9 E% G1513092 ADW DBEDITOR Create Footprint Model name is not working properly if it already exists in the local flatlib
5 ]8 i/ L+ G6 @7 ~, {1513737 ADW CONF DesignerServer from a different network domain does not show distribution data) ?4 E) Y0 L1 V. B5 N8 B* y9 |5 X
1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property
- g5 C% G) W' }5 J1514942 SIP_LAYOUT CROSS_SECTION AIR no longer permitted in stackup in 17.08 q7 {; N3 b$ U8 L$ Y; V
1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly8 C2 o7 Z- Z4 t: L' Y$ z
1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol
. M5 P0 y; n( @# H9 L1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via, Q9 ~, S( i" ^7 I* U3 S
1518032 CONCEPT_HDL SECTION Error SPCOCN-2009 displayed even when the user has not manually sectioned the design
$ y! n+ w {+ J) {( |3 l1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes9 [$ E& D6 l6 q+ |! T: I7 s
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.
$ _+ }: N7 }+ q7 S/ k3 G) r2 Y1519518 CONCEPT_HDL OTHER Genview does not generate split symbols
' a' H1 }5 B$ c" M/ |/ ^1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas
! k3 L' U. [, z1 _1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default2 u# @5 n; `8 o4 ~
1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net0 ~2 k. p) P; h9 p' t. W/ C
1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
2 s8 C, y: f1 x1520207 CONCEPT_HDL CORE Genview crashes after renaming ports
- S7 s+ P& |7 ]4 C; U) S$ f1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
; h$ ]7 c* Q+ j! E8 Q! B1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor
0 Q L3 R4 V8 V, r3 ^7 X8 {1521871 CONSTRAINT_MGR CONCEPT_HDL Constraint Manager launched from DE-HDL allows space in the name of layer sets
' y( k( ]3 D2 t9 o7 D1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.
) w9 U6 Z9 |# K7 B1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP Layout design
/ Y' s2 `1 W' j7 ?9 E, g" m& o1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash
* h. q0 o- i! A9 V6 d- q" p; ^1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated8 c4 g3 e5 N8 a6 I7 \' }
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine' G; S. m$ c$ l6 V4 |. P6 Y/ D. |
1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor0 k0 Z4 z; @% a1 w- [( b
1525883 ADW DATABASE Invoking libimport on an existing DB should verify that the 'libimp_su' variable is set correctly
$ z8 n3 s( a* o1 S9 k) g; [: W1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
7 b4 Q. L9 u& J3 w; k# g$ w# `1526914 ADW LIBIMPORT Cannot import to new library database
& \+ |3 D( Q7 F' Y& \1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63
/ m3 {: [; O- r1 `5 Q* `& ]* m1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
& n* l* t3 l5 q: s( Q1528235 ADW DBEDITOR Running rule 'Validate Classification Property and Property Values' results in property mismatch error& a! g. X% w2 G5 \. i$ |% x! p
1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes
7 J, |6 f, i' G1528398 ALLEGRO_EDITOR SCHEM_FTB Netlisting of pins with NC property results in error
' Z ~1 e" ? `' G2 E6 c1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design6 @6 M' j1 U1 g. z# y4 u
1528894 ADW DBEDITOR Lack of PTF_SUBTYPE in the classification prevents the release of the part
2 w4 m' L/ g( K1529178 SIG_EXPLORER OTHER When an ECSet is created from a net, values are not transferred correctly for PinPairs. t3 g& z8 ?" B; q
1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions9 x5 a! t! [. o3 e2 @6 H* Q6 E
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file
0 D/ u, U1 M ^* u A4 Y& @* Q1530445 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when 'Add Connect' is used
l- _# J( x! `+ e* j% l/ g; \1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes" q# @3 {" O! s4 f4 L Q
1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup
8 p+ e" Y; B- O1 T1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
& _, x5 |! ?, q5 ^; |! B. o1533543 ADW DBEDITOR Component Browser free text search returns 2 parts when only 1 exists5 X" I% L* b4 [
1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue" E2 S6 b5 E& M, Y- s
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties0 b+ q% y/ q+ a
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
; I$ X7 M- r1 @3 T1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform- M a& ~4 l/ i! s w4 R H' L
1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing 'Layout - Renumber Pins'; `9 E- i" Q# O* S( R8 [7 ?/ ~
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
6 ~) s% ?9 u: x* l" B+ O3 M5 P1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run5 ?9 E3 g4 [/ K, g9 ^( U
1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error
. F* M8 q2 b. E& h1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib* e* ]% C+ l, y6 y9 }
1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board
$ S" J3 f/ h% B& C1542949 ASDA EXPORT_PCB The Export to PCB Layout form: The file name specified in the 'Output Layout File' field is not accepted
% Q) F9 a. l$ Q; W- r1543537 ASDA NEW_PROJECT While creating new projects, the new folder name is not visible clearly in the explorer. v% s9 Q! e: `- V& Z& |
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash% ~$ L/ `' v6 j9 q2 }0 P; r. l
1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash
1 m9 d2 h8 D1 X; D1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked
8 W+ ^6 q9 X' h* q2 u& Y( X1544856 ASDA CANVAS_EDIT Edit > Find places the process (UI) behind the SDA tool.5 s, x+ |' u* r* o3 B& f
1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with( b9 Q" i9 K/ B% M# \
1546062 ADW TDO-SHAREPOINT Failure to launch TDO Dashboard, need to update error message with more useful information
! e5 f$ b) \4 d/ H& H1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'3 U; ~5 `- F7 |8 j3 v
1549658 ADW TDA An unmapped network folder in the Team Design Authoring option results in an error
) v& o; Q% V$ G2 R. `6 D3 N8 m6 x7 L1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols/ u% Y3 N2 q: ^7 B/ p
1551635 CAPTURE TCL_INTERFACE GetSelectedPMItems returns error for design cache objects
0 a/ P& z$ Z2 M: U1 i: y1553027 ALLEGRO_EDITOR UI_GENERAL PCB Editor canvas stops responding for tasks such as resize and workspace switch
8 l2 c9 p- K% H l# R6 y1555246 ADW DBEDITOR Part Copy As does not copy AML and reliability model relations.' y8 e2 |' k: g
1555254 ADW DBEDITOR Text in Free Text search box is removed if it loses focus/ G. P- g$ @& H6 q5 r" q- ?
1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon* C& {7 P' O7 |0 @! u1 v/ R
1573039 ALLEGRO_EDITOR INTERFACES IDX returns control to the general interface prematurely during an incremental IDX export; [/ t5 f0 J' \8 E b! y
1580571 ADW DBEDITOR XML files continue to appear in flatlib even after the padstack/footprint models were released
* k6 R- V) V1 X, M/ v1580580 ADW LIBDISTRIBUTION The .lis file contains references to old models even after they were purged.
: \1 R9 G0 g9 Y! x1582064 ALLEGRO_EDITOR UI_GENERAL User-defined menus not working in PCB Editor 17.2
2 E% W' V, Q/ J5 J8 T1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes
/ Z p; m2 ^3 c) a1582856 PSPICE MODELEDITOR Getting 'ERROR: [S2C3471] Base part library does not exist when Export to Part Library', though olb is created0 G4 k0 B; H2 ]# L/ p6 F1 o3 A
1584719 TDA CORE Caching errors are flagged for a board-ref project during block update
* e' y1 z9 M3 X, \. h1587045 CAPTURE IMPORT/EXPORT Unable to import PDF file7 u8 _1 f" s/ B( ~ Y$ { j5 |/ n
1587259 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not working correctly for the 'bottom' option% w* Z# K( A. S5 a# y( P! Q/ \
1588736 PSPICE MODELEDITOR The Model Import wizard displays 'Invalid configuration' message when a .lib file is opened in Model Editor) J9 d/ B! S- v& F7 K! V8 \9 v
1588742 PSPICE PROBE Browse icon is missing from PSpice File - Export - text
% {& A7 m3 Y/ f' M1590006 ALLEGRO_EDITOR UI_GENERAL PCB Editor 17.2 crashes when multiple browse windows are opened1 R# m4 Z! {+ R+ P) C& v
1590597 PSPICE PROBE Problem with the adaption in the Probe Window icons
8 Y! c% e2 x5 m8 A) H! ]) @) i! F1591264 ALLEGRO_EDITOR UI_GENERAL Film order in Visibility View is sorted alphabetically and does not match the manufacturing artwork. ~/ [ Q0 \, k/ ], M* k( f
1592089 PSPICE MODELEDITOR Cannot get the PSpice DMI Model DLL while using PSpice DMI Template Code Generator! f: x5 S/ k* b; r
1593436 ADW DBEDITOR Cursor does not automatically move to the model name cell when creating a new model" [ |+ c5 \8 m& Q G
1594076 TDA CORE TDO crashes on concurrent check-ins when one of the blocks was not modified.
! j2 c8 B4 g! o/ e/ K6 p6 B1595987 ALLEGRO_EDITOR PLACEMENT Subclasses not getting updated in Placement Edit mode
4 f3 n. I/ h# [1596162 ASDA IMPORT_DEHDL_SHE Importing sheets from DE-HDL imports the block as well
" ~' L i8 F3 j$ J3 d- p1597000 CONCEPT_HDL INTERFACE_DESIGN Renaming a NetGroup does not work if several segments of the NetGroup trace have the same netnames assigned." S" V2 \0 s; ?! T9 P- u" J( _0 J
1597406 ALLEGRO_EDITOR SHAPE Dynamic Shape does not void the traces and voids open areas
2 h( t( O: f& ?1597957 ALLEGRO_EDITOR PLACEMENT Quickplace: placed and unplaced counts not getting updated6 t; W! v! _% M9 N
1600194 ALLEGRO_EDITOR DRC_CONSTR 'drc update' gives a different DRC count each time the command is given in a multiple-cpu system
, H" U: f3 G2 u+ J: p4 k1600800 ALLEGRO_EDITOR GRAPHICS LINUX 17.2 operation of Update DRC is not the same as Windows – graphics not updating
' K$ ~' A: t. u/ v1 H5 }3 j8 s1602605 CONSTRAINT_MGR OTHER OrCAD: constraints not getting saved% ?. I) w m# V- w- R- w4 L
1602801 SIG_INTEGRITY OTHER Dielectric Warning message when opening SiP tool.
& k2 C6 q7 F$ w6 x( x: y. x6 v7 n1603377 PSPICE ENVIRONMENT Running simulation with the 'At Markers Only' option does not generate the .dat file
5 [ S8 w) j2 c4 {* j$ K' Z1604166 CONSTRAINT_MGR CONCEPT_HDL Audit ECSets does not work from 'Referenced Electrical CSet' column header- G/ ]6 w; I/ j& G6 A; {
1604741 ASDA CANVAS_EDIT Tcl console changes the present working directory when you open Project Preferences and close it.* X% l" ]6 P5 J; s
1605310 TDA CORE Join Project wizard: Random crashes in the Team Design Authoring option
# V* l1 @, O( i- q8 Y2 R* F8 h1606861 CONCEPT_HDL CORE DE-HDL crashes on Linux during the Generate View operation+ S" S' V1 P; B& o
1606917 CONSTRAINT_MGR CONCEPT_HDL Importing tech file in DE-HDL Constraint Manager is creating a duplicate 'DEFAULT' cset/ ^* Z! Y V" [* h# \7 U
1607157 ALLEGRO_EDITOR INTERACTIV Edit - Change allows lines to be copied to Cutout subclass, but that subclass requires closed polygons* E3 B- m- U" d" m, T$ R" R j
1607330 CONCEPT_HDL CORE Variant view schematic PDF corrupted with attach_props set; N. U$ ]0 Q% a1 Y
1607568 ALLEGRO_EDITOR NC PCB Editor shows wrong drill legend for Top-to-Top drill
/ L2 |# V( ^6 `1 U% b6 H, G1607986 CONCEPT_HDL SKILL cnGetSetupProjFilePath: The SKILL routine does not deliver the full qualified path and name of the project in 17.2# S" R7 o: S3 @% z; r. e
1608524 SIP_LAYOUT MANUFACTURING The Display Pin Text tool fails in the 16.6.073 version with a parseString error.
( Q; Z/ F. `% {3 u* z( r$ g& q1609400 ASDA CANVAS_EDIT The 'Assign Differential Pair' right-click pop-up menu command should be grayed out when a single net is selected( O% D0 ?, P0 e4 r. {
1609809 ALLEGRO_EDITOR UI_GENERAL Crash in Allegro PCB Designer version 17.2-2016 on Linux
+ I! O4 i6 h$ n1609856 ALLEGRO_EDITOR ARTWORK Embedded paste and soldermask showing up in both top and bottom gerber files., ?; h: E; C9 x: q" N( ^
1609922 CONCEPT_HDL INFRA Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only" B" B( d. o+ @: S' @3 f
1611226 ALLEGRO_EDITOR SYMBOL PCB Editor gives a crash message while saving a flash symbol8 Y0 f$ R% |0 r
1612108 ALLEGRO_EDITOR OTHER Netlist Import is crashing with the .SAV message.: `2 b1 I+ }; t
1613123 ALLEGRO_EDITOR SKILL DrillType for Oval Slot should be 'OVAL_SLOT' not 'OVAL SLOT'$ l# ~( Y$ Y! \) U2 T$ N
1614000 ADW LIBDISTRIBUTION Library distribution (lib_dist) does not complete; lib_dist.lck cannot be deleted when Configuration Manager is running
. l" e" u) ~0 r0 ~ O: P1614667 SIG_INTEGRITY SIMULATION Different results from Probe in Allegro Sigrity SI and SigXplorer5 X/ w: K+ G1 f0 r
1615601 GRE IFP_INTERACTIVE Delete Bundle then try to delete plan lines results in fatal error& [( K& Y* L- J- l7 \2 x
1616235 ORBITIO ALLEGRO_SIP_IF oio2sip import does not map layers correctly6 T6 _5 {5 j$ }: a' T9 V
1616540 SIP_LAYOUT DRC_CONSTRAINTS Same net DRC Line-to-Line reappearing after dyn shape update% ?% i2 f* g, D# S) E3 i( T- A
1616733 ALLEGRO_EDITOR INTERFACES 'genrad output' no longer working in 17.2. Gives the Error 'extracta process failed. Command terminated'
" g( S$ V3 e8 y* F5 q& E" X1618751 ASDA DRC Zero Node Net errors flagged when DRC checks are run, though RETAIN_ZERONODE_NET is set to 'NO' in Site CPM file; y; s9 D% T1 k9 k+ U
1618797 ADW FLOW_MGR Flow Manager cannot execute a specific command in 17.2.7 U y! m% J, T
1618930 CONSTRAINT_MGR INTERACTIV Hovering over row column cell causes the application to go into a not responding state.; P' j; v) Y2 w, m
1620350 ASDA EDIT_OPERATIONS Pin number is lost on updating the version of a connector pin
5 L! s& X; V" w6 y) _1 Z1621963 ASDA SELECTION_FILTER Selection filter: Pins in the symbol used in connectors are not selected: m$ Q. \; E( }4 r& j
1622715 CONCEPT_HDL CONSTRAINT_MGR Extracting an XNet crashes DE-HDL8 `" M: I6 Y9 s6 X4 E' z" a% P
1625209 ASDA IMPORT_PCB File Import from PCB Editor shows board differences
. v$ L& v D H7 a- S3 |7 b
; p# j+ X& v! K0 k# x- j! t4 h h: \. L' U/ ^6 I" u
Fixed CCRs: SPB 17.2 HF003* v; u4 {9 {* r' S* G
07-28-2016
4 s, z: z/ k U( ^# H& }===================================================================================================================================- [# u- [6 u# _+ u; h# |$ P
CCRID PRODUCT PRODUCTLEVEL2 TITLE2 ]3 E/ B; E3 p( u1 C
===================================================================================================================================
' p4 Z' k7 Y+ H7 d% M1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result! ]4 h8 a X8 i. t p( W$ `. X- F
1461626 CONCEPT_HDL CREFER Cross-references shown to the same pin on different block instances though the signal names differ N+ M: q9 k$ Q- F! z- n2 ~6 D
1472456 CONCEPT_HDL CORE The design connectivity (XCON) file and design data are not in sync$ s( A/ G& I4 V8 b) v6 m2 G' [
1546151 CONCEPT_HDL CORE Add port, Genview, move pin on block - the pin name disappears
: Y! ~- _) I& _: d% N# j( N7 ^' e1547356 ALLEGRO_EDITOR EDIT_ETCH AiDT gives different results in ISR S034 and S066+ k9 S8 @4 |9 O4 I
1560102 ADW FLOW_MGR Flow Manager: None of the eval commands working
% g$ X/ _% a% A0 G+ V1570032 ALLEGRO_EDITOR GRAPHICS 3D Viewer shows flat LED for a specific design4 l9 @6 q) Q5 V5 J/ x+ M
1574676 ORBITIO ALLEGRO_SIP_IF Updating the OrbitIO database with a modified .sip file gives errors) {- D, h+ G/ C5 L
1578876 ADW ADWSERVER Component Browser crashes when trying to show details of a part number$ z0 V% r# r/ O- x( I2 ^
1580744 F2B PACKAGERXL Running Export Physical results in error SPCODD-1145 ^# B4 r# e# i0 J) F# e; _
1582863 CONCEPT_HDL CORE Generate View creates non-existent ports, s4 p' Q% D R0 e6 y7 N" _4 [8 b$ h
1584317 CONCEPT_HDL CORE Provide an option to open pxl.log from the Design Sync window when packaging does not complete successfully3 F) o' n' R3 l# v0 \2 y
1587018 ADW FLOW_MGR User is prompted to specify the flow name each time the project is updated
. B, C* C8 P9 \2 K; ~* G1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties5 n' `4 n0 E" e
1587498 CONCEPT_HDL INTERFACE_DESIGN Need the ability to tap individual bus bits
* z: w( W/ T: F1587718 ADW LIBIMPORT Library Import - The Pre-analyze tool does not report errors
% T3 g4 W$ A8 p1 Y- D* |$ \ b8 p1588197 ALLEGRO_EDITOR INTERFACES STEP export fails when External copper is selected on Windows 10
2 ]9 S/ `& I+ q1588786 ALLEGRO_EDITOR OTHER strip_design reports 'Design has been corrupted'
0 ~, ]/ G/ e3 E+ i, Q# @1589252 CONCEPT_HDL CORE Search results zoom into the page origin instead of the selected components: P# E' Y% O7 |; F$ u$ Z* O7 |
1589318 ALLEGRO_EDITOR DRC_CONSTR Via to SMD Fit DRC reported between embedded pin and via which do not share layers. C; F c+ ^# a8 J7 t- e
1589979 ADW FLOW_MGR Design Name change does not reflect in Flow Manager in the same session of a project
8 e1 \2 O5 D$ A6 F1590538 CONCEPT_HDL DOC Open Archive: Some observations on the random behavior# n" w8 ^/ s' _& r4 Z8 G- u
1590639 CONCEPT_HDL OTHER Importing a design in DE-HDL results in a crash
$ X+ q( H g- m2 ~# m1590651 CONCEPT_HDL INTERFACE_DESIGN DE-HDL: Duplicate NetGroups created in Interface Browser and Constraint Manager
[' ~: y2 ?% }3 O2 T3 ~1590720 ALLEGRO_EDITOR INTERFACES Exported Text Size Parameter file does not load names into the text table) f- X" u/ U/ Y6 }* P# @+ a
1591070 PSPICE PROBE PSpice crashes when using the Trace - Measurements - Evaluate command1 X0 J( K N! ]. d# g1 X
1591223 CONCEPT_HDL CORE Variant information for lower-level schematic not displayed6 o: M- p/ d( V. `- w; z5 W* @( k7 d
1594240 CONCEPT_HDL ARCHIVER Archiver is not able to change the permissions of the cells archived
/ P2 Y# z. F' K; i) N+ m8 V+ q1594416 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when you create a new pad9 p- B& e O; x% h# ?8 l3 A
1596615 ADW DBEDITOR Unable to search parts: Component Browser did not launch; Database Editor did not return search results, |: T7 ?/ B2 m( R0 ~
1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save. [7 H) s3 v, H/ m/ ?+ G- R
1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor6 v7 C. _8 c( z# `1 ~* `
1597385 F2B DESIGNVARI Some 16.5 variant DNI parts appear in 16.6 as X-OUT and some without X-OUT or DNI! [* k# S4 T6 P/ n: w( J& O& d
1598629 F2B PACKAGERXL Export Physical crashes after flagging error SPCOPK-1458* _. b5 ?/ F( p0 |5 d
1599452 ALLEGRO_EDITOR ARTWORK Import Artwork with Mirror option does not import pins or shapes
; Q3 n9 V: g9 z. w( z1599744 ADW FLOW_MGR Flow Manager: Commands associated with some of the buttons not working" Y$ D% p `; G/ p& q1 g
1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.+ t$ ]* l/ D2 D) e) t9 D" P
1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group
" a% c5 t% g+ d1600618 ALLEGRO_EDITOR DRC_CONSTR Casing of property names is affecting results when working with Physical Constraint Set+ ^+ P$ @5 X. C* Z( U* u
1600914 ALLEGRO_EDITOR INTERFACES Exported PDF has unfilled shapes despite enabling the 'Filled Shapes' option
4 B$ d; G' c: K! r) H% f$ J1601165 ALLEGRO_EDITOR DATABASE Thermal Relief is not added for Rounded Rectangle pad
5 f1 e l0 \1 k$ t1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol$ @" c" Q+ |; Q" f
1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name.# _4 d1 [/ P! Y# \" v- c2 P( D
1602514 PCB_LIBRARIAN METADATA References to some primitives missing in block metadata;TDA errors reported for missing parts after joining a project X" C7 \2 O. }3 ?( \
1602823 SIP_LAYOUT WIREBOND SiP crashes when using the Add Wire command
$ e' M- B7 G9 V( K' g$ i+ b1602955 ALLEGRO_EDITOR SHAPE Shape to Route Keepout DRC not reported for attached database ^2 v$ t* J7 U q1 Y
1604223 CONCEPT_HDL CORE Tool stops responding after error SPCOCD-553: Connectivity Server Error) j3 A- c' P4 h! T7 m2 d
1604746 ALLEGRO_EDITOR OTHER In 17.2, layer data is getting changed when importing extracta files into other thirty-party extraction tools; }4 i& [" P( L$ [ [
1605322 ALLEGRO_EDITOR TECHFILE Generating tech file in 17.2 takes much longer as compared to 16.6) d. o0 v" U$ O8 m6 j
. f) N2 F& R- b' o
4 A. a' u, v+ w6 b: H; @# iFixed CCRs: SPB 17.2 HF002
1 ^+ {% v1 d" S# L06-31-2016
$ Z% h% A9 |( z% M x, G+ D. O, o' F: L===================================================================================================================================3 z' Y: `5 l2 Y8 {7 s
CCRID PRODUCT PRODUCTLEVEL2 TITLE
0 o* A6 d( a3 s" y/ A+ ^===================================================================================================================================& ]% o$ K' J5 G. f
1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets2 P4 e6 M8 I, n
1469146 ADW LRM Packaging error reported after updating the design using LRM
6 A; i9 S. A8 ?: y1481802 ORBITIO ALLEGRO_SIP_IF Import of an OrbitIO file to an existing SiP file offsets the results incorrectly
0 x1 \# N9 X: Z$ y1518957 APD SHAPE Shape void result incorrect/ M3 A5 K: s. P2 h" w1 B' t( i7 S3 K
1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error
N3 K4 C6 ?( G) Q% g, Y& p8 m4 D1524947 SIG_INTEGRITY SIGNOISE Custom Stimulus is not recognized correctly in Allegro Sigrity SI or PCB SI.9 a3 l8 @7 L: G; y: }
1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols." u$ F1 ?/ F% c& m& \, a
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in the attached design.9 D5 u; z7 @9 J y# Z' \" N4 i$ E1 D
1544675 ALLEGRO_EDITOR OTHER Export Libraries corrupts symbols if paths do not include the current directory (.). r: n7 y; z6 U, W
1549097 CONSTRAINT_MGR XNET_DIFFPAIR Show warning message if differential pairs are created for nets with voltage properties) a9 i% g3 Q6 z; x/ t- D! j
1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
$ z5 T0 u8 o/ r4 b) p+ s3 z1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library; _4 Y+ x' L" {' }& K+ k, ]( ^
1555009 CONCEPT_HDL INTERFACE_DESIGN Unable to rename a NetGroup.
# b h% V: F7 c# g+ r, Q( f9 o' x1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets
/ k# W3 o% l3 X; u# S8 _8 ~1559552 SIP_LAYOUT ORBITIO_IF device offset in oio2sip translation
' f1 a* c" M$ M+ _7 Y1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open9 _# Q8 [! N2 ] @$ `
1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters$ T# M; t4 S# g: s' t( C
1561501 ORBITIO OTHER OrbitIO stops responding when refreshing a design in SiP Layout
3 P/ h* V0 |6 j4 _2 f6 c+ I! C1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC1 O- n7 t$ }1 I% m9 T e9 j
1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins- r- k: b# C; e
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas1 P4 r1 s9 x8 k( j
1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions
( b, J T: G" L8 X( d1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete
! m( ? Y8 ~' a% _1 P! }1566942 ASDA MISCELLANEOUS Several extra files in the /tmp/ folder on Linux
, k4 N \+ a/ M/ R1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.
5 E7 ?5 m! }3 x: r* c) T: L8 B9 j1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct3 \2 Y+ a0 ?/ P3 E* H4 s: i5 i& _
1569056 CONCEPT_HDL CORE Opening the same drawing in multiple cascading windows view displays non-existent artifacts: ]6 D7 T- T$ } J/ u
1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'
5 Y/ U# w* p9 }" ?6 T1569147 CONCEPT_HDL CORE The signal name auto-complete drop-down list is not displayed correctly
) {/ |, W, x& f. }3 v, R+ h1569394 ALLEGRO_EDITOR SKILL axlPadSuppressSet( 'on 1 '(via)) not working on SPB17.26 N/ r5 s! \" k5 Z5 q* n
1569924 CONCEPT_HDL CHECKPLUS Checking in a large BGA into ADW results in an error related to negative signals
& _1 T0 X8 S S' y1570398 SIP_LAYOUT DATABASE Diestack layers cannot be deleted if there are unplaced symbols in the design
7 C$ a6 Z+ e' U3 g$ x3 i. T0 o* u1570419 CONSTRAINT_MGR CONCEPT_HDL Need to add a customized worksheet custom property weblink in Constraint Manager
, {0 Q$ q6 f& O/ r" Y# x' B. \* n1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short
( G6 i a: w* ^* Q ]; j, U. |1570678 F2B DESIGNVARI Variant Editor: Error when adding an RSTATE property
1 |* T2 j- Y$ A$ V, G1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only
k- R8 f* R( F! w2 b; I1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display
4 D* |, b' r7 z6 D1573127 CONCEPT_HDL COPY_PROJECT The CopyProject functionality creates an incorrect 'view_pcb' directive value9 G5 i1 W( B8 E
1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)9 z4 w" [( Y7 t
1573625 CAPTURE PROJECT_MANAGER Toolbar customization is reset when Capture is re-invoked in SPB 17.2: t) F$ \* C5 l- b
1573755 ALLEGRO_EDITOR CROSS_SECTION Changing a layer's type is also changing its material in Cross Section Editor, ?$ | U0 t# H5 e! V4 r: W
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the project CPM.arch file
' d5 h F! u) Q1574381 CONCEPT_HDL OTHER Packager crashes on repackaging a design with RefDes related advanced settings
; @6 ^# R* A9 G$ l9 T4 v$ s1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'
: ]4 z" ]6 S, Z6 ]7 f1577381 CONCEPT_HDL CORE ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure0 N } K5 J# C7 Y6 H
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files
$ l6 Y, ^0 p9 l8 w! \1580891 SCM REPORTS Dsreportgen crashes in different scenarios+ _" R$ ]# u! w# Q! A
1581254 SIP_LAYOUT CROSS_SECTION Cross Section Editor crashes when adding a layer
; Y7 b" ?5 J% Q3 s8 \. H1584957 ADW FLOW_MGR 17.2 Flow Manager, JavaScript - Tool Launch Error: c U& X! C, y$ A6 A1 @5 a
1588823 ADW FLOW_MGR Flow Manager: In 17.2, using back slashes in the UNC path results in problems in working with the tool
8 ~' e! ]0 B2 P1590064 ADW LRM Allegro EDM Flow Manager - An empty LRM dialog opens on design load in 17.2
. S6 ` O& p3 g) ?6 H
$ `# k- D q' b
?# ] U. K. }Fixed CCRs: SPB 17.2 HF001' c1 E* o7 f6 F: `$ J& Y
05-06-2016: J( n! M- D( X* g( C
===================================================================================================================================
0 Z& Q$ O8 R2 u4 U; P- p8 tCCRID PRODUCT PRODUCTLEVEL2 TITLE4 u5 e3 R0 A4 m# R3 W2 b( g
===================================================================================================================================
0 Z3 e5 D" c H1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output, d0 X3 h+ R' Y- ]9 I9 R
1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group
: y, y/ D9 I3 [1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
$ c# o( `4 Y* B1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail
$ q- N: Z) ^4 T& I1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
% _0 d' n+ T9 }! s- _& Q0 E1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
^/ k, B n4 J' L% e7 A1506672 ALLEGRO_EDITOR INTERACTIV In the attached board file, when using Replicate Place, some shapes are missing from some layers. t: K1 D5 D/ D# I
1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager/ \9 r7 P; \# g1 W
1523532 F2B PACKAGERXL Adding subdesign names in the 'Use subdesign' or 'Force subdesign' sections hangs for more than a minute
* X7 Q0 Y# {/ @, X$ z3 ?, D# B- I C1525783 CONCEPT_HDL CORE '\BASE' scope does not work for SYNONYMed global signals+ d4 Z Z/ A: x+ x7 y
1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash in the interactive and batch modes2 v9 [( \) W0 `6 e
1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork! I7 [6 h" k7 Q' I
1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed) |$ @: l$ Q6 x8 o& V; h
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.
* f& e; D! `& A1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
0 x( e; Y" K3 L# b" E, _! k1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols) y9 g( t6 R& C
1543410 ADW LRM LRM shows confusing part status; reports that update is needed but clicking update does not work T. A. n3 d) H5 O' Z9 Q
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
% H* ^: F( R& @; |, g5 {! }& r1 v* Y1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design0 S5 @5 B# m! K; ]7 k
1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license
* Z4 R8 H3 S, j/ M! O1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork- e. I w' M. u8 H, |7 _6 V8 r" u
1546877 CONCEPT_HDL CORE Align Left on wires fails with incorrect error message
( H E G% a Q, D3 r' o5 u1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system
6 a2 M8 X; ]5 o* w: q1547584 SIP_LAYOUT OTHER SiP - Design Variant: Delete embedded layer if not selected
8 \; l* F+ m/ ~% ~1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol2 a& h" y0 I u0 A8 x: T5 f- o: _" W$ k
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file
- h. Y) Z6 v4 i8 S9 x1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report3 d# m$ Q- r8 H& V( s6 l/ i7 a
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines
4 C) L0 V0 F+ W* d+ Y N, ?1549662 ALLEGRO_EDITOR OTHER Import Parameters Path fails if parampath does not have the current directory (.) set
, h, V- T3 I# ]# ?7 x' F1549836 CONCEPT_HDL CORE Tools - Customize - Keys - Reset does not reset keyboard shortcuts h3 N7 N1 p5 y! l5 ~! W* w+ a
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems4 _" Q: [4 g" D8 ?4 L5 ^( t& s! Y' g
1551713 ALLEGRO_EDITOR DRC_CONSTR Hole to Hole DRC between via and pin not shown
: a# U/ i8 z# O* A B0 u& A# s D1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl(pixel2UserUnits) crashes PCB Editor( }7 r8 W3 c1 s( q% e1 p, ]5 @
1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to NetGroups' _; h) c8 ~' j3 M7 N$ J8 |3 L
1555092 SIP_LAYOUT DEGASSING Degas offset is not working with hexagons
8 b2 J, h6 {) g/ L4 q1556261 ALLEGRO_EDITOR DATABASE DBDoctor crashes with the error 'Illegal database pointer encountered, Exiting DBDOCTOR.'' Q2 m6 r2 H, f# G
1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted
# n6 U; G/ Z, h( S4 N3 h8 ~. `6 `1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor - Refresh co-design die l" O. N$ p) a( X
1560197 CONCEPT_HDL CORE BOM-HDL adds extra characters to subdesign_suffix when generating hierarchical BOM
8 p6 D! l c/ S2 l( }% G) i' n1561077 ALLEGRO_EDITOR INTERFACES Beta - IDX User Layer export fails on Linux8 s/ T1 U! A8 {! Y9 p
1562537 ALLEGRO_EDITOR MENTOR Using mbs2brd in 16.6 gives a fatal error
6 S8 C: s; h; n5 ]* G1 q7 V& B% u1564203 ALLEGRO_EDITOR ARTWORK Cannot generate negative artwork
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发表于 2019-11-5 13:54
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