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5金币
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# allegro PCB Router
2 r- q) A9 I6 i( f) p9 n, G/ E I+ g# Copyright 1990-2006 cadence Design Systems, Inc. All Rights Reserved.
/ r# |6 B1 P5 i1 t# ===============================================================================7 n. E9 [2 J" `* V+ F
#
3 n' Z2 q! Y3 {5 w( F# Software licensed for sale by Cadence Design Systems, Inc.* r6 z) ~( F# Z7 X
# Current time = Thu May 19 10:53:42 2011
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# Allegro PCB Router v16-3-85 made 2011/02/14 at 12:53:30
6 z9 H q- C# b9 p4 f2 V# Running on: pc-200201020345, OS Version: WindowsNT 5.1.2600, Architecture: Intel Pentium
" g' M+ Q- z# U$ i s4 U8 U) [# Licensing: The program will not obey any unlicensed rules5 |2 g: t3 Q* Y3 ?& e! z5 r! n
# No graphics will be displayed.$ P1 E" V' c }% O4 l
# Design Name F:/orcad/DSP/dsp board\dsp_xnet.dsn
% \' {# K4 i$ B$ a0 U# V# Batch File Name: pasde.do0 q G+ r, j7 }6 _) k
# Did File Name: F:/ORCAD/dsp/dsp board/specctra.did
1 k6 A4 w, ^' v# Current time = Thu May 19 10:53:42 2011
, O+ C1 M9 ]# }5 v- p# PCB F:/ORCAD/dsp/dsp board$ e% O2 s8 [6 L
# Master Unit set up as: MIL 1000
; @" L% W j% @# PCB Limits xlo=-4032.0000 ylo=-4032.0000 xhi=14032.0000 yhi=8032.0000
+ m5 X' f. S! Y" G- W# Total 277 Images Consolidated.
$ t' G% m% n8 d9 T# Via 'VIA100-50-120' z=1, 2 xlo=-19.6850 ylo=-19.6850 xhi= 19.6850 yhi= 19.68502 ]0 k6 s& j- N5 \9 z0 F- N
# Via VIA60_35_95 z=1, 2 xlo=-11.8100 ylo=-11.8100 xhi= 11.8100 yhi= 11.81003 z- l/ `# O1 G0 p
#
$ m3 S% o: V; k; `+ E# VIA TOP BOTTOM
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3 T) e5 R% d4 `2 o. @# TOP ----------- VIA60_35_954 m t% o b5 p3 T C
# BOTTOM VIA60_35_95 -----------
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# <<WARNING:>> Net VCC3V3 is defined as a signal net and contains 118 pins.
3 ^' u9 g8 f* {2 u; B# This is more pins than most signal nets contain.
+ i( e" T8 Z: @) R# Please verify whether net VCC3V3 should be a signal net or a power net.
7 s9 D* @4 f( }- Q8 R# Note that a signal net will be routed as starburst or daisy chain.6 }! ^% a2 L6 {# I5 S
# <<WARNING:>> Net GND is defined as a signal net and contains 283 pins.
) r/ |. d& S! r0 J1 d ^" J% D# This is more pins than most signal nets contain.
3 g3 T# W5 m3 @# Please verify whether net GND should be a signal net or a power net.) [7 E2 @. V0 ~( G
# Note that a signal net will be routed as starburst or daisy chain.6 h9 _4 U. g* J) a, N4 n, b7 {
# <<ERROR:>> Error in file F:/ORCAD/dsp/dsp board\dsp_xnet.dsn, line 6226: token 5 = Orphan_net6 ~2 n% V1 f+ r8 @# Q1 r
# (content): (wire (net Orphan_net) (type route))
. Z7 g, z% D$ b# l( U; r# <<ERROR:>> Parser: Unrecognized token net while parsing shape2 j( m6 ?0 W% S" _
6 K3 o6 C( g/ W1 E* a! `! G报错的板子:
dsp_xnet.zip
(463.22 KB, 下载次数: 17)
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同一板子没设置约束前不报错:
dsp.zip
(398.35 KB, 下载次数: 6)
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. {& W) g+ D Y& F我对VCC3V3和GND只设置了线宽,它怎么提示:defined as asignal net ?
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7 K! J" H3 v) E+ R6 L7 E下面的错误能看明白字面意识,但不懂到底是怎么一回事, U# B; i) k A( K* }
t% U) J4 c# f' N" Z: ?' l/ V' ]# (content): (wire (net Orphan_net) (type route)):这一行它想提示什么?( z$ q" u4 o* z6 l/ ~ Z) \
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最佳答案
查看完整内容
很无聊,,所以帮楼主检验了一下
直接的确进不去
不过DB Check以后,,
可以进……
所以要做的就是DB Check!!
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