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1#
发表于 2011-5-19 11:58 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
5金币
===============================================================================
9 I) D  f2 h( c#                               allegro PCB Router                               6 @$ i+ f  I0 T5 w- q! L
# Copyright 1990-2006 cadence Design Systems, Inc.  All Rights Reserved.
& F+ g' I  \/ q' l7 g  i6 s, P% y# ===============================================================================* D% E! a. L' x7 M; L
#
: d! F/ \' D- a0 `( N+ G# Software licensed for sale by Cadence Design Systems, Inc.7 t6 [3 R; q9 o/ b
# Current time = Thu May 19 10:53:42 2011
  q. N5 q. r# i5 B# " E0 k) ]" z2 ~0 T0 n
# Allegro PCB Router v16-3-85 made 2011/02/14 at 12:53:30
3 K0 k. C' H- d$ I7 J# Running on: pc-200201020345, OS Version: WindowsNT 5.1.2600, Architecture: Intel Pentium9 p4 d; s7 X* V" G; s
# Licensing: The program will not obey any unlicensed rules
( A% F4 q& p3 i, F* ^1 i# No graphics will be displayed.
- d+ [" M" r; \# r- C# Design Name F:/orcad/DSP/dsp board\dsp_xnet.dsn
" H! m! \# W' u) }- R3 R3 l. j% f# Batch File Name: pasde.do, y0 T  C) e5 H
# Did File Name: F:/ORCAD/dsp/dsp board/specctra.did4 F' w% q4 ?$ R, c4 X9 D1 O
# Current time = Thu May 19 10:53:42 2011: A$ o) M* D: s. C+ B
# PCB F:/ORCAD/dsp/dsp board
' M( @# ]$ z$ l* e5 o( ~# Master Unit set up as: MIL 10002 q( P: h- _4 s0 R8 J9 o
# PCB Limits xlo=-4032.0000 ylo=-4032.0000 xhi=14032.0000 yhi=8032.00001 J1 m! N! O% n8 N
# Total 277 Images Consolidated.3 K9 ]  F9 b- j) P, g0 z6 p0 g
# Via 'VIA100-50-120' z=1, 2 xlo=-19.6850 ylo=-19.6850 xhi= 19.6850 yhi= 19.68508 m& Z3 k+ Y) z' \. ~
# Via VIA60_35_95 z=1, 2 xlo=-11.8100 ylo=-11.8100 xhi= 11.8100 yhi= 11.8100$ t1 W( A, ], g
#
* r& A) f; b  g% I* a0 C0 i#    VIA       TOP       BOTTOM   , [  Y5 q8 ]9 y
#
) z" u" s0 c, A. G#    TOP  -----------  VIA60_35_95
% \. U  C% t0 y1 v: W# BOTTOM  VIA60_35_95  ------------ b% i1 o( [7 n! e1 {* h
# 1 {1 V& E" X2 z* R! P
# <<WARNING:>> Net VCC3V3 is defined as a signal net and contains 118 pins.
! M2 d6 ?3 E4 N8 ?4 ?# v) x* N- I, z# This is more pins than most signal nets contain.
9 b! W& T% ~8 f* ]# Please verify whether net VCC3V3 should be a signal net or a power net.* W0 r/ [2 e& z/ j9 W- ?
# Note that a signal net will be routed as starburst or daisy chain.. Z$ f5 M, j) u* Y+ y
# <<WARNING:>> Net GND is defined as a signal net and contains 283 pins.
0 f/ W+ s& z, N* |$ U; s% V# This is more pins than most signal nets contain.
" L) v$ M$ u* ], Y- u* w# Please verify whether net GND should be a signal net or a power net.
; a# d4 b6 g8 C1 {4 M6 Y6 G# Note that a signal net will be routed as starburst or daisy chain.; Y2 \! j9 L. C7 G8 \; P# Q9 p
# <<ERROR:>> Error in file F:/ORCAD/dsp/dsp board\dsp_xnet.dsn, line 6226: token 5 = Orphan_net% E% u  _. s, t" ]
# (content):   (wire (net Orphan_net) (type route))
$ H. m1 ?& b9 c7 t% Q& b8 z; i# <<ERROR:>> Parser: Unrecognized token net while parsing shape* t8 o% `9 ^3 R
, ?/ V9 D) y1 b& x
报错的板子: dsp_xnet.zip (463.22 KB, 下载次数: 17)
  G; s4 J" p6 I  e' n1 w6 X& ?9 B. s2 @! [7 G
同一板子没设置约束前不报错: dsp.zip (398.35 KB, 下载次数: 6)
( C; ~  o$ Z) f! T9 \1 J8 H" P/ R+ t0 ?; p8 Z  e9 w+ _+ v9 u
我对VCC3V3和GND只设置了线宽,它怎么提示:defined as asignal net ?% d& @! }4 `! s; q

/ W# Q7 n- q/ V5 G$ a  c4 h下面的错误能看明白字面意识,但不懂到底是怎么一回事
% O: r/ b6 U; t+ \( o, c! H  G7 s4 t, L% [
# (content):   (wire (net Orphan_net) (type route)):这一行它想提示什么?
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' {6 I- A: _& Q7 |
8 t6 P. j- s8 [8 n- X6 A. X

5 ~4 ~7 `  @! V7 [( ~1 x

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很无聊,,所以帮楼主检验了一下 直接的确进不去 不过DB Check以后,, 可以进…… 所以要做的就是DB Check!!
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    2023-10-12 15:00
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    [LV.2]偶尔看看I

    2#
    发表于 2011-5-19 11:58 | 只看该作者
    本帖最后由 flyingc381 于 2011-5-19 14:57 编辑 ) I2 H& Z2 X7 G( J; _

    ' ~/ C( ?2 w" T1 C. a# Q很无聊,,所以帮楼主检验了一下3 q. x1 b- {/ Z& M$ c/ Z* T* X

    # `! `# |! {2 F5 U5 M直接的确进不去
    3 V0 Y; R7 h/ |( D6 {2 P
    . N# a9 T% `& C( h7 V! ~9 v* S不过DB Check以后,,( O7 c: ^% X$ I( _# ~" Y
    9 X- E4 ~% o6 [  x% L/ Y
    可以进……5 R7 h/ r0 r( x$ b" Y: B8 B
    9 B* n7 ?" W9 F' S+ X0 I6 `
    所以要做的就是DB Check!!% Y0 x4 ~+ n  W8 I" e

      O) |& t! ?* v% ^% C) i
      t5 ]0 u" n3 S( X! {% x

    点评

    支持!: 5.0
    支持!: 5
      发表于 2013-10-24 23:39

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    3#
     楼主| 发表于 2011-5-19 16:41 | 只看该作者
    回复 flyingc381 的帖子
    4 D" c7 z  n% ^* C% L2 Q! p
    , F! r% h% e9 j8 \1 V' }! m2 a  }( {谢谢啊,确实可以5 ~* y7 k: |: S$ m
    不过这俩WARNING搞不太明白,能解释一下吗,谢谢
    8 B4 C: i- h( Y- M: x: {! J
    , J2 Y  S* U5 I2 M( V' v% O3 ~6 ^: Q <<WARNING:>> Net VCC3V3 is defined as a signal net and contains 118 pins.
    9 }7 k. O$ S  h1 I5 J# q; T# This is more pins than most signal nets contain.
    ) A- r! u) @) D  U# Please verify whether net VCC3V3 should be a signal net or a power net.
    ! o2 s% w; N, k* I7 T$ c# Note that a signal net will be routed as starburst or daisy chain.) s/ l( e5 r4 Q6 x2 u" ^) r) W6 A+ e
    -----------------------------------------------------------------6 _3 @( j/ Z- v  u# ^
    # <<WARNING:>> Net GND is defined as a signal net and contains 283 pins.
    $ Z* B* U1 `6 M4 N* ~# This is more pins than most signal nets contain.2 s, ?) \0 \( c9 P6 ]
    # Please verify whether net GND should be a signal net or a power net.
    6 \5 S* H0 ~$ ]6 i6 n% Z# Note that a signal net will be routed as starburst or daisy chain.9 j: e$ r5 z( ^# c
      {4 X0 G4 b" O, a- I

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    4#
    发表于 2011-5-21 19:45 | 只看该作者
    先看看,学习一下,
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