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5金币
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9 I) D f2 h( c# allegro PCB Router 6 @$ i+ f I0 T5 w- q! L
# Copyright 1990-2006 cadence Design Systems, Inc. All Rights Reserved.
& F+ g' I \/ q' l7 g i6 s, P% y# ===============================================================================* D% E! a. L' x7 M; L
#
: d! F/ \' D- a0 `( N+ G# Software licensed for sale by Cadence Design Systems, Inc.7 t6 [3 R; q9 o/ b
# Current time = Thu May 19 10:53:42 2011
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# Allegro PCB Router v16-3-85 made 2011/02/14 at 12:53:30
3 K0 k. C' H- d$ I7 J# Running on: pc-200201020345, OS Version: WindowsNT 5.1.2600, Architecture: Intel Pentium9 p4 d; s7 X* V" G; s
# Licensing: The program will not obey any unlicensed rules
( A% F4 q& p3 i, F* ^1 i# No graphics will be displayed.
- d+ [" M" r; \# r- C# Design Name F:/orcad/DSP/dsp board\dsp_xnet.dsn
" H! m! \# W' u) }- R3 R3 l. j% f# Batch File Name: pasde.do, y0 T C) e5 H
# Did File Name: F:/ORCAD/dsp/dsp board/specctra.did4 F' w% q4 ?$ R, c4 X9 D1 O
# Current time = Thu May 19 10:53:42 2011: A$ o) M* D: s. C+ B
# PCB F:/ORCAD/dsp/dsp board
' M( @# ]$ z$ l* e5 o( ~# Master Unit set up as: MIL 10002 q( P: h- _4 s0 R8 J9 o
# PCB Limits xlo=-4032.0000 ylo=-4032.0000 xhi=14032.0000 yhi=8032.00001 J1 m! N! O% n8 N
# Total 277 Images Consolidated.3 K9 ] F9 b- j) P, g0 z6 p0 g
# Via 'VIA100-50-120' z=1, 2 xlo=-19.6850 ylo=-19.6850 xhi= 19.6850 yhi= 19.68508 m& Z3 k+ Y) z' \. ~
# Via VIA60_35_95 z=1, 2 xlo=-11.8100 ylo=-11.8100 xhi= 11.8100 yhi= 11.8100$ t1 W( A, ], g
#
* r& A) f; b g% I* a0 C0 i# VIA TOP BOTTOM , [ Y5 q8 ]9 y
#
) z" u" s0 c, A. G# TOP ----------- VIA60_35_95
% \. U C% t0 y1 v: W# BOTTOM VIA60_35_95 ------------ b% i1 o( [7 n! e1 {* h
# 1 {1 V& E" X2 z* R! P
# <<WARNING:>> Net VCC3V3 is defined as a signal net and contains 118 pins.
! M2 d6 ?3 E4 N8 ?4 ?# v) x* N- I, z# This is more pins than most signal nets contain.
9 b! W& T% ~8 f* ]# Please verify whether net VCC3V3 should be a signal net or a power net.* W0 r/ [2 e& z/ j9 W- ?
# Note that a signal net will be routed as starburst or daisy chain.. Z$ f5 M, j) u* Y+ y
# <<WARNING:>> Net GND is defined as a signal net and contains 283 pins.
0 f/ W+ s& z, N* |$ U; s% V# This is more pins than most signal nets contain.
" L) v$ M$ u* ], Y- u* w# Please verify whether net GND should be a signal net or a power net.
; a# d4 b6 g8 C1 {4 M6 Y6 G# Note that a signal net will be routed as starburst or daisy chain.; Y2 \! j9 L. C7 G8 \; P# Q9 p
# <<ERROR:>> Error in file F:/ORCAD/dsp/dsp board\dsp_xnet.dsn, line 6226: token 5 = Orphan_net% E% u _. s, t" ]
# (content): (wire (net Orphan_net) (type route))
$ H. m1 ?& b9 c7 t% Q& b8 z; i# <<ERROR:>> Parser: Unrecognized token net while parsing shape* t8 o% `9 ^3 R
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报错的板子:
dsp_xnet.zip
(463.22 KB, 下载次数: 17)
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同一板子没设置约束前不报错:
dsp.zip
(398.35 KB, 下载次数: 6)
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我对VCC3V3和GND只设置了线宽,它怎么提示:defined as asignal net ?% d& @! }4 `! s; q
/ W# Q7 n- q/ V5 G$ a c4 h下面的错误能看明白字面意识,但不懂到底是怎么一回事
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# (content): (wire (net Orphan_net) (type route)):这一行它想提示什么?
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最佳答案
查看完整内容
很无聊,,所以帮楼主检验了一下
直接的确进不去
不过DB Check以后,,
可以进……
所以要做的就是DB Check!!
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