自动布线器不能启动

fjh

===============================================================================
1 |6 j) A  Y& b% A- E& s$ Y#                               allegro PCB Router                              
# Copyright 1990-2006 cadence Design Systems, Inc.  All Rights Reserved.
# ===============================================================================
#
9 Z5 R" z" S% p& u6 g# Software licensed for sale by Cadence Design Systems, Inc.
# Current time = Thu May 19 10:53:42 2011
#
# Allegro PCB Router v16-3-85 made 2011/02/14 at 12:53:30
# Running on: pc-200201020345, OS Version: WindowsNT 5.1.2600, Architecture: Intel Pentium
7 O# w8 B+ B# O* S' ^& Z" \# Licensing: The program will not obey any unlicensed rules
4 A2 A2 p+ y: q* q  [3 Q( o# No graphics will be displayed.
# Design Name F:/orcad/DSP/dsp board\dsp_xnet.dsn
# Batch File Name: pasde.do
# Did File Name: F:/ORCAD/dsp/dsp board/specctra.did
3 g& X# n& P3 c2 x8 N# Current time = Thu May 19 10:53:42 2011
4 t6 r/ E  U: R, r7 A2 }. H& p# PCB F:/ORCAD/dsp/dsp board
8 P. R) |% W  [7 n8 o, X: A) h! R2 _# Master Unit set up as: MIL 1000
# PCB Limits xlo=-4032.0000 ylo=-4032.0000 xhi=14032.0000 yhi=8032.0000
5 c6 c5 x. P( O8 ]2 U1 i# Total 277 Images Consolidated.
2 Y' z6 X) q; D! _6 B- L# Via 'VIA100-50-120' z=1, 2 xlo=-19.6850 ylo=-19.6850 xhi= 19.6850 yhi= 19.6850
# Via VIA60_35_95 z=1, 2 xlo=-11.8100 ylo=-11.8100 xhi= 11.8100 yhi= 11.8100
( A  d0 r& J3 `. C1 O; N#
6 w' @% p  s2 }' r" U& B7 F#    VIA       TOP       BOTTOM   
#
2 N2 Z2 ~6 U) ]: l: X#    TOP  -----------  VIA60_35_95
+ V. y9 }3 k9 B6 S" N: ~# BOTTOM  VIA60_35_95  -----------
#
# <<WARNING:>> Net VCC3V3 is defined as a signal net and contains 118 pins.
# This is more pins than most signal nets contain.
3 D. l) H: i% j- N9 i  O# Please verify whether net VCC3V3 should be a signal net or a power net.
5 A+ F9 ^# B+ w7 z+ J7 i* x' r# Note that a signal net will be routed as starburst or daisy chain.
% R- @# T- r8 {7 k# u# <<WARNING:>> Net GND is defined as a signal net and contains 283 pins.
# This is more pins than most signal nets contain.
6 C) q$ H0 J' a- W# Please verify whether net GND should be a signal net or a power net.
( P2 i/ P( |1 l' U+ j0 {. o7 v  u# Note that a signal net will be routed as starburst or daisy chain.
# <<ERROR:>> Error in file F:/ORCAD/dsp/dsp board\dsp_xnet.dsn, line 6226: token 5 = Orphan_net
2 {% A  p# K9 j9 R/ W; _# (content):   (wire (net Orphan_net) (type route))
# <<ERROR:>> Parser: Unrecognized token net while parsing shape
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报错的板子： dsp_xnet.zip (463.22 KB, 下载次数: 17)

2011-5-19 11:41 上传

点击文件名下载附件
下载积分: 威望 -5

同一板子没设置约束前不报错： dsp.zip (398.35 KB, 下载次数: 6)

2011-5-19 11:41 上传

点击文件名下载附件
下载积分: 威望 -5

* l, q% b+ V/ d# h3 @- @我对VCC3V3和GND只设置了线宽，它怎么提示：defined as asignal net ?

下面的错误能看明白字面意识，但不懂到底是怎么一回事
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6 m( ~0 X6 W) D8 k5 E! {2 n# (content):   (wire (net Orphan_net) (type route))：这一行它想提示什么？
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7 A+ W1 \7 p6 a& j% {8 k

zzlhappy

先看看，学习一下，

fjh

回复 flyingc381 的帖子

谢谢啊，确实可以
不过这俩WARNING搞不太明白，能解释一下吗，谢谢
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<<WARNING:>> Net VCC3V3 is defined as a signal net and contains 118 pins.
, |/ T9 ], E+ o, z3 j# n$ J# This is more pins than most signal nets contain.
# Please verify whether net VCC3V3 should be a signal net or a power net.
+ [. Q0 N' T* f8 N9 S) \% H* _# Note that a signal net will be routed as starburst or daisy chain.
-----------------------------------------------------------------
# <<WARNING:>> Net GND is defined as a signal net and contains 283 pins.
. N$ t, s; s4 y) J4 U# This is more pins than most signal nets contain.
$ j  h# b( y# K5 G4 t- U# Please verify whether net GND should be a signal net or a power net.
# Note that a signal net will be routed as starburst or daisy chain.
/ j0 S/ E9 i  w

flyingc381

很无聊，，所以帮楼主检验了一下
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4 I4 z9 W! O5 h7 J+ K: G- E直接的确进不去
# x+ X( c# z3 @$ ?; U
不过DB Check以后，，

可以进……

所以要做的就是DB Check！！


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