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DATE: 02-13-2015 HOTFIX VERSION: 043
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7 R: o+ d! y- |$ W! ZCCRID PRODUCT PRODUCTLEVEL2 TITLE
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1259909 ADW DSN_FLOW Unlike Project Manager, parts cannot be copied from one design to another using ADW" v! G. f( E: Z! _* Y
1341092 ALLEGRO_EDITOR MANUFACT Export > PDF should show drill holes if the Filled option is selected
* A R$ |9 ~6 Z8 N. F; N( _; h1356711 SPIF OTHER Unable to use PCB Router function with PA5700 license.' g4 Y* a1 u- Z' N7 U0 m
1357880 ALLEGRO_EDITOR INTERFACES Incorrect Step model view in Step Package mapping window
0 c+ E" x* `0 h1362132 ALLEGRO_EDITOR DATABASE X hatch shape with cell High shows shape boundary error
Z1 Z6 C9 r: B% h3 g# ^! p/ E% J1362641 ALLEGRO_EDITOR INTERACTIV Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference
5 Z ]. p3 u! R4 V) D8 N9 P4 G% Y1362771 ALLEGRO_EDITOR EDIT_ETCH Running AiDT displays an error; the tool crashes on subsequent runs+ s! W* J* i( ] ^8 E0 d! X) ^# |
1363908 SIP_LAYOUT PLACEMENT SiP Layout crashes when refreshing symbols8 h( H1 ]9 v( p2 s0 n" f( E
1364113 ALLEGRO_EDITOR MANUFACT NC drill output does not comply with NC Parameters if the unit is inconsistent
# c# f1 ]3 O. M, v- g% k6 @7 F1364146 PSPICE SIMULATOR Simulating the attached Design gives 'RPC Server is unavailable' Error.* t* u0 g% R. L) {: u7 {
1364209 ALLEGRO_EDITOR INTERFACES STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM% E- E. |7 n; d
1364329 CONCEPT_HDL CORE Show Physical Net Name causing netlisting errors
$ W( ^0 k# Y3 s+ V1364367 PCB_LIBRARIAN IMPORT_VIEWLOGIC viewlogic2con translator does not complete1 i" t3 |) \: t$ \4 V4 j0 F) l! ]" F
1364771 ALLEGRO_EDITOR MANUFACT Incorrect Gerber created for mounting holes4 N' y8 {/ N5 G# U( i
1366415 CONCEPT_HDL CORE global navigation not working for few buses in the design: s5 b* s0 J: I j" d* u
1367650 SIP_LAYOUT IC_IO_EDITING Add Respace command to Symed app mode for I/O drivers0 ]+ Y7 }0 p% y) i+ J- w' {
1368246 SIP_LAYOUT OTHER Cannot delete die(s) that were placed manually in a design
* k+ l" l# T( ?, u1 D- [1 V( O1368889 ALLEGRO_EDITOR INTERFACES Unable to export incremental updates of the IDX baseline file9 o$ Q8 Y9 g0 V( h' w0 _; w" x2 U% b
1369177 SIP_LAYOUT OTHER Add a new command to create a bounding shape4 D! \4 [7 b# i s' c, H. U
1 y% P; h( R! b5 \& {0 CDATE: 01-30-2015 HOTFIX VERSION: 042
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# h: ?, \# |9 X* _: q1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines
1 z2 P, j, Q: ~/ T1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run
1 F; u( `6 k6 i5 g2 N: N6 ]1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.5 J9 Q1 c' `+ S/ s% m/ p
1349849 CIS OTHER Capture crashes on generating variant reports: f9 D# ?3 S1 r+ I) C
1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec5 z0 u2 S# r; y! u4 O
1350477 PSPICE SIMULATOR RPC server is unavailable
9 u+ H* b+ J2 n$ z5 A7 B( I6 F1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash
3 s" K( C x9 ~5 o5 @2 D0 S1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property
9 M4 o. f2 {* |1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error.3 C8 W3 ?; M7 _* l( W
1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers! X$ S* q: Q$ Z5 Y6 t& l
1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase! C2 z2 M0 e) ~7 d' {3 u- K
1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs.
; |0 T! d) b) v& K5 k: M7 W1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to
+ U; S q& D) j* x$ ` C1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly6 Z5 s8 o) V0 I9 S; w) Y k% x
1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts., [. | u( P* [: |+ A# X
1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces.
7 j( C$ ~4 ]* I: Z( q% _. Y+ V1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design
% \6 E' a: t! L3 k1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor5 k5 b2 W1 m- F0 w
1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.! h8 S6 i# A S4 g
1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.
5 r$ }- B% k$ p) g3 |+ j/ y1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.+ g: u1 [8 F" q9 d& _, w9 P6 F$ V
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发表于 2015-2-15 23:37
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