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DATE: 02-13-2015 HOTFIX VERSION: 043' l- S" @$ }; c" B2 x$ {: }
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. |+ y% t' ~, p6 Q5 r, T: \CCRID PRODUCT PRODUCTLEVEL2 TITLE
! _5 {, N& L# W: H+ `9 \$ Q6 M===================================================================================================================================
( A* T6 d% d; {. `1259909 ADW DSN_FLOW Unlike Project Manager, parts cannot be copied from one design to another using ADW
8 c% s+ e/ A+ E+ h! Y V1341092 ALLEGRO_EDITOR MANUFACT Export > PDF should show drill holes if the Filled option is selected! W1 T% ^' h' D) T' v" d5 Z
1356711 SPIF OTHER Unable to use PCB Router function with PA5700 license.
7 [8 O7 Q; y7 j' y! l1357880 ALLEGRO_EDITOR INTERFACES Incorrect Step model view in Step Package mapping window
) o7 x! v" ]) e) H/ i0 J# F- t1362132 ALLEGRO_EDITOR DATABASE X hatch shape with cell High shows shape boundary error
1 u2 ^7 F1 K; F# C1362641 ALLEGRO_EDITOR INTERACTIV Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference
0 j: r; ]; w1 c- a( L1362771 ALLEGRO_EDITOR EDIT_ETCH Running AiDT displays an error; the tool crashes on subsequent runs
5 m. X, }& M# B! u% v- C: o+ C1363908 SIP_LAYOUT PLACEMENT SiP Layout crashes when refreshing symbols4 k% R3 O& u) Q* B0 V
1364113 ALLEGRO_EDITOR MANUFACT NC drill output does not comply with NC Parameters if the unit is inconsistent$ T% S/ F) n6 m, h- s
1364146 PSPICE SIMULATOR Simulating the attached Design gives 'RPC Server is unavailable' Error.
9 \/ X g) K# r0 a$ ], I1364209 ALLEGRO_EDITOR INTERFACES STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM
# U+ b5 \6 {4 j1364329 CONCEPT_HDL CORE Show Physical Net Name causing netlisting errors
/ T) |' x, B+ F1364367 PCB_LIBRARIAN IMPORT_VIEWLOGIC viewlogic2con translator does not complete
& y! m, ]* q7 Q( G4 ?3 \( t1364771 ALLEGRO_EDITOR MANUFACT Incorrect Gerber created for mounting holes
S; ]% c" q O) t# e1 L6 o1366415 CONCEPT_HDL CORE global navigation not working for few buses in the design% m: ]* I7 [2 K* L1 Z
1367650 SIP_LAYOUT IC_IO_EDITING Add Respace command to Symed app mode for I/O drivers
. D. y/ }+ k5 ] F5 Y: M; k0 ^1368246 SIP_LAYOUT OTHER Cannot delete die(s) that were placed manually in a design
% X4 n' u/ ]! Y/ n& _- W1368889 ALLEGRO_EDITOR INTERFACES Unable to export incremental updates of the IDX baseline file1 {& Z/ x7 R+ Y' {- _2 l
1369177 SIP_LAYOUT OTHER Add a new command to create a bounding shape! I& K, X! N, p3 b0 I, ~( p. D" k
6 @ {* ^% r" c4 k. sDATE: 01-30-2015 HOTFIX VERSION: 042
5 \& b c$ q: {# O. ]& A! I' C===================================================================================================================================
$ {6 z9 R J$ @( v+ n0 PCCRID PRODUCT PRODUCTLEVEL2 TITLE* }. Y" U8 \5 {2 I: F& \- s
===================================================================================================================================( N) v- \3 h! J
1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines6 f0 \. R ]; L4 O+ u9 H
1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run+ a7 s/ m# V6 @0 n
1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.
8 b) z) T( H6 B) T1349849 CIS OTHER Capture crashes on generating variant reports
+ j1 h( i+ l/ |3 ?$ z+ D3 y1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec
$ F9 a% |$ F/ H$ z0 ~" m5 M1350477 PSPICE SIMULATOR RPC server is unavailable# |# t5 T( r4 g* t7 d1 [+ C
1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash
1 u9 L* z) M6 c. U1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property2 G. D4 k. { M0 g- d& G, s$ t
1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error.
% X/ h1 [- F+ ? d% M5 k1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers
5 T- c: |8 I9 {: X$ r, Z- D' I& Z1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase
1 D6 ]; x( W% |) ]% K Z) r1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs.0 x7 H9 W( t1 [) a+ S+ x# l0 E
1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to
" G& S# u: C4 Z7 |1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly
: z8 P# a8 q6 K. M1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts.
9 @5 P9 W4 [+ z1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces.
$ v' [) P4 u }" G( s) k1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design
) j: d. f9 A9 Q9 [8 s" d8 C1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor$ E8 O$ L$ q" R* \
1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.+ ]* g2 q) s6 W+ |0 b; T
1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.. G7 [& K# y+ G1 V" O: c- q+ @
1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.
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发表于 2015-2-15 23:37
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