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下载：http://pan.baidu.com/s/1gdhBNzl8 [6 T+ Z; n$ s% |4 w3 k
. P( F& U4 w/ _7 d3 [ DATE: 05-01-2015 HOTFIX VERSION: 0020 |( X3 I) m4 x) o" m. u
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" m$ X5 o$ X1 B CCRID PRODUCT PRODUCTLEVEL2 TITLE e" K* a7 O3 P( \ J9 `9 n
===================================================================================================================================( k/ w8 \1 u3 `" H; G5 L
1315048 allegro_EDITOR INTERFACES IPC2581 translation inconsistency on negative layer
; X0 u( w8 S" ?6 [. L 1362745 CONSTRAINT_MGR OTHER Allegro PCB Editor crashes on opening Constraint Manager with any design# g+ a; D8 b v3 Z' j# N% S
1373412 ALLEGRO_EDITOR GRAPHICS SigXP Print Canvas : Via model seems to be filled by black Via box.
% R% j7 g# l6 O( j; ^) t6 q' P5 S 1376765 CONSTRAINT_MGR ANALYSIS SETUP/Hold spreadsheet lists only one pin pair
# A# f- ^7 b) L& t8 E 1399646 ASI_SI OTHER Should be able to run mbs2brd with SI/PI base licenses* M9 L" _7 a9 G. X2 Y! Y. ^
1400215 SIG_INTEGRITY REPORTS cross talk failure on certain nets in PCB SI 16.6
& u9 @$ Q, J$ i' f) r. a 1400302 ALLEGRO_EDITOR MANUFACT Copper Thieving is working differently in SPB16.6 as compared to SPB16.58 d: L$ d4 j- B y' |% b$ w, B
1400755 ALLEGRO_EDITOR SHAPE Updating the shapes on the ATTACHED deisgn causes a short to a pad.
6 O o( `: o# {- M" k! d( A& s 1400813 ALLEGRO_EDITOR SHAPE PCB Editor crashes when you delete islands from all the layers and save the board
" p9 p# S0 U% E4 P0 v) b$ E 1404174 SIP_LAYOUT OTHER Creating bounding shapes generates INCORRECT shapes and DRCs
* H3 Q" d9 X; s 1404184 ALLEGRO_EDITOR INTERFACES Step package mapping - Save is disabled for certain symbol
) p% T8 F9 F1 B: w 1406457 ALLEGRO_EDITOR SCRIPTS Unable to launch allegro.exe -orcad after update hotfix 046
# W5 \, b+ o+ M7 q3 A0 }! R 1407123 ALLEGRO_EDITOR OTHER Lines with zero line width are not being printed in PDF format
+ m8 Q! u& P: Z% d 1407483 ALLEGRO_EDITOR REFRESH The 'refresh symbol' command creates an unrouted connection in a fully routed design
6 O3 d3 ? r! T5 q S 1408072 SIP_LAYOUT OTHER Net assignment for a BGA component fails on running the File - Import - Netlist-in wizard command.3 x8 }( r8 l! T7 }
1410857 ALLEGRO_EDITOR DRC_CONSTR Diff Pair Uncoupled length DRC gives different results in SPB16.3, SPB16.5, and SPB16.6.
1 u3 ]# x h- p/ }/ w 1413235 ALLEGRO_EDITOR INTERACTIV Find by Query with Via Structures: GUI freeze3 H" p. k5 z8 e3 P- P
; }: v: y5 z% V. @3 v DATE: 04-03-2015 HOTFIX VERSION: 001
$ W# d* J' i2 e1 j( ?8 q' J ===================================================================================================================================! \" q& ]$ H1 w2 U
CCRID PRODUCT PRODUCTLEVEL2 TITLE
( L m4 A4 a$ B& M ===================================================================================================================================; {1 z- t' P* o" A; O% v) Z9 F
491042 concept_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute
) f, ~ Q( i/ I 1205900 ALLEGRO_EDITOR INTERACTIV additional object polygon-rectangle for "snap to pick"
# B& B* `! q) B+ ^ 1327533 SIP_LAYOUT REPORTS Metal Usage Report fails
2 S7 j+ `# f( B% Q$ ^9 q1 u$ f 1341177 ALLEGRO_EDITOR PLACEMENT "Place Replicate Unmatched Component Interface" window size should be increased to show "Matched Component": q6 i) c3 [# s3 x6 X0 z. ]' v/ e
1360269 SIP_LAYOUT REPORTS Getting incorrect results in the Metal Usage report of SiP Layout when the variable METAL_USAGE_REPORT_NOARCS is set
5 A2 n$ _9 r0 P& Y7 `: w% q" {1 F 1361281 ALLEGRO_EDITOR INTERACTIV Moving stacked vs non-stacked via's should be the same.
( n( t. _2 s7 h3 K M- `4 j6 {8 D1 F 1366525 ALLEGRO_EDITOR INTERACTIV Add replace via with via structure command to Allegro PCB, W9 \1 E: B1 w7 [/ h) q
1368091 ALLEGRO_EDITOR INTERACTIV Snap pick to fuction should see fiiled rectangle as a shape& X! L: a! \% q7 t0 O# ^
1371510 APD DATABASE How to show DRC when tack point of wirebond out of finger boundary
. x! n0 V2 `) C, d6 Q 1373564 ASI_PI GUI Impedance results are incorrect in PFE6 r7 r; O0 n. a' Q7 ?: ?- \3 O
1374703 ALLEGRO_EDITOR SHAPE Inconsistent behavior on shape voiding2 D7 K3 z. e( n3 m' e6 r
1376851 CONSTRAINT_MGR UI_FORMS CM workbooks change after simulating8 j- [8 `$ {* S# S0 f' I2 b: u
1377555 ALLEGRO_EDITOR DRC_CONSTR The "Line to SMD Pin Same Net Spacing" DRC toggles everytime we run "Force Update" of Dynamic Shapes.
; c& ^! D9 ?2 [! R4 G. v 1378032 ALLEGRO_EDITOR REPORTS Report command and batch mode give different Waived DRC Report results in PCB Editor
2 z+ V' k; Q* C! ~1 W4 q 1378611 ALLEGRO_EDITOR INTERFACES Enable STEP export to convert the mixed unit into one single unit
: ?8 V [, `$ V 1379240 APD PLACEMENT Placement gives error regarding the difference in units between the database and symbol, which is not the case
) U1 }/ Y9 l6 w4 f. t 1394908 ALLEGRO_EDITOR DATABASE Database crashes on doing "Show Element" on selected net! {+ c4 Q7 H; u6 B! u
1395541 ALLEGRO_EDITOR PLOTTING Export PDF not correct for Phantom lines9 @) }$ l7 {$ i. ^
1395747 CONSTRAINT_MGR INTERACTIV Rename refdes causes Allegro to crash. Possibly due to CM being open.
9 b6 K' O% w/ K" A: | 1396915 APD STREAM_IF The question about MIRROR geometry function from stream out
! |5 X( @. k$ p" v9 |$ o2 X 1398184 ALLEGRO_EDITOR MANUFACT Mismatch in backdrill data with IPC-2581 export |
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发表于 2015-5-7 02:28
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发表于 2015-5-8 11:30
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