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本帖最后由 zgyzgy 于 2015-7-22 23:17 编辑 , H1 `& `. O; y# `5 G4 E
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DATE: 07-16-2015 HOTFIX VERSION: 053
2 R3 q8 s+ Y+ l$ t1 |/ w===================================================================================================================================
( ~- @: J7 `* N% ] vCCRID PRODUCT PRODUCTLEVEL2 TITLE
% ?. c3 ~3 ?9 h' N# ~% ^===================================================================================================================================: x0 s2 ?5 }) O+ D
1045706 SIP_LAYOUT INTERACTIVE Enhance the Split Via command to be able to split a stacked via into multiple vias
( ?% y3 D' Z/ J+ u# E6 v8 ?1356381 allegro_EDITOR INTERFACE_DESIGN PCB Editor hangs when adding net to a net group
& W7 W: _ }# F/ J1416250 concept_HDL CORE Save hierarchy from TDO crashes DesignEntryHDL8 \) S: p" a3 b+ c* f" D) B5 S
1424166 ALLEGRO_EDITOR SHAPE Dynamic shapes will not fill using the zcopy command! P5 r4 z9 w5 v0 P
1424853 ALLEGRO_EDITOR INTERFACES Error message "Failed to add (LW)POLYLINE" when importing DXF file into PCB Editor q" g" C2 G( S( h, ?3 e( D
1426668 ALLEGRO_EDITOR DRC_CONSTR Require shape DRCs with route keepout
$ r6 T5 z9 V5 f: _. y1 G1427168 F2B DESIGNVARI Variant directives don't get created in CPM while creating variants; }9 K' N3 x1 q
1427481 PCB_LIBRARIAN IMPORT_TEXT To enhance the import txt file in the PDV! v6 g8 c7 K( k) m k9 x
1428336 PCB_LIBRARIAN CORE Symbol Pin Property Attributes not editable with HF49
; S( s( ?5 B$ J1430405 ALLEGRO_EDITOR MANUFACT Running Export - IPC-2581: The exported .xml data does not contain the Probe figures or the probe information
+ Q- ]! K& K* W1 `0 j1431570 PCB_LIBRARIAN VERIFICATION PDV con2con should read additional properties like NC_PINS from part_table view independant on PACK_TYPE
% V5 Y/ n" t7 }& H9 n4 B- [/ h$ a& t8 J1431591 ADW LRM LRM should be able to Autofix the parts with $PART_NUMBER even if the SYNC_PROPERTIES has a value of PART_NUMBER
$ W: F6 q7 r. d5 i1431875 APD EDIT_ETCH When trying to multi-route a group of nets, APD crashes with the .SAV error.
) ~7 J% I/ K/ m; e( u) ^3 D" k1 ]1434375 ALLEGRO_EDITOR INTERFACES Running Export - IPC-2581: The last or largest pin in a series of pins listed in pinOneCfg.txt is selected: i* O# T- m- N- z! @( G
1434975 ALLEGRO_EDITOR MANUFACT Running Testprep > Manual causes Allegro PCB Editor to crash
0 _' I9 U$ _" N) _% F( y/ `. E9 J1435685 F2B PACKAGERXL Export Physical indicates 36 errors are found during backannotation, but the backannotate.log file contains no errors
/ x' z& y5 o2 q2 R+ `& m, z1436206 SIP_LAYOUT ASSY_RULE_CHECK Ignore shapes autogenerated by the crosshatch void fill routine in the acute angle shape boundary ADRC check* G: V/ p- l" @7 R# |# N8 }
1436699 CONCEPT_HDL INTERFACE_DESIGN model assignment not working if signal_model exists within a block
$ W( h$ W3 k, b7 ~1436989 ALLEGRO_EDITOR OTHER PCB Editor crashes after pouring copper planes
0 b- b U! G, U2 p3 c1437150 APD DIE_GENERATOR Creating a die using the Compose from Geometry command gives error, "E-(SPMHA1-70): Pin is outside of the extents"! K. u" U% g4 |7 p$ Y& F
1437287 CONCEPT_HDL CHECKPLUS CheckPlus Segmentation Fault in LINUX' t% |9 }' Y: U! @
1437560 ALLEGRO_EDITOR OTHER APD crashes when running gloss with dielectric generation for the given testcase.
0 q' }% n2 m: r1437565 F2B DESIGNVARI Variant Hier BOM report puts Block DNI in wrong report section$ f0 @& M( t, k/ D# a3 Q8 m& p: h' a
1437725 APD EDIT_ETCH Route > Slide exhibits erratic behavior on differential pairs
9 L( G, l' J% K$ W1437748 SIP_LAYOUT INTERACTIVE Allegro Editor and APD have the command opengl report defined in the menu. Please add this to the SIP menu structure' q7 ?8 e( P& l6 z% ^7 p' i o
1438933 CONCEPT_HDL CONSTRAINT_MGR Model Defined Differential Objects are named differently
0 n0 s: q2 J3 D5 {9 h, \! }' L1439104 ASI_SI SPDIF SPDIF popup window7 p7 j2 d5 k2 F1 j* p% j
1439574 CONCEPT_HDL CORE How do you rotate groups of objects in windows mode?
& ~+ |( g" f m) y) o; |0 ]1440393 ALLEGRO_EDITOR INTERFACES Ability to extract STEP properties from DRA requested% [, ~# q* s; w* i O y
1440589 ALLEGRO_EDITOR DATABASE Edit - Change crashes the database with errors. W# }$ X: z& C. ~7 f9 i
1441665 CONCEPT_HDL CORE Property not annotated visible as set in ppt_optionset.dat: L1 c8 R- _! a1 [
1441672 SIP_LAYOUT ASSY_RULE_CHECK ADRC Hangs and does not close
7 `5 n; w; u( F6 l/ Z1441724 SIP_LAYOUT PLATING_BAR Need to be able to set the Plating Bar Width.
8 o$ D% B4 u; O9 t1442144 ALLEGRO_EDITOR SCRIPTS PCB Editor crashes when replaying script& ?: d" z. Q. K
1442798 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running dbdoctor
, H7 y% x7 s4 K% J Y1443693 ALLEGRO_EDITOR SCRIPTS Change Accelerator keys for new orcad shape Menu
1 _9 p* j( C5 f- q" F1443738 F2B DESIGNVARI Automatically exclude Nets or Ground Symbols from the Group while adding to Variant* R, |# ~# F' K, m; M
1444066 CONCEPT_HDL CORE Replace parts in variant view crash DEHDL if cpm library list contains nonexisting libraries.6 S8 g% |6 A: P
1444076 CONCEPT_HDL CORE Replacing parts in variants backannotates ALL injected properties in variant view1 N8 X2 O$ o9 b3 E E/ x
1444676 ALLEGRO_EDITOR SCRIPTS difference in PCB Editor and OrCAD PCB Editor menus in Hotfix 510 z+ F0 A& \) `6 i* s1 ]
2 p4 Y1 k% [+ f* ?( a下载链接：http://pan.baidu.com/s/1pJoUvtp2 k2 K) N# } T1 F; F1 u( x' C
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发表于 2015-7-22 23:15
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