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DATE: 07-31-2015 HOTFIX VERSION: 0543 K# y5 Z t- l8 d7 u
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694479 concept_HDL OTHER Need version control of symbols in DE-HDL
7 R) |3 [- m4 @695025 CONCEPT_HDL OTHER Version option of Add Component should filter mismatched versions
* `3 R2 n- c& G5 n$ K( ?1004049 CONCEPT_HDL OTHER Grouping of PACK_TYPE specific symbols by version in Version and Version List3 p' s7 t, m6 J: t
1357843 allegro_EDITOR PLACEMENT The net association of a via changes when a replicated circuit is placed using Place Replicate- |" _ ^# T. a5 L. |" f/ }
1367917 CONCEPT_HDL CORE The PIN_TEXT property of a symbol increases in size when rotated at 90, 180, or 270 degrees# _/ s2 w; P' K- Y4 \) O+ X
1405364 ALLEGRO_EDITOR EDIT_ETCH Slide Via snaps to the near by vias+ |0 A/ |1 U: `& _+ D' i& \" i4 K
1412635 APD DATABASE APD crashes on saving design' `/ a( a& h& f$ S! J4 Z4 d
1413214 FSP FPGA_SUPPORT Need spreadsheet rules to support FPGA devices2 D E0 L! g* B+ ^/ R/ u, r
1427732 SIG_INTEGRITY SIGNOISE Constraint Manager does not display results of Xtalk simulation
" y' ^1 B$ ~6 ]( g+ T" H% Z3 {1430416 ORBITIO OTHER Importing a .sip database to OrbitIO should also import the shapes.3 U; t% [2 i }* [+ L9 x
1435246 ALLEGRO_EDITOR SHAPE Shape shorts with signal net in artwork in SPB166 Hotfix 501 I0 J& N$ c. ~0 s& r" T! M7 V% f
1437479 CONCEPT_HDL PDF The Publish PDF form appears truncated when the screen display is set to "Medium - 125%"
8 [. h4 s) Y. G" n% S1438848 APD OTHER Layers of a module, mirrored using the Mirror Geometry command, change on refreshing the module
6 J( k* n1 s4 u8 n: T1 S8 e1439536 SCM IMPORTS On running Import Physical on a .sip file with a die abstract, wrong pin names are generated
) ~2 {' c: g8 n$ t; x; y* s1440332 ALLEGRO_EDITOR ARTWORK The oblong slot hole changes size in the IPC2581 output
7 C1 j. Z+ {7 m1441408 PCB_LIBRARIAN VERIFICATION About Release command could not read NC_PINS property in Part Classification
0 n! w: n) i8 ]1443224 CONCEPT_HDL CORE Rotated Text appears bigger in size compared to the normal text.
3 ?# V3 j! X) }! U5 f6 d1 e1444562 CONCEPT_HDL CORE Use of Synonym not shorting nets0 c$ O. R. ?' R$ I
1444932 ALLEGRO_EDITOR INTERFACES When exported to PDF, the octagonal pads in a padstack are larger than their size in Allegro PCB Editor9 |, Y. W, h2 h2 I" y
1445606 CONCEPT_HDL CORE Make the Component Revision Manager UI similar to LRM in ADW Flow! i2 p: ]% b- k4 y
1445925 ORBITIO ALLEGRO_SIP_IF Merge Update of a SiP File failed
5 P7 Y" N4 q7 i1446259 ALLEGRO_EDITOR INTERFACES Export PDF prints a big square box instead of a frectangle on the board
$ A, |7 n) F9 L) c) ?- p# {1446792 CONCEPT_HDL CORE BOM-HDL: How to output attributes attached to the instances of reuse blocks
) ^% R$ ?3 L( J" N$ n4 @7 {, o/ j1446866 ALLEGRO_EDITOR REPORTS IMPEDANCE_RULE values not being extracted in reports. H9 F# f( ?3 n& M4 |
1447863 FSP MODEL_EDITOR Ability to assign clock pin to QBC
+ y& Y0 c$ F& R1448802 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on routing across constraint region boundary
) a8 S8 Z) t# Y1 p: q1449255 ALLEGRO_EDITOR OTHER Edit > Change causes Allegro PCB Editor to crash.
h3 ^$ X9 ^5 t! B( s( ~1 y1450470 ALLEGRO_EDITOR EDIT_ETCH Return path vias: need provision to specify spacing value of less than 1/ v$ U( i1 P" C, j B& z: c$ A
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0 i0 o7 k& i4 |4 W4 {http://pan.baidu.com/s/1mg28zJM
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发表于 2015-8-3 11:54
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