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DATE: 07-31-2015 HOTFIX VERSION: 054
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6 ]. [9 T; [( g6 I! K. t @. v694479 concept_HDL OTHER Need version control of symbols in DE-HDL: `7 p+ B2 k8 y: a3 y
695025 CONCEPT_HDL OTHER Version option of Add Component should filter mismatched versions2 ]/ Z" P% p. c
1004049 CONCEPT_HDL OTHER Grouping of PACK_TYPE specific symbols by version in Version and Version List
/ Q6 z6 _ ~, d& |" q4 R8 W1357843 allegro_EDITOR PLACEMENT The net association of a via changes when a replicated circuit is placed using Place Replicate# ~0 ~0 E/ }) p& p. u0 s
1367917 CONCEPT_HDL CORE The PIN_TEXT property of a symbol increases in size when rotated at 90, 180, or 270 degrees3 w5 K, s) T0 D. ~
1405364 ALLEGRO_EDITOR EDIT_ETCH Slide Via snaps to the near by vias
* ~ @# h7 x; H1412635 APD DATABASE APD crashes on saving design
7 V) q, [* I( e' h7 j+ a, Y1413214 FSP FPGA_SUPPORT Need spreadsheet rules to support FPGA devices3 E9 `5 L0 g' `
1427732 SIG_INTEGRITY SIGNOISE Constraint Manager does not display results of Xtalk simulation* ?* X* Z; }- V9 m: d5 w9 ~' W" ]8 }
1430416 ORBITIO OTHER Importing a .sip database to OrbitIO should also import the shapes.' ~: e8 \% x" L [
1435246 ALLEGRO_EDITOR SHAPE Shape shorts with signal net in artwork in SPB166 Hotfix 50
! R }; X. k$ X* m9 w& b1437479 CONCEPT_HDL PDF The Publish PDF form appears truncated when the screen display is set to "Medium - 125%"4 |% i4 G) ~2 G0 d% b) M) _: r) s
1438848 APD OTHER Layers of a module, mirrored using the Mirror Geometry command, change on refreshing the module" ^/ e& s' w6 `
1439536 SCM IMPORTS On running Import Physical on a .sip file with a die abstract, wrong pin names are generated' l0 u0 Q, B+ L x( _6 g" c' h
1440332 ALLEGRO_EDITOR ARTWORK The oblong slot hole changes size in the IPC2581 output
" _( u" X# y8 r3 k9 H1441408 PCB_LIBRARIAN VERIFICATION About Release command could not read NC_PINS property in Part Classification
$ L0 {6 m! K+ K4 {' P2 B$ t9 ~1443224 CONCEPT_HDL CORE Rotated Text appears bigger in size compared to the normal text.
; X- `+ q/ K& k6 p1444562 CONCEPT_HDL CORE Use of Synonym not shorting nets
. A: f' N/ u3 _' h1444932 ALLEGRO_EDITOR INTERFACES When exported to PDF, the octagonal pads in a padstack are larger than their size in Allegro PCB Editor) P3 z8 l/ r( R2 Y* B+ H
1445606 CONCEPT_HDL CORE Make the Component Revision Manager UI similar to LRM in ADW Flow+ x* X8 r* @' d4 A4 r1 A
1445925 ORBITIO ALLEGRO_SIP_IF Merge Update of a SiP File failed
+ T( l7 I/ ^( L$ r8 i1446259 ALLEGRO_EDITOR INTERFACES Export PDF prints a big square box instead of a frectangle on the board9 Q9 ]" i/ k4 _. C: _, w
1446792 CONCEPT_HDL CORE BOM-HDL: How to output attributes attached to the instances of reuse blocks9 I- _ E) I* a& _/ x/ B
1446866 ALLEGRO_EDITOR REPORTS IMPEDANCE_RULE values not being extracted in reports0 u' J% a r0 P
1447863 FSP MODEL_EDITOR Ability to assign clock pin to QBC& E1 w' c/ `7 t
1448802 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on routing across constraint region boundary
2 ]. u5 T$ V# L: {6 O1449255 ALLEGRO_EDITOR OTHER Edit > Change causes Allegro PCB Editor to crash.
. I: Q' M0 h6 ?; s0 ]( `! M& n1450470 ALLEGRO_EDITOR EDIT_ETCH Return path vias: need provision to specify spacing value of less than 1* \# D8 x6 c. G4 e( T% H( w
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发表于 2015-8-3 11:54
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