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不方便截图,这是新找到的,是17.2的问题
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( j/ ~" d/ Z! q7 N2 q0 b. J1 z( ]! ~' H1.Close the design if it is open in Allegro PCB Editor.
, e+ s& D2 H/ L2.Add the CDS_XNET_STATE_UI variable with a value of 1 to the User variables section in the Environment Variables form.3 U: l( ~$ u X! r
3.Open the design in Allegro PCB Editor.
, j' D! p _: h# g4.Go to File > Import > Logic and, if not already set, set the Import Logic Type to Design Entry HDL.
! x) O. c0 K) `. Y& ?1 r/ k5.Open Constraint Manager.' Y8 w( Q) x$ M1 H1 r8 z9 S% \9 d) l" C: P
6.Select Tools > Options.
P5 C4 ~, g' w* U3 T0 @5 C7.Select the Create XNets and Differential Pairs using DML Models (same as SPB 16.6) option. |
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