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[ 已解决]在哪能看到各个补丁包的修改内容呢?有谁整理过了

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  • TA的每日心情
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    2022-5-6 15:29
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    [LV.5]常住居民I

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    发表于 2019-11-5 13:54 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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    本帖最后由 leilei4908 于 2019-11-8 16:15 编辑
      l' ?, t9 F! G/ r+ p0 y: z7 |
    5 T; m2 ^5 U' A* w% I5 J看到多数人发的补丁包都附有Fixed CCRs,也就是修改内容的介绍: x, Q" `# T; {- n. L! X: t
    这个具体在哪能看得到呢?
    0 V0 _8 F2 F1 I2 u6 D在本地有对应的文件吗?
    7 \* m, W. ]: _( W想知道17.2的029到060一共修改了哪些内容
    4 I! f" r2 H  N一个个去找,太麻烦了,还不一定找的全
    8 S. K" v9 X* |$ M7 \6 l* I& H, [8 j* j9 }( ]
    找到了,在
    9 d) a( W+ `4 ~* t%cdsroot%\README_CCR.txt: C3 {" f# E+ N/ l
  • TA的每日心情
    慵懒
    2023-6-20 15:22
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    [LV.1]初来乍到

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    发表于 2019-11-5 14:06 | 只看该作者
    Readme for SPB Release version 17.2
    4 H4 Q" i' {4 f" N( C3 `/ ^! a, a+ `6 n9 L% `& J; F
    Copyright (c) 2019 Cadence Design Systems, Inc.
    5 K( _% \3 I0 P$ X8 ^! {2 ]8 X" qAll rights reserved worldwide.' G) m- J  ]4 _0 a* R- H

    $ W- W  s* `- r9 R1 T& g  {7 [' C$ b. ?: U
    Fixed CCRs: SPB 17.2 HF060
    9 j( {" H; Q; p5 U& m10-11-20191 K, _+ `8 e7 I: v
    ========================================================================================================================================================
    3 G7 H9 y" {8 l, h; pCCRID   Product            ProductLevel2 Title
    ) u! x. K% N7 Y========================================================================================================================================================
    8 A/ r+ b8 I; v  J& ~4 s2 F3 F3 m7 [2137594 ADW                DBADMIN       EDM is not allowing to modify step model
    7 m; ]# o, j% x  r; Z% u2115805 ADW                DBEDITOR      'BOTH' in ALT_SYMBOLS prevents correct generation of part_table.ptf/ L' v2 }" z3 R) p% {5 N2 K% k( {
    2135452 ADW                DBEDITOR      DBEditor poor performance in high latency networks
    9 V& g+ F  i4 L( l* ~2 [2142315 ADW                LIBDISTRIBUTI EDM Library Server stops often and adwserver.out file is extremely large, more than 1GB
    8 ?( W( L4 {, m  g2155396 ALLEGRO_EDITOR     DATABASE      Netlist error when importing from Capture CIS
    0 s6 a) m  M1 ^; t8 e6 c, ]2118231 ALLEGRO_EDITOR     DRC_CONSTR    Crash during DRC: DBDoctor exits with error 'Illegal database pointer encountered'+ G1 B( Q1 c0 e( B3 x
    2150923 ALLEGRO_EDITOR     DRC_CONSTR    Via at SMD fit DRC not detected with rounded rectangle pads
    0 g$ V2 Y$ B/ n) N# P( M2140441 ALLEGRO_EDITOR     EDIT_ETCH     Drill hole to line DRC while sliding but 'Allow DRC' is not selected in the Options tab5 g% I6 O, C9 R# h3 R
    2141329 ALLEGRO_EDITOR     INTERFACE_DES Error message (SPMHSY-49) displayed on running 'Tools' - 'Database Check'+ e# O1 C4 _$ f7 S/ r- s% Y6 y
    2126562 ALLEGRO_EDITOR     MODULES       Create Module File / Place replicate assigns incorrect netname
    - m/ B" g3 f# @  z2150410 ALLEGRO_EDITOR     SCHEM_FTB     netrev.lst is created in the wrong folder
    7 y/ o& W& D: K3 \, T6 ]0 T2136158 ALLEGRO_EDITOR     STEP          Update STEP Mapping Data Only should be seperate Menu/Command.
    1 p8 F7 A# W1 j; E: \2137801 APD                VIA_STRUCTURE High speed via structure instance not adding properly
    6 {( f/ C2 n  {& p2145072 CONCEPT_HDL        CORE          Error on choosing 'Enable Hierarchical Variant'8 p2 r- A2 E, s7 T  @
    2124843 PCB_LIBRARIAN      CORE          Prompt displayed for license choice marked to be used as default: g) e4 y& n9 N9 o
    2141656 PCB_LIBRARIAN      CORE          Part Developer pop-up option 'Edit' for symbols displays an error message
    . [8 W& h- {6 J* s/ H$ i2125794 PCB_LIBRARIAN      SYMBOL_EDITOR Part Developer new Symbol Editor: cannot move inverted pins that contain circle and dot
    4 p. G* u9 Y* \/ ^+ b5 R2161864 PULSE              R2PLM         Second publish with CPM-derived item number and cadName set to $NUMBER causes 'an item is not unique' error
    0 k  K2 y# K. F1 ?& m' Q, r1997911 SIP_LAYOUT         ORBITIO_IF    Support keepout translation between OrbitIO and Allegro layout/physical editors
    4 T7 [& D7 r8 |/ d/ G+ X7 U8 s! R/ R
    1 p' |) o1 `4 i/ Z# x; |$ t- a8 u  P, V; y% C
    Fixed CCRs: SPB 17.2 HF059
    7 y, m" V: c1 `8 t! d0 o09-13-20191 y: v/ {. ], `. {; E' N% _' \
    ========================================================================================================================================================. i6 G% W% V+ I- p5 g, H+ S
    CCRID   Product            ProductLevel2 Title5 `6 r$ _" B- c2 h: S
    ========================================================================================================================================================
    ) y  E/ t, E, w3 i* r2112454 ADW                DBEDITOR      Icons in DBEditor do not start applications after renaming a model
    ! [: T& P. P; z* Q. H1 M6 r2120548 ADW                LIBIMPORT     Missing alternate footprints from vault area after library import.  B5 f8 Z- c3 |/ I+ E/ l
    2143314 ADW                PART_BROWSER  Component Browser does not start after installing HotFix 057 of release 17.2-2016+ B! v, u, O  f; a* E
    2122302 ALLEGRO_EDITOR     ARTWORK       Coverlay details not being output to Artwork data as per the visibility
    ; H. k' {' ]: c% C3 U! H3 W2135521 ALLEGRO_EDITOR     ARTWORK       Artwork dimensions do not match Allegro PCB Editor
    + ]% E* B6 Q2 M2054584 ALLEGRO_EDITOR     DATABASE      Through hole mechanical pin in zone area without Soldermask Top still shows a pad on Soldermask Top
    # M" w# D! t6 n4 ^3 B2111444 ALLEGRO_EDITOR     DATABASE      No soldermask for mechanical holes within zone+ n% z5 O5 N+ m! w
    2115596 ALLEGRO_EDITOR     DATABASE      Unused Pad Suppression removes pin connected to shape using Net_short property  g( l4 C7 _- x$ u$ X! u. c
    2135436 ALLEGRO_EDITOR     EDIT_ETCH     Allegro PCB Editor crashes when routing with VOID_SAME_NET property on cline
    & M: @2 E( \3 [8 j8 e& Y) i9 @1825020 ALLEGRO_EDITOR     INTERACTIV    GUI ( Quickplace ) not adjusted to current resolution, b6 h: Y# P! X: p7 a- j$ Y4 ]$ ^
    1949705 ALLEGRO_EDITOR     INTERACTIV    Quickplace GUI not adjusted to lower resolution
    6 w( E) L. L1 u4 k+ B; b% N2023090 ALLEGRO_EDITOR     INTERACTIV    Dialog boxes do not fit vertically on the screen& H4 c# I/ ^" \. n( ~) H; k
    2109940 ALLEGRO_EDITOR     INTERACTIV    Quickplace pop-up window does not fit vertically on the screen
    3 r! [( U' g# V$ s8 d5 m; S2136823 ALLEGRO_EDITOR     INTERACTIV    Cannot resize or move dialog box to access buttons/ l! `7 T4 Q5 E: G
    2116748 ALLEGRO_EDITOR     IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets
    ! X4 u9 d$ k% Z- T2138977 ALLEGRO_EDITOR     IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to HotFix 057
    8 h+ d; \' ^+ [0 p# n2132628 ALLEGRO_EDITOR     NC            Improve the User Preference description for BACKDRILL_OVERSIZE_OPTION
    1 c. C# ~$ q4 a) ]1 p2152244 ALLEGRO_EDITOR     SCHEM_FTB     Netrev.lst is written in the package folder
    : ?6 K" e9 q% \$ P1 ]2152493 ALLEGRO_EDITOR     SCHEM_FTB     netrev.lst is not created in the correct folder - error displayed for neltist import
    6 U+ ~# }) I6 t( O& [! A1 O8 n2104559 ALLEGRO_EDITOR     SHAPE         PCB Editor crashes while performing shape operation 'andnot'9 C1 q. c! R$ h4 r
    2108207 ALLEGRO_EDITOR     SHAPE         No Void Overlap option is not working in AMB( a+ U! o7 O; l8 m8 f' u
    2125571 ALLEGRO_EDITOR     SHAPE         Allegro PCB Editor crashes for a RAVEL rule
    9 ?, f, U9 _5 A* k( ?  i) p. K4 t2140707 ALLEGRO_EDITOR     SHAPE         Allegro PCB Editor crashes on creating dynamic shape
    % A& g- o) y7 n6 C* d; u  w2078434 ALLEGRO_PROD_TOOLB CORE          Shield Router - cline end caps treated differently than cline-segment end caps
    4 b! l$ l" g! f) _# c, w: a2101020 ALLEGRO_PROD_TOOLB CORE          Productivity Toolbox Z-DRC with multiple net classes: script selects only the last two classes in a group
    $ C& a, ]% H+ u+ d7 K2029279 CAPTURE            SCHEMATICS    Slow response when selecting parts in schematic* X0 P4 f  @: x7 Z; e6 Q
    2039931 CAPTURE            SCHEMATICS    Slowness in OrCAD Capture when ITC is enabled% I1 {% h, B' ]$ h! ]4 R4 t1 `
    2106942 CAPTURE            SCHEMATICS    Inter-tool communication needs to be disabled to resolve the lag issues in Capture
    ; u/ ?% U. {6 X6 V; j  P( k% h$ }: o2131683 RF_PCB             ROUTING       PCB Editor stops responding on using RF - Add Connect
    9 N  g9 _3 h( v1 {2126505 SCM                OTHER         Thevenin Termination dialog displays resistors incorrectly
    0 @5 ~! h/ v8 C$ l2102383 SIP_LAYOUT         WLP           Advanced WLP Non-standard fillets not working properly: fillets not added* R+ o5 f& M' h0 M5 q8 c" y( x: T
    6 p/ T( _- g' i+ g+ m- L5 r9 g/ P3 o# H

    " @. P. Q, d5 y8 h+ V' t% C7 f* lFixed CCRs: SPB 17.2 HF058
    # a" ]! ~: t# l5 A( G5 z9 |; X08-16-2019
    . Q0 g$ y- [7 n9 G7 W" Q========================================================================================================================================================
    % y' t% K: K5 r  x" [CCRID   Product            ProductLevel2 Title, {; _& P9 s% C: j& K
    ========================================================================================================================================================/ ^: j$ Y7 D8 z  T# b* T3 K4 U. N6 L
    2113265 ADW                LIBDISTRIBUTI Various DB operations take too long, rebooting server seems to fix the problem7 f( O  X1 b/ U& A$ s) I3 ~
    2122941 ADW                LIBDISTRIBUTI Lib_dist execution taking too long to run, Capture CIS DBC File appears to be taking the most of the time, E$ ]! T; @, R. S' p3 P/ i  o
    2127319 ADW                LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250)- B( _9 S9 D5 c6 L  q& P: l
    2107578 ALLEGRO_EDITOR     3D_CANVAS     Allegro 3D Canvas shows split layer5 L3 n0 c2 o, n5 Q2 r
    2099538 ALLEGRO_EDITOR     EDIT_ETCH     'Glossing - Via Eliminate' shifts traces to another layer
    ; O4 v' g  n( E* k2031883 ALLEGRO_EDITOR     INTERACTIV    Sub-Drawing: clipboard origin point is not set correctly
    ' ~# `% L+ j$ L6 W7 ]/ N2100433 ALLEGRO_EDITOR     INTERACTIV    Pad Edit displays error for extents (SPMHA1-69) if pads are at 90 or 270 degrees" J" Y7 G' {7 g8 q* p" V% w1 \
    2127239 ALLEGRO_EDITOR     INTERACTIV    Exporting a query result changes the working directory
    & E- Y) J4 S9 K( g! M% K. l2117160 ALLEGRO_EDITOR     MCAD_COLLAB   Error encountered when importing IDX file into MCAD tool in HotFix 056
    2 O; S" \0 y8 r2117427 ALLEGRO_EDITOR     MCAD_COLLAB   IDX files exported from HotFix 056 cannot be read in MCAD tool (the same files from HotFix 055 can be read)% t2 M$ m3 p1 [; U% v3 N4 j0 Y
    2117839 ALLEGRO_EDITOR     MCAD_COLLAB   IDX file created from release 17.2-2016 with Hotfix 056 is not readable in MCAD tools- q. G! l* C& v& @1 o
    2118019 ALLEGRO_EDITOR     MCAD_COLLAB   Export IDX is not working in Hotfix 056 but working in HotFix 055
    0 c) V' Q1 Q+ Y2106425 ALLEGRO_EDITOR     NC            Disable undersize regular pad and oversize soldermask pad for start layers' m$ J' z  Z( `, w0 s& ]
    2126766 ALLEGRO_EDITOR     REPORTS       Cannot generate reports and export ODB on board: S, y5 K2 u* E/ f0 Q2 V
    2107849 ALLEGRO_EDITOR     SHAPE         PCB Editor stops responding on updating shapes& |3 s& E* ?1 E1 k. G( N. L
    1778109 ALLEGRO_EDITOR     UI_GENERAL    Constraint Manager exits on doing 'Undo' in PCB Editor1 V7 g- X. G; v; s' M
    2064092 ALLEGRO_EDITOR     UI_GENERAL    Allegro Constraint Manager closes on clicking Undo in the layout editor  K: E7 c8 D* ~6 g+ k7 D- S
    2093341 ALLEGRO_EDITOR     UI_GENERAL    Show Element incorrectly displays in report window on a single line if an HTML Report is open when show element runs
    : W; Y% n1 f: C. s1 z2110909 CONSTRAINT_MGR     UI_FORMS      Cannot type dot (.) in DFA Table of Package to Package Spacing in DFA of Constraint Manager.
    ; y7 U2 E+ ?  E' g; x2096846 INSTALLATION       ADW           Component Browser does not open if adwservice.exe is not added to the Windows firewall exception list
    + m- X" ?/ f* F$ M9 k  y2128118 INSTALLATION       ADW           Unable to connect to Component Browser.
    + f& i( t9 ]0 C1 ~' q+ [' h2116749 PCB_LIBRARIAN      OTHER         Cannot open Part Developer with a Venture PCB license (PA3810)" i' r0 }" o* ?' p& _, W2 [
    2115302 SIP_LAYOUT         IMPORT_DATA   Performance issues with die text in and pin use codes, function utcle pwrgnd
    / G+ P" B) X( }0 v2103784 SIP_LAYOUT         MULTI_USER    Symphony Server rejects the move void commands on a specific shape instance
    * X0 V+ J, l- D: H2096239 SIP_LAYOUT         STREAM_IF     Database fails to create stream out file6 |4 b" g7 r3 T* P5 t
    2117572 SYSTEM_CAPTURE     EXPORT_PCB    System Capture crashes with multiple Export to PCB Layout# Q( Q, \3 V  A$ t/ ?: I3 Z* N

    - `* [: j, V" ~# q- N) i  \" o0 |* R" B8 r; l
    Fixed CCRs: SPB 17.2 HF057
    6 S7 e. `% u+ L) P6 T& @1 a. n, l4 w07-19-2019! O) J2 `" X1 j) q' Z
    ========================================================================================================================================================
    ! z( y' _  }9 ~. ZCCRID   Product            ProductLevel2 Title* k! W: c  y! W8 M+ X# v0 m7 t
    ========================================================================================================================================================" B- @# ^# J8 v+ T
    1920958 ADW                ADWSERVER     Designer server will not start due to corrupt inr file
    : U' Y+ N: I4 G8 e, D4 N: c) x; D2039243 ADW                LIBIMPORT     libimport ignores footprints generated by Library Creator due to changes of attribute names0 ]  C5 F. R+ k+ u+ O1 n; P; L6 ~
    2113226 ADW                PART_MANAGER  System Capture stops responding while importing DE-HDL sheets# q5 S6 b" V( Q7 |7 _+ W
    2035942 ALLEGRO_EDITOR     ARTWORK       'Create Artwork' is slow when all films are selected: C$ W9 L+ P) z4 c* X& z
    2096958 ALLEGRO_EDITOR     DFA           Cannot launch Constraint Manager after assigning CSet and closing% m9 L( x. g4 V! V. z: T& B& U. Y) i
    2087181 ALLEGRO_EDITOR     DFM           DFM reporting false positive hole to hole with stacked microvias! Y' K4 v5 n0 T2 z. j  ?
    2099400 ALLEGRO_EDITOR     DFM           Placing a mechanical pin on a cutout causes PCB Editor to crash
    4 d9 D- l6 {$ g5 p4 B% s2067214 ALLEGRO_EDITOR     DRC_CONSTR    Constraint Manager crashes for design linked board
    , O* V$ _/ y; A, p2097464 ALLEGRO_EDITOR     MULTI_USER    Design data lost if network connection drops in Symphony
    ( i6 U# w8 C6 o* t2108211 ALLEGRO_EDITOR     MULTI_USER    Error: Update #1 (Perm shape) was rejected by server4 q- Z0 ~/ t' ~" |: d; O$ t* Y
    2117154 ALLEGRO_EDITOR     MULTI_USER    Error message needed for Symphony  for client disconnections+ I, y( b. t$ {
    2100149 ALLEGRO_EDITOR     REPORTS       Error message (SPMHDX-9) for too many field names while generating dangling via report* `# z& l2 K1 |, u7 }; X
    2101932 ALLEGRO_EDITOR     REPORTS       PCB Editor internal error (SPMHDX-9) for too many field names when running BOM report% ]: z8 T6 ~9 @8 k+ H# f, a
    2111449 ALLEGRO_EDITOR     SYMBOL        'Layout - Renumber' results in error6 a$ B6 D9 o! H& n1 E8 |0 B
    2102177 ALLEGRO_EDITOR     UI_GENERAL    axlDMBrowsePath returns incomplete information
    ( B8 ~! k; b( P2105342 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor stops responding for 'Show Element - Find - Symbol Type' on a particular board
    + d" S/ ?8 U' F0 y2085443 APD                ARTWORK       Gerber lacks precision required to void some vias for a design in artwork output: need warning2 E3 q. v) h, W( _; ~3 {
    2080118 CONCEPT_HDL        CORE          Getting error after adding offpage to bus and assigning a new value to $sig_name
    5 z/ r) `) Z6 D2099438 CONCEPT_HDL        CORE          Genview allows dragging group of signals in split symbol distribution form( m; a3 e1 e  G) G) b1 x- }
    2108289 CONCEPT_HDL        CORE          Variant data is not in sync with the packaged data# s5 X# V& L& H( P# T5 P( ?) d/ O
    2087217 CONCEPT_HDL        OTHER         Variant back annotation will not work if there is a double quote (") in the description field of a part
    1 s0 C% {. D0 }* w2 p+ Y2107430 CONCEPT_HDL        PAGE_MGMT     Insert page is not working
    . ^2 {) K; c. J2063875 CONSTRAINT_MGR     OTHER         PCB Editor crashes on deleting match group without closing Constraint Manager4 x, s' j5 G  U3 s4 n$ d
    2103729 F2B                DESIGNVARI    Cannot enable hierarchical variants for block
    & S; g7 N9 \9 o& y2099076 F2B                PACKAGERXL    Package fails for 'Save Hierarchy', but succeeds for 'Save'* b/ y$ }0 _2 G2 x* ^7 b
    2081132 INSTALLATION       SPB           Part Information Manager cannot connect to EDM server after upgrading to HotFix 053/ W6 [& W0 X8 ?( [" ]/ h( s
    1599964 PSPICE             ENVIRONMENT   Version Info displays 'OrCAD Version Viewer MFC Application has stopped working'
    ! o+ M0 p5 u4 f- i" w% w2045497 PSPICE             SIMULATOR     'Illegal Parameter Value in File' error when loading Monte Carlo parameter file/ g3 J. T4 E6 |: }4 _
    2025997 SCM                TABLE         Copy-Paste Broken in Physical View! q) |4 w! l' w& v! m  P. h
    2102652 SCM                TABLE         Unable to copy the Associated Components Ref Des values to Excel
    : ?8 b: [! t+ i: a7 V2 r2054225 SIG_INTEGRITY      SIGNOISE      Cross Section Editor bug after changing the impedance value in Analyze - Preferences
    * J5 Y2 h1 x) h; S6 Q% `# e7 i2100075 SIP_LAYOUT         DIE_ABSTRACT_ Refresh co-design die running slow
    2 _4 G% H2 `, h" e/ E2106312 SIP_LAYOUT         DIE_ABSTRACT_ Die abstract I/F to bring into SiP Layout and OrbitIO power/ground and signals not designated as RDL  V5 V! Q7 Z" V' R  V4 d/ |
    2106314 SIP_LAYOUT         INTERACTIVE   Large design causing severe lag in Windows Server machine7 {+ C, [8 J$ A. ?
    2101622 SIP_LAYOUT         MULTI_USER    Symphony Server rejects the slide commands when tapered trace option is on
    & O8 p% t7 U. {+ E' s2107897 SIP_LAYOUT         WIREBOND      Design stops responding when running Wire Bond Auto Spread in HotFix 055
    8 v; }3 R  J; |& S+ w0 D8 A# @2104885 SIP_LAYOUT         WLP           Advanced WLP: Metal Density Scan, scan area in report is incorrect
    * H+ ~6 _' V+ \) }2 s) |
      ~! K: b4 u' O0 D) s
    : s7 R/ p! ~( R/ _0 O+ w! ^Fixed CCRs: SPB 17.2 HF056
    2 ^; P- Z9 R4 Z! S) q8 y06-21-20191 E2 E$ K2 B8 @
    ========================================================================================================================================================/ u. z" x  I7 q  e& ~9 ^! v# f
    CCRID   Product            ProductLevel2 Title
    % O, f5 @0 o& C' j========================================================================================================================================================& t5 V9 e% }5 Y
    2086463 ADW                PART_MANAGER  System Capture cannot add components when accessing remote machine via Citrix4 P) ^# s7 X8 Y4 n- B
    2092868 ADW                PART_MANAGER  Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not to flow from pstchip" B3 [8 X- \5 u  }0 ~# B* r5 V3 O
    2092872 ADW                PART_MANAGER  Import DE-HDL Sheets stops responding
    ; ^4 \& u" [1 r) E0 V  V7 n2088975 ALLEGRO_EDITOR     3D_CANVAS     Bending in 3D Canvas causes PCB Editor to crash1 Z$ t* R2 H- M5 [5 ?8 O4 P9 P
    2088577 ALLEGRO_EDITOR     COLOR         Export color nets does not write all the nets in param file; G3 U. W+ q  `$ g8 }
    2028867 ALLEGRO_EDITOR     DFM           False DFF Trace to Thru via pad spacing DRC0 I+ z/ z% C: n" b
    2037361 ALLEGRO_EDITOR     DFM           Soldermask features drawn with a line do not DRC to pin, via, or shape soldermask features. E& M- ~8 ], z) o
    2077913 ALLEGRO_EDITOR     DRC_CONSTR    When running a simple SKILL command, the tool will run for a very long time
    + q* H2 {3 z! |+ m2079642 ALLEGRO_EDITOR     DXF           Drill symbols are rotated in exported DXF in release 17.2-2016
    / W4 e+ \! H/ h; Z8 ^$ i2083493 ALLEGRO_EDITOR     MANUFACT      Manufacture - Cross section chart is not readable for rigid-flex designs
    1 y9 u( k7 b" I- ?( O' B( x7 l2073607 ALLEGRO_EDITOR     MCAD_COLLAB   IDX_IN batch program to allow a batch update of an .idx file( ?9 y& K! ~: M$ k" b( m
    2095632 ALLEGRO_EDITOR     MULTI_USER    Design server on Symphony stops responding and cannot be closed or downloaded0 U6 W) A- ]2 m  Z
    2098221 ALLEGRO_EDITOR     MULTI_USER    Symphony Server Manager allows connection to databases deleted from the project area
    : `9 N/ C) x. j% O" I2087315 ALLEGRO_EDITOR     NC            Backdrill exclusions raised on pins of a component$ J# b9 k: ]) O+ N. f- C+ c
    1947929 ALLEGRO_EDITOR     OTHER         The 'show measure' function crashes when measuring pin to pin distance! ?- F2 G5 }7 g; R/ R
    2091932 ALLEGRO_EDITOR     OTHER         Unsupported Prototypes command missing for the OrCAD licenses
    - t% X& b3 T& U( ]$ e+ i2 J2089470 ALLEGRO_EDITOR     REPORTS       Summary report shows the exclamation character (!) in the middle of numbers and words- X, W* U6 k1 h0 D7 G- B3 j$ R* h
    2067324 ALLEGRO_EDITOR     SHAPE         Netin crash during third-party Netlist import
    ) Q0 A! V9 |* h- k) t7 s2075191 ALLEGRO_EDITOR     SHAPE         Delete islands in the design: update out of date shapes and Database Check
    & R5 M3 B7 m; O" Z) D2090604 ALLEGRO_EDITOR     UI_FORMS      Undo/Redo UI grayed out when invoking Color192
    - _) n, Z3 y2 W; N# L3 p' W2043825 ALLEGRO_EDITOR     UI_GENERAL    Custom toolbar settings are not retained upon restart of Allegro PCB Designer
    " k8 i$ T/ K3 Y2090185 ALLEGRO_EDITOR     UI_GENERAL    UI setting in INI file not retained
    ( s, }- k' D" E, g- s+ `2090517 ALLEGRO_EDITOR     UI_GENERAL    Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane2 p2 p" P% }. K" n5 X7 o1 L
    2092436 ALLEGRO_EDITOR     UI_GENERAL    RefDes length of input string for Modify Design Padstack is limited to 20 characters
    - W/ u" d. A* w. J3 @6 j* z2099070 ALLEGRO_EDITOR     UI_GENERAL    UI setting not working properly, Icons missing after restart.
    . [) g% p4 K; i+ q$ m2088484 APD                DATABASE      Some objects (Vias and Cline) cannot be modified (edit, delete and slide) in the mcm database$ B# _6 h& h- o) S6 E9 A$ ]
    1951623 APD                DEGASSING     Shape Degassing fails with specific Void to Shape boundary value4 \& v2 _$ r+ J! L2 y7 n
    2081363 APD                DEGASSING     Cannot degas for specific shape4 n  F; v" b  z" |+ T
    2083498 APD                WIREBOND      Cannot wire bond from a diepad to another diepad on the same component
    ) F; O! y) U* O' H/ i# ~2086589 CAPTURE            NETLIST_ALLEG The generate the CM enabled files from the command line using pstswp.exe.
    % {6 K7 t; I, u' o2098248 CAPTURE            NEW_SYM_EDITO Ignore pin is not working for individual pins in Edit pin spreadsheet when edited for all pins
    1 K9 F1 m2 p9 Q0 B, a: {+ A) Y1773047 CIS                PART_MANAGER  Pin numbers and names for DNI parts will get disappeared in variant view mode if they are relocated in part editor" V# H% v* ~0 g5 y* T
    2003818 CIS                PART_MANAGER  Pin name and number of 'do not stuff' parts are not visible in the View variant mode) w9 l: N; h. H* r+ k3 j' i
    2076265 CIS                PART_MANAGER  Variant view pinnr/pinname disappears
    . V5 a9 F/ I! Z7 ?2 t. K3 _2076282 CIS                PART_MANAGER  View variant does not show pinnr and pinname$ C  p: V8 F6 |0 z" G1 n( V
    2083394 CIS                PART_MANAGER  No pin names and numbers on variant view for specific parts
      P0 k. v; e- C3 d. O2090027 CONCEPT_HDL        CORE          Cut and move of split hierarchical symbol to another page results in error due to lock or write permission issues: E1 `6 z! H# N& D
    2071355 ORBITIO            ALLEGRO_SIP_I Dummy nets creation in die after performing Merge Updated SiP
    : _5 q8 a" F" a$ j2067703 PCB_LIBRARIAN      OTHER         PDV crashes immediately for vector pins if MSB is lower than LSB
    ( A8 c3 g2 ^: A- @% l# P9 n6 v& a& M2041348 PCB_LIBRARIAN      SYMBOL_EDITOR Grid setting change cannot be saved in new Symbol Editor) o& q% M8 d; {6 D2 f
    2041365 PCB_LIBRARIAN      SYMBOL_EDITOR Improve copy drawing objects in new Symbol Editor
    1 Z- Y9 V' K- H# P; i& e, T/ r2067931 PCB_LIBRARIAN      SYMBOL_EDITOR New symbol editor grid issue: documentation grid spacing value changes4 i6 g' i& `: e* V0 e' Q
    2093849 PCB_LIBRARIAN      SYMBOL_EDITOR Symbol font text and appearance different when placed in Schematics
    : o0 K* ?5 Z' p: v1919298 PSPICE             FRONTENDPLUGI Capture crashes on archiving project) g0 U' I4 z/ U2 e* d& c
    1953001 PSPICE             FRONTENDPLUGI Archive project causes Capture crash.
    ) D9 n1 g$ z8 q! X  {7 P) A2035572 PSPICE             FRONTENDPLUGI Crash on archiving project/ x  V8 _$ j! u' |# K
    2041286 PSPICE             FRONTENDPLUGI Archive project crashes when using lib as global./ Q) |0 k" X8 K
    2081796 PSPICE             FRONTENDPLUGI 'Archive Project' crashes Capture in release 17.2-2016, HotFix 0539 h! y( F- X: b1 B; G: x8 |
    2106017 PSPICE             FRONTENDPLUGI Capture crashes when archiving PSpice-enabled project" i, o  `  Z. h4 A2 s( m9 @
    2051450 PSPICE             PWL           PWL Sources application: pop-ups and messages when browsing and placing source2 n2 F9 ?  q$ d, U
    2090021 PSPICE             PWL           Modeling Application - Sources - PWL Sources Dialog is not properly displayed
    ( h9 N4 I! P5 J0 @8 {2094548 PSPICE             SIMULATOR     Model undefined error on TL494
    & o/ H1 d: Q- k" a; B$ w2058018 SCM                PACKAGER      Reference designator mismatch in 'exportsch' schematics and board file3 |. \1 K: w1 m* J- x2 X  n8 Z- k
    1955868 SIP_LAYOUT         STREAM_IF     APD/SiP Layout: Export rounded features as circumscribed and not inscribed polygon in GDS
    6 L) s( [$ T4 A3 m2081914 SIP_LAYOUT         STREAM_IF     Release 17.2-2016: GDSII stream out drops shapes
    5 a% N" s7 C7 b9 n2013647 SYSTEM_CAPTURE     CANVAS_EDIT   Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections
    - k( D3 T; X+ }- P8 }. i0 R9 @! n  i1 B2 q+ Y4 G! C& r
    , p" R8 Z  R$ ^" j
    Fixed CCRs: SPB 17.2 HF055. n9 @. W& q8 q, q& q) x; J
    05-24-20197 }& z( K1 p1 l6 O% E3 i6 J
    ========================================================================================================================================================
    - O4 }' p: e( M# K* J9 V% C" E3 MCCRID   Product            ProductLevel2 Title
    3 @- G  \* E5 T3 m========================================================================================================================================================% _1 x4 F( c, M+ i: J
    2078057 ADW                PART_BROWSER  Symbol Graphics preview is not available in the Designer Server* P  j( c7 Q9 u: ~
    2092863 ADW                PART_BROWSER  Component Browser is not displaying the symbol & footprint preview& ^  N5 ]3 C0 ^1 L
    2076339 ALLEGRO_EDITOR     3D_CANVAS     Floating parts on bending a board in 3D Canvas with HotFix 053
      X& Y6 m- k1 f2051075 ALLEGRO_EDITOR     ARTWORK       Incorrect Gerber import in Allegro PCB Editor
    3 ]1 I% ~6 ?& Z: x2073407 ALLEGRO_EDITOR     DATABASE      axlDeleteByLayer deletes fixed shapes
      J3 S6 ]2 Z( r3 i6 D0 A5 j0 ?2079117 ALLEGRO_EDITOR     DATABASE      Release 17.2-2016: Board file saved in HotFix 049 cannot be opened in HotFix 014
    6 }" J9 P' M4 ]( o9 J- X2079204 ALLEGRO_EDITOR     DFM           Enabling option to update analysis mode and run DesignTrue DFM wizard causes PCB Editor to exit: z' e8 ]& \0 V" l
    2082394 ALLEGRO_EDITOR     DRAFTING      Angular dimension not owned by the same parent symbol in the layout are not deleted on moving object
    8 A, n. y/ [. z1 w# R2067916 ALLEGRO_EDITOR     INTERACTIV    Place replicate module bounding box does not move with circuit after module is updated
    ! |2 Y! Z. Y/ X& M+ a8 M/ V2068449 ALLEGRO_EDITOR     MANUFACT      Stackup chart and table shift slightly from original location on re-generation in Allegro PCB Editor release 17.2-2016
    0 |$ C* W) u" w5 [2065820 ALLEGRO_EDITOR     MCAD_COLLAB   Selected objects deleted from the design on clicking Cancel in IDX Flow Manager Import
    6 M0 R: W. i/ z3 Y9 [2080164 ALLEGRO_EDITOR     MCAD_COLLAB   IDX outputs two sets of masks
    3 y/ C6 }) O$ I. t2081955 ALLEGRO_EDITOR     NC            Artwork file error for via size
    8 G: d& s: b8 d. L% J; k2045061 ALLEGRO_EDITOR     PLACEMENT     Setting PSMPATH: axlSetVariableFile() does not update Place Manual but User Preference Editor does7 {+ N' A) r! H
    2049949 ALLEGRO_EDITOR     PLACEMENT     Get import errors and cannot place some parts if user-defined option is turned on for netlist import0 q! B2 O* a5 G  H  A' Q
    2069289 ALLEGRO_EDITOR     PLACEMENT     Cannot place part because attribute definitions are incompatible for the 'DESCRIPTION' attribute (SPMHDB-154)
    , L# h7 S% d% \( g. _; @2056573 ALLEGRO_EDITOR     SCHEM_FTB     Import Logic takes a long time when checks are turned on
    5 @+ V3 A3 Y5 M2076452 ALLEGRO_EDITOR     SHAPE         Shape Degassing crashes if 'Inside Shape' is selected. p' C; S4 p$ z
    2076873 ALLEGRO_EDITOR     SHAPE         Symbol Editor stops responding on editing shape with a .dra file0 O# [0 l" s% a+ Y
    1788703 ALLEGRO_EDITOR     SKILL         axlPadSuppressSet does not work when 'none' switch is used  V) D, t1 v* e% D9 T/ U. {
    1955127 ALLEGRO_EDITOR     SKILL         axlPadSuppressSet( 'off 'none ) returns a warning message and does not work per the documentation& }. K4 v4 V$ ]2 a9 R# q, n4 w& k
    2031711 ALLEGRO_EDITOR     SKILL         Syntax error related to allegro.ini shown if allegro.ilinit loads INI on startup7 {! ], r" [# m# l
    2062527 ALLEGRO_EDITOR     SRM           RF elements are shown in Symbol Revision Manager
    2 x) K1 U9 A* D/ y0 W& U5 E7 R2074249 ALLEGRO_EDITOR     TESTPREP      Testprep re-sequence causes PCB Editor to crash if 'Labels with Net Name' is selected$ i2 q# C8 ?8 V1 Q  V
    2070534 ALLEGRO_PROD_TOOLB CORE          Productivity Toolbox bar code generator is creating corrupted shapes in the database% B4 S) U' w- {  H8 M# f
    2046278 ALTM_TRANSLATOR    CAPTURE       Third-party import fails
    + L$ c3 W, R+ y1 C& {' o0 W* j! S2052399 ALTM_TRANSLATOR    CAPTURE       Third-party CAD translation stopped with error message; T7 `" [6 g! _) I6 x7 S( V
    2005087 ALTM_TRANSLATOR    DE_HDL        Cannot translate third-party to Allegro Design Entry HDL
    , J7 P) p0 S1 D1922222 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translation converts to board with unconnected nets
    & B; S: |9 O, A6 k1987263 ALTM_TRANSLATOR    PCB_EDITOR    Third-party board file: copper not imported
    . k) [, y$ Y5 P: ~2017988 ALTM_TRANSLATOR    PCB_EDITOR    Third-party to Allegro PCB Editor import issues with routes, constraints, size, and accuracy
    % E: ~$ W: c9 Y( L2021300 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator does not show any results on PCB Editor canvas4 `& v7 H4 L4 O+ [$ n0 o/ K
    1890675 APD                DIE_EDITOR    Mirror Geometry is Mirroring the symbol from TOP to BOTTOM Layer in SIP file/ K+ ?8 O0 z+ z$ E0 A
    2064219 APD                DIE_EDITOR    Applying mirror geometry results in mirroring: moved from TOP to BOTTOM layer0 I) Z! {7 L, _5 |
    2086574 APD                OTHER         Duplicate layer text shown on the vias
      e9 U; ?- O5 B0 b: m1948169 CIS                CONFIGURATION Auto Symbol Refresh Checking not working for shared folders
    / g' ^; i; h; K% p" X2025385 CONCEPT_HDL        CORE          Hierarchy Viewer expands/collapses randomly after clicking the '+' or '-' symbols
    7 b7 I' F6 x) d/ M2050010 CONCEPT_HDL        CORE          Copyproject does not properly copy the variant files' M$ {, Q% _) x
    2063457 CONCEPT_HDL        CORE          DE-HDL: very slow rendering on some systems2 r! E; ^' e1 p' f: W% H7 D
    2076312 CONCEPT_HDL        CORE          Getting 'Variant out of sync' warning when creating BOM for a design with no variants4 y9 Q! z% h- E- Q- t& c; }8 d0 E
    2083650 CONCEPT_HDL        CORE          Lower-level signals are appended with _1, _2, and so on1 o% v1 D' q$ p/ e4 L, {
    2083651 CONCEPT_HDL        CORE          The physical net names still do not sync with the assigned signal name9 C5 [$ a- s5 C3 |* T
    2056736 CONCEPT_HDL        GLOBALCHANGE  Global Property Delete does not operate on the entire design unless the top-level page 1 is open! ^! \4 j! C0 L2 H5 N
    1955357 SIG_EXPLORER       OTHER         Signal explorer invocation with OrCAD PCB Expert Suite license
    1 u( a; c% U5 W. E5 I( w+ e2079071 SIP_LAYOUT         SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die/ k) X8 h" _3 H* Q% u
    2081884 SYSTEM_CAPTURE     CANVAS_EDIT   Symbols take a long time to move, and results in DRCs and broken connections
    5 I* V+ V2 g( X$ J1 c# e0 {9 w1942542 SYSTEM_CAPTURE     IMPORT_PCB    System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks
    0 m8 G# q8 a0 ^9 S3 y4 ?+ f1 A" q2071303 SYSTEM_CAPTURE     MISCELLANEOUS cds.lib file is picked up from wrong location
    % z. q0 g7 U5 E2058979 SYSTEM_CAPTURE     OPEN_CLOSE_PR System Capture prevents a project from opening by putting a single quote at the end of a line in CPM file3 t5 j3 x8 p, S; k
    2088210 SYSTEM_CAPTURE     OPEN_CLOSE_PR The 'enable pspice' entry in CPM file is occasionally corrupted
    ) d) L& L7 G* |1 }+ n
    , @/ l& T$ g$ v& A9 U" n- ?: B( h
    7 m% @: w& s% l  N" TFixed CCRs: SPB 17.2 HF054
    1 h0 B8 c9 j, o+ N9 [1 }04-26-2019
    1 {1 S# X1 k) v5 w7 m========================================================================================================================================================% n/ c# ?, z0 x) ^  Q) D( z0 @
    CCRID   Product            ProductLevel2 Title- T: ^& }- y# n2 n# |
    ========================================================================================================================================================, U1 J! r7 ?' M) F
    2060269 ADW                DBEDITOR      Unable to create ECAD type mixed-case schematic model attributes4 `9 [2 j( b- V/ F7 p$ d' w
    2030086 ADW                LRM           Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property5 N9 I& w3 E4 ^+ |) [9 j2 C0 V
    1975317 ADW                PART_BROWSER  Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser
    3 L  K2 N8 S2 \% o; A( |9 S2076340 ADW                PART_BROWSER  .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache
    ; r% l$ Y; h3 K" q2 J" W, a2025147 ADW                TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name; C% k4 K; u* \1 E8 T3 @* V8 M! Y
    2025201 ADW                TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design6 N* |; j" W% Y+ t7 p% L
    2056694 ADW                TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object4 e& I! ]0 |; q: \$ z" v, z& K
    2054243 ALLEGRO_EDITOR     3D_CANVAS     Plating is not shown on stacked vias in 3D canvas' _) M3 f! P7 f6 _' P
    2054327 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
    - O& G: A$ R: R$ ~) [9 b2044980 ALLEGRO_EDITOR     ARTWORK       'Import - Artwork': PCB Editor stops responding and no artworks are loaded
    ) u9 `, I. j- `* }2060489 ALLEGRO_EDITOR     COLOR         SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off
      e) x3 ?. Z) a: i7 D$ \2072695 ALLEGRO_EDITOR     COLOR         Clines of colored nets not colored when 'display_nohighlight_priority' is set; x# e1 r1 s9 l' `( i+ ~; n  L
    2061203 ALLEGRO_EDITOR     CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone4 O7 d; C3 o$ e% R! B* Q
    2010812 ALLEGRO_EDITOR     DATABASE      PCB Editor STEP model offsets should follow origin movements
    5 P3 [; i7 ~. Q2011993 ALLEGRO_EDITOR     DATABASE      Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin+ F. T) g7 l, y) O! _
    2051596 ALLEGRO_EDITOR     DATABASE      Error for unsupported property in element$ h! e9 S2 u5 {% e5 [" L
    2056497 ALLEGRO_EDITOR     DATABASE      Place manual is slow
    : o4 n8 i( t* j4 v  Z# E2059489 ALLEGRO_EDITOR     DATABASE      DBDOCTOR in batch mode with argument '-check_only' detects text error$ _& U2 t3 j6 [5 \% ]
    2064268 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes when running SKILL code
    - d7 z7 k6 d/ o" d) M: L4 }2068588 ALLEGRO_EDITOR     DATABASE      Crash on opening release 16.6 design in 17.2-2016
    + y2 B$ ~8 g) D& }% b, c+ f2079131 ALLEGRO_EDITOR     DATABASE      axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
    6 E$ \; n2 K) H$ ~2034759 ALLEGRO_EDITOR     DFM           Importing DFT constraints on board does not assign csets to design but shows the csets% u) o) |2 |# \4 N
    2039992 ALLEGRO_EDITOR     DFM           Cset is not set in Pastemask element of DFA when importing XML Constraint File.1 Z. ]9 p5 a6 A# Z. l
    2046824 ALLEGRO_EDITOR     EXTRACT       Extracta ECL_NETWORK View reports incorrect pin layer.
    9 q  [5 P# L6 D1 F' b! I! U/ c7 U2048912 ALLEGRO_EDITOR     IPC           Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
    ) r$ F& D5 q, O4 y2 W2066597 ALLEGRO_EDITOR     IPC           Graphical compare not completed because of self-intersecting shape locations
    ( b1 q+ h' q$ L9 N7 s) j2079719 ALLEGRO_EDITOR     IPC           IPC2581 import fails with error 'Failed to add (LW)POLYLINE'6 T/ @  z# a1 C' c5 ~- T
    2066229 ALLEGRO_EDITOR     NC            Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill6 {9 K( w6 t- y" v. x
    2070379 ALLEGRO_EDITOR     NC            After running backdrill some vias are shorted to other nets
    % J/ U' x# q; e2041881 ALLEGRO_EDITOR     PAD_EDITOR    Difference in locations of drill in pad editor and symbol editor
    8 e0 y! r8 y- _# U/ A2058852 ALLEGRO_EDITOR     PAD_EDITOR    Net associations lost on refreshing vias1 f2 j& c. r4 X5 P' T8 B
    2061580 ALLEGRO_EDITOR     PAD_EDITOR    Lock Layer Span settings specified in padstack editor not reflected in PCB Editor9 ?7 M& q% f2 K: Y: \  I
    2048116 ALLEGRO_EDITOR     REPORTS       Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable6 T2 T( T0 c5 k: I1 {
    2038949 ALLEGRO_EDITOR     SCHEM_FTB     Netrev is slow if there is an input board file with many modified components
    0 m8 N$ @. |6 u  c1 @: L7 p2052758 ALLEGRO_EDITOR     SCHEM_FTB     Connectivity objects are being reported as Added and Deleted in Constraint Differences Report8 T: I. Y! v( X5 m* N
    2066099 ALLEGRO_EDITOR     SCHEM_FTB     Inconsistent net names on export physical after changing net names in DE-HDL! b2 b, }" X) k
    2043882 ALLEGRO_EDITOR     SHAPE         Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
    $ F9 O$ t% ?2 M2048483 ALLEGRO_EDITOR     SHAPE         Shapes not getting updated post backdrill update4 A) F+ O! m/ g# \5 o$ ?
    2052063 ALLEGRO_EDITOR     SHAPE         Cannot import IPC2581 due to 'Shape intersects with itself'! ~' T2 F: M$ W& |  a$ j( y/ X
    2056478 ALLEGRO_EDITOR     SHAPE         Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
    5 q( J% |: X, M# E$ ~8 y& z: L: _0 P) t2058017 ALLEGRO_EDITOR     SHAPE         Shape not voiding correctly when fillets are present
    1 W& T6 G. @' C. M4 s# e3 N2066473 ALLEGRO_EDITOR     SHAPE         Teardrops create strange copper shapes& P; Q8 k: _8 D, r' ?4 ]/ N
    2079698 ALLEGRO_EDITOR     SHAPE         IPC2581 import fails with error 'Shapes intersects with itself'
    ' M* h: ~- e  s$ L2 V2010569 ALLEGRO_EDITOR     SKILL         Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.$ W! E; ]6 x) s8 f! i
    2055055 ALLEGRO_EDITOR     SKILL         Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
    8 S- z, q0 o+ y7 k9 P2023755 ALLEGRO_EDITOR     STEP          Export STEP includes enclosure even when it is not selected.. |' j# m. }' |
    1881233 ALLEGRO_EDITOR     UI_GENERAL    Green/white canvas without grid when creating a board file (File - New); F/ C& U1 H, A
    1900525 ALLEGRO_EDITOR     UI_GENERAL    Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
    / j+ t* P7 k0 Z: d& P2003861 ALLEGRO_EDITOR     UI_GENERAL    Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
    ' v9 D2 r. L3 e  r6 Z" E" A/ \2033958 ALLEGRO_EDITOR     UI_GENERAL    Incorrect canvas display on creating a design from the Start page and then opening an existing design/ O  ]9 E! }. S
    2053496 ALLEGRO_EDITOR     UI_GENERAL    Confirmation dialog is behind canvas
    * ?9 Y  h$ i3 r$ r, I2054429 ALLEGRO_EDITOR     UI_GENERAL    Editor stops responding until choosing Done after clicking Zoom by Point twice
    ' Q3 W" F" Y0 j* H2059707 ALLEGRO_EDITOR     UI_GENERAL    'HTTPS' links are not shown as hyperlinks when using allegro_html
    $ p; d. Z" C3 X, P" Y2 E2063423 ALLEGRO_EDITOR     UI_GENERAL    Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
    / L: r3 K2 {& Z4 N. C5 r2038105 APD                DRC_CONSTRAIN APD crashes on update DRC in release 16.6$ H/ }2 Y" }+ j5 P# h. _; ?
    2050674 APD                PARTITION     Cannot remove C-Point from a partitioned design: V' \3 f. r- M( }
    2068814 APD                WIREBOND      Bond wires cross on auto-separate# K3 R9 {( |. @% J
    1967433 CAPTURE            OTHER         Cannot open DSN or OPJ files by double-clicking if Capture is already open7 z# \% t; j) G  t8 b. }  g3 ^
    1967332 CONCEPT_HDL        COMP_BROWSER  Crash in customer environment on clicking on last row border in PIM after filtering2 @7 o0 Z. z1 U6 S, C
    2001759 CONCEPT_HDL        COMP_BROWSER  Using Modify Component crashes Design Entry HDL
    * ~1 W$ W2 X4 `4 B0 j2020788 CONCEPT_HDL        COMP_BROWSER  Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
    8 u! f3 x5 b% J2053578 CONCEPT_HDL        CONSTRAINT_MG Values specified for custom properties are not preserved
    / U* [# u. `# C/ V2 @" Y2013002 CONCEPT_HDL        CORE          Ability to regenerate Netgroup names to remove '_1' suffix) q1 O7 L* @# [% J) n7 O
    2026637 CONCEPT_HDL        CORE          DE-HDL crashing often when launched from EDM Flow Manager4 k9 @8 ?& |$ B( u  _" s
    2041145 CONCEPT_HDL        CORE          Set font size & color of netgroup names and netgroup taps
    5 E8 y* O% _. v+ Z6 x$ \6 R2 t% c2056743 CONCEPT_HDL        CORE          NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM0 J7 A8 Z- _" z( [0 Z
    2065889 CONCEPT_HDL        CORE          DE-HDL Modify command moves location of attached symbol properties
    , t5 j7 y  d& Y4 n6 E5 e% B+ h* \2074410 CONCEPT_HDL        CORE          Full net connectivity not shown in Allegro PCB Editor.
    ' N& u* R& A2 x: ~2045717 CONCEPT_HDL        RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses
    7 q* K1 H+ {( w; p! l2045274 CONSTRAINT_MGR     CONCEPT_HDL   Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor; C! Q, s2 E9 m& [' |  T
    2050521 CONSTRAINT_MGR     OTHER         Unexpected Xnet removal from schematic when Export to PCB Layout is executed.
    8 A# }; o' U* m- d' A2066270 PCB_LIBRARIAN      SYMBOL_EDITOR Unable to edit note text containing comma
    , A# U/ Q- n8 I/ r/ Y+ H2069181 PCB_LIBRARIAN      SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.  i9 ]! ~6 [& H) P' Q8 x
    2070007 PCB_LIBRARIAN      SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character/ ^" y& t/ A  a0 f$ Q. V& C2 U
    2072793 PCB_LIBRARIAN      SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped: c5 e; R: n& P4 x
    2073138 PCB_LIBRARIAN      SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties- G4 Q# N' ]% k4 K( B' d  c
    1957458 PSPICE             FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated4 d% x; s/ y4 [$ z3 F
    2022211 PSPICE             FRONTENDPLUGI Bias Point results are not updated
    & G/ i! b2 |( ~  O) ?& J4 F/ d2031058 PSPICE             FRONTENDPLUGI PSpice bias values are not getting updated
    5 }" _6 ~* F* o$ i* ~2038021 PSPICE             FRONTENDPLUGI Bias display is not updated6 S9 h! c2 ~+ a7 w4 ~1 P  k4 `
    2055274 PSPICE             FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open* I! W' b8 z6 _! A& v7 g2 ]: G
    2053432 RF_PCB             OTHER         Property on RF component not transferred to new design not containing the component; k: H  L  `4 x" F! }( u( {( e
    2003341 SCM                SCHGEN        Unable to generate a schematic for hierarchical blocks
    8 x$ b8 ]" J) I2069924 SIP_LAYOUT         DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
    2 L& @  d3 _$ }  R! g5 y- L2067894 SIP_LAYOUT         OTHER         sip database size is enormous for a small component definition used in fdesign
    : P7 U6 F0 w# G4 f8 ]; a, p5 u2067987 SIP_LAYOUT         OTHER         Orphaned die attachment in SiP Layout cannot be removed
    ; v$ B0 l8 B# W8 b0 [9 M2072857 SIP_LAYOUT         OTHER         SiP Layout crashes when using Find by Query and choosing 'Symbols': l' J( ]: V4 F& B
    2068973 SIP_LAYOUT         REPORTS       SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
    $ v6 y2 ?, v2 m6 ^9 U2059533 SIP_LAYOUT         SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
    0 C4 J( w% }. }1981749 SYSTEM_CAPTURE     ARCHIVER      System Capture: Archiving a design from the Tcl command window results in error
    " C/ W" n- X: y* {3 D4 K2054869 SYSTEM_CAPTURE     AUTOMATION    syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files; h( w1 [* ~; j7 z# `" \# `
    1966488 SYSTEM_CAPTURE     CANVAS_EDIT   New folder rename box does not show the text typed.
    ! v" [5 p1 s2 D7 @) @& r' Y% V1814813 SYSTEM_CAPTURE     COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
    0 L6 b1 o" X/ A: N1977673 SYSTEM_CAPTURE     COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
    2 W! w9 S8 T/ P' c% Y) G; [6 M- i2027100 SYSTEM_CAPTURE     COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written
    + h$ Z/ ~8 Q; f$ B7 e1961274 SYSTEM_CAPTURE     CONNECTIVITY_ Xnet removed during pin swapping, R; n. f4 j7 d; M; C3 z8 T
    2041879 SYSTEM_CAPTURE     CONNECTIVITY_ xnets on net with only pull-up resistor4 a) {8 B2 q5 h6 ~3 `
    1889238 SYSTEM_CAPTURE     COPY_PASTE    Wire fails to connect during copy and paste1 C* l# x* o; {- J$ ]
    1993146 SYSTEM_CAPTURE     DESIGN_EXPLOR Cannot move page up by only one position
    * M  d* Z( w" [- t* K8 {1 W+ ^1910941 SYSTEM_CAPTURE     MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM
    & h+ `+ E, |$ W' r7 v  J" k1902347 SYSTEM_CAPTURE     PRINT         Prints all sheets if one sheet is specified as the print range
    % d6 y" ^- D+ U1 {  V2041272 SYSTEM_CAPTURE     SMART_PDF     Smart pdf displays component outline when component is not de-highlighted.
      B9 B& f5 y/ Q2065768 SYSTEM_CAPTURE     SMART_PDF     Custom Variable in Table Object not getting passed to PDF
      N( b7 H6 z2 k8 J, v2 q; p8 Q1969243 SYSTEM_CAPTURE     VARIANT_MANAG Export variant does not name file correctly if the filename contains a space' f7 Y5 h' R0 R6 N5 b
    1990258 SYSTEM_CAPTURE     VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number# z8 _( [7 p. p
    1992250 SYSTEM_CAPTURE     WORKSPACE     Double-clicking a .CPM file runs System Capture but does not open project
    $ i; H6 E' n# O, t8 y! O# ~4 t$ k' m5 ]8 ~3 n" K
    ( _  z, p% H5 I2 Y  {
    Fixed CCRs: SPB 17.2 HF053
    7 w6 }6 s0 v" M" o03-30-20191 t" n0 ]' F8 N; o4 ~1 y! B( T' V
    ========================================================================================================================================================
    * v# j2 {& z# p! {4 B" |4 o$ xCCRID   Product            ProductLevel2 Title, b2 ~3 A  \6 C* \
    ========================================================================================================================================================' \* E8 H. P! n. V- Y+ U# X
    2035766 ADW                DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right0 B' W" g5 M& `! L9 h  C: n* w
    2044872 ADW                PART_BROWSER  Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag* u- S1 r4 F8 ~+ S% R
    2025147 ADW                TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name! |. l# B1 ?6 @$ W2 c
    2025201 ADW                TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
    2 U& x, t& v+ a4 r9 p1 l% V- S2052046 ADW                TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error1 T- y4 `9 e+ @$ ~, t5 d
    2056694 ADW                TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
    + K$ r; m: S2 s5 c1 T7 ?$ f. h% p2047512 ALLEGRO_EDITOR     3D_CANVAS     Mechanical components do not move when bending in 3D Viewer5 F+ _" f2 g- ~
    2048086 ALLEGRO_EDITOR     3D_CANVAS     Wirebonds are not linked to diepad when component is embedded body down
    $ `. R3 q8 y1 s% w* n% K9 O2051277 ALLEGRO_EDITOR     3D_CANVAS     3D View Vias are Offset from Board in Z direction
    ) n; |8 y7 h5 m, L5 V2054327 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation$ c3 c5 h! P, w* i! Z3 ^
    2056547 ALLEGRO_EDITOR     3D_CANVAS     3D model not shown for component with STEP file assigned+ ~7 }# w1 L. Q  Z: a, A
    2044980 ALLEGRO_EDITOR     ARTWORK       'Import - Artwork': PCB Editor stops responding and no artworks are loaded
    / F: \2 i9 s3 S" l# h& Z; V2061203 ALLEGRO_EDITOR     CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone: C* h) M! L- s& v) E" ^3 a0 L7 W
    1826533 ALLEGRO_EDITOR     DATABASE      Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.
    ! O) b. G0 {1 B% V* b# w8 |8 c1857282 ALLEGRO_EDITOR     DATABASE      PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization
    8 P5 Y5 l5 S# O- Z( u2052767 ALLEGRO_EDITOR     DATABASE      Allegro PCB Editor crashes on editing padstack
    9 s0 i4 u+ s4 m! }. F- l! H# ]1825692 ALLEGRO_EDITOR     DRAFTING      Dimension line text moved by Update Symbols$ d6 M" n8 X8 u% m- k4 u  Y
    1874814 ALLEGRO_EDITOR     DRAFTING      'Connect Lines' does not merge overlapping lines6 G, [  i4 u9 G0 q5 u
    1874935 ALLEGRO_EDITOR     DRAFTING      Angular dimension text has extra spaces added before the degree symbol.: d9 P* E7 u% E- H$ F
    1882597 ALLEGRO_EDITOR     DRAFTING      'Trim Segment' should allow trimming for all intersecting segment types1 \+ Z/ b: x0 a3 j2 g( @
    2052315 ALLEGRO_EDITOR     DRC_CONSTR    DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.. j$ _2 U: a' ]5 F4 n
    2040603 ALLEGRO_EDITOR     EDIT_SHAPE    Shape is not updating correctly after the 'move' command, g2 X! `9 Z4 D8 q
    2050177 ALLEGRO_EDITOR     INTERACTIV    Letters need to remain aligned and uniform after performing Boolean ANDNOT operation
    5 U- Y5 `$ R0 G' V& Y2 `2052586 ALLEGRO_EDITOR     IPC           IPC356 showing shorts and disconnects for chip-on-board design* U/ Y! A- r) Y" `) ~- v
    2044350 ALLEGRO_EDITOR     MANUFACT      Cross Section table showing multiple decimal digits for the Tolerance column6 \9 ?0 B6 N, e' l) ]; ?& Y, V
    2051150 ALLEGRO_EDITOR     NC            Counterbore/Countersink holes not being shown in the NC legend table., G1 {( d6 ?( H, ?' _
    2058199 ALLEGRO_EDITOR     NC            'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table, Y5 C0 w4 m) [( n
    2061809 ALLEGRO_EDITOR     NC            Counter bore NC Legend does not show any data: e' B+ n. i% q* ^9 R& K
    2063477 ALLEGRO_EDITOR     NC            Counter bore NC Legend does not show its value
    , O+ `+ A# H/ X  T$ l  F7 t2033849 ALLEGRO_EDITOR     PLACEMENT     PCB Editor stops responding when removing a plane that the Place Replicate command added
    * i) m' e' D5 s3 a  [+ J; W2037509 ALLEGRO_EDITOR     PLACEMENT     Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
    / ^- }: y0 _( V2047480 ALLEGRO_EDITOR     SCHEM_FTB     Importing netlist using Capture-CM flow in PCB Editor is crashing netrev! G- P, `" J- |% k9 h5 W
    2046276 ALLEGRO_EDITOR     SHAPE         Add notch is not snapping to the grid point
    ; x8 o, l0 o8 W3 o  H, p4 @2047572 ALLEGRO_EDITOR     SHAPE         Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding7 j0 C+ u  N* u' n4 a
    2048483 ALLEGRO_EDITOR     SHAPE         Shapes not getting updated post backdrill update
    2 j, o4 i; ^8 Y7 B+ Q) i9 t2050120 ALLEGRO_EDITOR     SHAPE         Dynamic fill is flooding over other etch shapes within a symbol.
    ' F6 Q# W" H6 J( o! v# P" i/ G0 Q2058017 ALLEGRO_EDITOR     SHAPE         Shape not voiding correctly when fillets are present
    / T! M$ l# t" R7 z! g4 d2010569 ALLEGRO_EDITOR     SKILL         Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.& S1 u) l9 {+ ?! w$ \) p7 U
    2055055 ALLEGRO_EDITOR     SKILL         Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash8 h5 d. W) ^' n5 y7 M8 T  H0 s
    1961689 ALLEGRO_EDITOR     SYMBOL        Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
    ! P+ Z! B" ~7 u2 K2034949 ALLEGRO_EDITOR     SYMBOL        Angular dimension from DRA not created in PCB; ~% W3 d9 J! h3 O1 j
    2046242 ALLEGRO_EDITOR     UI_GENERAL    Searching User Preference Summary results in crash
    * @. N8 F. E9 f' A6 B2053496 ALLEGRO_EDITOR     UI_GENERAL    Confirmation dialog box is behind canvas
    ) D0 U6 Z' d* {2063423 ALLEGRO_EDITOR     UI_GENERAL    Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
    ) e* ^4 |( ^) v. O+ U' l1886781 ALLEGRO_VIEWER     OTHER         Opening Color192 in Allegro Free Viewer causes it to crash! h9 G* N: w5 Z9 P
    1699433 APD                EDIT_ETCH     Field solver runs when not expected4 e, `  {, _; H8 x7 ^- ]: H
    1937159 APD                EDIT_ETCH     Routing clines takes long time
    5 k3 x# |! b% n+ L$ C; s4 _( b2050863 APD                SHAPE         Taper voiding process is different in Within the region/Out of Region, R, z5 e% ^3 z( G
    2047391 CAPTURE            PART_EDITOR   Pin type cannot be changed in hotfix 051
    : J. a' `* q. v+ `* W5 V" \0 Q2049161 CAP_EDIF           IMPORT        Fatal error 'cannot determine grid' when converting third-party design to Capture% A+ X7 d- z) L! N2 [& ?& k
    2053578 CONCEPT_HDL        CONSTRAINT_MG Values specified for custom properties are not preserved
    7 n$ c1 j4 d3 o3 q7 W2047583 CONCEPT_HDL        COPY_PROJECT  Design Entry HDL crashing when trying to open page 52 of copied project
    ; d2 a- R. A/ v8 V+ x2036239 CONCEPT_HDL        CORE          When cutting/pasting, multiple error pop-ups appear for the same notification
    ' b: P4 m% n6 M# u2037572 CONCEPT_HDL        CORE          Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM4 k3 k! }) ]8 E! B/ Y6 k
    2037578 CONCEPT_HDL        CORE          VOLTAGE property gets deleted after copying it from a non-synchronized source
    ) s' R$ a6 R4 _9 R$ |2046958 CONCEPT_HDL        CORE          Moving block pins from symbol right to left places pin names outside the symbol
    4 P) Y9 L8 |( Y6 u4 L" Z  K2032480 CONSTRAINT_MGR     CONCEPT_HDL   Incorrect matchgroups created when working with multiple level nested hierarchical blocks2 W! a9 g- s: o$ R. |% ?
    2045274 CONSTRAINT_MGR     CONCEPT_HDL   Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
    0 f- P* r5 ?1 `0 F/ G# q1 g0 T2046765 SIP_LAYOUT         DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library+ I: x- c# K) s9 ^; }0 V
    2067970 SIP_LAYOUT         DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
    7 s- _7 y0 C; j: E/ I8 d# p1981749 SYSTEM_CAPTURE     ARCHIVER      System Capture: Archiving a design from the Tcl command window results in error
    5 U0 B# k/ \' V! a- ^* e3 f( _" i' R1968437 SYSTEM_CAPTURE     ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled- @( Q" k, x. {& x4 |0 e, u+ p1 D
    1983063 SYSTEM_CAPTURE     AUTOSHAPES    Auto Shapes are being shown as part of components
    ' y) \) i" I' j6 v9 y1968463 SYSTEM_CAPTURE     CANVAS_EDIT   System Capture should not allow illegal characters to be entered for net names' c( M7 g2 i- Y! }
    2006593 SYSTEM_CAPTURE     CANVAS_EDIT   Asterisk in a search string is not treated as a wildcard character
    & I. l) Y- s! V! A: o1721863 SYSTEM_CAPTURE     CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
    6 G( n. m: O3 g5 \4 G1960130 SYSTEM_CAPTURE     CONNECTIVITY_ Disconnected nets when using the mirror option
      R: f( R9 G' _3 M1985029 SYSTEM_CAPTURE     EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped$ Z8 T  q5 X; G) |, H
    1895142 SYSTEM_CAPTURE     EXPORT_PCB    System Capture reports incorrect unsaved changes when closed after running export physical
    7 W% E) t% n, Q$ J, f/ V5 [3 E1628596 SYSTEM_CAPTURE     FIND_REPLACE  Alias issue in Find: Results do not show the resolved physical net names* \8 c$ b- _3 y# I* L  ~- m- p
    1988297 SYSTEM_CAPTURE     FIND_REPLACE  Edit > Find and Replace does not replace a net with an existing net on the canvas4 j7 T: y' U9 S- b% U) @
    1843885 SYSTEM_CAPTURE     FORMAT_OBJECT Renaming a net causes it to lose custom color assignment( _- b, o2 Y$ G: z2 P! k# T
    1969308 SYSTEM_CAPTURE     FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast
    4 N) L+ Z9 Q( B' R& Q# T1990060 SYSTEM_CAPTURE     FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently- x. D2 B: k! D3 t( p, x
    1993208 SYSTEM_CAPTURE     FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page$ W$ D  l) A/ o- T7 h
    1981775 SYSTEM_CAPTURE     IMPORT_PCB    Import Physical takes a long time on some designs to launch the UI4 ^! M" h+ V. B9 D" \6 M
    1982320 SYSTEM_CAPTURE     IMPORT_PCB    In the B2F flow none of the *view files are created- a) t6 s) P# |, p7 L9 L/ k! Z
    2010996 SYSTEM_CAPTURE     INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
    1 ~/ u4 m$ N4 d: u. A; `% B# l1967614 SYSTEM_CAPTURE     MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
    $ w- t+ Y/ ?; Q9 g9 x3 y$ O1980999 SYSTEM_CAPTURE     NEW_PROJECT   System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL
    6 _, n4 f, N: S, Z2 C1 R# e1 G1 q0 l3 @1973437 SYSTEM_CAPTURE     OPEN_CLOSE_PR Opening a design crashes System Capture
    + ]2 l( {5 [2 k$ q1986566 SYSTEM_CAPTURE     OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message4 ^8 |) O8 v" I2 W/ z/ D
    1993093 SYSTEM_CAPTURE     OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor
    ) O8 i9 w5 _# i! I1 L2 k2042360 SYSTEM_CAPTURE     OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder
    ( [1 b* l* Q* B3 j/ \+ l1992247 SYSTEM_CAPTURE     PART_MANAGER  Part Manager displays message for undo and redo stack even after specifying not to show message8 j6 v( I: c# k" k- \
    2048000 SYSTEM_CAPTURE     PERFORMANCE   Performance issue when instantiating and moving a component
    - ]+ f! i! q: a/ g1892120 SYSTEM_CAPTURE     PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES4 k: {2 z. G' `
    1970009 SYSTEM_CAPTURE     PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option
    - s" \- ?8 i( F% g6 _8 L6 w  \0 F2042707 SYSTEM_CAPTURE     VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor3 Y0 `2 w" ~7 m/ t, J* T
    9 ?. b3 s4 J5 q3 C) U
    4 m& Q7 M, \' g4 C( w7 F5 `
    Fixed CCRs: SPB 17.2 HF052
    ( G, B# [8 n7 S* t& F03-01-20191 i' w8 z" W, T  [, y# i
    ========================================================================================================================================================
    % @4 D* N+ L8 v  E* h/ QCCRID   Product            ProductLevel2 Title. o& }! I4 W1 B
    ========================================================================================================================================================
    9 }6 T2 O/ p# q( I2020429 ADW                ADWSERVER     Incorrect adwservice status on Linux, `, {  H7 z; K' a4 k% K) y) h! V
    2034815 ADW                LIBDISTRIBUTI Cannot mark classification obsolete because it is associated to objects in the database
    9 H! _* {4 m1 T; a( t/ v2015461 ADW                PART_BROWSER  New Component Browser should read the mapping of symbol and associated package as it results in error PKG-1005' N' H# t  V1 h6 e
    2049380 ADW                PART_BROWSER  System Capture Import HDL not importing complete PTF File data
    9 Y9 F5 c  a7 A9 [- v" e1948608 ADW                TDA           CUSTOMVAR directive value in project CPM was not updated by TDA UPDATE command.
    # d# ^+ d1 H9 ~* o( g  |) D; P1992662 ADW                TDA           Custom directive added to the cpm file not updated after check-in
    ) X+ o6 I, k. z0 V( q1 q1733129 ALLEGRO_EDITOR     COLOR         'Display - Highlight', double-click permanently highlights symbol0 z" ]4 x- o4 O% `+ J& Z: t
    1861938 ALLEGRO_EDITOR     COLOR         Changing layer color changes layer visibility
    5 @" ~6 K9 k! y$ n2034753 ALLEGRO_EDITOR     CROSS_SECTION Allegro PCB Editor crashes when a cross-section technology file is imported in Overwrite mode& A; |- T! s- z  R
    2036895 ALLEGRO_EDITOR     CROSS_SECTION Replay script error during import of tcfx Xsection file
    : _  P8 D  a/ I3 d! I( k1929360 ALLEGRO_EDITOR     DATABASE      Via color is inconsistent on Vias with color assigned2 u* y* T) j8 P4 t! Q' S  U
    1984203 ALLEGRO_EDITOR     DATABASE      Drill holes not displayed correctly in the Zone area
    5 Z) O" U, |' b$ _2013596 ALLEGRO_EDITOR     DATABASE      Assigning net name on Vias does not change the Via Color to that on Net Color automatically
    ( t' P; M8 N! P6 h2025798 ALLEGRO_EDITOR     DATABASE      Assign net to via changes color of the via to the default color$ Y. o/ H) p6 i9 }- O
    2032678 ALLEGRO_EDITOR     DATABASE      Unable to delete layer on design
    1 z  D3 K+ U$ q6 r' ^2 D0 k4 u$ h4 R2032725 ALLEGRO_EDITOR     DATABASE      Dehighlight removes color assignment from color dialog# e! \5 O! c2 t/ |3 z# v* _' _4 c% ^
    2029542 ALLEGRO_EDITOR     DFA           Interactive Placement with Manufacturing Package to Package spacing
    0 Q7 L/ Y3 j2 ], b/ U6 s4 {9 Y2020548 ALLEGRO_EDITOR     DFM           Cadence DFM Customer site cannot Submit Request( P- v4 H4 o1 r3 i. L! d- F
    2020566 ALLEGRO_EDITOR     DFM           Error when sending Design True DFM Rules Request! t5 L/ O9 [% r4 E! ~, \
    2030179 ALLEGRO_EDITOR     DFM           Allegro PCB Editor .brd file will not save after routing using Automatic Router
    " ^  t$ U' j6 {% y6 b+ ?8 |6 l1 W5 P2052907 ALLEGRO_EDITOR     DFM           The Submit Request button for DesignTrue DFM Rules Request does not work+ V% g' s3 \: [+ N+ R/ m* E5 T
    1928915 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor constraint status bar does not match Constraint Manager data when z-axis delay is turned on.
    - e, V' i( E; H* a& n1932165 ALLEGRO_EDITOR     EDIT_ETCH     Arc slide behavior with clines at odd angles: notches on slides( j( U$ v; q- F$ p8 M0 a  V
    1943901 ALLEGRO_EDITOR     EDIT_ETCH     arc segment incorrect on slide.: H# M! R  G( }
    2031055 ALLEGRO_EDITOR     EDIT_ETCH     On drawing cline the width on a Layer is larger than defined constraint8 _! z) {* y* H* G- }
    1877891 ALLEGRO_EDITOR     GRAPHICS      Allegro PCB Editor crashes when started from EDM for projects without a board file or empty master.tag file
    - t$ V9 B% h  e- S7 u. `2 ^% ]2040689 ALLEGRO_EDITOR     NC            The decimal digits of a rotated oval padstack do not match the Drill Chart.
    + E# J. o/ F& F! P4 y5 E( ]2 P8 o2028105 ALLEGRO_EDITOR     PLACEMENT     Delay in moving a large count pin symbol
    7 E; P+ q. N! {! l2019027 ALLEGRO_EDITOR     REPORTS       Information shown in the Report Viewer is not correct.
    / ]+ U4 F# o8 |$ z  y7 W) D" S2022461 ALLEGRO_EDITOR     SHAPE         Abnormal termination of  thieving function in Allegro PCB Editor
    6 I: ]/ M7 U# b6 F2032048 ALLEGRO_EDITOR     SHAPE         shape void difference from hotfix 026 to 048: need square corners for full round
    % ^4 O: c. D  `% d7 R; h  H; Q2040138 ALLEGRO_EDITOR     SHAPE         shape_rki_autoclip affects the overlapping shape boundary
    & w' f; C( g, w  Y6 z+ R! Z' E2040259 ALLEGRO_EDITOR     SHAPE         Same net shape and cline adds shape void around cline
    " [% \# A$ V9 U! }$ |( D: D" q0 }2031468 ALLEGRO_EDITOR     TECHFILE      Cross section import (.tcfx) not working correctly.# E8 P; X! L1 A% R% P1 Q, C
    2006425 ALLEGRO_EDITOR     UI_FORMS      Option to disable 'Create a New Design' window in OrCAD PCB Designer; P+ U' ?6 d8 c6 S  f2 L
    2007451 ALLEGRO_EDITOR     UI_FORMS      Option to suppress 'Create a New Design" window for File > Open in OrCAD PCB Editor from hotfix 048+ ]! G5 ^4 t6 A6 u- O5 D
    2009314 ALLEGRO_EDITOR     UI_FORMS      Existing scripts that open OrCAD PCB Editor not working in hotfix 0480 A# D, A, L: P% K1 h: ~! G
    2021476 ALLEGRO_EDITOR     UI_FORMS      PCB Editor is slow when using the command 'add connect'
    2 g5 `0 ~% o9 ]4 A/ g: m5 _; I7 L6 L2039462 ALLEGRO_EDITOR     UI_FORMS      Hovering over Default symbol height in Design Parameter Editor does not display a description
    5 {& O3 E" I. D" M5 r1808054 ALLEGRO_EDITOR     UI_GENERAL    Illegal value in axlFormSetField crashes PCB Editor
    / n: H0 V7 Y( D  T; N% X3 N1822679 ALLEGRO_EDITOR     UI_GENERAL    'Symbol pin #' field is truncated on rotating components in the Placement Edit mode
    5 P* G. _  }8 u) h1856438 ALLEGRO_EDITOR     UI_GENERAL    Script recording messages not displayed in the PCB Editor task bar when using the script window.0 A4 X+ |, n8 R2 h" C4 b5 u" s1 p
    1879078 ALLEGRO_EDITOR     UI_GENERAL    Running PCB Editor from command prompt with '-product help' should list all products and options( Q$ r- u" @' R0 |9 {
    1944225 ALLEGRO_EDITOR     UI_GENERAL    Cannot close log file window till we close report dialog box" h) f" d( h4 @
    1967708 ALLEGRO_EDITOR     UI_GENERAL    New Command Window Shows Last Command in UI- m2 k3 \* A: h, G
    1968380 ALLEGRO_EDITOR     UI_GENERAL    Write all open editing sessions in MRU. i# C: ~% K& Y2 `8 b2 F. r+ j3 a
    1982138 ALLEGRO_EDITOR     UI_GENERAL    axlFormListDeleteItem(fw field -1) not deleting last item of a list
    . W6 f7 w$ q! b% B2003054 ALLEGRO_EDITOR     UI_GENERAL    Grids not shown when 'nolast_file' is set
      N/ k. n' v% y% I$ ^+ U( u7 b2010760 ALLEGRO_EDITOR     UI_GENERAL    Pressing tabs is selecting only vias and not selecting clines in PCB Editor in hotfix 048' }, s4 a% E  F4 K8 w8 l- x0 M+ ~
    2019120 ALLEGRO_EDITOR     UI_GENERAL    Tab key is not working when there are two objects on top of each other
    + a$ E3 t# W. e: q2 a+ b6 V2029248 ALLEGRO_EDITOR     UI_GENERAL    Colorview load is not working when using absolute path" G; i9 u/ A" n# C, f. \
    2030985 ALLEGRO_EDITOR     UI_GENERAL    The view of the PCB is offset after closing and opening the board.
    ) G0 X0 ?- U9 p& W2037968 ALLEGRO_EDITOR     UI_GENERAL    Tab key will not cycle between cline elements.8 _; h6 {4 }$ P* j& x) h, ~
    2015766 ALLEGRO_PROD_TOOLB CORE          Advanced Testpoint Check does not work
    : {) L0 J1 S% L) [% G& m2023356 ALLEGRO_PROD_TOOLB CORE          Edit new session does not work in quick symbol editor tool box
    1 Z4 W7 N* k. a! q2017162 CAPTURE            CONSTRAINT_MG Cannot apply ECSets in Constraint Manager-enabled Capture
    # E' L* d4 ~$ t$ M2026777 CAPTURE            CONSTRAINT_MG Cannot apply electrical CSet (ECSet) in Constraint Manager-enabled Design Entry CIS
    8 t) @7 S7 R2 u0 Z4 D: v2027545 CAPTURE            CONSTRAINT_MG Getting error (ORCAP-40320) while creating ECSet+ l. O! n4 |5 w
    2012967 CAPTURE            OTHER         Capture license is loaded slowly in hotfix 048, K: z$ {/ q4 x+ b, s! i
    2010093 CONCEPT_HDL        ARCHIVER      Archive .zip file keeps the whole folder hierarchy and not only the project hierarchy
    5 E3 v5 F/ o  A2040431 CONCEPT_HDL        EDIF300       EDIF300, Schematic Writer, crashes in release 17.2-2016
    ' H7 H2 s$ c3 ~# o; r7 j) q7 K2034077 SIP_LAYOUT         DFA           DRC is not catching all Shape minimum width violations
    8 g- ~6 r* X: l9 F9 U0 C2034094 SIP_LAYOUT         DIE_ABSTRACT_ [VSDP-RDL Exchange] some traces are lost in SiP Layout
    ) ]! ~* a" r( e9 g  p2037462 SIP_LAYOUT         DIE_ABSTRACT_ Cline Segments are lost on saving and re-opening the design in next session
    ( s% q; k; H  c0 |4 {2025321 SIP_LAYOUT         IMPORT_DATA   compose symbol from geometry defaults need to change due to performance1 @+ f! U$ ~8 v# e0 |3 R
    2017759 SIP_LAYOUT         PLACEMENT     Placing a die creates extra place bound and puts pin numbers in the wrong place, causing future netlist import failure/ l8 A. [$ z7 G
    2021057 SIP_LAYOUT         SHAPE         Polybool assert error when adding dynamic shape prevents shape voiding.
    ' O5 \1 a2 {5 S0 A: m! k1 Z: \' o2012381 SIP_LAYOUT         SKILL         Ability to check if the Dynamic Unused Pads Suppression box is selected using SKILL
    . g' p  l( l. V1990299 SIP_LAYOUT         UI_GENERAL    Pressing 'Esc' cancels DRC checking when there is no focus on the Allegro PCB Editor canvas8 ?% Y- T8 V$ a. D* ~
    1997317 SIP_LAYOUT         WLP           Advanced WLP, Metal Density Scan does not correctly calculate scan region count in Y direction9 a6 k; p+ `) y, M( Q/ U
    2029524 SPECCTRA           ROUTE         SPECCTRA stops responding when executing the quit command) _. F9 ^7 J( o" V; P  y6 Y% Z  T
    1670888 SYSTEM_CAPTURE     CANVAS_EDIT   Rotation error when connected to a power symbol
    4 R! T/ n# h9 ~5 o+ \! t1880809 SYSTEM_CAPTURE     CANVAS_EDIT   Can modify only one RefDes from canvas for duplicate RefDes; can modify both from the Properties window
    3 I6 U  a8 X+ l7 n& t' K- n6 c0 \; Q1979063 SYSTEM_CAPTURE     CANVAS_EDIT   System Capture : File > Close is grayed out
    5 `: J5 u$ l7 @5 o2034498 SYSTEM_CAPTURE     CAPTURE_IMPOR Cannot find parts via Find & Replace after importing Capture design+ o* t$ E7 N8 V2 d: x3 p! x7 I
    1984561 SYSTEM_CAPTURE     CROSSPROBE    System Capture: Cross-probing from layout does not work when zoomed into a specific area on canvas
    / {% Z+ }2 |! X( o6 U1863460 SYSTEM_CAPTURE     DARK_THEME    thumbnail preview of pages is in light them but dragging the page the previes is dark
    $ w  `( T. n+ W) I4 s1 R2 z; q. |2025876 SYSTEM_CAPTURE     EDIT_OPERATIO Route failures when dragging a circuit
    % B" y$ b9 E2 i/ b% D2005904 SYSTEM_CAPTURE     FORMAT_OBJECT Pin name text is smaller in System Capture than in DE-HDL by about 25%
    0 v5 H8 v* p, t' f# L2036782 SYSTEM_CAPTURE     IMPORT_BLOCK  Unable to import the block from project.
    3 f+ }- W! R+ w3 p9 G8 h, R2025949 SYSTEM_CAPTURE     IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not  translate in System Capture0 q) N! Z9 k- `
    2025950 SYSTEM_CAPTURE     IMPORT_DEHDL_ Broken connectivity on imported ground symbols2 u' `% H- ]: c3 F  m3 {
    2040923 SYSTEM_CAPTURE     MISCELLANEOUS System Capture - Multiple Symbol Replace, disconnects and changes orientation8 g- L& J: ?2 _" x$ s6 @( [
    2017526 SYSTEM_CAPTURE     NAVLINKS      Page information missing in NAVLINKS! D3 f! ~: a1 Q6 u# _, i0 k
    2015346 SYSTEM_CAPTURE     PAGE_MANAGEME Rename page fails in some cases* o8 G! v7 }8 m( o. c! [) {
    2038811 SYSTEM_CAPTURE     PRINT         Black & White PDF showing colors
    # l4 ^+ u" L" ~2 R2 l9 _/ |% c2048493 SYSTEM_CAPTURE     SYMBOL_GEN    Symbol Editor, Modify outline adds an 'X' in symbol incorrectly+ w* Q+ E& i6 m9 w2 U! J; e
    2031995 SYSTEM_CAPTURE     VARIANT_MANAG Variant Editor does not load the design and restarts the machine after sometime.4 |) U8 b8 H# t- h: s7 e' A( U
    2032005 SYSTEM_CAPTURE     VARIANT_MANAG Custom variables not saved for variants
    / k$ [, p5 b$ P+ k2 V) ?1968431 SYSTEM_CAPTURE     WORKSPACE     Unable to reorder the pages (tabs) when opened in the workspace
    3 H  z5 c6 P$ d1 h1 q2040995 XTRACTIM           GUI           Running XIM from APD enables "skip DC R simulation" by mistake
    4 @% y! e! A- P# {3 q  y  d: w) c0 X1 q' d, r9 k
    ' e0 C* l5 F! e! f
    Fixed CCRs: SPB 17.2 HF0510 ~7 q( |- E+ ]* K0 d4 R
    01-30-2019' p8 T/ `) Y! F: G7 Z) V
    ========================================================================================================================================================9 i/ G; z( @1 |, h& ?4 m$ Z" O; }
    CCRID   Product            ProductLevel2 Title6 D) n* w; J, o' _6 R& f, l  W
    ========================================================================================================================================================8 y5 y( O" E& o+ ?; d; E# E
    2015843 ADW                LIBDISTRIBUTI Error for library distribution (lib_dist_client) regarding string index out-of-range5 O' H9 Q: i5 b8 ~
    1869914 ADW                PART_BROWSER  Adding components to System Capture schematic canvas takes long time in Linux clusters
    % [# u# S4 e+ d# [& C! J# ?2010458 ADW                PART_BROWSER  RefDes values not appearing on parts, T8 k: b: V- T7 g
    2022630 ADW                PART_MANAGER  Unable to successfully import a DE-HDL Design into System Capture7 L9 X) l5 F  H) \
    2005033 ALLEGRO_EDITOR     3D_CANVAS     3D Flex issues: Error message when opening design with bends in 3D viewer+ W4 k; Q5 ~+ T
    2023496 ALLEGRO_EDITOR     3D_CANVAS     Error for designs with bend in 3D Viewer
    & \3 d8 c, `0 r( L4 C2033459 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
    % Q: s/ B, t& v% B+ o. X1996431 ALLEGRO_EDITOR     ARTWORK       Via holes for connection have incorrect coordinates in Gerber
    ; ?! {- d% g' v* O) U" z* L1995656 ALLEGRO_EDITOR     DATABASE      Attaching and Detaching a text file created with SKILL writeTable() function corrupts the text file  f" E/ H0 n% v$ ?
    2027122 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes when creating Place Replicate module2 D, D, O$ x3 U% r5 k( Z
    2023916 ALLEGRO_EDITOR     DFM           DFF Annular Ring: Thru via pad to Mask violates on via in pad instances." g" \( N9 d( ]  v1 \1 ]2 Q  ~1 Y
    2024523 ALLEGRO_EDITOR     DFM           PCB Editor crashes in Mask To Trace check of DFF.
    7 A  g/ [- t1 W- e# P2021318 ALLEGRO_EDITOR     IN_DESIGN_ANA Integrated Analysis and Checking: Unable to run simulation with Crosstalk flow
    - H; o) J" r* ]0 g2014162 ALLEGRO_EDITOR     NC            Backdrill results using an OrCAD Professional license showing wrong values with hotfix 048, v9 y  G3 |" K. p
    2010791 ALLEGRO_EDITOR     PLACEMENT     Setting dfa_pause_level to 3 and then moving and rotating part places the part with offset9 C  G' J$ m( }' p
    2017112 ALLEGRO_EDITOR     PLACEMENT     place_boundary shown at wrong location when moved with User pick and footprints rotated
    7 d) r$ M, y5 [! A' y2028048 ALLEGRO_EDITOR     PLACEMENT     Rotate option using pick is rotating the outlines in different axis in view6 P6 r9 B9 a7 u" @, o% ?
    2028314 ALLEGRO_EDITOR     PLACEMENT     Crash on moving components in Allegro PCB Editor$ C: C: @3 k( H
    2029235 ALLEGRO_EDITOR     PLACEMENT     PCB Editor crashes when moving more than one component and hovering on IC
    5 L, j, N* P( o5 n  I8 p; @: s* P4 f2022644 ALLEGRO_EDITOR     SHAPE         dv_fixfullcontact obsolete in release 17.2-2016( N# K* r+ d1 r1 q0 U7 R, t1 h' u
    2023322 ALLEGRO_EDITOR     SHAPE         Gloss does not add teardrops on all clines.
    ' E$ t1 G3 `" |4 t; u8 K, r2024235 ALLEGRO_EDITOR     SHAPE         Copper Pour disappears when area includes parts. [7 Q2 X6 l. b$ _! e
    2024531 ALLEGRO_EDITOR     SHAPE         rki_autoclip is not working at a special XY location, P. ~* f& z9 X
    2024599 ALLEGRO_EDITOR     SHAPE         Cannot create round corner for shape. @0 [" Q( D4 @) E3 \  n5 V4 ?7 r
    2024707 ALLEGRO_EDITOR     SHAPE         In-line void control does not work when there is no_shape_connect property attached
    0 C  E9 q# t) n9 K2026849 ALLEGRO_EDITOR     SHAPE         Cannot assign region name using the 'next' operation" }- W& @; H/ D, l0 e& W! U0 m( f
    2030156 ALLEGRO_EDITOR     SHAPE         Shape Area report for cross-hatched shape includes hatching and boundary
    . d& ~1 A2 I& O5 S' d5 _# F  @1852981 ALLEGRO_EDITOR     SKILL         Error message while creating Copper Mask layer without a name using SKILL not clear- \2 ]2 w  I9 m
    1968054 ALLEGRO_EDITOR     SKILL         Document of axlClearObjectCustomColor should indicate that it can clear color for DBID of Net
    , \; h' X' x9 [( ]6 I  g  Q$ l2026429 ALLEGRO_EDITOR     UI_FORMS      PCB Footprint wizard: horizontal and vertical lead pitch level reversed in the image/ W# }0 B! I3 e" L4 K% B+ ~
    1768032 ALLEGRO_EDITOR     UI_GENERAL    Numeric keypad does not work for file selection shortcut
    % B3 D1 r6 f; h1797376 ALLEGRO_EDITOR     UI_GENERAL    Release 17.2-2016: Padstack Designer saves padstack to the working directory when script is used' i! ?! N# v" R. y- @
    1798524 ALLEGRO_EDITOR     UI_GENERAL    Unable to save a padstack using script
    ' l$ w* x( L, V0 G1 q1823031 ALLEGRO_EDITOR     UI_GENERAL    Help not working for OrCAD Productivity Toolbox* Q" z0 m2 y$ D% _$ ?9 |6 R" V
    1849921 ALLEGRO_EDITOR     UI_GENERAL    Analyze menu missing in OrCAD PCB SI
    & B$ `% a0 P- ~# }8 n& l: K: z1951740 ALLEGRO_EDITOR     UI_GENERAL    Trigger for 'open' does not work when opening a .dra file: a8 J$ ^' A) O) @3 D2 @
    1952163 ALLEGRO_EDITOR     UI_GENERAL    Analyze menu missing in OrCAD PCB SI  x: S2 S7 S: k# U+ |! e8 O4 A' B  }
    1982966 ALLEGRO_EDITOR     UI_GENERAL    SKILL command to access the Option window fields while in Interactive commands.
    ' i) N3 F' ^6 P6 u. h& J7 g7 A/ O; E1983567 ALLEGRO_EDITOR     UI_GENERAL    Alias with Ctrl not working with 'command window history' variable enabled0 N; t0 j( a' J% D
    1989507 ALLEGRO_EDITOR     UI_GENERAL    Third-party tool causes PCB Editor to stop responding to command& Y! w- M7 @+ c/ m9 `
    2003511 ALLEGRO_EDITOR     UI_GENERAL    Aliases using control (tilde) characters stopped working after upgrading to hotfix 048+ r2 Q8 D* d0 [
    2010418 ALLEGRO_EDITOR     UI_GENERAL    New command window breaks funckeys
      T3 Q' K* R. Z9 a0 g/ g: w; z" T: }: i2018201 ALLEGRO_EDITOR     UI_GENERAL    SKILL axlDBControl ('activeLayer /') updates active class/subclass but ministatus form not updated
    . D  `$ A4 G, p, v& J2023468 ALLEGRO_EDITOR     UI_GENERAL    axlZoomInOut does not zoom out, always zooms in regardless of zoom factor (positive or negative)
    + Q# x# H# q+ ~/ D7 b2026428 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor takes several minutes when saving a design/ c+ t! s- k0 x8 |
    2032697 ALLEGRO_EDITOR     UI_GENERAL    Funckeys with Ctrl not working with 'command window history' variable enabled( Z7 ^/ {/ |& r
    2032717 ALLEGRO_EDITOR     UI_GENERAL    Funckey combinations, such as Ctrl + M, not working
      G! \7 m1 k  Y) E* H8 w2014211 ALLEGRO_VIEWER     OTHER         Arrow keys are not panning in Allegro Physical Viewer: T4 y8 Y% v% g* r& q3 v2 e. O5 q7 z
    2039081 CAPTURE            NETLISTS      Netlist not created: netlist fails for numeric pin names with backslash '\'
      z, ?5 R7 y, c: q1993057 CONCEPT_HDL        CONSTRAINT_MG Constraints disappear in hierarchical design (Electrical->Net->Routing->Relative Propagation Delay)1 I$ D7 V/ r7 C) g; z) o
    2004641 CONCEPT_HDL        CONSTRAINT_MG 'Save Hierarchy' (hier_write) deletes bus object in Constraint Manager
    ' }* h$ ~9 j& R2020901 CONCEPT_HDL        CONSTRAINT_MG Incorrect match Groups created in CM (TDO design)
    1 l( Z; }! B  ~1 S2 N) P- U0 o' c$ I2014979 CONCEPT_HDL        CORE          The active schematic page randomly changes while editing text
    ' c+ E% a: J, ]( U+ x2027905 CONSTRAINT_MGR     DATABASE      Pin Property changes in CM during uprev to release 17.2-2016( n8 |- I+ K' n2 O' e6 C
    1762263 ORBITIO            INTERFACES    Add set allegro_orbit_import variable to user preference* n* `, J4 ~: K
    2005860 PSPICE             LIBRARIES     Error when simulating design with TL494 part in release 17.2-20164 n! \/ g: a8 l4 e
    1980072 PSPICE             SIMULATOR     Noise in the waveform when using DELAYT and DELAYT1 with capacitor
    9 `) |! ~, a3 F, K% @) k( T* f  @1977615 RELEASE            INTEGRATION   Cannot import third-party schematics into OrCAD Capture in release 16.67 o: W, o; X% o1 y' @; `
    2027009 RF_PCB             SETUP         'RF-PCB' - 'Setup' changes not saved on Apply
    * h0 M, t+ d* Y7 C7 P& H2002040 SIP_LAYOUT         MANUFACTURING IPC 356 'ignore die layers' does not work: netlists to die
    . J* j* h# N3 F2024703 SIP_LAYOUT         WLP           Cannot Add Pin Text: Error on 'Manufacturing' - 'Documentation' - 'Display Pin Text'
    . {. ~/ m% P4 S: m* X9 f4 r2 Z4 `2010045 SYSTEM_CAPTURE     CANVAS_EDIT   Cannot snap back vertical CAP until moved up and down horizontally# t- W0 l! A3 k, _' _, J* h2 `
    2010443 SYSTEM_CAPTURE     CANVAS_EDIT   Cannot select the CAP part9 m* S" Z4 M2 x, i
    2012843 SYSTEM_CAPTURE     PACKAGER      Cannot short two grounds in the schematic
    ( X$ C' _, ^% H- B2015574 SYSTEM_CAPTURE     PACKAGER      System Capture is treating quotes in PTF files differently from DE-HDL
    0 t8 b3 O8 m" |+ ?( `" t% ^# l2022653 SYSTEM_CAPTURE     VARIANT_MANAG Variant Editor - Allow Alternates where ALT_SYMBOL is a valid match for JEDEC_TYPE% S  T# h  G& O% A
    2024742 TDA                SHAREPOINT    Accessing projects is taking time
      ~) a0 h! `  R4 o2010531 XTRACTIM           OTHER         Allegro crash on repaint of command window: @5 q, X! U. k  W) O: X0 I
    2022351 XTRACTIM           OTHER         XtractIM is crashing the latest HF S049
    , b3 y/ o# o5 r/ A$ Q+ Z
      A1 J+ w4 B2 L' L: L' L3 b: k3 C4 H& |. `2 G
    Fixed CCRs: SPB 17.2 HF050
    ' R0 |+ \7 D/ h0 V2 p12-23-20180 Q% u- w' ^, C0 h* c
    ========================================================================================================================================================1 ], C- [( z' B1 Q5 B
    CCRID   Product            ProductLevel2 Title+ S2 d5 [& g( ^4 Q7 A+ |, u
    ========================================================================================================================================================6 u: I  j+ g, N3 e2 ^; B3 ~- T
    2012119 ADW                ADWSERVER     Cannot connect Component Browser to server' @# D7 n. a' W
    1998856 ADW                ADW_UPREV     adw_uprev fails and a typo in rule name
    - P0 {4 L) A, M0 O& ~7 j) H1673333 ADW                CONF          Configuration Manager stops working and gives Java Timer-1 Error
    . `( G- q, M8 y1900342 ADW                DBEDITOR      'Link To' on a schematic classification attribute does not work with linked attributes containing parenthesis
    % H3 X! j. e2 @$ k+ l  D1997516 ADW                DBEDITOR      DBEditor stops responding on changing attributes
    1 h* {+ E8 S# a8 c5 F1986292 ADW                LIBDISTRIBUTI Some parts are not updated in the part table in all_noauto and ini_noauto (restricted_sites).5 P: i/ Y7 n+ N* e7 U& S
    2010460 ADW                PART_BROWSER  PKG-1002 error when opening a DE-HDL design2 g% K& X% R% v( ?' E' ~- t5 U
    2013430 ADW                PART_BROWSER  Add component is inactive if WB_SHARED_RESOURCES is not pointing to the installation directory
    - c2 A$ Y4 \8 r7 j. s) h8 U3 P2022806 ADW                PART_BROWSER  PKG-10005: Cannot package the following primitive instance in any section of the physical part
    ! G7 z! L3 G1 q# }$ @2006528 ADW                PART_MANAGER  Part Manager does not update parts when Key PTF property value changes' u$ f7 j/ t7 R) N1 J# i) K: }
    1980397 ALLEGRO_EDITOR     DATABASE      Mechanical pins with route keepouts (RKO) not updated7 r) F' @4 e5 I) o  D
    1988171 ALLEGRO_EDITOR     DATABASE      Backdrill clearance Keepout is not applied consistently
    $ t9 {# ~$ d* p3 w' ~! g, y1994280 ALLEGRO_EDITOR     DFM           PCB Editor crashes during Unplace component% b9 S0 W$ Z* B% N8 o6 [2 V
    2012742 ALLEGRO_EDITOR     DFM           DFT for testpoint to outline not showing DRC7 @0 {+ t; K( e1 L$ P( X8 L: `
    2002680 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashes on choosing Add Connect for two selected nets5 |/ f4 ~% o0 i# b
    2004597 ALLEGRO_EDITOR     EDIT_ETCH     Illegal BMS Identifier error when copying multiple via structures: t9 @: Z( n8 u/ O/ Y
    2004929 ALLEGRO_EDITOR     EDIT_ETCH     Net with physical pin pair constraints is using incorrect line width when routed
    3 s+ ?1 Z& M3 L% M. p( l2008314 ALLEGRO_EDITOR     EDIT_ETCH     Adding nets in tabbed routing crashes PCB Editor+ L( z, g3 m- l8 S" y
    2018710 ALLEGRO_EDITOR     GRAPHICS      Using the mouse to zoom by scrolling stops working randomly  S. M& S# I+ `) n+ k1 [
    2018841 ALLEGRO_EDITOR     GRAPHICS      Canvas does not regain mouse focus after working in the Options pane in hotfix 0493 X" g1 s! N+ r/ i; E/ o' T
    2019482 ALLEGRO_EDITOR     GRAPHICS      Canvas does not regain mouse focus after working with the Options pane in hotfix 049 on Windows 7
    " i3 i* n5 k2 o2019864 ALLEGRO_EDITOR     GRAPHICS      Using the mouse scroll button to scroll the canvas: focus is in the Options pane
    5 [" |% ^% y3 E( S2020750 ALLEGRO_EDITOR     GRAPHICS      Zoom in/Zoom out scroll does not work
    ! V. X4 q4 V0 ]# W$ O2020847 ALLEGRO_EDITOR     GRAPHICS      Scroll up/down key focus remains in command screen even when canvas is selected
    + C0 z: O; e5 ^/ {% N  I# H% m+ f1908812 ALLEGRO_EDITOR     INTERACTIV    Tools > Design Compare command does not work on Windows9 U& i' `/ ^7 X3 n4 R8 D
    1995846 ALLEGRO_EDITOR     INTERACTIV    When there is an embedded component, the result of Metal Usage report is incorrect.
    ! M2 |6 j" K, F2011449 ALLEGRO_EDITOR     INTERACTIV    Command not found error (_impvision) for Impedance and Return Path DRC visions$ C: x3 s; u+ A' S3 m& o, d) r
    1982867 ALLEGRO_EDITOR     INTERFACES    DBDoctor displays error for objects outside extent that cannot be fixed because the extents cannot be increased
    # l! f3 d1 s7 K- P1983177 ALLEGRO_EDITOR     INTERFACES    PCB Editor crashes when reading IDX file9 u# ]6 O0 q$ Q
    1985623 ALLEGRO_EDITOR     INTERFACES    STEP model not exported from PCB Editor) t; _8 w4 t8 H! K7 j, m* H+ Y* h
    1994855 ALLEGRO_EDITOR     MANUFACT      Drill legend with counter-bore: legend size not uniform when database set to inches
    $ [, P: d# t4 G6 S, X8 F2001355 ALLEGRO_EDITOR     NC            PCB Editor crashes with NC route parameter% S0 o' L2 y/ `4 P# `) K: f
    1753414 ALLEGRO_EDITOR     OTHER         Ability to add Rigid Flex class in a format symbol
    ! T% c$ h( u* }7 s( S7 x2004786 ALLEGRO_EDITOR     OTHER         Legacy menu option missing in OrCAD Professional
    . t: U, u) W, l# o1 p9 ~1949695 ALLEGRO_EDITOR     PADS_IN       Third-party to PCB Editor translation does not make a clean conversion, ?) D: e! |& b( @
    1949658 ALLEGRO_EDITOR     PLACEMENT     SKILL module creation issue: subsequent runs rotate module incorrectly
    . i* ]# i# L( S; H1 o0 b1 W2001496 ALLEGRO_EDITOR     PLACEMENT     Constraint Region not replicated as part of the Place replicate apply command4 s" l$ D* F& r& G9 E1 k$ \, L" `+ d
    2002989 ALLEGRO_EDITOR     PLACEMENT     Default rotation point is set to 'User Pick'
    : D) Z0 L6 A" Y9 w2007301 ALLEGRO_EDITOR     PLACEMENT     DFA boundary is shifted when moving components with User Pick
    $ D% P* N5 T$ b2007312 ALLEGRO_EDITOR     PLACEMENT     DFA boundary is shifted when moving components with User Pick
    % k+ i  H( p- B7 S2008098 ALLEGRO_EDITOR     PLACEMENT     DFA boundary shows a shift if anchor point is set to 'User pick'
    3 H( `! {8 L- {- I# {  L1 Z9 A2009085 ALLEGRO_EDITOR     PLACEMENT     DFA boundary is shifted when moving components with User Pick4 J. p) i5 W, O" L! c( r3 d
    2009090 ALLEGRO_EDITOR     PLACEMENT     DFA boundary is being offset when moving components with User Pick- |' j9 o" k$ b& Y  ]
    2009580 ALLEGRO_EDITOR     PLACEMENT     Component outline offsets during move process
    0 p1 `" e0 o- [, K! s2010726 ALLEGRO_EDITOR     PLACEMENT     Two images appear when moving component in release 17.2-2016, hotfix 048
    8 Y8 A4 p3 u8 f  ^) C2010819 ALLEGRO_EDITOR     PLACEMENT     A separate outline appears when moving components using User Pick
    1 N0 O. }* N! C% D9 B' }7 T: c" \. u2011454 ALLEGRO_EDITOR     PLACEMENT     DFA boundary is not centered correctly on moving components
    . i0 \  P7 \; a2011497 ALLEGRO_EDITOR     PLACEMENT     DFA boundary shifted from the part when moved% `; M5 v" s0 Z0 ^* S! P* u
    2014250 ALLEGRO_EDITOR     PLACEMENT     Moving a symbol using the 'User Pick' causing an offset image of the symbol outline getting attached to cursor
    - q) E/ V5 n* A2015676 ALLEGRO_EDITOR     PLACEMENT     Strange end-to-end DFA checking: offset of DFA from component when in user pick) E$ n( a% q: K% O! B% |3 e1 }! A& d
    2016421 ALLEGRO_EDITOR     PLACEMENT     Fail to place symbols because definition is incompatible for attribute 'PW_GENERATED'; @7 R- C0 y4 `9 |8 D6 u
    2016452 ALLEGRO_EDITOR     PLACEMENT     Some symbols cannot be placed due to property definition differences
    & _2 Y7 [$ e- s; `- |* x+ E% w2016527 ALLEGRO_EDITOR     PLACEMENT     PCB Editor crashes on moving all components on board
    " x+ ?3 D2 O- e% k5 o2017364 ALLEGRO_EDITOR     PLACEMENT     Strange behavior when moving component: DFA or place bound area is centered around the User Pick position
    & h5 H1 A1 q& r6 d7 n# |2018859 ALLEGRO_EDITOR     PLACEMENT     Moving parts by 'User Pick' or 'Sym Pin #' shows two component placement boundary outlines% T  N" O0 t! ~& J  r: B5 D
    2019364 ALLEGRO_EDITOR     PLACEMENT     PCB Editor stops responding when moving components- ]( {8 S$ h6 S9 H! V2 Z$ ~# a
    2019478 ALLEGRO_EDITOR     PLACEMENT     PCB Editor crashes when moving more than one component across the design" m% E! Q/ L! ]- U/ B) ^
    2019624 ALLEGRO_EDITOR     PLACEMENT     DFA Boundary is offset from definition when moving symbols with user pick9 P, D0 z( t/ A( Y/ M
    2021625 ALLEGRO_EDITOR     PLACEMENT     Graphical Issue with Edit - Move and User Pick: additional outline image shown( ^  W) C& p& m. W9 K; f# g# m( ^/ _
    2022203 ALLEGRO_EDITOR     PLACEMENT     Place bound outline is shown at the center of the pick when moving a part by User Pick( o# p8 A3 M& |) T0 z9 q
    2024655 ALLEGRO_EDITOR     PLACEMENT     Moving multiple components causes PCB Editor to crash" T8 d% O1 m( C5 t& U/ |
    2025895 ALLEGRO_EDITOR     PLACEMENT     PCB Editor stops responding when multiple symbols are moved and on getting too close to another symbol
    . ?& C" X5 {. n3 v2004497 ALLEGRO_EDITOR     SHAPE         Automatically deleting antenna shape is not deleting thermal reliefs associated with those shapes
    0 ~. A! o8 P: I" B1 p6 |2007832 ALLEGRO_EDITOR     SHAPE         Cannot void shape properly after rotating symbol
    * l6 {" C" s) O& Q! Y# f2009601 ALLEGRO_EDITOR     SHAPE         Error for shape created using third-party SKILL utility7 Q0 H+ @0 t+ m+ n
    2010924 ALLEGRO_EDITOR     SHAPE         Dynamic shape does not void in route keepout areas: q7 _0 y, M: S4 I0 u$ \
    2011176 ALLEGRO_EDITOR     SHAPE         Nothing happens on choosing 'Shape- - Change Shape Type' in Allegro Sigrity SI
    ; o* u# ~/ D0 E3 M; v2015446 ALLEGRO_EDITOR     SHAPE         Thermal relief connection created for static shape covering pin when inside a void in a dynamic shape.
    , J& n! H, v+ L2017273 ALLEGRO_EDITOR     SHAPE         Same net spacing does not void properly for shape to hole.) y5 s  ~' c( i+ W# d/ z6 d6 s$ H
    2012878 ALLEGRO_EDITOR     UI_FORMS      Custom toolbars cannot be loaded as size differs for customState and customExteded in registry
    2 d3 `4 g* t( B7 O. [% |) J1 @2018177 ALLEGRO_EDITOR     UI_FORMS      Custom toolbars cannot be loaded as size differs for customState and customExteded in registry' Z7 P& {+ ^7 J. G1 G* d& n$ {
    2019437 ALLEGRO_EDITOR     UI_FORMS      Custom toolbars cannot be loaded as size differs for customState and customExteded in registry
    ) ~4 d; x/ W" F3 l2020491 ALLEGRO_EDITOR     UI_FORMS      Cannot load custom toolbars because the customState and customExtended Windows Registry entries are incorrect; a% b) ?! w0 q- ~, k# x
    1897843 ALLEGRO_EDITOR     UI_GENERAL    Function Keys, such as F3, F6, and F7, are not working if tool is idle for some time
    - f$ A6 x$ u0 V2000445 ALLEGRO_EDITOR     UI_GENERAL    Funckeys not working in hotfix 048 with the new Command Pane as default
    2 y+ k/ u9 [+ n: _8 u3 H2001847 ALLEGRO_EDITOR     UI_GENERAL    Ctrl related funckeys not working in hotfix 048
    & Y4 w4 K+ W  n2008112 ALLEGRO_EDITOR     UI_GENERAL    Funckeys using Ctrl and Shift do not work in hotfix 048 (QIR 7)
    8 ]( ?" A& b! D2 h5 g2010370 ALLEGRO_EDITOR     UI_GENERAL    Shift + arrow key does not move component in release 17.2-2016, hotfix 0488 a( M9 t/ U# P$ m$ `, W& ~. T
    2015418 ALLEGRO_EDITOR     UI_GENERAL    Funckey not working
    3 P* U4 b1 r  I% M0 R8 W; W0 S- X2015443 ALLEGRO_EDITOR     UI_GENERAL    Text does not regain focus even on clicking after using a drop-down menu1 @) x4 ~, r1 _
    2016899 ALLEGRO_EDITOR     UI_GENERAL    Dynamic zoom and funckeys are disabled after clicking a combo box in the Options pane
    3 `, J/ D. n, w/ Y- N2019753 ALLEGRO_EDITOR     UI_GENERAL    Infinite Cursor disappears regularly in hotfix 049 when infinite_cursor_bug_nt is set" C( w$ T0 c* ^( R8 G* t1 C% y
    2019990 ALLEGRO_EDITOR     UI_GENERAL    Mouse over does not highlight pin, need to click
      m$ S! M& J/ c0 ~2020162 ALLEGRO_EDITOR     UI_GENERAL    Funckeys not working in hotfix 049: pressing F4 not running Show Element
    $ ]' w% _8 o0 R6 v$ G" X# X; o- `2020168 ALLEGRO_EDITOR     UI_GENERAL    Data tips not shown on mouse hover
    $ m$ [8 c7 B3 x' w2 H$ G; G2020840 ALLEGRO_EDITOR     UI_GENERAL    Page-up/Page-down (remapped to zoom-in/zoom-out) stop working until mouse scroll button is pressed
    # K* K# @! I' f9 ]/ ^2021416 ALLEGRO_EDITOR     UI_GENERAL    New user interface does not shift input focus and zoom in/out does no longer work in layout window- ^3 w( Y8 m% h% N7 T7 Z
    2022185 ALLEGRO_EDITOR     UI_GENERAL    Ctrl related funckeys are not working
    & a  o1 b( [5 ~2023402 ALLEGRO_EDITOR     UI_GENERAL    During Add text, focus does not move from the subclass dropdown to the canvas.
    , D/ t' F  c% r8 t2025806 ALLEGRO_EDITOR     UI_GENERAL    Function keys and shortcuts not detected, ]% u1 @" |( O1 ^, x8 u, G& [0 Z
    2027581 ALLEGRO_EDITOR     UI_GENERAL    Funckey problem: focus lost from canvas on using another window
    7 w' l+ @' D! V! v2009382 ALLEGRO_EDITOR     ZONES         When deleting zone by Zones - Manage, the shape in zone is out-of-date9 U* t/ [) q. G! L
    1977211 APD                DXF_IF        APD: die pads shift after export DXF
    & T" i( @& c' J1 I& G6 D* Z1 H2018483 CAPTURE            NETLISTS      Error when extracting netlist from schematic (ORNET-1193)
    * m- Z! C% W% O! F1 e4 T, j4 M2022764 CAPTURE            NETLISTS      Schematic will not generate pstchip.dat file+ a- ~! I, m, T+ _
    1921557 CAPTURE            NEW_SYM_EDITO Zoom to region option grayed out
      l& K  P6 ]$ c8 y# {: U/ R6 @, s4 E# f1945203 CAPTURE            NEW_SYM_EDITO Symbol Editor: No Zoom to Region and cannot edit Pin Type and User Pin Properties for multiple pins! B8 Q& ~) \- e+ ^  `! k) [3 \' @9 {
    1950178 CAPTURE            NEW_SYM_EDITO Ability to remove convert view of a component0 J2 u" E% Z  i( x5 P9 V0 N
    1966792 CAPTURE            NEW_SYM_EDITO JavaScript error on trying to edit pin name for GP0
    ( Y0 L$ Z" @0 H: L; [4 C1969099 CAPTURE            NEW_SYM_EDITO Cannot add convert view after creating a part
    1 k. F7 G. h3 \1969834 CAPTURE            NEW_SYM_EDITO Shapes not mirrored around center if more than one shape selected in Symbol Editor
    7 W9 n7 W! C1 M' G# j# b' N& O4 H1970984 CAPTURE            NEW_SYM_EDITO New part is getting Numeric Numbering automatically
    ' N) d2 h) B3 @! S; i# B$ t7 z1972607 CAPTURE            NEW_SYM_EDITO New Symbol Editor: name cannot be edited unless value is entered for a new property
    ; {( Y# B# v' t; q1972635 CAPTURE            NEW_SYM_EDITO New Symbol Editor: wrong listing of Symbol Properties in right pane4 Z4 r4 z! S( g' C' n2 X0 v& r
    1974296 CAPTURE            NEW_SYM_EDITO Design Template font settings are not being honored for new library/part creation7 I" [$ X/ W3 v) G1 h: @$ o
    1982783 CAPTURE            NEW_SYM_EDITO Part Editor is blurry when zoomed out.
    4 s, q5 Z5 w3 g1993361 CAPTURE            NEW_SYM_EDITO Cannot change part numbering, set to Numeric by default
    2 W( \1 r8 C8 M) O& t2003749 CAPTURE            NEW_SYM_EDITO Cannot save edits to hierarchical blocks in new Symbol Editor in hotfix 048  B; y, l8 L$ i0 ^/ n( U4 E7 U$ b
    2004395 CAPTURE            NEW_SYM_EDITO 'Pin ignore' modifications not saved in new Symbol Editor 'Edit Pins' after hotfix 0488 n, d# s3 e5 j& Q* q
    2007747 CAPTURE            NEW_SYM_EDITO Cannot add Convert View after creating a part
    4 D( D4 @" M, n' o. O2011321 CAPTURE            NEW_SYM_EDITO 'Place - Picture' is not working for blocks in hotfix 048
    . g4 H5 M* Z; O5 J2013146 CAPTURE            NEW_SYM_EDITO 'Part Edit' not updating changes in hierarchical block8 D; `) e" P& B$ U8 I: ~
    2002904 CAPTURE            OTHER         Unable to check out Capture license in release 17.2-2016, HotFix 048# ]: d. ?  q1 l, u  T
    2002922 CAPTURE            OTHER         Unable to check out Capture license in release 17.2-2016, HotFix 048
    ( l$ d3 x7 m. {! E9 k1988812 CAPTURE            PART_EDITOR   Parts created or edited with hotfix 038 Part editor do not use default font size9 p/ E$ u( Q/ E, `& y+ W+ i, d2 j
    2008912 CAPTURE            SCHEMATIC_EDI Design Compare shows 'NaN' in the graphical output( a- H% R% B9 C1 b) W$ Y. J
    1985701 CONCEPT_HDL        CHECKPLUS     Library symbols are missing from the examples folder
    ( w4 K/ F- i3 v5 ]" b1933789 CONCEPT_HDL        CORE          honor_sch_custom_texts
    # @6 l3 [4 [! @7 x# w1 g4 I1933892 CONCEPT_HDL        CORE          HONOR_SCH_CUSTOM_TEXTS
    , {" ?1 Z  Z) `+ }2001737 CONCEPT_HDL        PDF           DE-HDL crashes on choosing File - Publish PDF( ~# Y# v& K% w3 u2 l& e' n9 w
    2010508 CONSTRAINT_MGR     CONCEPT_HDL   Schematic data corrupted on reading the data from CM database using the CM SKILL APIs. }0 @5 d( @+ x. y& D3 ]- x# f
    1997461 PSPICE             AA_FLOW       'Edit PSpice Model' from 'Assign Tolerance' window does not work  I! O/ \/ ]# f) U
    2005948 SIP_LAYOUT         DIE_EDITOR    CTE expansion tool shifts pins off the die! E. x; M# V$ O+ X
    1893045 SIP_LAYOUT         INTERACTIVE   Refreshing bond finger labels causes all the labels to shift location! c8 }- V  z+ v. H
    2006926 SIP_LAYOUT         ORBITIO_IF    Bundle translation from OrbitIO is incorrect
    " ?( O: F% e+ I, D( m' P3 |; H2006659 SIP_LAYOUT         SHAPE         Cannot form fillets inside a shape in hotfix 048
    & R+ C4 G* l9 T1969192 SYSTEM_CAPTURE     CANVAS_EDIT   Pin Numbers of Discrete Symbols visible
    : t% p' }: Z. Q2 [' y" y, z1982368 SYSTEM_CAPTURE     CANVAS_EDIT   System Capture switches to Auto Pan, even if the option is disabled, in the Notes mode
    ) G9 I+ ~- h/ V- d# }7 G1995012 SYSTEM_CAPTURE     CANVAS_EDIT   Connect lines do not move with components% C6 E9 r3 U' u* ?& }+ c/ u: F
    1907992 SYSTEM_CAPTURE     CONNECTIVITY_ Draw stubs is not respecting stub length setting.1 H: M" _6 C4 c  p/ n; C
    1960100 SYSTEM_CAPTURE     CONNECTIVITY_ Moving components after routing failure:  connect lines do not move resulting in disconnected route
    , m# }. _- ]8 C4 |6 K% P- q( t1988284 SYSTEM_CAPTURE     CONSTRAINT_MA Log files and topology files are being stored at the top-level design (CPM) folder level/ N0 }- p. y. V$ O
    1996039 SYSTEM_CAPTURE     COPY_PASTE    Cut and Paste change the pin numbers for connector after saving design.
    : W. n/ p$ \1 n) l1951700 SYSTEM_CAPTURE     EXPORT_PCB    System Capture: Export Physical - Change Directory UI entry block not displaying properly
    9 U/ ~+ u( ~; n, n" H0 G1970761 SYSTEM_CAPTURE     EXPORT_PCB    Cannot import System Capture netlist if PCB Editor is launched with -proj argument- O9 C. }1 g- Q. f" A
    1997533 SYSTEM_CAPTURE     IMPORT_PCB    Pins do not swap in System Capture on backannotation* e9 [) a, q' t9 C$ i
    1910962 SYSTEM_CAPTURE     MISCELLANEOUS Dragging GND symbol placed on a pin sometimes disconnects the GND symbol
    $ M- u1 K9 X8 e& C- k& v* E1962037 SYSTEM_CAPTURE     TABLE_OF_CONT Table of content link number not same as page number in the title block, i* L8 [- S. H* n5 w
    1986317 TDA                SHAREPOINT    Cannot enable Design Management and SSO session expires9 [# N7 J0 v5 E9 |
    , x* Z  C. Z1 n; f* c1 J- D

    - f4 l6 K7 W) I. UFixed CCRs: SPB 17.2 HF0498 f% y/ p& u7 a( ]; F' `) a
    11-16-2018) N5 z) r6 G7 f, o- W6 p8 ^7 g
    ========================================================================================================================================================+ Q/ d! @2 W- P/ t, c8 Q0 u( v: L
    CCRID   Product            ProductLevel2 Title( ?% c( n# }3 u* @: U2 W
    ========================================================================================================================================================
    5 K0 e% c! X! [1 e6 E2002642 ADW                ADWSERVER     Exception in adwserver.out with LDAP enabled
    - w- g- h$ S! S# X1 _2007046 ADW                ADWSERVER     Component Browser is not connecting to server in hotfix 048
    6 D7 @$ \( L5 z8 H1997678 ADW                DBEDITOR      Model not deleted due to missing cell model relation
    ; P1 ~* J% _0 U% N9 \1985059 ADW                FLOW_MGR      Flow Manager issues warning about project path that contains a period, removes from catalog file
    % N+ ?& [8 H6 Z7 ]2 t7 x/ F1991515 ADW                FLOW_MGR      Flow Specific Tools: Launch error after upgrading to Hotfix 044 and extending code. x$ J6 E# i- _- S
    1972762 ADW                PART_BROWSER  The Schematic Models icon does not match the definition in EDM Component Browser
    ! o% L+ L5 Z6 H1830062 ALLEGRO_EDITOR     DATABASE      Uprevving release 14.0 design with stand-alone DBDoctor in release 17.2-2016 crashes; works in release 16.6
    " m) q0 A* _% B7 A0 D0 p1980161 ALLEGRO_EDITOR     DATABASE      NODRC_ETCH_OUTSIDE_KEEPIN assigned to text in library part is not passed to PCB Editor
    , C- m, F. F- d+ k9 w2003757 ALLEGRO_EDITOR     DATABASE      Open circuit not detected by PCB Editor: reports unconnected pin as connected: S( q. G6 m; Z2 f$ v2 f; ?! |
    2009748 ALLEGRO_EDITOR     DFM           PCB Editor crashes on Update DRC
    ! P5 U% m# g3 J3 E' p7 Q1796895 ALLEGRO_EDITOR     DRC_CONSTR    Increase precision of Inter Layer Spacing check6 t# n) ^( v  x
    1997487 ALLEGRO_EDITOR     DRC_CONSTR    Cannot add teardrops to some pins4 B% m2 ?' Z0 X8 b/ d. I
    1857024 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashes on using funckey 'y FORM mini padstack_list -+'! P4 H7 r6 h. }$ B2 Y% v: J& b: k
    1979750 ALLEGRO_EDITOR     INTERFACES    axlStepSet not working for component definitions; S  t# W* W. H$ x3 ]& F
    1988168 ALLEGRO_EDITOR     MANUFACT      Graphical Compare in productivity toolbox terminates with errors
    3 I0 N4 l' J% ^& t! d: Z1982233 ALLEGRO_EDITOR     SCHEM_FTB     Netlist files cannot be imported into board as the process is not finishing+ ?: W, ~# R& @1 z" ^# o3 ^* {
    2000367 ALLEGRO_EDITOR     SCHEM_FTB     Cross-probing between OrCAD Capture and PCB Editor does not work in HotFix 048. C" x: y& `0 S( L- P
    2000397 ALLEGRO_EDITOR     SCHEM_FTB     Cross-probing not working with hotfix 048' E  n  w, i6 ]
    2000552 ALLEGRO_EDITOR     SCHEM_FTB     Cross-probing is not working if we are importing Netlist from PCB Editor6 Y1 {+ a2 n! }  L+ {
    2001165 ALLEGRO_EDITOR     SCHEM_FTB     Cross-probing between Capture - Allegro PCB Editor fails after hotfix 048
    + f4 h% @( A; f, r2002635 ALLEGRO_EDITOR     SCHEM_FTB     Cross-probing issue because of Unique MPS Session in HotFix 048 (QIR7)' }  b) p" I$ o
    2004252 ALLEGRO_EDITOR     SCHEM_FTB     Cannot do cross-probing between Capture and PCB Editor
    , [: J9 L$ C  s0 p, I0 N# P( Y/ T2004305 ALLEGRO_EDITOR     SCHEM_FTB     Inter-tool communication is not working properly in PCB Editor release 17.2-2016, hotfix 048
    5 M0 J' B3 C5 a' k1978660 ALLEGRO_EDITOR     SHAPE         Static shape on dynamic shape issue: thermals not removed when component is moved
    6 z9 M) T# c/ L2 ^1985035 ALLEGRO_EDITOR     SHAPE         Thermal reliefs not removed on moving parts
    & W$ {5 q; F% ?1 g$ @1960966 ALLEGRO_EDITOR     SKILL         Stackup import is not working in release 17.2-2016 via automation8 c' ^5 P# M$ l, b. p# b" s% Y
    2003651 ALLEGRO_EDITOR     UI_FORMS      Error on starting and loading footprints in hotfix 048: message about customExtended and customState
    % {7 p( W; K$ Y- L1 O( w2003810 ALLEGRO_EDITOR     UI_FORMS      OrCAD layout editor font size is too small for almost all UI
    0 @7 A; r% x8 i$ Y' X% H( C) o! ^2003832 ALLEGRO_EDITOR     UI_FORMS      Error on loading footprint in hotfix 048: custom toolbar cannot be loaded due to registry problem
      }$ r0 ?9 b; S. l; r8 C2004769 ALLEGRO_EDITOR     UI_FORMS      Custom toolbars cannot be loaded as the size of customState and customExtended differs in registry8 `/ p3 \1 X- q; B1 K/ L
    2007669 ALLEGRO_EDITOR     UI_FORMS      Broken scalability between OrCAD PCB Editor and Allegro PCB Editor% l" S2 k* r  H  H+ h2 N
    1987164 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor stops responding when multiple sessions are accessing third-party tool  A$ |  Q; _6 I4 L7 p& a; S. i
    1983512 ALLEGRO_PROD_TOOLB CORE          Allegro Productivity toolbox: Advanced Testpoint Check is not working9 ]" P2 }6 Q- n6 g; g. w
    1996008 APD                3D_CANVAS     New 3D Canvas does not work in APD' K7 Q5 i4 ^) B6 U! k& e
    1993698 APD                SHAPE         APD stops responding and database is corrupted on moving, deleting, or updating a symbol" k; k5 H: }+ O9 {* h
    1999446 CAPTURE            OTHER         Update symbol database in Trial
    4 D, D9 t' A) z; E1962222 CONCEPT_HDL        CORE          Nested hierarchy block RefDes transfer issue: suffix added to RefDes; _9 z% _  Y+ _3 y
    1964260 CONCEPT_HDL        CORE          RefDes not updated in a hierarchy block on repackaging release 16.6 design  j. r, ]3 S, ]6 ^  `; ~
    1972243 CONCEPT_HDL        CORE          Version filter does not work correctly+ x, H' N  ?. X+ P2 j) v( \; z2 V) X
    1993448 CONSTRAINT_MGR     DATABASE      CSet is duplicated with same name when modified in SigXplorer: a9 u9 @, A! N* e# p9 q
    1976148 CONSTRAINT_MGR     INTERACTIV    DRC worksheet in Allegro PCB Editor: 'Go to Source' flickers worksheet and does not switch) I, a0 w0 q' Y2 M7 w) q0 e( P- q
    1948372 CONSTRAINT_MGR     UI_FORMS      cmDiffUtility fails to compare and gives the message 'Failed to read the configuration file'
    1 ]  e$ W$ J' X/ p# _1961750 EAGLE_TRANSLATOR   PCB_EDITOR    Voids and some shapes of third-party board not translated correctly) z1 l8 s; M! G+ h* Z/ `% X
    1984569 FSP                DECAP         When a pin function is in an interface or custom connector is changed, decaps defined for the part is deleted
    * n) @0 z6 v9 V1984588 FSP                DECAP         FSP crashes when changing pin functions or bank settings for a connector
    3 ~7 A  s% ~; J1 [5 j0 ~6 I- J1984590 FSP                DECAP         FSP design fails to load if pins are defined with a pin function that is later changed in custom_connector.crf& d. J- w0 G" {
    1985555 PCB_LIBRARIAN      IMPORT_EXPORT JavaScript exceptions on opening libraries converted using con2cap
    $ F$ a8 N! Q# j" x1961944 PCB_LIBRARIAN      SYMBOL_EDITOR Hide symbol outline in new Symbol Editor2 o, ?) f3 P0 e( d% u
    1967532 PCB_LIBRARIAN      VERIFICATION  libimport fails with ERROR(SPDWPAR-102): Metadata has the ErrorStatus value set.) _6 D& Q% ?4 {8 C* N0 Z; e3 z
    1976965 PSPICE             SIMULATOR     PSpice 'Tools - Generate Report' not working in release 17.2-2016
    9 X5 o" L) j. m1982260 RF_PCB             FE_IFF_IMPORT Unable to successfully pull in .IFF file created in ADS.1 U- c6 @7 b3 }# F7 P
    1981585 RF_PCB             LIBRARY       Cannot load RF symbol via2 into PCB Editor
    8 n2 ?& r: w% Z- @$ H# r: `' c- w1 B1 Q1976845 SIG_EXPLORER       OTHER         CPW trace models do not solve in SigXplorer after changing some trace parameters7 }; t0 z$ `8 K7 T+ B0 d
    1986466 SIG_INTEGRITY      OTHER         Delay in Relative Propagation Delay worksheet is displayed as a negative value
    $ g" Q6 k5 {" Z& g4 D1980264 SIP_LAYOUT         INTERACTIVE   SiP Layout crashes on running 'Manufacture - Documentation - Display Pin Text'
    & W( \6 C+ u; Z2 F3 o$ x4 |1983381 SIP_LAYOUT         REPORTS       Incomplete Design Summary Report8 l2 y- J! Y0 N8 _
    2005709 SIP_LAYOUT         SHAPE         Dynamic shape voiding around same net cline segment: no property attached% z( |* O7 S, M
    2008064 SIP_LAYOUT         SHAPE         Hotfix 048 (QIR 7): Shape creates void for same net cline, it should be shorted
    8 w% ~! A; w* y6 o9 G- T( a1980967 SYSTEM_CAPTURE     CANVAS_EDIT   System Capture does not reflect part symbol changes, A5 f) j  s( Z9 A
    1988928 SYSTEM_CAPTURE     CANVAS_EDIT   Changing version 2 of the resistor part makes the PART_NUMBER property visible
    ) o; Q$ d& S1 J. h6 j1990215 SYSTEM_CAPTURE     CANVAS_EDIT   Draw Multiple Bits: Bits do not follow mouse smoothly, c5 \- [7 ^0 i" R
    1972658 SYSTEM_CAPTURE     EXPORT_PCB    Modified injected properties do not get updated in the pstchip.dat file after running Part Manager and Export Physical
    , d( U9 O* J. O/ V( I9 S+ R1989421 SYSTEM_CAPTURE     EXPORT_PCB    Part Manager does not update the PTF values
    ' d% N7 ?2 y' A6 ^4 v9 s1992407 SYSTEM_CAPTURE     PART_MANAGER  Part Manager removes part properties and main window and details window updates are inconsistent
    ! u  c4 |7 x; r0 {7 p5 l% Y# w5 w% O

    - e' Q5 V# [6 z9 q) @  L: bFixed CCRs: SPB 17.2 HF048
    4 F6 J2 S* `$ U1 J  ]10-13-2018
    + f5 b' P  e- I0 K. |: R1 K; D5 a========================================================================================================================================================" R& V$ K) ~5 k& s4 X% ^
    CCRID   Product            ProductLevel2 Title1 S) {9 m/ l, l2 l0 t
    ========================================================================================================================================================; E0 J! E+ f5 Y' g1 h  Y
    1913039 ADW                ADWSERVER     EDM Library Server exits with error message on starting library server service
    8 n% T0 |- H0 W8 I( Q$ V1709155 ADW                COMPONENT_BRO Search query does not search for all the parts in the library6 P, t" I4 J' S) k+ {3 z) s6 h
    1827231 ADW                COMPONENT_BRO Clicking the 'a' key in Part Manager launched from DE-HDL crashes DE-HDL
    + @: Y) Y  j9 c3 E0 m, T4 R2 N% B1903818 ADW                COMPONENT_BRO Parts that have comment_body do not display version/ O, a) x5 Y3 g8 o0 k
    1917961 ADW                COMPONENT_BRO Component Browser PPL column values are truncated when selecting the top '*' filter
    4 Y3 G5 m! |' t& ?+ F1938172 ADW                COMPONENT_BRO Symbol version with COMMENT_BODY set to TRUE cannot be instantiated6 g: J# Z6 j( z/ ?' u
    1914103 ADW                CONF          conf creates incorrect path in fetch_dump.ini when MLR is enabled.3 x' E) o/ Y: Q& m2 V. T) \4 i
    1911422 ADW                DBADMIN       RuleP101 - PACK_TYPE check against schematic model not working
    2 A. p* E- \0 D1 ^1926691 ADW                DBEDITOR      Adding a new classification and immediately trying to delete it results in errors- Q2 U% y. s; l- Q+ u2 W% @& m
    1926694 ADW                DBEDITOR      Renaming a classification and then renaming it back to the original results in error
    . I' @7 x1 m: G# _" {/ J) j1934870 ADW                DBEDITOR      Adding a new classification and immediately trying to delete it results in errors" u* R8 O- E5 x8 T
    1872387 ADW                DSN_MIGRATION Design Migration does not cache all used parts into flatlib/part_table.ptf3 m" p5 j8 }! g4 W$ p: D
    1254292 ADW                FLOW_MGR      Flow Manager Open Last Project should open last project closed: Z6 ?9 A2 n0 T- d
    1281817 ADW                FLOW_MGR      '-proj' switch in 'pcbdw_fm' does not work; launches Flow Manager without loading any project
    % t7 P7 n5 m# m' p: R- E' P* w1727286 ADW                FLOW_MGR      Product options for PCB SI and Power Integrity are incorrect in the flow and tool launchers
    " A: H, {3 K; D5 ~( L1 r" K% i1875498 ADW                FLOW_MGR      EDM fails to open or becomes unresponsive.: R$ R( A$ Z8 X4 i
    1879386 ADW                FLOW_MGR      Unable to access COS with the default Firefox version in the 17.2 installation9 p' Y! h7 B, |* q, d9 Q8 _% r
    1922541 ADW                FLOW_MGR      Warning message for unavailability of Java version appears on opening a project on Linux
    + }0 }8 @" M! `" F! h7 b( y1945451 ADW                FLOW_MGR      Checklist does not work with two-byte characters3 s( d0 F% k. m5 F; m2 |% f6 O4 I
    1956213 ADW                FLOW_MGR      Not able to invoke Flow Manager on the remote system
    . X% E  q. W) ^4 r7 W. G" l+ W; x1892285 ADW                LIBDISTRIBUTI Symbol not consistently available in 16.6 ADW Library+ h; V) w+ m( `7 y
    1961731 ADW                LIBIMPORT     libimport fails to create tar for two Capture models% k9 K( q1 q) R. l
    1836620 ADW                LRM           Library Revision Manager crashes on clicking Help0 S8 S9 c  H0 |4 \( X
    1961845 ADW                PART_BROWSER  Error regarding environment variable; f1 d7 y% ~7 a: Y; R8 d. a  F+ K
    1890782 ADW                TDA           Launching TDO dashboard connected to PLM returns a license error
    ! }' h' F" K' k; T1980914 ADW                TDA           Cannot start Design Entry HDL and Component Browser in a TDO design% o8 T' \5 |* [% V0 I: I7 C9 O" b
    1833750 ALLEGRO_EDITOR     3D_CANVAS     Soldermask Text is not shown in 3D Canvas
    ; w8 O4 K7 R9 F& ~1891230 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas Viewer not bending PCB with proper radius
    3 q4 L7 U$ @9 C* x) G7 ?/ V$ ^4 t1913338 ALLEGRO_EDITOR     3D_CANVAS     STEP models missing from exported .stp file
    $ {. ~# O7 |+ {; x& ?# W3 q1927507 ALLEGRO_EDITOR     3D_CANVAS     Get Error: All bend operations are disabled due to licensing and/or DLL installation issues on invoking 3D Canvas
    * ?( R6 z0 ]! G4 I1931508 ALLEGRO_EDITOR     3D_CANVAS     Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas( X) ^$ T( P' v2 Y
    1943060 ALLEGRO_EDITOR     3D_CANVAS     Placebound bottom is not showing correctly.8 C! F5 a1 t" `% }# }, ^! N
    1950099 ALLEGRO_EDITOR     3D_CANVAS     Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas2 o8 @+ }  P1 y/ [: e' N' L
    1988307 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation8 ^$ g$ s3 H, T5 B5 f9 s
    1923585 ALLEGRO_EDITOR     ARTWORK       Additional unwanted subclasses appear in film control when a new film definition is added
    # N$ y; k: C" H& `9 E1944079 ALLEGRO_EDITOR     COLOR         Export of Board Parameters (Net Colors) does not contain entries for nets with spaces
    ; v, R9 j; j) m1 S" ]1856320 ALLEGRO_EDITOR     DATABASE      Donut pad fails to connect with cross-hatched shape in full contact thermal mode, despite hatch overlap of donut.
    * E) X7 ~! Y  k4 ], Z1912313 ALLEGRO_EDITOR     DATABASE      Database corrupted during background process
    % `7 `! f% n6 ]' B; l9 S- M" m1913344 ALLEGRO_EDITOR     DATABASE      When changing accuracy of design, the thermal relief for donut pad's outer pad connects to inner pad# I9 ]; m7 p5 t) s& y
    1914470 ALLEGRO_EDITOR     DATABASE      Release 17.2-2016: export libraries command does not inherit posi/nega information
    + S, W( g# D; X% W% ~5 t" O, B1932086 ALLEGRO_EDITOR     DATABASE      Unable to resolve DBDoctor error
    ( {& ?  p3 m& w- |0 [) |1963932 ALLEGRO_EDITOR     DATABASE      DB Doctor is not recognizing placed parts and showing them as unplaced.' L# z0 I! m" ^) M# d
    1987735 ALLEGRO_EDITOR     DATABASE      Interior sub-lamination backdrill holes are displayed with Top Soldermask pads where backdrill does not exist
    2 A, Y% G3 q" [& h, d1977622 ALLEGRO_EDITOR     DFM           Not able to add value '5' or multiples of 5 in in DFF constraints for maximum stacked via count# o$ h7 j% P  s$ I1 f
    1892809 ALLEGRO_EDITOR     DRC_CONSTR    NODRC_ETCH_OUTSIDE_KEEPIN property is not working on TEXT$ H& {" l4 U5 g- |5 j$ w3 I; m- k' V! Z
    1894765 ALLEGRO_EDITOR     DRC_CONSTR    DRC for no_drc_component_board_overlap is not created if the place bound is outside Place Keepin- C7 F) j- W9 D' t( [* X
    1896627 ALLEGRO_EDITOR     DRC_CONSTR    Moving components takes long time while doing placement0 g2 k0 d- |2 Y! @
    1914591 ALLEGRO_EDITOR     DRC_CONSTR    Spacing constraints for Mechanical to Hole shows resolved constraints different from the actual air-gap/space
    7 g1 a$ W; _, Q. n* d7 B0 Q& X$ E1956468 ALLEGRO_EDITOR     DRC_CONSTR    DRC getting generated while moving the uvia and getting removed after updating DRC.' T1 V* G  `$ U, P4 x( v8 y
    1884149 ALLEGRO_EDITOR     EDIT_ETCH     Arced Routing of differential pair creates unexpected arc radii
    ; o+ D4 C. d4 ^- ~, T1891985 ALLEGRO_EDITOR     EDIT_ETCH     Etch edit does not follow the constraints
    4 Y3 v, M: C9 Z! @  \& I8 }1860056 ALLEGRO_EDITOR     GRAPHICS      PCB Editor crashes on right-click after choosing the Move command9 }; i) i* p: H4 o* `8 Z' J' \  Z) b
    1860723 ALLEGRO_EDITOR     GRAPHICS      APD crashes on right-click when using the Move command: R% V% f/ K, c
    1870058 ALLEGRO_EDITOR     GRAPHICS      PCB Editor crashes when using Place Manual -H command7 s. y$ N3 e5 o8 j  a. J) p
    1930282 ALLEGRO_EDITOR     GRAPHICS      PCB Editor crashes on executing axlVisibleDesign(nil) from allegro.ilinit5 S/ ?7 v+ g3 Z  f7 f8 O) t3 n# E4 @
    1882813 ALLEGRO_EDITOR     INTERACTIV    Unable to set the end point with 'snap pick to' when adding an arc$ u9 C2 h& ~2 |8 a, P3 L3 @
    1884725 ALLEGRO_EDITOR     INTERACTIV    Edit and Move vertex operation not working as desired' N, i# u  }  ?1 F) K% F
    1902359 ALLEGRO_EDITOR     INTERACTIV    Connector boundary remains ON for a layer if visibility toggles in Shape Edit application mode: n  K% j% B* F: ~: h# c  t
    1909004 ALLEGRO_EDITOR     INTERACTIV    Parameter description showing wrong for Padless Holes under Design Parameter Editor
    4 i! X. Y, ^  m9 U( }/ }4 _1912055 ALLEGRO_EDITOR     INTERACTIV    PCB Editor crashes on Delete By Query - AutoSilkscreen - Find By Query
    ! B2 {, m0 d$ k; F: W9 S) a* b1924503 ALLEGRO_EDITOR     INTERACTIV    Editing shape causes PCB Editor to crash
    6 J2 v3 U/ P3 P/ K7 v7 z* }1929614 ALLEGRO_EDITOR     INTERACTIV    Unable to Place Via Array when Staggered ring is selected in Global Ring Parameters., I1 D/ _$ j, \9 x% O
    1938523 ALLEGRO_EDITOR     INTERACTIV    Change Shape Type message is same for dynamic and static shapes
    / v' k$ i1 b' l! L6 @1940827 ALLEGRO_EDITOR     INTERACTIV    Irrelevant/incorrect warning message when doing Edit- Change on Clines
    4 {4 j: H9 v& [. K! Y6 f! }5 f1872653 ALLEGRO_EDITOR     INTERFACES    DXF export shows embedded layers in the layer configuration file1 a; h" z# [3 F8 e7 {6 F
    1873971 ALLEGRO_EDITOR     INTERFACES    IDX proposal comments are not shown when importing the IDX file into Allegro
    - @. Q5 S; \: i1892172 ALLEGRO_EDITOR     INTERFACES    STEP Package Mapping form needs to be larger$ E: K' t7 W( y. x$ v: J
    1893311 ALLEGRO_EDITOR     INTERFACES    A line became two lines after import dxf
    + z2 r( ~6 r1 q, x. x0 r1937816 ALLEGRO_EDITOR     INTERFACES    Unit as % in Property Definition not supported by SubDrawing
    / e1 ^: C! m' F0 P5 e1973084 ALLEGRO_EDITOR     INTERFACES    Physical library not placed if design and IDF database not matched while running! B) Y/ Q0 f0 V. R
    1987526 ALLEGRO_EDITOR     INTERFACES    IDX import Fails to recognize SURFACE FINISHES Class! c/ @. k# o, t+ X
    1872856 ALLEGRO_EDITOR     IN_DESIGN_ANA Message displayed when creating directed groups needs to be improved
    5 {3 A) n) _8 B" x1900832 ALLEGRO_EDITOR     IN_DESIGN_ANA RTP: Return Path DRC does not check circle void correctly
    ) H) _; ~8 L& Z  u% Y1935641 ALLEGRO_EDITOR     IN_DESIGN_ANA Return path DRC crashes PCB Editor# Z: l/ H7 h# D0 H/ _& b- G
    1649465 ALLEGRO_EDITOR     MANUFACT      Manufacturing options are not visible in OrCAD PCB Designer legacy menu5 `& u! e: U+ F
    1873417 ALLEGRO_EDITOR     MANUFACT      Autosilk fails to add line information. Only part of the line is getting copied to the autosilk layer.( P) p. b! H2 ]$ f) I
    1911596 ALLEGRO_EDITOR     MANUFACT      Documentation Editor drill chart shows two different rows for the same slot.
    4 L6 ]5 x& s, w  F/ [1937721 ALLEGRO_EDITOR     MANUFACT      Drill figure character scaled up in GERBER4 h* Y. g% z" O2 Z$ F2 r2 `+ g
    1957768 ALLEGRO_EDITOR     MANUFACT      Import IPC2581 on cross-section does not import line width and impedance3 N7 }& g- s. l$ W1 A# m+ E5 B6 S8 i
    1969363 ALLEGRO_EDITOR     MANUFACT      Pressfit connector backdrill depth is considering MNC Layer
    ' L; W/ `' g! s/ G0 l$ V1891102 ALLEGRO_EDITOR     MULTI_USER    Rejected by server error messages when using Symphony Team Design, a$ R6 ?% `% t) t. \- F# R# G
    1928082 ALLEGRO_EDITOR     MULTI_USER    Unknown SubClass BOUNDARY/MULTI_USER_LOCK automatically added when defining Artwork Output.( E# m& A4 C' j/ X. z
    1976705 ALLEGRO_EDITOR     MULTI_USER    Symphony client disconnects from server without any notification - despite ping mechanism9 D8 s: f7 {9 J" R! s6 F8 R9 `9 j$ r  n8 E
    1972554 ALLEGRO_EDITOR     NC            Mill symbol moved from Nclegend-slots-1-2 to Nclegend-1-2 subclass if nc_param.txt not present+ R8 v, i/ a, n' e& G5 a6 X/ e& P
    1914412 ALLEGRO_EDITOR     OTHER         Autosilk lines do not clear padstacks that are not rectangular3 `4 N8 A5 S/ p: E( Z. \% P
    1921933 ALLEGRO_EDITOR     PAD_EDITOR    column clearance cannot reset to 0 in padstack editor
    . Q$ [3 c* n, ?9 k! L! r+ w1922234 ALLEGRO_EDITOR     PAD_EDITOR    DBDoctor reports 'illegal value for pad' and does not fix when zero corner radius for Rounded Rectangle is defined& a  o' ^+ `! E* t2 a: v
    1932183 ALLEGRO_EDITOR     PAD_EDITOR    Drill Symbol information not exported in Padstack XML if Drill Figure in none
    / E7 p* T9 z/ A& C  n& ?1934880 ALLEGRO_EDITOR     PAD_EDITOR    Shapes with offsets not displaying properly in Padstack Editor views2 n; P6 @9 ]. q5 k3 T( k) F+ ~
    1813270 ALLEGRO_EDITOR     PLACEMENT     When a place replicate module is updated, the vias used in thermal pad are removed
    % g2 g  c" L6 J1840275 ALLEGRO_EDITOR     PLACEMENT     Placing component with the Mirror option causing display problems
    ! L) H5 {/ w7 Q, N* `1854099 ALLEGRO_EDITOR     PLACEMENT     Align components to zero spacing causing mirrored components to overlap+ L0 k3 ^. C$ J5 |
    1854696 ALLEGRO_EDITOR     PLACEMENT     Pins shown incorrectly when the Alt Symbol and Mirror commands used consecutively
    . b. m% R0 Z/ _1862863 ALLEGRO_EDITOR     PLACEMENT     Too many messages in the command window when symbol does not support mirroring5 m  K2 c7 c( S+ s
    1909857 ALLEGRO_EDITOR     PLACEMENT     Using Mirror with Alt Symbol placement displays incorrect graphics
    % e( m' u5 i' Y% X( T1917128 ALLEGRO_EDITOR     PLACEMENT     Place - Autoplace - Room when all the components of the room are placed on board causing crash
    * m) r( @" Z$ y1925144 ALLEGRO_EDITOR     PLACEMENT     PCB Editor stops responding on using the Autoplace - Room command
    ; f  _& v+ i0 {2 Y, S5 v1961509 ALLEGRO_EDITOR     PLACEMENT     PCB Editor crashes on choosing Place - Autoplace -Room
    * Z; r9 r- q/ M5 u1930669 ALLEGRO_EDITOR     REPORTS       Net 'VSS' not included in the Etch Length By Pin Pair Report, r- k$ v5 `0 G& k
    1982934 ALLEGRO_EDITOR     SCRIPTS       PCB Editor stops responding if Generate button is used to create script from journal file
    6 _4 S1 M6 j; @, X# g6 `1337346 ALLEGRO_EDITOR     SHAPE         Shape Check is generating problem point errors that seem unnecessary
    ! G, _- _! W. q" }9 y1396692 ALLEGRO_EDITOR     SHAPE         Zcopy with expansion not following board outline1 A' \: D2 q& W% v
    1902001 ALLEGRO_EDITOR     SHAPE         Shape behaving differently across hotfixes: M9 n1 U, V% P
    1921287 ALLEGRO_EDITOR     SHAPE         3D canvas is showing some stray objects
    1 Z* K3 Y: V6 R. u" E1936482 ALLEGRO_EDITOR     SHAPE         Option for Fillet to not obey NO_SHAPE_CONNECT Property% N6 B7 O! J$ n: q. g
    1943899 ALLEGRO_EDITOR     SHAPE         Only one Shape to Route Keep In DRC in release 17.2-2016 compared to two in release 16.6- _- k' g" Q5 L4 S1 B
    1944041 ALLEGRO_EDITOR     SHAPE         shape_rki_autoclip makes shape voiding incorrect3 f4 e; U5 H6 [, V. O9 n3 U/ W, B
    1947675 ALLEGRO_EDITOR     SHAPE         Shape void error when dv_squarecorners is enabled. ?9 e  ?$ s8 A% M4 B
    1949250 ALLEGRO_EDITOR     SHAPE         Shapes are filled even after raising and lowering priority
    : y# C# ~' }9 Z! v% V# w5 B1984526 ALLEGRO_EDITOR     SHAPE         Same net shape voided is inconsistent with respect to vias4 j9 g# e, a- V0 x  i0 Q$ c
    1984955 ALLEGRO_EDITOR     SHAPE         Dynamic shape creating same net spacing drcs.
    ) v4 y+ _; g' j6 F$ w) C1 V1839147 ALLEGRO_EDITOR     SKILL         axlDBGetLength() reports that the segments of a filled rectangle shape are invalid database ID arguments
    ( Z$ G5 v% g( V6 ?. E1882776 ALLEGRO_EDITOR     SKILL         SKILL documentation for axlIsBetween() is wrong
    + Z; v% u. Q. K1882882 ALLEGRO_EDITOR     SKILL         Example for axlMathConstants needs correction in Allegro SKILL Reference
    1 a! F- ?, E1 A5 V  \( o; t1902712 ALLEGRO_EDITOR     SKILL         axlAltSymbolReplace moves symbol to the top of design while replacing
    ) c: p+ F+ Q$ h6 o1906329 ALLEGRO_EDITOR     SYMBOL        Mechanical Pin to Conductor property set on a pin in a symbol does not pass to the board
    - S: @- B; ~: v( q9 @/ y) H1911343 ALLEGRO_EDITOR     UI_FORMS      Global Visibility not turning all layers off2 w$ \1 A! F! P2 [! |& I# d. P
    1985584 ALLEGRO_EDITOR     UI_FORMS      Import logic changes the Current Working Directory' w, k+ g( d9 K+ U# J, F3 |" K/ u
    1987829 ALLEGRO_EDITOR     UI_FORMS      Import logic changes the current working directory0 G. L: ]! y4 `# P5 W! o) f
    1992722 ALLEGRO_EDITOR     UI_FORMS      After netlist import process, the board file is changing its current path
    + W7 q$ W0 C3 ^" M' {- p1697506 ALLEGRO_EDITOR     UI_GENERAL    Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-2016
    - }8 k( k: Y1 Y; G) T1702631 ALLEGRO_EDITOR     UI_GENERAL    Etch Length by Net report does not list correct net name for nets in a bus
    7 s3 @, p) _- K; b3 U. |1703105 ALLEGRO_EDITOR     UI_GENERAL    Bus net names are incorrect in reports when using the allegro_html_qt variable
    6 @; U- U* d( e' m" h+ }, M1770786 ALLEGRO_EDITOR     UI_GENERAL    Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-2016+ F3 I7 ?" u: c# U& E
    1784938 ALLEGRO_EDITOR     UI_GENERAL    Etch Length by Net report does not show net names with angle brackets in release 17.2-2016
    6 Q# m$ P- I4 {( @* v% x1822557 ALLEGRO_EDITOR     UI_GENERAL    axlUIWCloseAll is not closing text window in release 17.2-20160 R& x& g7 x* b: T& r) f" ^) ]
    1836400 ALLEGRO_EDITOR     UI_GENERAL    Net names are truncated in HTML reports7 x# U7 h  k0 `- m" {
    1869879 ALLEGRO_EDITOR     UI_GENERAL    Links not working in the Net loop report0 C6 w+ T8 |; @$ `" [  U3 ~
    1895878 ALLEGRO_EDITOR     UI_GENERAL    axlUIWClose()/axlUIWCloseAll() functions do not work when allegro_html_qt setting is enabled.
    " P2 R. W# h, g" l' w1912282 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor exits with error message on editing objects
    ! f5 k% J/ d" T/ V+ Z: T9 y1913962 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor toolbars change on choosing View - UI Settings - Save Settings and then restarting
    1 B1 M5 i* G1 D& {1933172 APD                UI_GENERAL    Cannot paste text into the command prompt without clicking when 'enable_command_window_history'  is set8 R/ h! W' ?, a( n0 N5 H$ K5 Y' M7 G
    1843712 CAPTURE            NETGROUPS     Signals shown only for first segment of NetGroup% w. q# T+ B1 ?# }3 }
    1917768 CAPTURE            NEW_SYM_EDITO Missing package pin overview in Symbol editor
    # E! k3 @+ C+ K0 M1920088 CAPTURE            NEW_SYM_EDITO Package view missing in the new Symbol Editor
    % a0 P8 N! l& d1 m8 Z( J$ X3 Q0 R1922196 CAPTURE            NEW_SYM_EDITO Snap to grid issue in Symbol editor2 `1 B5 C) C1 i; q; n0 w
    1927268 CAPTURE            NEW_SYM_EDITO View Package is grayed out in release 17.2-2016, hotfix 038 and later versions
    $ D3 j% V( R" b' o  Q$ @1928012 CAPTURE            NEW_SYM_EDITO In new Symbol Editor, View - Package is grayed out/ k5 E! Y* `4 m" \& L1 U2 }
    1930865 CAPTURE            NEW_SYM_EDITO View Package missing in hotfix 038
    8 R/ M  k/ J# n( z* r4 i: v" `1938507 CAPTURE            NEW_SYM_EDITO Issues with new Symbol Editor: Justification and spreadsheet usability9 A! U! m/ _* e' z' a6 A
    1940869 CAPTURE            NEW_SYM_EDITO Missing pins in 'Edit Pins of All Section' table view for 4k resolution but not in 2k resolution8 I/ O* L5 M2 i( H( h: D
    1940888 CAPTURE            NEW_SYM_EDITO Copying pins from a part and pasting on different parts not working properly.; E) R$ ^3 a. k& k+ \% Q, D
    1942994 CAPTURE            NEW_SYM_EDITO Cut / Paste of object in New Part / Symbol editor always pastes on grid
    & m% y7 M' ~1 d# D+ f4 P0 ?6 i8 @( Y1944396 CAPTURE            NEW_SYM_EDITO JavaScript error while copying from 'Edit Pins of All Sections'% M' z) l6 ]2 g' }, ]
    1950224 CAPTURE            NEW_SYM_EDITO Cyrillic alphabets are not displayed properly on Schematic.
    7 X% P" M' M  V; d6 ?! O1951369 CAPTURE            NEW_SYM_EDITO Cancel closes Symbol Editor
    # {) w2 v* |$ B: ?2 T, B2 O1966785 CAPTURE            NEW_SYM_EDITO Edit Part is grayed out
    2 r. F- T: ~& }3 h& q9 B1973135 CAPTURE            NEW_SYM_EDITO Issue with new Symbol Editor: cannot copy-paste pins; z6 N/ h- J3 }4 T& V& v1 X
    1973344 CAPTURE            NEW_SYM_EDITO JavaScript error on opening part from design/ `, M4 e  D4 K
    1974122 CAPTURE            NEW_SYM_EDITO Cannot copy-paste all pin list on the new Symbol Editor2 ^( F! n: E3 k) C) y* V6 c
    1983593 CAPTURE            NEW_SYM_EDITO Script error on copying and pasting to property sheet
    7 D8 Z! W& G) V% H3 r7 |1 z7 B1929692 CAPTURE            OPTIONS       PACK_SHORT issues with Pin Numbers that contain letters/alphabets
    . b* v' d9 v' E- K1876939 CAPTURE            OTHER         Incorrect Capture renaming error (ORCAP-1310)2 _! t5 e" ^# p5 g
    1916090 CAPTURE            OTHER         Incorrect error message when 'save as' fails due to long directory path
    : _4 v# _0 y, l' s; P( i4 J5 J1921927 CAPTURE            OTHER         Two functions are mapped to Shift + R in OrCAD Capture in hotfix 038& Q% I1 z6 L/ F1 E+ }& U
    1946453 CAPTURE            OTHER         Shift+R shortcut is assigned to two functions.
    & w6 L$ `0 e  U: m1965456 CAPTURE            OTHER         Shortcut Shift + R is not opening the Independent Sources dialog box: u+ R0 H  k6 q+ O3 M! N. C7 J: R
    1968757 CAPTURE            OTHER         Close CIP is grayed when right-clicking on the tab in Capture.
    $ P* c0 w! E- N1938437 CAPTURE            PART_EDITOR   OrCAD Capture new Symbol Editor Pin Type missing in table
    ) U$ Q# f/ _* j3 ^& i$ b* f1906757 CAPTURE            SCHEMATICS    Intersheet reference is overlapping with the offpage connector name
      o8 g! @/ W5 p1867016 CAPTURE            SCHEMATIC_EDI Part placeholders not being positioned when moved
    ' k( x# }' [! P4 L( O1932837 CAPTURE            SCHEMATIC_EDI Parameters graphics are not correctly positioned* A1 w3 C( ^- m3 d
    1949518 CAPTURE            SCHEMATIC_EDI Getting error when comparing designs
    1 C8 G$ p) x* j  G: c2 q1967545 CAPTURE            SCHEMATIC_EDI Only section A of heterogeneous part being placed and not sections B, C, or D: D1 C5 Z/ N% e% ^6 u
    1933919 CIS                DBC_CFG_WIZAR New CIS Configuration .dbc file created in release 17.2-2016 shows release 16.3
      R9 x& ^& ^/ b' d4 n1932550 CIS                RELATIONAL_DB VIEW NAME in Relational Database configuration is not working as expected.* P* F% \: X" e5 O% H: N2 h7 o" B
    1832524 CONCEPT_HDL        CHECKPLUS     Default checkplus rules show body height of 0 (sym_2 of the attached cell). This causes the cell to fail verification.
    % [' r8 _( z# T1912023 CONCEPT_HDL        CHECKPLUS     signalWidth predicate does not recognize SIG[1..0] as bus.: m" g! q5 ^- s% b  \# ^2 \; k
    1966120 CONCEPT_HDL        COPY_PROJECT  Copying release 17.2-2016 project results in message stating the project is of an older version
    + h# T$ V4 s) k$ @9 ?7 B- u$ w* J1879425 CONCEPT_HDL        CORE          Adding signals with the right-click menu is not following the defined color scheme3 q& L( g7 p+ V2 h9 E
    1890542 CONCEPT_HDL        CORE          Getting ERROR(SPCOCN-1911) when running export physical with backannotation
    $ R' w0 B7 E9 s1907684 CONCEPT_HDL        CORE          Moving symbol makes canvas unresponsive for a long time
    ; l5 [+ t( H$ ]1 l; p) w0 g1920711 CONCEPT_HDL        CORE          Pin names changes when mirroring the swapped section.3 ?4 x( a2 G. Q7 k9 i1 e
    1931421 CONCEPT_HDL        CORE          On Linux, 'cpmaccess -read' returns incorrect value
    % J1 @6 B% w, w! b" R- B  H1931782 CONCEPT_HDL        CORE          Setting DONT_FORCE_ORIGIN_ONGRID to ON does not work for sig_name& _; @$ p' ^& P: q9 o" j  Z
    1932433 CONCEPT_HDL        CORE          _movetogrid causes signal disconnection# \. R: j/ b$ I, u; i
    1946993 CONCEPT_HDL        CORE          DE-HDL Part Manager fails to update parts on schematic if new KEY properties exist in PTF but not in schematic
    / Q) ]4 I( L" ?+ X9 d# i& O8 N7 D1947029 CONCEPT_HDL        CORE          Design Entry HDL Font Support not working for signal rename
    9 R( K5 c# r, d, W1962865 CONCEPT_HDL        CORE          Schematic symbol creation with '-' as pin name not packaging
    " A! ^* f" M, }, q: }6 |9 f# T1966805 CONCEPT_HDL        CORE          Issues with packaging design containing cells named with a leading underscore4 A( ?0 d" q( [! W5 I$ L
    1967760 CONCEPT_HDL        CORE          DE-HDL crashes on moving Net Group/Port in release 17.2-2016, hotfix 044* D. X. m  x& F! `  z% _2 N4 v
    1968282 CONCEPT_HDL        CORE          DE-HDL Part Manager fails to update parts on schematic when new KEY properties exist in PTF and not in schematic; u- S8 y' K. B( Z- r) W6 M' Y
    1972815 CONCEPT_HDL        CORE          Part Manager not updating missing key attributes from the ptf file by using 'Update instances' option
    " |* z- X- K; R, q3 ~; {7 L. Z6 q+ ~1887790 CONCEPT_HDL        CREFER        CRefer links not working in selected cpm file8 V0 d$ c+ H) k! d3 k& _
    1898535 CONCEPT_HDL        INTERFACE_DES Global Navigation window does not reflect removal of a net on page2 that is part of a netgroup on page1
    0 `* N( @) m  n5 d' A1888048 CONCEPT_HDL        PDF           Japanese characters are not output correctly to PDF on Linux.; u* U0 F: s7 O# R( ^1 u+ l- _
    1937505 CONCEPT_HDL        PDF           Missing intersection dot in schematic PDF! F% J2 i" E( z  ~" @
    1942486 CONSTRAINT_MGR     CONCEPT_HDL   CM crashes when you save after importing a TCF file7 R! j/ h' k8 G" K
    1983743 CONSTRAINT_MGR     CONCEPT_HDL   Region Class-Class members are being duplicated in CM in the current session% y8 v2 D/ ~+ X( P! [* a7 \
    1906573 CONSTRAINT_MGR     ECS_APPLY     Database corrupt and DBDoctor reports illegal database pointer error
    : T" s; ~. o2 p  {8 d1913805 CONSTRAINT_MGR     OTHER         Setting environmental variable CM_PARTIAL_DCF in release 17.2-2016 causing crash
    7 V4 k# J0 H& G0 t1914813 CONSTRAINT_MGR     OTHER         C++ Runtime error and non-recoverable crash in class-class worksheet
    4 x% ?8 M/ _+ q( f0 F1920142 CONSTRAINT_MGR     OTHER         Xnet names are not consistent in the design
    8 x- |$ h5 U# _0 U* N  }7 w% o1898549 CONSTRAINT_MGR     SCHEM_FTB     Importing netlist causing crash in release 17.2-2016, hotfix 036* e2 x5 t8 F) K( d3 [: C5 O
    1814851 CONSTRAINT_MGR     UI_FORMS      Field solver /DRC check running forever4 M" m1 c- m7 L0 Y1 d% V6 z' v- Y
    1889862 CONSTRAINT_MGR     UI_FORMS      PCB Editor hangs while assigning net voltages in CM
    $ R4 n5 E* \4 B6 _4 ?+ l+ d/ B1965470 CONSTRAINT_MGR     UI_FORMS      Constraint Manager GUI Issue in release 17.2-2016, hotfix 039: Font size small and rows/columns in shrink mode
    8 V/ c+ R4 ]2 v# P+ ^& E1945406 ECW                ADMINISTRATIO Tree view was not refreshed soon after changing the site permission.+ i, k9 _. r7 F6 {0 F5 }0 Y+ P
    1826848 ECW                METRICS       SPDWECW-551 and SPDWECW-553 should be warnings, not errors
    ; |( D9 `1 Q& b' h! S0 I1933373 ECW                PROJECT_MANAG ecwbatch does not accept password and does not ignore invalid users3 X: ^' g+ o$ {$ Y' ]
    1921502 F2B                PACKAGERXL    Errors on running Export Physical:SPCOPK-1138 and SPCOPK-1149
    & a0 G- n0 O8 S: T" D- J: \1929846 F2B                PACKAGERXL    PackagerXL is still creating the pstcmbc.dat file on a release 16.6 design uprevved to release 17.2-2016
    6 G: |4 ?8 w8 g4 L2 y1 V1953780 F2B                PACKAGERXL    Updated subdesign package information not updated on the top-level design in the reuse flow
    8 h' |& `. v' Z/ V' u3 p  ^- C1971738 F2B                PACKAGERXL    Deleting blank space from pstxnet.dat file crashing DE-HDL; C8 j% Z; G# X
    1891002 INSTALLATION       DOWNLOAD_MGR  Issue with Download Manager (Change Preferences Option does not Work)
    + v5 L3 V2 V& A4 [$ M1972890 ORBITIO            OTHER         OrbitIO-APR failed to run if PCB design included
    ' Y. [' n$ J- R4 ~5 G4 r6 r: k1954262 PCB_LIBRARIAN      CORE          Footprint model check in fails with verification checks failed error
    7 _0 @3 `5 [( b  V9 a3 ]1943656 PCB_LIBRARIAN      GRAPHICAL_EDI Symbol Editor is blank if .ascii file is newer than .css file
    " T4 E5 s6 m/ T8 ~1897887 PCB_LIBRARIAN      SYMBOL_EDITOR New Symbol Editor: Inconsistent symbol results when adding vector pins in Part Developer; V( V' A$ X  Q4 p! c# |. a
    1898003 PCB_LIBRARIAN      SYMBOL_EDITOR Issue with Page Border Symbol3 }& A! s; q* Q3 R' S$ u0 ~
    1842007 PSPICE             LIBRARIES     Change required in swit_reg.lib! f9 B* [/ H9 s% m9 @; m+ K
    1906922 PSPICE             LIBRARIES     Mismatch in mapping of IC pins in model and PSpice template for analog device AD8138
    6 z& ~* N. f  b! K8 E1947586 PSPICE             LIBRARIES     Update the model AD8138/AD in ANLG_DEV.OLB
    2 K# f$ |! I- i: Z0 f1748470 PSPICE             MATLAB        PSpice displays an error when sending current in co-simulation# q  o% c# Y  n- E+ B
    1802455 PSPICE             MATLAB        Incorrect current direction for pins in SLPS flow* M& W8 v* h5 S! G. r" l
    1852811 PSPICE             MATLAB        ORPSIM-2604 being reported in SLPS simulation: o4 l$ I& V; i2 _' O7 ?! J$ v
    1858716 PSPICE             MATLAB        Co-Simulation fails if 'RC' is used as reference of resistor' S+ j& W0 A9 H: [" d# R% n+ {8 X
    1921641 PSPICE             MODELEDITOR   Model Editor in Client Server installation slow to invoke
    3 z8 ^, I) M/ {0 Q' G+ y3 Q8 p1922160 PSPICE             MODELING_APPS New Capture Associate Symbol GUI not reading libraries
    : x0 k" e* ]1 J% I1843698 PSPICE             PROBE         PSpice icons appear very small on a specific computer! k8 T* S- X' B; q
    1773841 PSPICE             SIMULATOR     orSimSetup64 crashes when running the simulation for attached design
    6 [, z8 c) z9 O. }0 b. J1 X( |5 ], B1816316 PSPICE             SIMULATOR     Simulation stuck; however, the status bar is correctly updated during Pseudo Transient Analysis" q% r+ G5 j0 {& ?2 B
    1887119 SCM                IMPORTS       Cannot selectively update changes in VDD
    4 q- o4 a0 ^* R  I) r1889362 SCM                IMPORTS       Cannot selectively update changes in Visual Design Differences
    3 F8 U( }6 L* Q) H7 U( Y1958545 SCM                SETUP         Auto assign models does not work in SCM same way as in DE-HDL
    ( |# w4 g& ]4 c# ]/ @: Y7 Y1988841 SIG_EXPLORER       INTERACTIV    SigXplorer stops responding or crashes in hotfix 047 when a design is saved
    % S' w; z; y7 M+ J$ H1988943 SIG_EXPLORER       INTERACTIV    SigXplorer crashes on selecting Update Constraint Manager( C5 @2 Y' ?. M7 I9 N* e7 Y" w
    1991375 SIG_EXPLORER       INTERACTIV    SigXplorer crashes when clicking Save
    5 F- ^3 O- e. ]3 W0 P0 |1993749 SIG_EXPLORER       INTERACTIV    SigXplorer crashes on saving topology
    5 {$ v( J$ x, f) S4 H' z1969975 SIG_INTEGRITY      GUI           Model Browser edits model above the one that is selected
    1 [* E1 F9 {0 l' H- e1953184 SIP_LAYOUT         IMPORT_DATA   Sub Drawing not saving dashed lines
    7 i8 d) v; `9 d1913864 SIP_LAYOUT         ORBITIO_IF    SiP Layout design import results in wrong die rotation1 ]/ c# {1 v8 g( `, n
    1880237 SIP_LAYOUT         PADSTACK_EDIT Background Window comes to the forefront when closing the Padstack editor% u$ r7 R7 n1 W' M8 W2 s4 i$ `, o
    1972560 SIP_LAYOUT         STREAM_IF     GDS Export fidelity issue: inverted arcs
    2 `, e* ]" H4 L1920317 SIP_LAYOUT         THIEVING      Thieving pattern does not allow for OOPS operation
      T: }7 A! G. X: u+ l) a  m1909075 SYSTEMSI           DOC           SystemSI PBA channel and circuit simulations do not respond if bit pattern is 1s or 0s
      K# l" b' w" b8 `$ l1916101 SYSTEMSI           DOC           Lack of stimulus in file causes Serial Link Analysis to become unresponsive
    4 O1 F0 ^3 y0 L  b* Y1919562 SYSTEMSI           ENG_PBA       SystemSI generates wrong timing bathtub curves in channel simulations for write and read
    " a* Z* u) Y' f5 Y( Q$ a1964064 SYSTEMSI           GUI_PBA       Able to sweep AMI parameters in SSI-PBA
    ) S$ \% o. P, U; I1971266 SYSTEMSI           GUI_PBA       MCP header shows only 49 ckt nodes instead of 52 for s52p S-parameter file/ ]( u( t- ?/ o: D" H
    1885625 SYSTEMSI           GUI_SLA       Manage AMI + DLL from Setup Analysis Window
    0 P0 H1 P5 M( o* ~& w: j1924382 SYSTEMSI           GUI_SLA       Data Rate field in SystemSI Stimulus property form is confusing for PAM4 operation5 N( E% K; N, e$ U) ]
    1982341 SYSTEM_CAPTURE     CANVAS_EDIT   Signal rename does not maintain new signal name value
    % Q; U5 C, s! a5 \2 i1976857 SYSTEM_CAPTURE     CONSTRAINT_MA System Capture-CM Match Group Creation is not updating correctly
    + h  U0 F, f( y1929606 SYSTEM_CAPTURE     DESIGN_CORRUP Opening design causes System Capture to crash
    / F! A( B& }+ e" b! {% @; ?1914697 SYSTEM_CAPTURE     DRC           Overlapping component DRC does not work
      C8 T1 ^6 [$ X9 J1 K0 U" ^& y4 r- T1973467 SYSTEM_CAPTURE     IMPORT_PCB    System Capture Import Physical shows many component and physical differences on a design that is synced up
    ; k; x& P2 v$ h6 Q/ u  s4 m1962603 SYSTEM_CAPTURE     NAVLINKS      Ability to not underline hyperlinks for Navigation Link values, z  S2 A" E! U% y$ Z
    1967639 SYSTEM_CAPTURE     PART_MANAGER  Part Manager does not open in System Capture for part property value changes even after setting the cpm directive.. t. g  U' L! G* [0 R% d
    1964388 SYSTEM_CAPTURE     SMART_PDF     Some shapes are not visible in the smart PDF schematics/ _' a# }$ b9 t- e, |/ _9 J- f) s
    1976832 SYSTEM_CAPTURE     TDO           Rolling Back local lower-block requires check-out of higher-level packaged & variant views- G& m4 U+ ~9 m
    1976844 SYSTEM_CAPTURE     TDO           CM - TDO check-out dependencies are broken- m  y! c( F; M6 D: b, @
    1976859 SYSTEM_CAPTURE     TDO           Variant Editor in System Capture -TDO allows to delete a variant without checking out variants view
    % Y5 _$ W+ v$ \/ b+ G' E( |* ?1839816 TDA                CORE          All the design objects are locked in the EDM dashboard after a DSFrame error
    ; a+ M- ^+ m7 h1 Q' d1889898 TDA                CORE          Cannot check in the top level of the project in TDO% ^. u: Q* Y# j5 ^
    1892411 TDA                CORE          Unable to undo the block checkout if something fails6 @: O1 x6 I/ d- G3 b" g
    1877757 TDA                DEHDL         Refresh Hierarchy does not show latest TDO lock/unlock status in DE-HDL" ~# _8 ^* n. H1 N( e. W3 T$ j5 R
    1 Y3 H" L. W% I$ k* c7 {
    , y: v7 L- C) o( y
    Fixed CCRs: SPB 17.2 HF047
    ; T2 L" P# h$ W! T+ P1 H9 W; l09-9-2018: P' K, _- q5 Y  \
    ========================================================================================================================================================
    , X! W3 M7 X) ]% C. u+ BCCRID   Product            ProductLevel2 Title! e* U6 L1 H1 I" C
    ========================================================================================================================================================4 M8 }* {( `- R6 f$ y
    1969527 ADW                LIBIMPORT     Getting  java.lang.NullPointerException error on bulk import in hotfix 044, n9 n8 _5 |; X' F
    1976219 ALLEGRO_EDITOR     DATABASE      .SAV file not created although message states it is created
    . s' J) f8 o" {( X4 Y1968270 ALLEGRO_EDITOR     DFM           PCB Editor crashes when running DRC$ T+ ?1 |8 }9 B" K: @
    1978421 ALLEGRO_EDITOR     DRC_CONSTR    False DRCs between via and its fillet shown after editing shape boundary8 w) K. }! e2 F5 c
    1966772 ALLEGRO_EDITOR     PAD_EDITOR    PCB Editor and DBDoctor crash on editing DRA file: Found bad pointer, run dbdoctor
    , J! o* Z  C2 Z" z3 i+ @# H7 V1973866 ALLEGRO_EDITOR     SHAPE         PCB Editor crashes when deleting a group5 e- f( Q- a1 L  p6 `
    1818779 ALLEGRO_EDITOR     UI_FORMS      Dialog box goes behind main window on clicking PCB Editor canvas1 _- M$ `% V: o7 X
    1880175 ALLEGRO_EDITOR     UI_GENERAL    Multiple sessions of PCB Editor gets mixed up in Linux in release 17.2-2016  c' v1 C# j6 b+ P7 n
    1946027 ALLEGRO_EDITOR     UI_GENERAL    Arrow Keys in Canvas stop responding after changing the view.$ E/ f3 ~0 t! t. a9 D! }  ?
    1967701 ALLEGRO_EDITOR     UI_GENERAL    Arrow Key panning does not work when third-party SKILL call is active
    & }9 T- _% u  \- z1967706 ALLEGRO_EDITOR     UI_GENERAL    Observe Special Characters when command is run- }: v' g  C! E
    1971183 ALLEGRO_EDITOR     UI_GENERAL    Focus is lost from command line when Save icon is used4 Z( B! p5 Y9 _9 O6 ]% `" y2 R
    1971186 ALLEGRO_EDITOR     UI_GENERAL    Focus from Command line is lost when using CTRL + N
    1 Z, Y. L2 j1 q! Q8 I1971190 ALLEGRO_EDITOR     UI_GENERAL    Focus from Command line is lost when using CTRL + Alt* u4 |! G" D, Q+ j0 |/ y/ P: E$ ]
    1971200 ALLEGRO_EDITOR     UI_GENERAL    Focus is lost in comand line when you save using command save: h. u! q% B9 L5 O# f
    1961833 APD                SHAPE         Crash when changing dimension of existing via padstack in the design, v" O$ V. `- ]( u5 T
    1968256 ASDA               EXPORT_PCB    SDA crashes directly after Export to PCB
    5 _- Y$ g2 p$ {# ?* H+ G  k) Y+ U1970284 ASDA               EXPORT_PCB    Placing part crashes SDA% r1 q5 a4 |0 y: B
    ( c' i. O4 P% L
    ( q$ J- f" ^- V, B+ i  W. a1 P
    Fixed CCRs: SPB 17.2 HF046
    5 T/ K/ P3 ~# p, ~# T08-24-20182 e0 X8 f9 u+ V2 _2 ~2 H4 ^7 V1 N
    ========================================================================================================================================================5 S- w6 }! V7 E% e
    CCRID   Product            ProductLevel2 Title
    $ C9 \& a/ U) m5 V========================================================================================================================================================3 F5 M# ^: n- ?) O
    1880800 ADW                PART_BROWSER  Server connection failure on a running SDA session.  a  R) ?; y3 k% S; h+ l
    1880895 ADW                PART_BROWSER  NCB - components missing from the component browser/ R" Q! ^$ X+ f  P5 A4 Y! Q
    1962336 ALLEGRO_EDITOR     INTERFACES    Smart PDF shows both top and bottom probe layers for a film layer with only a single probe layer (top or bottom)
    2 O" X/ U  \& n* f8 w1955128 ALLEGRO_EDITOR     MANUFACT      Need to close PCB Editor to delete xsectionChart.log generated on placing a cross-section chart2 L  W/ D# Q5 Y) `% h, `
    1969088 ALLEGRO_EDITOR     SHAPE         PCB Editor crashes on updating shapes to smooth
    0 I+ }/ P9 v, S5 @3 e1963828 ASDA               DESIGN_EXPLOR Unwired schematic block movement with text is not correct' R* R( L* j' @# c2 T! x9 {3 m
    1954426 ASDA               OPEN_CLOSE_PR Double-clicking to paste a note crashes SDA$ }6 G1 ^) `$ O, Z
    1965423 ASDA               OPEN_CLOSE_PR Crash when working with notes in SDA: n+ Y6 d. i' |) E& M
    1960060 ASDA               PART_MANAGER  Original property differences not displayed in Part Manager on selecting a new part from CB and doing reset# @2 _4 [% ^, x2 C' Q$ I" H, `1 h8 H
    1960112 ASDA               PART_MANAGER  Part Manager incorrectly updating part property values
      N: r# ^! V/ h' B# T9 c3 M1955723 ASDA               ROUTING       Draw Multiple Bits misses bit 0 when in reverse order.( p7 p& u8 r/ d$ h8 A
    1952963 CONCEPT_HDL        CORE          Variant Editor takes a long time to load
    ! F( M3 W, l- X8 w: q5 Z7 F1962568 CONCEPT_HDL        CORE          Directive DEHDL_BROWSER_FILEPATH does not work
    ( ]0 [$ R- v" \1939192 PCB_LIBRARIAN      SYMBOL_EDITOR pin_text size and location very different between DE-HDL and Symbol Editor resulting in text overlap
    : _: A7 e: H% e4 u1952967 SCM                OTHER         Error while copying a release 17.2-2016 design: message says design created in release 16.3 or an earlier version
    5 g3 E5 Z, h3 [$ m2 H( n" q1948999 SPIF               OTHER         Some place_keepout shapes and antipads not exported/ ]" {( \! s" D  U: I6 i) p4 i
    ) r" O4 X; \: D2 Z
    ) g4 B; w9 l+ Q" X# X8 e
    Fixed CCRs: SPB 17.2 HF045; s$ o) k6 ?0 J) k# m, X
    08-10-20187 |& ^7 B! K$ |4 v. S+ L* {
    ========================================================================================================================================================
      Z. ~. h. s' yCCRID   Product            ProductLevel2 Title
    5 \  Y, a  Y3 p5 }========================================================================================================================================================& u: {7 K% y2 W: p! N3 d
    1934956 ADW                DBEDITOR      Footprint missing from part in release 17.2-20160 E+ @% o$ S6 r3 a7 k# P+ r
    1945005 ADW                DSN_MIGRATION Right side of Migration dialog box is cut off: c/ R: a& E* f/ O* M1 }& p
    1933245 ADW                FLOW_MGR      'Open last Project' button should open the last opened project& m* s5 o5 B; F8 T* c
    1953210 ADW                LIBDISTRIBUTI Library Distribution is not distributing all symbols. No errors for the missing schematic models.
    4 [0 d6 d, v$ L1953727 ADW                LRM           LRM missing two symbols when migrating from release 16.6 to 17.2-2016
    , Q" o4 w/ v* v8 N$ _# r1952923 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes on trying to delete layer
    % M, N0 k0 O7 X1957171 ALLEGRO_EDITOR     DATABASE      Pastemask offset not working when creating a symbol that requires two top-paste masks" I' M7 [1 e, `9 B( @/ O" E" k) ?
    1960059 ALLEGRO_EDITOR     DATABASE      Stackup definition causes custom script to crash
    ' L, R& U, L/ d4 T# W1 S8 J/ Z1932864 ALLEGRO_EDITOR     DFM           Exporting DFM Constraints losing the association to design level. N' E7 R& }) u- p
    1957467 ALLEGRO_EDITOR     EDIT_SHAPE    Compose Shape copies lines to wrong subclass: h, U: F( @# B5 v
    1938536 ALLEGRO_EDITOR     GRAPHICS      Multiple crashes on different boards after installing hotfix 040* E& @  }& m  z# f' v. d% t8 Z
    1954075 ALLEGRO_EDITOR     SHAPE         Dynamic Crosshatch shapes should be clipped inside RKI if RKI Autoclip is enabled
    0 ?4 J8 ^/ x, E, v7 \. q1957803 ALLEGRO_EDITOR     SHAPE         Wrong dynamic shape status# t6 F2 L7 U) M7 O" I; v* X0 u
    1949923 ALLEGRO_EDITOR     UI_GENERAL    Focus lost from command window when any command is active. j, H+ E2 @3 n8 j# h, n
    1963245 ALLEGRO_EDITOR     UI_GENERAL    Alias behaves as Funckey in release 17.2-2016, hotfix 044, [! U6 ?: A1 ]" h: s6 U3 I! S- P7 E
    1892126 ALLEGRO_PROD_TOOLB CORE          Clines disappear and then reappear suddenly on using Route - Shield Generator
    9 I& X1 v0 _0 g1931127 ALLEGRO_PROD_TOOLB CORE          ZDRC not working for Xhatch Shape
    0 D/ d+ q( U5 ]7 C( G7 M1932563 ALLEGRO_PROD_TOOLB CORE          allegro_legacy_board_outline environment variable not set in PCB Design Compare.2 b/ z! ?& y: |' u8 @
    1929855 ALLEGRO_PROD_TOOLB OTHERS        Outline not exported correctly for PCB design compare if Design_Outline and Cutout exist
    4 k& N9 h& T9 h! ?$ U1956494 APD                DATABASE      DBDoctor removes pads
    / E( {+ G) o9 I, H* y1956291 APD                INTERACTIVE   axlSpreadsheetSetStyleProp should accept 0 and 1 as Boolean values for protection style4 G# a$ n; ]9 G3 D
    1960127 ASDA               ARCHIVER      Using the Tcl command 'archiveproject' crashes SDA
    / W; h5 l; |- K, C& H1953718 ASDA               CONSTRAINT_MA SDA Import Pin Delay fails with extra columns, does not explain why
    2 [" \1 |( o. C  o3 Y1924498 CAPTURE            SCHEMATIC_EDI Cannot place part 'B' for heterogeneous part if 'Preferences - Miscellaneous - Auto References' not set
    % B0 H& k* ~" @3 d5 k, s9 E1927129 CAPTURE            SCHEMATIC_EDI unable to place heterogeneous part section directly from place part window
    $ B5 K9 A8 y; f3 a' {1 E( q( i: i1928255 CAPTURE            SCHEMATIC_EDI Unable to place a specific section from Place Part
    . e5 X' {% [- c% i* b1945207 CAPTURE            SCHEMATIC_EDI Part selection pull-down reverts to part '1|A' when placing heterogeneous part9 y; d) `* w* `, F3 T
    1945661 CAPTURE            SCHEMATIC_EDI Section drop-down in Place Part window is not working6 I8 \; U# E. W8 k# J3 \0 F
    1958121 CAPTURE            SCHEMATIC_EDI Preview and placement of sections of Heterogeneous parts is not correct in New Symbol Editor8 s6 Y; T1 p. B0 a, O6 p& J
    1956535 CONCEPT_HDL        CORE          DE-HDL crashes on Import Pin Delay for a CSV file5 R) g7 x! L/ x7 X, @: V
    1960922 CONCEPT_HDL        CORE          DE-HDL crashes on moving netgroup on Windows 10
    ; m" m" K: s  f1964016 CONCEPT_HDL        CORE          In DE-HDL moving around nets connected to Netgroups causes crash on Windows 10" d6 p# h5 v2 T: b' P1 t' Q; Y
    1907040 F2B                PACKAGERXL    Export Physical output board file name reverts to old when changing options
    * r' g, w6 I0 g2 A% l3 E9 N1957862 ORBITIO            ALLEGRO_SIP_I allegro2orbit failed to translate rounded rectangle padstack
    7 W: S' Q5 A- V" f7 o
    + [6 `! o+ }+ R9 J3 }+ f" X7 \, L. r& B' ?
    Fixed CCRs: SPB 17.2 HF044
    " e: J8 |! i/ Z4 [, e/ e( F07-27-2018
    ! f- l! O. P& ^3 V: F& z========================================================================================================================================================: R- D7 p5 f! y) W, G! |1 S
    CCRID   Product            ProductLevel2 Title% M* J! U; E1 H% E; C
    ========================================================================================================================================================
    5 F: N4 ^/ C4 M$ S5 g' D* ~* n% o1943727 ADW                DBEDITOR      EDM DBEditor: Cannot check in/out schematic model symbols with many linked parts, t0 O& l  w9 h, x: W! g
    1800630 ADW                FLOW_MGR      Support spaces in design directory path on Windows: ]" l/ I; D9 c3 O' ~! I/ _" x: S
    1951052 ADW                LRM           LRM stops responding on project update and removes parts from design, K4 u6 J7 ~$ @" q$ V2 C$ C/ r
    1891428 ADW                PART_MANAGER  Resistor turns into a capacitor when placed
    3 |+ v& f+ A7 q% k" E6 K+ Y4 ^1945194 ALLEGRO_EDITOR     3D_CANVAS     3D Viewer crashes when opening from board file.
    $ b! K. G. k% A0 W8 E) f1935558 ALLEGRO_EDITOR     INTERFACES    Exported STEP file missing components when viewed in free STEP viewer
    5 l  V+ v$ f. O1945640 ALLEGRO_EDITOR     MULTI_USER    Symphony client disconnects from server without any notification7 ^- T1 P5 I7 g9 q
    1948454 ALLEGRO_EDITOR     MULTI_USER    Window DRC stops responding when run in Symphony
    ; r7 J; U# _( L1 Z8 E1946619 ALLEGRO_EDITOR     SHAPE         Pin/via with suppressed pad on shape layer and thermal connection type of none should void to drill hole.
    & K  c2 Q8 K; M' `1946708 ALLEGRO_EDITOR     SHAPE         Same net hole to shape voiding is incorrect.
      p+ g% N6 _: `; o) b# U) d1952213 ALLEGRO_EDITOR     SHAPE         Shape voiding from Thru Via when the via regular pad is not completely drilled out by Backdrill hole is not consistent
    6 U& `" y# ^2 y% p2 O1889433 ALLEGRO_EDITOR     UI_GENERAL    Command window shows result at the end of a command rather than showing dynamic updates" D, F% x! z- g' `
    1933503 ALLEGRO_EDITOR     UI_GENERAL    Extra click required to enable command window
    + }0 x; B2 O! M) o* w+ l8 N$ X1 h: p1943692 ALLEGRO_EDITOR     UI_GENERAL    Funckey commands are not working% x7 r5 Z0 n8 W+ T" \; G! b" Q
    1945914 ALLEGRO_EDITOR     UI_GENERAL    Mouse focus lost in the command console when doing an 'undo' from the toolbar icon
    7 l6 Z; |* ?/ [- P6 _# W" S& I1945920 ALLEGRO_EDITOR     UI_GENERAL    Focus lost from command window when the toolbar is used for any operation) ~; j$ T: I+ ?5 R( Y; E
    1949922 ALLEGRO_EDITOR     UI_GENERAL    Focus lost from command window after save or even autosave
    2 o+ F) J3 z  y9 P# @8 [1947551 ALLEGRO_EDITOR     WIREBOND      PCB Editor crashes in wirebond edit mode( D6 C8 ]2 b7 l. `( w& Y; m4 G# V
    1935722 ALLEGRO_PROD_TOOLB OTHERS        Panelization: Cannot place parts after migrating design from release 16.6 to 17.2-2016: I2 A: N7 l3 D! ^1 k) Y% T  @
    1951511 APD                REPORTS       The result of Metal Usage Report is incorrect.# e/ N1 C2 R4 W" y( l
    1952942 ASDA               GRAPHICS      Need metric (mm) support in grids in SDA/ ?8 W3 N! k/ x1 v: F% H- K1 Z
    1948122 ASDA               TDO           If user ID has uppercase characters in teamassignmenttemplate.xml, TDO fails to join a project
    $ X" @& v/ e( t3 n, [* D2 y) z9 k1931199 CONCEPT_HDL        COPY_PROJECT  Stop hard coding Copy Project license inside EDM- x2 R8 e+ ^3 w3 ]0 f3 J0 b9 x, p
    1938153 CONCEPT_HDL        OTHER         Component Browser stops responding on replacing and modifying components; R/ W( P5 }3 S6 c
    1770601 CONCEPT_HDL        PDF           Wire Pattern set to two-dot chain line not shown in PDF! W1 g2 y/ T% C! Z
    1791175 PCB_LIBRARIAN      CORE          Allow baseline of cells with pins at symbol origin: change error to warning
    * [6 ^, ]; O* j: I  V* S3 G1922238 PCB_LIBRARIAN      CORE          Unable to check in into EDM Server due to con2con error SPLBPD-323 - Origin on pin connection point
    5 j9 r! C) D( e1 @& X% `4 c  q  }1936812 PCB_LIBRARIAN      GRAPHICAL_EDI New Symbol Editor: Wrong text being updated when editing text after copy and paste
    0 X/ ]9 m% b0 r( t7 S1804159 PCB_LIBRARIAN      SYMBOL_EDITOR Copy and paste of pins in new symbol editor: issues with pin name, rotation, and move" T: N- Z  ^; ?2 f; a- B' Z7 p
    1927422 PCB_LIBRARIAN      SYMBOL_EDITOR Symbol outline not updated correctly in the new default graphic editor in Part Developer release 17.2-2016: B- M$ _9 [; @& C% I8 \0 N
    1939272 PCB_LIBRARIAN      SYMBOL_EDITOR Symbol Editor changes origin to bottom left, outline to invisible, shows rectangle with center rectangle at new origin/ S  d: A# I3 c0 Q# h: S; ~0 z
    1928076 RF_PCB             DISCRETE_LIBX dlibx2iff does not work with managed libraries and library-level PTF# [9 E- Q0 S6 C( |$ [6 A& a; ]
    1929574 RF_PCB             DISCRETE_LIBX Discrete Library to third-party Translator does not populate the Available Parts section correctly8 _, p2 o* N7 N7 U4 y
    1850360 TDA                CORE          TDO crashes while changing the root design& S  Z+ C( C9 H, T4 o3 `  E
    1934388 TDA                SDA           SDA TDO crashes on attempting to check in a 'New Block in Shared Area', I2 i8 {9 }8 `1 Z. C

    9 U+ @2 H. N/ ~: e- Z' f1 C! D5 b" j9 @- Q2 \
    Fixed CCRs: SPB 17.2 HF043
    # d/ ]' @' v" k1 m9 I" N* M07-13-2018
    9 g6 t7 `  L7 c" ^========================================================================================================================================================6 e$ b: ?9 K, o
    CCRID   Product            ProductLevel2 Title
    9 @4 ]: G( L" |3 @========================================================================================================================================================0 x9 V8 Z3 Y. n" L0 y5 \
    1935813 ADW                DBEDITOR      Auto merging of DE-HDL and Capture Classifications is not working, k) u' f1 z7 d+ q. K
    1935834 ADW                DBEDITOR      Some DE-HDL only classifications are removed during the CSV merge process of libimport7 k0 V2 A$ _% w5 z4 U, [& p$ j# N( A
    1941570 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes or stops responding on performing 'Info' or 'edit properties' on select pins
    3 Y1 p8 }0 |& y1942536 ALLEGRO_EDITOR     DATABASE      Allegro PCB Editor fails to create backdrill plunges in Zone area/ r: h$ j! S9 a1 {2 Z
    1925899 ALLEGRO_EDITOR     DFM           PCB Editor crashes when placing components in Hotfix 039
    * v. m' C3 V% L# x: M1943113 ALLEGRO_EDITOR     DFM           Restore normal move/slide via performance when annular ring checking is enabled.. S7 F& a5 N2 a% R
    1940939 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashed on running the Gloss - Line and via cleanup tool
    ! T5 N6 J4 m( a1937754 ALLEGRO_EDITOR     GRAPHICS      Text string disappears when selected during 'Edit - Text' if using PCB_CURSOR6 {4 T* D: H2 p
    1937056 ALLEGRO_EDITOR     INTERFACES    Cannot import IDX acceptance of third-party change to PCB Editor( z6 Z. b+ O- u" u6 \0 J0 R
    1940197 ALLEGRO_EDITOR     INTERFACES    PCB Editor crashes when reading IDX file from third-party$ i7 _3 u5 P4 n- f  _0 u
    1940232 ALLEGRO_EDITOR     IN_DESIGN_ANA PCB Editor crashes when running Return path DRC/ H2 U% o+ }# `- `
    1916921 ALLEGRO_EDITOR     PLACEMENT     Property Pin_Global_Fiducial not inherited from symbol into board
    ; {6 @" |- b4 C+ o1862241 ALLEGRO_EDITOR     REPORTS       In 'Summary Drawing Report', the listed quantity for HDI vias is incorrect under Drilling Statistics
    5 J4 \0 S4 |$ W1935448 ALLEGRO_EDITOR     REPORTS       Etch Detailed Length Report lists only one coordinate pair per trace
    * u5 E0 }  c$ v3 `1948322 ALLEGRO_EDITOR     SHAPE         Allegro hangs when axlPolyOperation api is called; g3 t: O. G4 [  h" c& Q
    1795564 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, focus is lost from command window after right-click
    ! L- E; A/ O$ U9 }& J, C% z. a1919247 ALLEGRO_EDITOR     UI_GENERAL    Infinite cursor graphics issues on move: Cursor disappears and symbol image remains at old location till refresh' y% V5 G" ]; t4 Y# M( {& m
    1919256 ALLEGRO_EDITOR     UI_GENERAL    Infinite cursor graphics issue: Symbol disappears during rotate& P8 s) W7 }9 b9 q& W
    1933526 ALLEGRO_EDITOR     UI_GENERAL    Panning is slow in PCB Editor in Hotfix 038  D; S; b: Y; V, t$ r( R
    1933530 ALLEGRO_EDITOR     UI_GENERAL    Strokes are slower to respond in release 17.2-20160 ~" f) e/ g" e& F
    1933536 ALLEGRO_EDITOR     UI_GENERAL    Third-party dialog stops responding on running commands: q$ y: ~+ o+ C  [" s
    1782227 APD                DIE_GENERATOR Ability to specify rectangular shapes in die text in
    2 y' G5 T; |6 N( \3 i1933011 ASDA               PART_MANAGER  Parts changed in library with new pin names are not reported or updated by Part Manager( G7 Z) d" @6 M, ^" Y
    1924529 CAPTURE            NEW_SYM_EDITO Global colors for pin name and number and part body not allowed in release 17.2-2016, Hotfix 038/039
    - V# u1 y5 y$ Y& Y1925846 CAPTURE            NEW_SYM_EDITO Opening library or component with special characters in path throws JavaScript exception  V* b$ @1 A; v, p# D1 ?$ i
    1928905 CAPTURE            NEW_SYM_EDITO Pin name justification, length, and casing incorrect for generated parts in Hotfix 038
    & U+ C6 ]: ?6 k& Q4 G1928965 CAPTURE            NEW_SYM_EDITO Cannot move pins in Capture if Pin Name is missing
    4 E6 x9 f( R9 U/ E8 N8 r& [1932149 CAPTURE            NEW_SYM_EDITO JavaScript exception if path to part contains special characters in Hotfix 039
    ( n$ p( T$ c0 C/ _" T8 O1936301 CAPTURE            NEW_SYM_EDITO Cannot edit symbol in new symbol editor: Displays parsing error (SPSMI-1)2 v: H# q. p  g7 F$ u  ]
    1917172 CAPTURE            PART_EDITOR   Pin name rotating on schematic even when pin name rotate is off in symbol editor0 G/ p, k, |" a  v7 e; q
    1924456 CAPTURE            PART_EDITOR   Color preferences for pin, pin name, and pin number do not apply in part editor but only in schematic
    ' e- I. X0 T/ i% N: h) @9 e1928872 CAPTURE            PART_EDITOR   Pin name locations are wrong and each needs to be placed manually, v+ Y( d! o; B( c* t5 p6 ]: Z
    1929562 CAPTURE            PART_EDITOR   Changing pin name while adding a pin not intuitive in Symbol Editor
    " Q. A% A+ `/ t$ n. N. K1932732 CAPTURE            PART_EDITOR   Part Editor issue: Pin name selection box too long and text not justified in Hotfix 0403 p6 o* q* T2 i  R' `/ [# ?
    1933523 CAPTURE            PART_EDITOR   Connection box does not appear after changing pin of a placed part in Hotfix 040* `9 Z8 i+ n; ]6 C7 k& F3 Q1 j
    1936994 CAPTURE            PART_EDITOR   Error because of illegal characters in pin name and number and net name
    ) j8 a! k  r# M* P1943074 CAPTURE            PART_EDITOR   Pin names rotated in Part Editor not rotated when placed on page6 j4 J$ L& a- ]! _, o
    1943078 CAPTURE            PART_EDITOR   Pin name rotate not working.
    $ L3 F+ i) X  y3 O' C5 K# q1945055 CAPTURE            PART_EDITOR   Pin names not rotated in schematic
    * k' X0 U% O; D% K1925700 CAPTURE            VIEWER        Pin numbers and text not shown during Variant View mode anymore.: E( Z7 h+ W* a' T' n
    1914437 CONSTRAINT_MGR     CONCEPT_HDL   Constraint Difference Report appears even though there is no difference in constraint.+ Z. d) w- V7 ]4 `$ |
    1935152 CONSTRAINT_MGR     CONCEPT_HDL   Match Groups are not formed with the correct pin pairs' O; E$ S# a4 g
    1940575 SIP_LAYOUT         ORBITIO_IF    Need new routing flow
    . u6 \5 C# W& x& P  @" H. G, i1923722 SIP_LAYOUT         STREAM_IF     Use one symbol for all instances of a Via Structure9 _, k- D3 T& c0 [; M
      I: Z. f; j3 |, b" c
    8 b/ y. J, r% o; a
    Fixed CCRs: SPB 17.2 HF0429 J' Y- E( W) a& T2 Q
    06-22-20186 d0 ]; f) a$ @5 X! ]
    ========================================================================================================================================================7 Z5 Y  y$ [$ w, ^
    CCRID   Product            ProductLevel2 Title
    1 `8 s6 p" M7 `7 d========================================================================================================================================================1 F: k3 }4 S- {+ {
    1922654 ALLEGRO_EDITOR     ARTWORK       Difference in board and Gerber display
    ! u4 g2 A$ ], a' w1932714 ALLEGRO_EDITOR     COLOR         Manufacturing subclass NCDRILL_FIGURE missing from Color Dialog when editing .dra file
    8 K2 o, _  F7 O3 R. ~1 V" N1932316 ALLEGRO_EDITOR     DFM           DFM constraint reporting wrong DRC between backdrill via hole to shape clearance under copper spacing6 Z) s! z2 C. |" w! V( c: C
    1914334 ALLEGRO_EDITOR     INTERFACES    Design Compare does not import some netlists created using Export - Netlist with properties from PCB Editor
    . r0 D6 |6 d5 w4 O- |- v6 y6 u3 {1910213 ALLEGRO_EDITOR     MANUFACT      OrCAD PCB Designer shows Backdrill Status in Check - Design Status! O0 ]7 r1 R1 t: J
    1933049 ALLEGRO_EDITOR     MANUFACT      NC Route seems to put all routed drills in the same .rou file regardless of what layer they are on.2 T0 o5 U$ P6 v0 `  N
    1880576 ALLEGRO_EDITOR     PLOTTING      Extra lines appearing in plots that are mirrored; r8 i% Y9 n, ], Y- _
    1881031 ALLEGRO_EDITOR     PLOTTING      Plot Preview with the Mirror option in the Plot setup creates fancy lines on shapes
    ) V8 T) N. C) b7 i1908005 ALLEGRO_EDITOR     PLOTTING      Plotting with mirror options set results in strange lines on the plot
    6 U3 ?& L2 U% ^$ x. r$ `2 q1909530 ALLEGRO_EDITOR     PLOTTING      Use mirror function when plotting lines to design
    % W( N) h+ p) k& ~. i  M1919405 ALLEGRO_EDITOR     PLOTTING      Printing with the mirror option results in arcs in Print Preview5 R, |. L9 |1 M( k8 I
    1830419 ALLEGRO_EDITOR     SCHEM_FTB     Import Logic with 'Overwrite current constraints' deletes attributes from drawing6 b$ m9 ~; ]: ^6 D9 f
    1935253 ALLEGRO_EDITOR     SHAPE         Compose shape command causes tool to stop responding
    $ t8 F( m- _: d6 T4 T1571600 ALLEGRO_EDITOR     UI_GENERAL    File - Capture Canvas Image missing in release 17.2-2016- z. T9 w6 }2 y* T- B" h0 I
    1650403 ALLEGRO_EDITOR     UI_GENERAL    Include Capture Canvas Image command in Allegro PCB Editor release 17.2-2016
    ! U# k( u' w, P9 q3 B1710310 ALLEGRO_EDITOR     UI_GENERAL    'Capture Canvas Image' command is absent from the file menu in PCB Editor in release 17.2-2016. T' `1 g% r3 z" J0 |
    1718407 ALLEGRO_EDITOR     UI_GENERAL    Reintroduce the Capture Canvas Image command
    9 d& ^2 k1 a1 t: \% a! {3 e0 b1729699 ALLEGRO_EDITOR     UI_GENERAL    Capture Canvas Image is not present in release 17.2-20163 z$ Q/ n  S0 g# }7 D
    1753234 ALLEGRO_EDITOR     UI_GENERAL    Capture Canvas Image missing from the File menu
    - t0 f4 l7 |( _1 O: ]* K1754222 ALLEGRO_EDITOR     UI_GENERAL    Need command to capture view window as image in release 17.2-2016
      a3 K* G% Y4 f0 E$ ]1794348 ALLEGRO_EDITOR     UI_GENERAL    Reintroduce Capture Canvas Image in PCB Editor in release 17.2-2016
    / g/ |3 v' H6 a0 o4 h1818610 ALLEGRO_EDITOR     UI_GENERAL    Restore the option to capture canvas image in PCB Editor in release 17.2-2016- j: p, y+ Y; R* d$ V2 I* i
    1844591 ALLEGRO_EDITOR     UI_GENERAL    Reintroduce 'Capture Canvas Image' in release 17.2-2016
    , S* y! W! s$ g, _: w1869380 ALLEGRO_EDITOR     UI_GENERAL    File - Capture Canvas Image missing in release 17.2-2016
    3 W/ D. P1 K5 o) N1889412 ALLEGRO_EDITOR     UI_GENERAL    Cross-probing between two boards in release 17.2-20167 g7 N1 m! q+ ]1 k: J) I
    1922329 ALLEGRO_EDITOR     UI_GENERAL    Add the 'Capture Canvas Image' command in release 17.2-2016
    , V, ?! l" i) v6 e6 a1932070 ALLEGRO_EDITOR     UI_GENERAL    File - Capture Canvas Image is missing in release 17.2-2016
    * a. c2 A' z* ?) t2 B4 S; r1885594 ASDA               PACKAGER      Export to PCB Layout exits without reporting error when Netrev fails8 S5 o- p& Z2 J3 R; D" D8 X
    1931657 ASDA               PACKAGER      Export to PCB Editor does not work for a project/ z: w4 B" {# r- W1 h
    1937757 ECW                METRICS       SDA metrics not getting collected' m/ l3 ^8 e9 M8 w- w
    1934482 EMI                SETUP         EMControl function flow is not working correctly in release 17.2-2016; T1 D" p6 X+ t: c& `* D+ j: p
    1931623 SIP_LAYOUT         EDIT_ETCH     Shapes are not updated and force update does not work
    ! L/ d5 R% n2 o& v) U* q
    ) @3 W" W; k6 E# t5 z) U: I  j. f& Q7 U6 _% J& r% m2 t, I
    Fixed CCRs: SPB 17.2 HF0412 z% |/ X8 q6 d9 y% G+ v
    06-9-2018
    5 ~, p9 y; e' e9 J5 J========================================================================================================================================================
    * I$ P* Z+ x/ p7 ]; I" o1 ^CCRID   Product            ProductLevel2 Title8 c' [: Q" s# Y
    ========================================================================================================================================================2 R  s' E6 |8 J
    1880083 ADW                ADWSERVER     ALM fails to connect and authenticate LDAP server
    8 S( }/ J  G8 A1 U1922218 ALLEGRO_EDITOR     3D_CANVAS     PCB Editor stops responding when 3D Canvas is opened for a symbol
    7 t3 c& i) r1 m$ m" A! N. t1915838 ALLEGRO_EDITOR     DFM           Outline to non-signal geometry is not working for non-etch layers in design3 `. j( x' N) d0 S" ?! l
    1925263 ALLEGRO_EDITOR     DFM           False minimum spoke count DRC0 @- ]+ s" `- L1 W5 j% z" t6 n
    1895486 ALLEGRO_EDITOR     INTERFACES    Importing IPF displays error regarding line being outside drawing extents (SPMHMF-409)$ y# a1 [1 L' j$ L4 H3 w( g0 A
    1927266 ALLEGRO_EDITOR     INTERFACES    Miniaturization license required when using enterprise licenses
    / N; u4 ]' N! o8 z6 u5 e1912186 ALLEGRO_EDITOR     IN_DESIGN_ANA Coupling analysis on one net takes a long time* Q2 m3 r1 n7 H9 w' m
    1916015 ALLEGRO_EDITOR     NC            Improve the message for reporting unsupported characters in the directory path while generating NC Drill data
    ' u; m( {% K2 c% ~3 I. a1926072 ALLEGRO_EDITOR     SHAPE         Dynamic shape to route keepout not voiding correctly
    4 q, X' Y  V! h2 b: p" y1903202 ALLEGRO_EDITOR     UI_GENERAL    HTML report dialog does not handle relative links to files correctly1 V" Q+ F3 a0 Y5 r1 j: L
    1880684 ALTM_TRANSLATOR    CAPTURE       Importing third-party schematic is not working in Capture9 J% k% x8 q  N& C- f$ v& d& I
    1870218 ALTM_TRANSLATOR    DE_HDL        Unable to translate a third-party design to DE-HDL
    2 ?* Z9 T0 Y3 [% }1881208 ALTM_TRANSLATOR    DE_HDL        Third-party to DE-HDL translation: schematic symbols missing all pins# J- j2 u/ m, w; M" P- t# I
    1889909 ALTM_TRANSLATOR    DE_HDL        Third-party to DE-HDL and OrCAD Capture translator fails with error message or crash
    ) V" r: y3 P' u9 ?3 J1924375 ASDA               NEW_PROJECT   SDA new project path truncated at ellipses
    - t! V3 I, J* |) }7 b1900957 ASI_SI             OTHER         axlLicDefaultVersion() in SKILL console crashes PCB Editor in release 17.2-2016 and works in release 16.69 q6 w* B. O6 D, `8 K  y! A7 w2 r' P
    1918499 CAPTURE            NEW_SYM_EDITO Text in new Part Editor is always left-justified and justification cannot be changed
    ! v# E5 ^0 D' {% }1921505 CAPTURE            NEW_SYM_EDITO Error if property name starts with the less than character '<'
    : S7 j# `9 X' j& h! }0 B& n1924273 CAPTURE            NEW_SYM_EDITO Error if property name starts with the less than character '<'
    " R, f. c4 a5 D. A9 f8 L& L- k; L% M1924332 CAPTURE            NEW_SYM_EDITO Capture reports an error when editing pin numbers where names contain the less than character '<'
    6 p( O) C( d$ R2 {$ W; J6 Q1934655 CAPTURE            NEW_SYM_EDITO Properties populated in older release show up blank in new Symbol Editor
    + n- x% l, y. ?% [3 [2 Y& c) v1855851 CAPTURE            OTHER         Crystal Reports not working in release 17.2-20167 u: N# d' f+ x
    1918048 CAPTURE            PART_EDITOR   Unable to modify pin type and shapes for multiple pins simultaneously in new Part Editor
    : L" X- o6 H: g) \& ?1919459 CAPTURE            PART_EDITOR   Part Editor background display color is not consistent when zoomed out/in
    % @1 }9 X" l; i8 c- Z1920078 CAPTURE            PART_EDITOR   Option needed for updating pin type of multiple pins in the 'Edit all pins' menu" }' q& r! ?) x; {. S, |( K
    1922785 CAPTURE            PART_EDITOR   Cannot place pin array with zero in the suffix in Symbol Editor, t9 W. B* Y: `0 s0 `2 r* K
    1922831 CAPTURE            PART_EDITOR   Symbol Editor redraws when scrolling with non-default background and when zoomed out
    6 F9 [( O% @1 j4 C4 g/ T4 N6 ?& g1923772 CAPTURE            PART_EDITOR   Placing pin arrays results in error1 c' p8 E" b0 n1 b
    1888897 CAPTURE            SCHEMATICS    Capture slowly redraws schematic page; ]- G! s& E, W. v2 \, q8 ~4 n) m# f
    1910087 CONCEPT_HDL        CORE          DE-HDL crashes when adding Current Probe to a design3 }) L2 O# c( }+ q1 n8 a  }
    1930364 CONCEPT_HDL        CORE          SIGNAL_MODEL properties not deleted on importing release 16.6 DML design into release 17.2-2016 non-DML design
      k) q( P( a: q  p* y  h1920716 CONSTRAINT_MGR     CONCEPT_HDL   Issue with the passing of physical and spacing CSets between Design Entry HDL and PCB Editor) Z( S5 E6 T! ~) V
    1902591 ECW                OTHER         Flow Manager reports a digital certificate error when launched with Pulse9 @$ v5 X2 r( R& [2 ~( E
    1926029 PCB_LIBRARIAN      GRAPHICAL_EDI PDV Symbol Editor opens to a blank page in release 17.2-20161 ~, s4 A1 Y! o
    1884694 PSPICE             ENCRYPTION    User-defined library encryption is not working as expected
    , P( H5 v9 J7 S( F1 p1927537 SIP_LAYOUT         ASSY_RULE_CHE SiP Layout crashes when running manufacturing checks on specific designs
    - }+ {) i. t, g. H* O0 }" f1878733 SIP_LAYOUT         CROSS_SECTION Layer Function and Manufacture fields in Cross-section Editor are grayed out for soldermask layers in SiP Layout; S0 Y( ^5 N4 ?( y- N
    1900628 SIP_LAYOUT         CROSS_SECTION Board thickness in Cross-section Editor does not change even after soldermask layers are added: b5 p4 g- Z3 O

    & N  I, p6 Y* k5 A
    8 e" G' q5 i& h" zFixed CCRs: SPB 17.2 HF040
      w: `. O6 b! U05-27-20185 S7 ]! D& R2 C
    ========================================================================================================================================================5 M9 p2 b0 W& H& B5 f4 {% S: W
    CCRID   Product            ProductLevel2 Title
    ' k! a; U% N7 G/ k========================================================================================================================================================# p0 R1 a- L3 T: N" P  a9 r5 p; b& k; h
    1924541 ADW                CONF          Designer Server configuration cannot be completed0 b$ o9 m2 k$ ^  I. n! X1 L, F
    1906973 ADW                DBEDITOR      Rename attribute fails to preserve values in affected parts
    ( H+ E( V* w7 f% a1718524 ADW                FLOW_MGR      FM: Find Projects does not find any projects when Project Path contains a period* Q8 z. F" c/ {/ U8 J' q9 W' b
    1803310 ADW                FLOW_MGR      EDM Find Project no longer supports dot in the project path6 {3 P- u* w$ F1 ?: Q2 }
    1916898 ADW                FLOW_MGR      Flow Manager does not recognize projects with a dot in the path
    8 Q3 }! l7 W% G' r- C1887669 ADW                LIBDISTRIBUTI ptfgen displaying Java errors
    0 ?' [* W9 F$ |0 }1897991 ADW                LIBDISTRIBUTI ptfgen fails with error LIBDIST-1062 in library distribution.
    6 i, V; _, c5 I! f" }0 q( P7 Q1915319 ADW                LIBDISTRIBUTI ptfgen should rerun with the -rewrite2db option automatically8 S: d. X8 [8 |3 W0 j
    1920309 ADW                LIBDISTRIBUTI Java exceptions in the ptfgen log file) H6 ]! A; t/ [
    1914706 ALLEGRO_EDITOR     DFM           False Mask to trace DRCs$ B, W, i. q( O
    1912290 ALLEGRO_EDITOR     GRAPHICS      Infinite PCB cursor: symbol move results in symbol trail and disappearance of cursor and symbol
    ! H4 n2 P/ N' m- }2 N$ W1 J2 J$ Z4 D* b1927425 ALLEGRO_EDITOR     GRAPHICS      Infinite PCB Cursor disappear while moving objects on layout
    ! L! q6 [* a. U/ {. k7 c1908867 ALLEGRO_EDITOR     INTERACTIV    PCB Editor crashes in release 17.2-2016, Hotfix 036 and 037
    7 m" `5 k; S/ T! z0 S$ w0 b% V1906116 ALLEGRO_EDITOR     IN_DESIGN_ANA Allegro Integrated Analysis and Checking: Coupling vision shows the influence of voltage net
    # n, W# C. k4 h( I4 q1918161 ALLEGRO_EDITOR     MULTI_USER    Symphony crashing and clients disconnecting from server cannot leave session, error applying DBupdate
    ' n- c, y. i5 n4 e' T# b4 E8 y1919467 ALLEGRO_EDITOR     MULTI_USER    Random crashes while routing design in Symphony. _+ y" n) R* U6 G
    1918702 ALLEGRO_EDITOR     SHAPE         Differential Pair vias not voided in a split plane
    2 J- s' e: S' h- ^, M1905109 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor randomly stops responding in release 17.2-2016 in Linux5 \5 q& ]2 Y, z9 a. F4 g
    1882365 ASDA               CANVAS_EDIT   SDA - body changes but not properties when changing version of a symbol2 }  V7 ]$ L4 d. w
    1900370 ASDA               CANVAS_EDIT   Version command in SDA should use placeholders from selected version6 u6 @: p1 X/ Y
    1901120 ASDA               CANVAS_EDIT   Choosing a different version of a placed component does not use the property placeholders as per the new symbol5 D- C5 g2 I2 |% N
    1907497 ASDA               GRAPHICS      DNI Cross Mark much larger than Components! g+ t0 y- J; E( H
    1895135 ASDA               MISCELLANEOUS Design created in SDA has the cds.lib containing a pointer to worklib& `; S; J2 b  e1 ~
    1895139 ASDA               MISCELLANEOUS Irrelevant warning related to worklib when running checkplus on SDA design
    * t( }: y' _" L4 g0 F) o1920753 CAPTURE            LIBRARY       JavaScript exception reported on opening part with name containing '\' in hotfix 038
    6 k7 \& \: q. @- L1925848 CAPTURE            LIBRARY       New (QIR6) Symbol Editor has Script error / SR 600037969. r" J. i! g9 `4 t6 s" O3 C) E* _
    1916991 CAPTURE            NEW_SYM_EDITO New part/symbol editor ignores grid color set in Preferences
    % J" z3 x$ V  w7 w2 K1917090 CAPTURE            NEW_SYM_EDITO New symbol editor goes into permanent pan mode on clicking the middle mouse button) s3 S' n& B3 {- p
    1918041 CAPTURE            NEW_SYM_EDITO Saves As for symbol in library from new symbol editor saving 0 byte files
    4 a! Q/ t+ p+ V- R1918497 CAPTURE            NEW_SYM_EDITO Moving multiple items using the arrow keys results in error in new part editor
    # q& K5 X2 l9 o0 k1918711 CAPTURE            NEW_SYM_EDITO Unable to do a Save As from a Library part to change the name# s& t9 ^7 f3 D% r
    1920889 CAPTURE            NEW_SYM_EDITO Unable to edit symbol with name containing '/'
    ' W, [9 L' ^+ @! Y* E1922123 CAPTURE            NEW_SYM_EDITO Save As for symbol in library from new symbol editor saving 0 byte files( k& m" E, i% U( s
    1922276 CAPTURE            NEW_SYM_EDITO Space between pin name and pin for names having bar
    ! g( q, L9 Q6 I/ O9 g1922282 CAPTURE            NEW_SYM_EDITO JavaScript exception on closing new part editor window using keyboard shortcuts7 F% C2 {+ P1 d, B! K& T+ h- F
    1923526 CAPTURE            NEW_SYM_EDITO Unable to "Save As" in new symbol editor.- G+ N# A  G* r# U# Y7 E& _- C  k  K
    1927262 CAPTURE            NEW_SYM_EDITO The File > Save As command in version 17.2-s038 differs from earlier versions
    % \, G# `) [' ]3 b8 Y0 q1919322 CAPTURE            PART_EDITOR   JavaScript exception on opening parts and creating new part using right-click
    . F5 e4 x3 B  p& q7 a6 ?9 h1914183 CONSTRAINT_MGR     XNET_DIFFPAIR ECSet fails to map in PCB Editor but maps fine in DE-HDL, w2 U! ], X/ _( X
    1908102 ECW                DASHBOARD     Some lines in Design Dashboard in Pulse are grayed out
    ( Y/ L8 D% r0 s0 _+ o+ W$ r& j1914812 F2B                PACKAGERXL    Hierarchical variable not evaluated3 ]6 p: Q" i, Y7 c4 K' z; ], m
    1639231 PSPICE             ENVIRONMENT   Remember last location in simulation settings
    & q8 p) I1 Z  |6 J' V/ H/ X5 ]" `1804391 PSPICE             ENVIRONMENT   Libraries with uppercase extension (.LIB) not retained if added using 'Add to Profile'" ^) X- r/ v+ m1 ~5 E
    1879915 PSPICE             ENVIRONMENT   Check points cannot be loaded from a directory with space in its name
    2 z  D) |# D8 J1695306 SIP_LAYOUT         STREAM_IF     SiP Layout - Stream out issue: Embedded or stacked components using pad reference in more than one layer0 A# [% J; t9 v7 J: B

    7 h+ v4 q+ U5 d+ {4 q
    ' h1 G3 n" l0 s% p1 t0 k* e( iFixed CCRs: SPB 17.2 HF039
    8 c7 n) x$ M% v05-11-2018
    ' X; Y; h( T: L% Z* ?4 a========================================================================================================================================================
    1 C# e- b6 [; QCCRID   Product            ProductLevel2 Title: H4 c9 k; \$ K6 q8 C. v) q, f8 u5 w
    ========================================================================================================================================================) g3 W, N' w8 q# e4 S. S
    1915149 ADV_PKG_ROUTER     OTHER         Auto-connect fails to initialize when rats are selected, but works with bundle! Z" Z( J/ P, Q! K0 N* O2 x4 k
    1870109 ADW                ADW_UPREV     Most mandatory properties turned into optional properties following database uprev
    8 M2 F+ {7 V9 I( T( H- j1758396 ADW                CONF          Server Memory setting in setting.ini is lost if server is re-configured using Conf
    % l0 z) T8 a  L% A( T3 T1911591 ADW                FLOW_MGR      Flow Manager does not start on high latency (> 25ms) networks: displays Java Content Disabled dialog2 c2 w, W" f& Y
    1887861 ADW                LIBIMPORT     Library Consolidation reports front2back issues but does not provide information about the issues.
    " @8 W0 B0 T' C( C2 [& r5 e1778977 ADW                REPORT_GENERA reportgen memory setting too high in release 17.2-2016 resulting in launch failure
    ( O7 H" S! [9 V( o( x; {1900422 ADW                REPORT_GENERA Save in reportgen does not save Preferred Part List entry into .rep file
    / i" d; B1 G1 L9 z. u& E. }1903888 ADW                REPORT_GENERA Report generator not outputting values as expected for PPL field& p& n% A- y3 Y/ P0 N* y
    1916903 ADW                REPORT_GENERA Reportgen -gui is not producing the expected result
    / E- J; G+ A& s% |. z1902184 ALLEGRO_EDITOR     DATABASE      Add connect in package symbol crashes PCB Editor when using the 'clearance_view' variable
    $ {! R6 g! b* K! R$ d# D' j1 G1914793 ALLEGRO_EDITOR     DATABASE      Updating shape crashes Allegro PCB Editor
    ( [" B" L1 m  p5 b1905138 ALLEGRO_EDITOR     DRC_CONSTR    Max Via count DRC disappears on running DRC update, K6 {2 D# {  h/ M# t" _* }. t
    1848015 ALLEGRO_EDITOR     MANUFACT      Export Creo View cannot find the webpage on the PTC site4 S. N' q  T7 Q8 _
    1850553 ALLEGRO_EDITOR     MANUFACT      'File - Export - Creo View' is not working$ V6 i$ v" m5 t  }8 O2 z
    1853960 ALLEGRO_EDITOR     MANUFACT      PTC Creo Interface link is broken
    , h: w, B% [9 p  y4 D" w- ~1862305 ALLEGRO_EDITOR     MANUFACT      PTC Creo interface link is not working
    5 J7 Y5 d6 H5 V! y% b7 |1878682 ALLEGRO_EDITOR     MULTI_USER    Delay in Symphony server session when server is started from Allegro PCB Editor/ ]3 f9 {7 x( \* `
    1890108 ALLEGRO_EDITOR     MULTI_USER    Database rejections in Symphony
    % b, y9 W4 j1 n0 s) B1887331 ALLEGRO_EDITOR     NC            Milling (NC route) in Gerber tools is not the same as what it is in the board.& G- ?* |0 ~, V  h/ U( p
    1898179 ALLEGRO_EDITOR     RAVEL_CHECKS  PCB High-Speed option required for high-speed rules when Venture license is selected
    $ K1 z6 q; a% X2 j1461142 ALLEGRO_EDITOR     SHAPE         Pin with nearly-tangent via fails to generate void in dynamic shape, results in short.4 o0 G: e8 V1 Z; D* F
    1863467 ASDA               CROSSPROBE    Highlighting all parts in PCB Editor does not highlight all parts in SDA
    + X* Q7 m- g+ S* Q1910974 ASDA               CROSSPROBE    Cross-probing between SDA and PCB Editor does not work
    0 p! A5 U0 M- P' ^  ?1904440 CONCEPT_HDL        CORE          SPCOCD-577 error on migrating from release 16.6 to release 17.2-2016& ]' G3 B9 I2 y1 ~' [+ I
    1909611 CONCEPT_HDL        CORE          DE-HDL stops responding on running '_movetogrid' and clicking 'No'7 m; h4 K0 |4 @3 F/ L; s. C0 \
    1808743 CONCEPT_HDL        PDF           Inconsistent display of Publish PDF hyperlinks9 M; T5 V2 j) |3 C
    1894868 CONCEPT_HDL        PDF           XREFs getting clipped in the Published PDF
    * a4 }+ \" i! E4 M2 d# d1911676 CONSTRAINT_MGR     CONCEPT_HDL   DE-HDL Constraint Manager crashes on selecting ECSet and then creating pin-pair option
    + U4 p& N) K* S) x( ?2 [# o2 ?1913968 CONSTRAINT_MGR     CONCEPT_HDL   Match Group pin-pairs are not created on applying ECSet to differential pair7 L8 n4 G& Y( h0 v: O# _2 `
    1899638 CONSTRAINT_MGR     XNET_DIFFPAIR Differential pair buffer models are extracted differently in release 17.2-2016 and release 16.6
    ' p- q; o* i1 `( _1914116 ORBITIO            ALLEGRO_SIP_I Unable to import OrbitIO file to SiP Layout
    3 E1 p3 X  X( k+ U1896487 PCB_LIBRARIAN      GRAPHICAL_EDI Use lower-case characters for notes and pin text in New Symbol Editor
    ; \  Z. O3 {5 `" g1 y+ E/ |1898008 PCB_LIBRARIAN      SYMBOL_EDITOR Styling is not available for custom shape and pins.
    ! p! X  f  e* ~( j$ ^" g1644787 PSPICE             FRONTENDPLUGI PSpice Model Search window does not show complete library path
    1 ^& G  h) p, Q. O8 {; p* t1785939 PSPICE             FRONTENDPLUGI PSpice Part Search library browser should display path of the library directories
    * e; h* D5 P3 Y, t8 u1855867 PSPICE             FRONTENDPLUGI PSpice Model Search window does not show complete library path# \/ `& O  ]" c& ^& L
    1887016 PSPICE             SIMULATOR     Pseudotran should always be invoked first time in case autoconvergence is ON
    2 S& w( X6 \6 ?4 J; ?1895752 SIG_INTEGRITY      OTHER         Layout Cross Section: Wrong Differential Impedance calculation (0 ohms) in RHEL Linux 7.1 or later versions" _8 p4 S  _2 i. }! Q
    1895759 SIG_INTEGRITY      OTHER         Cross Section does not calculate correct differential pair impedance in Linux CENTOS 7 and gives 0 value
      @9 g# ]+ W/ _7 H1909257 SIP_LAYOUT         INTERACTIVE   Error 'E- (SPMHGE-639): Copying component with bond wire is not allowed' when copying SMD symbols5 {: Q$ D: g  J8 _( U$ W) L
    1900970 SIP_LAYOUT         SHAPE         Shape does not void around SMD Pins and Vias inside pad: _" A, {: W6 L
    1885496 SIP_LAYOUT         SYMB_EDIT_APP Pin Numbering: different results for release 16.6 and 17.2-2016 for the same case.
    $ d4 q: ?$ h" z  l( F% \+ T% B! n: ^1907796 SIP_LAYOUT         SYMB_EDIT_APP SKILL commands fail to change pin number in SiP Layout2 W- z" x" N' m0 e& g6 q" S% I
    1887703 SIP_LAYOUT         WIREBOND      On trying to add wire bond to a die, SiP Layout crashes displaying a restart message1 f4 b  l6 E1 i: o8 q6 ^
    1903081 SPECCTRA           LICENSING     PCB Router is failing in Linux 7.1 in release 17.2-2016
    " u! P' {; q! l$ Q' D# q7 {1721606 SPECCTRA           ROUTE         PCB Router stops responding on exit if opened in the stand-alone mode, g7 g# u% t. ]( ?) I; O& v
    1844366 SPECCTRA           ROUTE         Allegro PCB Router will not exit
    7 c9 n2 G6 L+ x1873716 SPECCTRA           ROUTE         PCB Router does not close if opened from Allegro PCB Editor or in the stand-alone mode; \: T7 ^: Q+ F
    1907703 SPIF               OTHER         PCB Editor crashes on choosing 'File - Export - Router' in release 17.2-2016* w) x5 I7 j1 {6 |
    1889059 VSDP               DIEEXPORT     Incorrect pin location if bump cell origin is not at lower left for rotation other than R06 x+ a# }' j7 \
    . M/ |% S: u) q8 ^5 F9 Z4 k3 m5 p
    ; v* Y- N7 D) n) e3 S6 ^8 e0 T2 I9 W
    Fixed CCRs: SPB 17.2 HF038
    * m4 j! a) |# X' r) u+ O& \04-27-20181 s8 v3 V+ S$ j$ _7 f, k# o- t0 v
    ========================================================================================================================================================
    % l- S7 u( _8 H) x' vCCRID   Product            ProductLevel2 Title
    5 @" F4 L" X2 P& i/ m9 F========================================================================================================================================================# ?9 ^0 c% s+ j& O; K9 ]6 F
    1861616 ADW                TDO-SHAREPOIN Team Design Option requires Allegro_ECAD_Collab_Workbench license feature. U' ~5 R3 E" c8 A
    1784170 ALLEGRO_EDITOR     3D_CANVAS     Allegro 3D Canvas does not show the flex zone thickness correctly
    * i) ~! t& \- n) }, m1801053 ALLEGRO_EDITOR     3D_CANVAS     Moving component in 3D Canvas does not move the pads8 _; f% F* X6 t
    1805038 ALLEGRO_EDITOR     3D_CANVAS     Soldermask and drill not refreshed when component is moved in 3D Canvas, or on the board with Canvas open
    2 Z' G( `5 i9 `1808579 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas displays annular ring incorrectly# z' T3 _& F& X7 u; @
    1816732 ALLEGRO_EDITOR     3D_CANVAS     Mismatch in shape width between board and 3D Canvas
    " P  I* A5 Z. [1 I* ^0 o% T3 V1822778 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas does not display nets when selection is done through click drag
    9 `9 m# Y) Q' v5 q! w+ l1838129 ALLEGRO_EDITOR     3D_CANVAS     User is not able to create a pastemask layer that is visible in 3D Canvas
    + J8 Z: k- U7 {* l. m3 v, y3 N1842911 ALLEGRO_EDITOR     3D_CANVAS     Etch shapes not visible in the 3D Canvas when invoked from a symbol drawing. c9 Z7 x+ [5 U/ q9 C
    1849380 ALLEGRO_EDITOR     3D_CANVAS     Mirrored components placed in flex zones are not displayed in the 3D Canvas1 d1 a1 v& Y( E8 w" p6 a
    1851898 ALLEGRO_EDITOR     3D_CANVAS     STL export from 3D Viewer scales it up by 100. l; d; x3 P/ q# Y1 s" P3 A6 C
    1853378 ALLEGRO_EDITOR     3D_CANVAS     The new interactive 3D Canvas has a display issue with the off-centered drills.  B% Y  M* W" a# g  ?* u9 M$ Q
    1859713 ALLEGRO_EDITOR     3D_CANVAS     PLACE_BOUND shape with package_height_max and package_height_min set displayed incorrectly in 3D Canvas
    0 q3 g, B( H. @1880073 ALLEGRO_EDITOR     3D_CANVAS     Design Outline is not displayed correctly in 3D Canvas
    + o( [  h4 }' T  x$ F% N, s1880338 ALLEGRO_EDITOR     3D_CANVAS     Step Model missing in interactive 3D canvas." `+ M0 }, j3 W8 F4 D% ^/ ~% I
    1881889 ALLEGRO_EDITOR     3D_CANVAS     Changing the color of STEP model in STEP Mapping Window does not display this color in 3D Canvas.
    $ v6 k* x3 V, W# a0 w1889861 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas swaps padstack from Bottom to Top" x# X$ W& S! x! |: p
    1830749 ALLEGRO_EDITOR     ARTWORK       Gerber 4x and 6x output do not fill the shape3 n9 `8 M; i  u: F3 n
    1848514 ALLEGRO_EDITOR     COLOR         axlVisibleDesign does not interact with wirebonds/ M  p2 `+ K7 x! ]8 v
    1837388 ALLEGRO_EDITOR     CROSS_SECTION Cannot add solder mask to the site layer mask file
    5 c0 j& s  i. F$ u! c0 l9 t1859797 ALLEGRO_EDITOR     CROSS_SECTION The Report only option does not work when choosing Setup - Cross-section - Import - IPC2581( ?5 \5 {0 D+ S! j) t+ Z
    1877858 ALLEGRO_EDITOR     CROSS_SECTION Dynamic Pads Suppression option is not working correctly( ]: P  I+ D$ V4 q# ]: Q8 y4 }% b
    1880093 ALLEGRO_EDITOR     CROSS_SECTION Unused Pad Suppression options are not working correctly and are reset on opening cross-section
    2 p! }  @" L. m$ R, ?7 Y9 G3 I# l# \' I7 p1886283 ALLEGRO_EDITOR     CROSS_SECTION Unable to turn on 'Dynamic Unused Pads Suppression'8 m/ O& R( R7 k! I
    1890959 ALLEGRO_EDITOR     CROSS_SECTION Dynamic Pads Suppression option is not working correctly' B5 S8 T! N- ~7 b  l! M
    1900397 ALLEGRO_EDITOR     CROSS_SECTION Dynamic Unused Pad Suppression option in Cross-section not working at one go.
    % A2 ^0 s; I/ I1905315 ALLEGRO_EDITOR     CROSS_SECTION 'Dynamic Unused Pad Suppression' cannot be turned on.) Q. v1 v3 s9 o5 X; Q  v: \$ p5 b
    1861406 ALLEGRO_EDITOR     DATABASE      Refresh symbol for flex zone not mapping padstack layers correctly5 u# B1 \( T" R3 E. w
    1877132 ALLEGRO_EDITOR     DATABASE      Fail to open #Taaaaed17598.tmp file and save database' Z6 C5 W: B* J0 f) @% F4 n
    1883747 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes on stackup modification
    7 {, ?  ^8 Q5 Y. [+ |1860238 ALLEGRO_EDITOR     DFM           Applying a DFF constraint set closes PCB Editor instantly
    / G+ j* k' k& y3 g; l7 \1872780 ALLEGRO_EDITOR     DFM           DFF false pin to via DRCs: Copper Spacing, SMD pin Pad to Thru Via pad3 O6 L+ _  V4 J% r; P" R
    1823912 ALLEGRO_EDITOR     DRC_CONSTR    Thru pin to Thru pin DRC between Symbol Pin to Mechanical Hole (with NO regular pad)' \" _* h6 o$ }& Q- N0 }
    1828168 ALLEGRO_EDITOR     DRC_CONSTR    Upgrading from release 16.3 to 17.2-2016: Differences in spacing constraints
    9 _, S4 n1 A9 _7 U! e6 x8 A1844780 ALLEGRO_EDITOR     DRC_CONSTR    Mechanical Pin to Shape Air Gap value is reduced when updating shape
    4 P2 C7 I7 P9 `- T$ U1845011 ALLEGRO_EDITOR     DRC_CONSTR    When upgrading from 16.6 to 17.2, Spacing constraints for shape to mechanical pin not being resolved properly
    5 K1 B6 @) B1 }) R. l9 k1861548 ALLEGRO_EDITOR     DRC_CONSTR    Inconsistent Micro via to Micro via drill to drill overlap DRCs
    ' C3 x0 S5 ]! t. n1862281 ALLEGRO_EDITOR     DRC_CONSTR    Mechanical Pin/hole to Shape spacing too small! D8 @: L* Q. U2 m. j6 R2 J
    1887145 ALLEGRO_EDITOR     DRC_CONSTR    Mechanical pin to conductor spacing setting is overriding constraint region in release 17.2-2016
    * l) C, E. b# R& s1 U8 f  b1893012 ALLEGRO_EDITOR     DRC_CONSTR    Shape voiding not taking the shape to hole spacing rules for NPTH2 P8 W- W: ]7 x! s3 {
    1906840 ALLEGRO_EDITOR     GRAPHICS      Context menu stays when PCB Editor is minimized.
    ( W* T0 X" y9 }: Z; u, P$ U1738624 ALLEGRO_EDITOR     INTERACTIV    'Invalid Sector' error when saving psm file for symbol that has die pads, which are copied
    + Q  E& R7 |2 Z+ p1800741 ALLEGRO_EDITOR     INTERACTIV    Search in User Preferences Editor is giving incorrect results
    9 Q7 K1 J( G& ?; }' q2 u1812530 ALLEGRO_EDITOR     INTERACTIV    PCB Editor crashes when opening a file that is in an unsupported format% Q5 N. F' \) L4 w$ X1 g, Q
    1812570 ALLEGRO_EDITOR     INTERACTIV    PCB Editor hangs when an invalid pin number value is specified as the rotation point in the symbol preselect mode8 m7 m, Z) F5 y+ X9 G; l0 q& }
    1826819 ALLEGRO_EDITOR     INTERACTIV    'Route - Resize/Respace - Align Vias' menu is not available7 U  y6 }0 l' u' K# N) I
    1842645 ALLEGRO_EDITOR     INTERACTIV    Via align command is missing from the menu path/ Y  m' U4 y. F. Q
    1845748 ALLEGRO_EDITOR     INTERACTIV    With 'Shape - Change Shape Type' enabled, changing visibility reverts the Shape Fill selection to dynamic copper.
    / I' L+ l6 l. |. w" O1849700 ALLEGRO_EDITOR     INTERACTIV    Add the reason for generating DBFIX_PAD, to the dbdoctor.log.
    / @' \( C! U% H( n- I$ P, [1860934 ALLEGRO_EDITOR     INTERACTIV    Auto-Paste environment variable is not working as it should+ h+ N" w. d: v1 Q+ m8 ^
    1861928 ALLEGRO_EDITOR     INTERACTIV    Provide a Persistent snap pick option for Display - Measure  y0 r) g4 n; }1 q7 S: k
    1864238 ALLEGRO_EDITOR     INTERACTIV    Shape place rectangle issue: Dimension of placed rectangle changes on cancelling action
    ; W1 E# I5 a7 h2 Q( F* y+ x% l1877026 ALLEGRO_EDITOR     INTERACTIV    Filled rectangles on ETCH/TOP and ETCH/BOTTOM are not getting copied
    4 `( B! n  w5 L! i1881637 ALLEGRO_EDITOR     INTERACTIV    Radius of Shape changes when trying to place circle using Place Circle mode.9 E1 ~1 E8 @, _) A) G, n
    1883032 ALLEGRO_EDITOR     INTERACTIV    Find by Query does not find all padstacks in a symbol drawing
      \5 |, m, U! H% m7 k! b0 R1855248 ALLEGRO_EDITOR     INTERFACES    The Technology Dependent Footprint command returns an error
    ( B; R8 y% Y* j3 @1885716 ALLEGRO_EDITOR     INTERFACES    Increase supported STEP model size to enable the use of models larger then 500MB, {1 a6 D% a9 l: |7 _9 O! Z
    1860835 ALLEGRO_EDITOR     MANUFACT      Display a message when backdrill_max_pth_stub is defined for vias or pins only
    , s8 H6 u5 L5 r4 ~1869528 ALLEGRO_EDITOR     MANUFACT      Backdrill out of date when deleting Teardrop and Sliding cline with Teardrop9 i- W% Y' m- Z5 M0 j3 k$ \
    1885672 ALLEGRO_EDITOR     NC            NC drill is creating false backdrills when repeat code is turned on in release 17.2-2016
    : E7 T6 C" w  f, C$ A2 ?1895084 ALLEGRO_EDITOR     NC            Padstacks with backdrill data trigger backdrill out-of-date even if the board is not set up for backdrilling& d" b) Y# a, ?! ^5 Y8 ~' Q4 }
    1837514 ALLEGRO_EDITOR     PAD_EDITOR    Offset is not consistent for keepout and mask layers in padstack editor.
    1 l4 l3 s* Y! n1 H! N+ M% B1842902 ALLEGRO_EDITOR     PAD_EDITOR    Scrolling through the .pad files in the Library Padstack Browser displays Error(SPMHA1-161)* @9 f, G1 z* E( F' P- j
    1846504 ALLEGRO_EDITOR     PAD_EDITOR    COVERLAY_TOP definition lost while opening and saving a 16.6 pad in 17.2 padstack editor
    / C! K  o- E9 H' B/ B* A1879453 ALLEGRO_EDITOR     PAD_EDITOR    The 'Y' tolerance in the Padstack Editor does not update when changing the units of the padstack.
    , g5 f! r7 G8 P( O9 J1805202 ALLEGRO_EDITOR     PLACEMENT     Place via array adds via on differential pairs incorrectly- }) y' ]$ z  J8 S" o0 \8 E- l
    1806675 ALLEGRO_EDITOR     PLACEMENT     Place - Manually - Quickview displays the Assembly Top details only
    8 l8 X: J$ }( n' e/ B1 `0 s) ?5 R1835177 ALLEGRO_EDITOR     PLACEMENT     Can place symbol even after cancelling copy by choosing 'Oops' from pop-up' i, N: |4 X- |0 n5 K5 W7 o
    1846892 ALLEGRO_EDITOR     PLOTTING      PCB Editor Export PDF does not show lines correct for certain component
    2 g9 T, ]! a' L$ z* B1006328 ALLEGRO_EDITOR     SHAPE         Static shapes should void around corners as dynamic shapes do
    . ]) M: A4 F, D- Z* s% y7 M1033326 ALLEGRO_EDITOR     SHAPE         Cannot compose lines to shape' f" m2 x" j" ?$ m
    1045089 ALLEGRO_EDITOR     SHAPE         Dynamic shape voiding is inconsistent for solid and xhatch shape fill type) U  ?% s# u; j
    1069959 ALLEGRO_EDITOR     SHAPE         Compose shape crashes PCB Editor7 N: `) Y! p8 i+ B  S
    1085907 ALLEGRO_EDITOR     SHAPE         Pad does not get thermal connections to shape if outside of the shape outline by more than DRC spacing.
    * Q7 x1 T6 V/ E, s3 n1143563 ALLEGRO_EDITOR     SHAPE         The pin void inline clearance does not seem to dynamically update the shape and requires a 'force update'.
    5 g4 n9 q$ p3 H5 Z, D1243688 ALLEGRO_EDITOR     SHAPE         shape_rki_autoclip fails to clip shape to route keepin
    6 g! w% N1 G( U  I  `1269069 ALLEGRO_EDITOR     SHAPE         Shape void not working properly in release 16.5 hotfix 0542 c6 M& @) \' R/ T: k( [
    1327755 ALLEGRO_EDITOR     SHAPE         Need the ability to nest dynamic shapes on different nets partially or entirely
    & d% Z3 M' m2 q- l5 N- i1417394 ALLEGRO_EDITOR     SHAPE         Shape not updating correctly; ?/ W! @$ k: e4 @
    1430742 ALLEGRO_EDITOR     SHAPE         When adding fillet to an irregular pad, the fillet might not be added or be strangely shaped
    ' O- a" G  o3 M- R1750760 ALLEGRO_EDITOR     SHAPE         Shape to Route Keepout DRC for a void that meets route keepout/ {6 }7 X4 _6 u& b  Y% o4 K
    1793898 ALLEGRO_EDITOR     SHAPE         Add teardrops fails to add anything with different settings
    # j% @0 E4 f$ k9 r1811662 ALLEGRO_EDITOR     SHAPE         'show measure' gives incorrect air gap value between two pins
    - E# W( l$ _& z% R) {1820901 ALLEGRO_EDITOR     SHAPE         The pins on adjacent layers are voided as Rounded Rectangle instead of Rectangular as defined in padstacks( D: c# A, }: ~' J" l" @
    1829570 ALLEGRO_EDITOR     SHAPE         Display measure airgap value is very large; [1 S$ k8 K: r) D6 H
    1858696 ALLEGRO_EDITOR     SHAPE         The via to the edge of the board is not connecting to shape even with the PAD_SHAPE_TOUCH_CONNECTION property added+ v9 @& [4 o4 Q% L4 w: G$ T
    1873384 ALLEGRO_EDITOR     SHAPE         Boolean AND operation returning nil
    . p4 `1 V' r# Z! W, U4 q8 [1873860 ALLEGRO_EDITOR     SHAPE         Copper shape does not respect route keepout( _; a$ R+ a  e% x8 H5 u! t
    1889312 ALLEGRO_EDITOR     SHAPE         Shape voided for net vias on adding 'PAD_SHAPE_TOUCH_CONNECTIONS' when enabling via suppression  K2 p0 N5 E8 y
    1890702 ALLEGRO_EDITOR     SHAPE         Not able to add teardrop in release 17.2-2016- ^% O, {* p& o
    1892692 ALLEGRO_EDITOR     SHAPE         Thermal relief connections being added to static shapes present in the void inside Dynamic Shapes2 f6 U9 t2 S7 a9 m' h2 Z# d$ x
    1893492 ALLEGRO_EDITOR     SHAPE         'merge shapes' results in moved void
    ( w( n$ E7 D1 x% e' _1896543 ALLEGRO_EDITOR     SHAPE         Same net pin will not add thermal connection to shape if it is a rotated slot in the symdef
    $ H- M7 v8 _! {  R# [7 n# P  k1897645 ALLEGRO_EDITOR     SKILL         axlCNSGetSpacing() returns nil if active class is non-etch.3 p5 n4 {! w+ |" L4 t
    1822364 ALLEGRO_EDITOR     UI_FORMS      Design Parameters dialog disappears if prmed is called while show measure is active
    3 `* c. Y' Z! m9 l) M/ Z7 @. h1834395 ALLEGRO_EDITOR     UI_FORMS      Setup menu of OrCAD PCB Editor is missing the Anchor 3D View command; {, e+ I/ e/ z) S. H
    1838941 ALLEGRO_EDITOR     UI_FORMS      Anchor 3D View command is not available in OrCAD PCB Editor Setup menu
    ( H; w+ \$ x+ m7 U' X1716433 ALLEGRO_EDITOR     UI_GENERAL    Alias keys do not work until mouse scroll key is activated# ^' i7 |, t4 L6 n# E# Y
    1721761 ALLEGRO_EDITOR     UI_GENERAL    During manual placement of symbols, hovering over symbols does not highlight them+ e! C+ j8 P' B7 @0 A6 k; i
    1732915 ALLEGRO_EDITOR     UI_GENERAL    Alias does not work in release 17.2-2016 when switching windows/ B% m3 ~1 [/ `% |& z4 {4 C
    1770723 ALLEGRO_EDITOR     UI_GENERAL    Funckey does not work if focus is not on canvas in release 17.2-2016% d$ H' S  }4 v. o% L
    1793839 ALLEGRO_EDITOR     UI_GENERAL    Function Key does not work if a form is opened by a previous command0 S3 e* H+ {# Q- T7 a
    1813961 ALLEGRO_EDITOR     UI_GENERAL    Inconsistent file formats available when saving reports
    1 u9 x  X3 B: \$ w* F8 j. H2 h1816716 ALLEGRO_EDITOR     UI_GENERAL    Shortcut not working when using working layer with 'add connect'
    / L  P! k% Q" W$ K4 N5 b8 ]1864321 ALLEGRO_EDITOR     UI_GENERAL    Funckeys not being registered after focus has moved to other window and back again in PCB Editor6 y( M* b9 E# \) q, r" w2 s" b
    1865010 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor does not get focus when clicking shortcut after switching from any other program or application
    6 a; P; l  m. M1 a$ E; u* T1 M1868708 ALLEGRO_EDITOR     UI_GENERAL    Allegro PCB Editor, funckeys stop working intermittently in release 17.2-2016, hotfix 032
    # A3 ~5 `, u# d4 o/ T" f" b1869745 ALLEGRO_EDITOR     UI_GENERAL    Allegro 3D Canvas window becomes active on pointing at minimized icon on taskbar
    1 S/ z5 W! G8 s; b% m$ \. N5 U! @1869860 ALLEGRO_EDITOR     UI_GENERAL    Hotkeys no longer functional on switching from PCB Editor to another application and then back again3 p# @' I- ^/ C' i" j5 q
    1870744 ALLEGRO_EDITOR     UI_GENERAL    Need html extension added to Save pull down menu.
    - ~4 C; x1 }5 N; W" h6 ^1870996 ALLEGRO_EDITOR     UI_GENERAL    If you switch from one active window to other, hotkeys stop working* _! ]8 V: ~, ]
    1883507 ALLEGRO_EDITOR     UI_GENERAL    Hotkeys stop working after Allegro PCB Editor UI window is opened  ?, `" G% L# d: ?! T- y" N. c# w
    1886981 ALLEGRO_EDITOR     UI_GENERAL    Focus lost from layout when switching between PCB Editor and Capture$ s7 {; ]9 ?5 z! J' R- m
    1887519 ALLEGRO_EDITOR     UI_GENERAL    Release 17.2-2016, hotfix 034: Shortcuts defined using funckeys not working correctly+ D- Z8 _0 r# A, s
    1887660 ALLEGRO_EDITOR     UI_GENERAL    Alias does not work in release 17.2-2016 when switching windows.
    8 s' d8 O( I0 o: Z5 s! Z: M8 R# V1891204 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor crashes if SKILL form is closed using the Close icon ('X')7 a* m! b0 l4 r
    1898059 ALLEGRO_EDITOR     UI_GENERAL    Funckey commands are not working consistently in release 17.2-20160 ?0 P" ^+ |( p5 B1 a
    1902322 ALLEGRO_EDITOR     UI_GENERAL    Cannot use funckey commands when cross-probing4 m9 \' d+ H+ A3 L9 f6 H# z
    1905906 ALLEGRO_EDITOR     UI_GENERAL    Issue with keys and focus when navigating between windows
    7 R9 s4 q$ l7 g  F/ w- K1913768 ALLEGRO_EDITOR     UI_GENERAL    Uppercase funckey shortcuts do not work) G9 t3 A* x( \
    1751586 APD                OTHER         axlGetMetalUsageForLayer() for etch returns value including pins and vias$ d* t/ B# l0 W' K  k# u+ B0 w% K+ }9 ]4 h) e
    1863241 APD                SHAPE         Fillet is left on the T-Point without Cline(center) connection.
    $ a, L8 @  ^9 W6 i$ H2 {1894438 APD                STREAM_IF     APD/SiP Layout: Export rounded features as circumscribed and not inscribed polygon in GDS
    ( e2 U2 v, M& S6 b: @+ [9 ]1812699 ASDA               AUTOMATION    Enhance the performance when extracting data from SDA, using TCL functions
    8 ~. b6 ^2 B1 e1863436 ASDA               CANVAS_EDIT   alignment guides are not displayed when placing or copy a part, only when moving. They are most needed during placement
    % f0 c6 n8 V* \) S8 J6 G1863445 ASDA               CANVAS_EDIT   Dark theme blue text in docked CM needs to be of a different color: difficult to read$ j' U. A, a$ J5 \: o8 H
    1802111 ASDA               DARK_THEME    Dark theme in SDA should also change the border line color and text color of grid references: they are still black
    # A. x2 t0 E# ?! N9 Z/ l1869951 ASDA               EXPORT_PCB    File browser button in Export to PCB Layout flashes graphics of the window behind the form
      {9 v6 ]) k/ v8 ~0 _& j1845831 ASDA               FORMAT_OBJECT Width of the twisted pair of wire should automatically be set to 6, otherwise it is not drawn correctly0 Q+ R% W7 k+ g& U& {& O) n1 V
    1879914 ASDA               INTERNATIONAL Using French Keyboard cannot use the . (point) delimiter to set VOLTAGE property value' R( F' T1 s. `) M
    1865753 ASDA               MISCELLANEOUS Inconsistent and non-ideal behavior in SDA product choice dialog, small box, hard to check unlike the bottom box
    * R5 X- Q4 Y( l6 R1 y/ ~1 e/ o1863457 ASDA               PACKAGER      Unset all user-assigned references globally% v; c$ h0 u- z& P% p4 u
    1889301 ASDA               TDO           SDA TDO Crashes when switching to/from Offline mode& q2 a7 ~) `- Q& N1 z- ^
    1823203 ASDA               VARIANT_MANAG Variant setting part to not present does not do anything) j/ D! r" G7 |) X1 b& y9 K1 ?. f
    1823992 ASDA               VARIANT_MANAG Variant Editor fails to read netlist if a net is named NC7 w' {$ G/ g9 s3 e
    1863451 ASDA               VARIANT_MANAG variant mode can select multiple parts to add to variant but can't select multiple parts to hit reset
      z3 q$ I( T. j1 l6 o0 y1863455 ASDA               VARIANT_MANAG Cannot resize any panels in the Variant mode) w6 Z. t( _* @- h# a( ]; P+ y" _& j
    1874952 ASDA               VARIANT_MANAG Letter I in the alternate part icons in variant spreadsheet should be  white for readability
    6 S- t2 G8 @% b' a6 ~, h: l2 ?- i1878401 ASDA               VARIANT_MANAG SDA Variant Display - DNI marker color switches between black and red
    0 |6 n  {) x8 A1 r, q1877239 ASDA               WORKSPACE     SDA DRC window is hidden if undocked and minimized
    1 h4 M  j/ C" K6 Q5 X9 V6 M- e1809605 CAPTURE            LIBRARY       Part has pins in the incorrect order in the Connectors library
    " @; D* j. {8 j2 D" x1638693 CAPTURE            OTHER         Capture Footprint Viewer not showing footprint.
    5 W+ U, i+ [1 H, x5 G/ o1873612 CONCEPT_HDL        COPY_PROJECT  Copy project causes nets to be added to net groups and ports - fails to package due to mismatch' [& p# U/ l8 t9 G" z
    1779289 CONCEPT_HDL        CORE          Adding a component and wire and saving the design results in a 'Connectivity save failed' error
    5 w2 m9 H0 v# B! @1878719 CONCEPT_HDL        CORE          Cannot enable or apply block variants at the top-level in a hierarchical design.6 l4 l; o/ n1 T: N% }2 F
    1865480 CONCEPT_HDL        OTHER         'partmgr -ptfMode shoppingCart' cannot output cell name with project ptf file into shoppingCart.xml
    , p* Y& ^3 u, m/ u1829966 CONSTRAINT_MGR     CONCEPT_HDL   DML independent flow: Export Physical audits missing signal models in release 17.2: {" [) y% ~4 K1 b9 H1 A
    1904458 CONSTRAINT_MGR     ECS_APPLY     'Audit - ECSets' crashes DE-HDL in release 17.2-2016, Hotfix 037
    6 |6 f4 c. N& H8 ^+ X  ]1798269 CONSTRAINT_MGR     OTHER         Script changes '-' in layer name to '_'( {5 @, x* J! x9 _9 P
    1835520 CONSTRAINT_MGR     OTHER         Cannot add members to netclass name with parenthesis
      Z0 y" N' ]' _1 {& g- _) }0 C1896638 CONSTRAINT_MGR     OTHER         Constraint Manager worksheets jump abruptly
    - x- F+ z: Z4 G  c1801938 CONSTRAINT_MGR     UI_FORMS      Add To Netclass window: Focus not on ClassSelection/ s5 F4 w6 D" {2 I; I' v! b+ j
    1854060 CONSTRAINT_MGR     UI_FORMS      Using the tab key in the Manufacturing workbook jumps a cell
    , ?0 k' a5 k4 ]* a! |2 q3 M1881832 ECW                ROLES_PERMISS Adding Users in SSO environment using PS is error prone
    : n& F5 w3 b. R( W7 _1864870 F2B                BOM           Incomplete BOM report generated# b/ i' @% o& ]) M0 c& G! l* b+ i
    1846578 PCB_LIBRARIAN      GRAPHICAL_EDI radio buttons and clickable buttons are hidden in the UI for verify rules3 r1 y8 ?  W" ]7 S
    1854080 PCB_LIBRARIAN      METADATA      con2con needs to support special characters in Primitive Name' _( C3 H5 `0 t- Y
    1796377 PCB_LIBRARIAN      SYMBOL_EDITOR Unable to move pins using arrows when symbol is opened in Symbol Editor3 p/ u3 C: [/ d6 f; V% c
    1839692 PCB_LIBRARIAN      SYMBOL_EDITOR Properties tab grayed out in Symbol preview window
    7 k' e1 l4 t) R: Q$ A/ `" R1865657 PCB_LIBRARIAN      SYMBOL_EDITOR Cannot change symbol properties using the General tab3 |/ L  }6 D6 w
    1906888 PCB_LIBRARIAN      SYMBOL_EDITOR Properties button in Symbol Pins tab of the Symbols section is inactive.+ X% T2 y/ i8 M# V
    1891248 PCB_LIBRARIAN      SYMBOL_EDITOR Copy and mirror arc drawing object in the new Symbol Editor results in wrong arc on opening symbol in DE-HDL
    3 z" f' c" E. t7 W/ ]6 s1908381 PDN_ANALYSIS       PCB_STATICIRD Allegro PCB PDN Analysis crashes after performing analysis and saving result in release 17.2-2016
    6 C. g* P/ E: Q* F# B1825087 PSPICE             AA_OPT        Graph view menu does not appear when we use 'Curve Fit' in Optimizer.: P( ]' \0 s" O# d% J  t
    1808091 PSPICE             ENVIRONMENT   'orSimSetup' crashes when 'Restart Simulation' is selected
    & P# p$ J3 {1 U) C1811782 PSPICE             ENVIRONMENT   Setup Simulation Profile no longer enables Advanced Markers when appropriate
    / S& n# a! C7 R1834147 PSPICE             ENVIRONMENT   PSpice Part Search library icons not displayed if product is installed in the Program Files folder in release 17.2-2016$ D2 A: f/ y" X& H! p* e/ p
    1841992 PSPICE             FRONTENDPLUGI Getting a blank Error dialog while adding a marker
    . l* I/ ], F8 k, X) f3 J) U1858574 PSPICE             NETLISTER     PSpice simulation: Some models cannot be used after upgrading to release 17.2-2016) H# j5 G( a. o6 L
    1865022 PSPICE             NETLISTER     The division operator is not recognized by PSpice in DEV expressions in release 17.2-2016
      u# m% o. u" Z8 `- z# X1677119 PSPICE             PROBE         PSpice crashes when plotting simulation message summary
    ; m  @, v3 M1 d$ ^% O1837046 PSPICE             PROBE         On Windows 10, PSpice crashes on clicking Yes to see message
    : [& j; M" \& |3 \1 H6 p1879387 PSPICE             PROBE         PSpice crashes when we choose to plot simulation message summary* P5 h. z1 w4 N1 J
    1842231 PSPICE             SIMULATOR     Wrong results in PSpice Advanced Analysis for DC Sweep Analysis3 |1 o! r) Y2 R; J
    1843446 PSPICE             SIMULATOR     Distribution type is not showing under Assign Tolerance window for transistor
    ) @' k/ G" f9 v4 ]! y1872630 RF_PCB             ROUTING       Transition taper length does not work in route- Add RF trace
    0 f) w; \1 E( b) u5 [) h) L+ F! M1872636 RF_PCB             ROUTING       Inherit Width parameter in Route -RF trace only uses width of one side
    ( [( a: e5 R/ C% k1872644 RF_PCB             ROUTING       Regression RF trace: change in trace width not retained while routing4 G2 K; i! `$ Q2 |
    1901201 SIP_LAYOUT         EXTRACT       extracta is not retaining custom layer names
    3 E3 v( A$ z5 T) O" r, X6 K2 s" ^1813380 SIP_LAYOUT         OTHER         Layer Compare is not adding the required shapes! ]( ~4 l4 Z8 i) x# s
    1852762 SIP_LAYOUT         OTHER         Error generated in Package Design Integrity Check when adding soldermask to my design% [+ w6 G" i5 J: V
    1886847 SIP_LAYOUT         REPORTS       Incorrect metal area in metal usage report
    & f6 U( z. u% n5 y$ d1491315 SIP_LAYOUT         SHAPE         Dynamic shape filling exceeds the shape boundary on running 'create bounding shape' command
      X: p+ n( m7 c, J& N6 Z1853989 SIP_LAYOUT         SHAPE         'Shape - Select' and then' Move' from pop-up with ix 500 iy 0 moves shape diagonally
    6 k6 k2 N, m" m+ m% N1 c1868509 SPECCTRA           PARSER        Autorouter takes long time to invoke
    5 j9 y' i% W8 L7 ?1869317 SYSTEMSI           ENG_PBA       SystemSI PBA does not align correlation waveforms correctly on Linux platform
      g3 T; e  A2 a# t; B* e0 p
    + S7 T# v9 C: I  s7 ]# m  l1 q4 g7 D2 U1 ?/ d+ f. W- x
    Fixed CCRs: SPB 17.2 HF0379 l; t- b+ S1 L4 r. ?6 Q# x
    03-30-2018# I0 D: h% Z* s2 i$ ~! f8 O
    ========================================================================================================================================================
    ' \6 L3 a2 r9 y/ {; WCCRID   Product            ProductLevel2 Title6 q. l- A9 w; |9 Y0 C9 }/ o1 S
    ========================================================================================================================================================& i4 K& q' [8 V* Q/ j
    1886573 ALLEGRO_EDITOR     IN_DESIGN_ANA Fail to launch Sigrity executable from release 17.2-2016
    ; q  _" Q! x7 W/ u1891113 ALLEGRO_EDITOR     NC            Clubbing total backdrill layerwise data- o* s& _/ \8 k( ^$ _$ {
    1886085 ALLEGRO_EDITOR     SHAPE         Line to Thru Via DRC is not displayed automatically
    4 j% Q  C/ l/ N! a9 G  W: r3 b" C1850888 ALLEGRO_PROD_TOOLB CORE          Design Compare crashes immediately after execution
    2 a9 _6 ]1 ]) j6 s. w: B' S1639079 ALTM_TRANSLATOR    CAPTURE       Title block issues with third-party design
    # t# @7 R8 F5 c4 T6 U: o5 N! C1722577 ALTM_TRANSLATOR    CAPTURE       Third-party translator does not work in Capture in release 17.2-2016 if CDSROOT is not defined
    " B8 N* f" A0 ?2 p5 s! ~6 V3 y1744697 ALTM_TRANSLATOR    CAPTURE       Third-party translator crashes
    # m8 H2 j  F; E& f% ?1820160 ALTM_TRANSLATOR    CAPTURE       Title block does not show ghost image when selecting it for placement
    . ]5 ^' Q2 Y( R' ^) D1628560 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translation to PCB Editor not working properly* a: Z: `9 X; S! _, c& d+ I9 Q- N
    1836750 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator fails to translate a complete design; p$ ?5 t5 L' i, P5 ~% E0 A* K- g: k& i
    1844423 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translation takes a long time in release 17.2-2016, i( t, o0 a5 d% O, ~
    1849338 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translated board not correct
    ' S9 X( {+ @8 z3 V1894607 CONCEPT_HDL        CORE          Closing CM during 'Save Hierarchy' crashes DE-HDL
    7 F0 j1 d9 l3 b, C1703351 CONSTRAINT_MGR     CONCEPT_HDL   SigXplorer shows invalid models instead of default models in extracted topology- O# H% x& i2 \1 `2 }
    1868687 CONSTRAINT_MGR     CONCEPT_HDL   DML-independent flow: some pin-pairs missing for Differential Pair XNets when migrating 16.6 design to 17.29 S, _; Q3 e+ Y, A
    1868747 CONSTRAINT_MGR     CONCEPT_HDL   Additional pin-pairs created on migrating design to release 17.2-2016 DML-Independent flow
    & B/ C; `- W% M6 R$ a  |1887794 CONSTRAINT_MGR     OTHER         Ability to disable cross-section changes in F2B flow2 a1 H5 y5 F8 z6 T6 t9 f3 g
    1859193 MODEL_EDITOR       TRANSLATION   DML provided by Model Integrity has a parsing error: curve must start at time zero
    " c1 h( A: D4 P* P+ Y
    4 d$ J2 m; c; V! m9 ]1 w+ q  f
    " e( H# v& ^( L9 SFixed CCRs: SPB 17.2 HF036
    ! C# _0 s! ^  B03-16-2018( W7 ?9 ?8 Z, T& S0 X; u5 a) n" K- J, l
    ========================================================================================================================================================
    6 V2 w! H1 M: r1 Q3 i4 [9 }. bCCRID   Product            ProductLevel2 Title
    # h8 q' `" ?5 j# w========================================================================================================================================================  U0 N% l  g% U( j, b
    1880209 ADW                DBEDITOR      DBEditor quick search is resetting the check boxes in the Attributes tab! p8 T& z2 S$ p8 G2 F: O
    1880376 ADW                DBEDITOR      Allegro EDM Database Editor wildcard search functionality broken after installing hotfix 034.
    ( b4 D/ j8 z' d2 z% i5 j% J1855444 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes on creating MDD files after deleting subclasses
    % Q0 X  p- `. A/ _8 l5 h4 z1863478 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes on a specific machine when loading any .mdd file
    0 M/ `# W+ r$ ?! Q+ U5 u% W  j1875544 ALLEGRO_EDITOR     SCHEM_FTB     Constraints are getting removed) ?+ k" K# V4 Y! c
    1719683 ALLEGRO_EDITOR     UI_GENERAL    Incorrect display when using infinite cursor.
    - F# t2 l& D% X: L6 b( u  C1765989 ALLEGRO_EDITOR     UI_GENERAL    Selection window does not work correctly with infinite cursor option checked
    ( Y) j# X& v% _& _3 L! B# t# c1885667 ALLEGRO_EDITOR     UI_GENERAL    Infinite cursor is not working correctly
    5 \7 w* K+ ^" X1 F9 C1873954 ASDA               IMPORT_DEHDL_ SDA: Inconsistent pin number positions on part in an imported DE-HDL project
    3 F5 k# c9 l5 |$ w5 `' Z1873883 ASDA               NEW_PROJECT   SDA: New project from DE-HDL creates blank Page 1
    9 J: r1 ]/ o2 P0 S; `1852036 ASDA               VARIANT_MANAG Design with variant cannot generate a variant BOM
    2 [; {7 `( g/ N6 \$ P1875549 CONCEPT_HDL        CORE          Incorrect PART_NUMBER/VALUE properties on schematic5 L0 a2 z3 j4 n
    1881848 CONCEPT_HDL        OTHER         License issue: Cannot open Allegro Design Authoring and unable to choose options and features
    / @$ G5 k( S& U+ V7 c4 c' r) T5 G1872189 CONSTRAINT_MGR     CONCEPT_HDL   Pin-pairs are created for incorrect members of differential pair after ECSet is applied  x0 r1 Z3 l: P3 M2 Z; \
    1880235 CONSTRAINT_MGR     UI_FORMS      Ability to lock auto-generated Constraint Set in UI! o( K; ~8 C2 X
    1868711 CONSTRAINT_MGR     XNET_DIFFPAIR Nets are dropped from XNets on the BRD file in the front-to-back flow' e* ?6 z& c: i! A0 f' j6 y
    1879296 ECW                PROJECT_MANAG Mode to remove Uprev Lock from locked webs in admin keys7 t( t& V; d, p9 V, w
    1881632 PSPICE             SLPS          PSpice creates 'psp_input.log' during co-simulation flow
    : z+ L4 K3 e$ u. k% X; d% T4 }1879302 SCM                OTHER         SCM crashes when global nets are changed in the Block Packaging Options dialog box0 F0 `" z/ F: s5 q! a
    1879580 TDA                SHAREPOINT    GetData error when opening a project in Design Data Management* P, S! t9 x1 I1 k
    0 f3 K1 w  {! D- B) @* t
    " k( x/ j( M3 J0 g( z. d" z+ R  N
    Fixed CCRs: SPB 17.2 HF035
    ' E+ w" F5 ]1 ]' d03-02-2018
    ) b+ G, }1 ]% a, O. C5 e========================================================================================================================================================
    0 S7 C( ], P# S. c! j# pCCRID   Product            ProductLevel2 Title
    # f/ D* P# f0 j, M( W========================================================================================================================================================& @/ t/ ^$ L6 [( W
    1873547 ADW                ADW_UPREV     adw_uprev resulted in incomplete footprint XML: \, G' {, t8 d. O1 @
    1643895 ADW                DBEDITOR      Create Footprint model name is not working properly if footprint exists in local flatlib( ?1 I) z" \5 i5 h& X0 o! j
    1846400 ADW                DBEDITOR      'Copy As' and 'Rename' STEP model options do not work/ n$ j/ L. O! \# z% g
    1868299 ADW                FLOW_MGR      Copy Project fails and makes Flow Manager unresponsive
    & x9 \; `0 |: Q1872796 ADW                PART_BROWSER  Part/Model Details Attributes are all empty when connected to the EDM DB5 ~9 Y- T7 q8 S) i
    1877199 ALLEGRO_EDITOR     DATABASE      Purging backdrill adds bottom filmmask to vias when it is not defined in the padstack
    2 g9 d5 h$ h$ q1877219 ALLEGRO_EDITOR     DRC_CONSTR    PCB Editor crashes on updating DRC2 d# ]( t2 B0 `0 M' |/ M
    1875528 ALLEGRO_EDITOR     GRAPHICS      Subclasses disappear in partition
    ! Q4 O# f3 f- H1868364 ALLEGRO_EDITOR     OTHER         Translator for Layout to PCB Editor fails in release 17.2-2016 but works in 16.6
    : A: T& {  ], I4 I4 ^* e1822989 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor very slow when using infinite cursor
    6 i) f2 I' d) ^1855275 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor becomes slow if OpenGL is disabled
    + M' E' M: {2 p$ P& j1868803 ALLEGRO_EDITOR     UI_GENERAL    Infinite cursor not working as expected5 r5 e( l% K1 r1 z0 z0 Y8 A, O
    1869523 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor hangs inconsistently on axlOpenDesign" x$ t$ b9 Q" d" K
    1871409 ALLEGRO_EDITOR     UI_GENERAL    ESC key does not function with Enable_command_window_history set4 X  M' B- f* N) t/ N; I
    1812306 ALLEGRO_PROD_TOOLB CORE          Incorrect DIFF result of PCB Design Compare6 Y" a7 c! z" k$ I  z: f
    1872772 ASDA               MISCELLANEOUS SDA pulls a license for 'Allegro_performance'
    4 m/ T5 ~9 W% C- W, J1877070 CAPTURE            OTHER         Capture redraws icons& N' Q& o7 ]$ t4 P9 }4 w
    1863624 CONCEPT_HDL        CONSTRAINT_MG XNet names are changed in the designs migrated to release 17.2-2016
    / G* y- Z* u' P2 }% V- w7 B) @1866290 CONCEPT_HDL        CORE          variant editor/DE-DHL crashed when changing a component property
    0 g7 T6 o( C( ~6 B5 f9 B1858139 CONCEPT_HDL        OTHER         Slow graphic response in Windows10: Icons redraw
    # h& d+ w# ?& ^7 \: U) z1872703 CONCEPT_HDL        OTHER         Icon and toolbar in DE-HDL keeps on refreshing for every command. G! `3 l# A/ ?; Z2 [8 F4 L
    1873949 CONCEPT_HDL        OTHER         DE-HDL user interface refreshes frequently
    ; F& _! b4 X9 g# z1 N+ W1871542 CONSTRAINT_MGR     INTERACTIV    Extracting object with 'Referenced ECSet' does not inherit T-points from the applied ECSet" \/ v8 {1 J2 t* t+ Z' |( d" n5 r
    1868812 CONSTRAINT_MGR     UI_FORMS      Cannot Save Log File from CM ECSet Audit.
    ' R1 a( _# h" X1878574 ECW                PROJECT_MANAG Duplicate entries are created in SharePoint users list while creating project on SSO setup& u- D" L5 c1 K5 I
    1878619 ECW                PROJECT_MANAG Too many mails generated on doing create project2 E$ p3 S3 Y8 M- q
    1862772 ECW                TDO-SHAREPOIN Logical BOM file name not displayed in Changed Files of Pulse Activity Log.9 Z2 I$ X" ~  q+ r! T
    1860641 INSTALLATION       DOWNLOAD_MGR  Download Manager remembers credential settings
    1 w  a( T4 }( B, v% E, b& T( q1867195 INSTALLATION       DOWNLOAD_MGR  Download manager crash  ~4 t+ o5 \  k: }7 w: F* w
    1872187 SIP_LAYOUT         DRC_CONSTRAIN Sliding a cline removes DRC markers but updating DRC shows more DRC markers
    + }( M) O  ]7 S7 ?, {. g/ |
    0 v3 R6 k% D4 z/ O; g: d3 D/ b& R2 R7 a8 }  L1 m/ s! N! x7 r
    Fixed CCRs: SPB 17.2 HF034
    * W: Q' j0 W: I2 h8 t8 E! }02-11-2018
    * [. E( [, a0 x  D: S4 W2 F, r========================================================================================================================================================
    3 n! o' q! A6 D- S/ SCCRID   Product            ProductLevel2 Title' D  M+ n/ Y8 K' p
    ========================================================================================================================================================
    / d8 w) R/ x7 Q& L3 Z0 h1863981 ADW                ADW_UPREV     adw_uprev is taking a long time after installing hotfix 031+ F) o! r1 D' O) v  z) q. a' \6 ?5 w
    1868186 ADW                DBEDITOR      Configured LDAP authentication giving error on launching DBeditor after ISR31 installation
    ! o+ D: ?1 v3 z1861524 ADW                LIBDISTRIBUTI Library distribution is checking for obsolete classifications every time it is run hence taking more time5 g+ G; V8 J! w% N
    1842998 ADW                LIB_FLOW      Footprint model check-in fails with verification checks failed error
    & V/ F  `6 z" A7 f1863047 ALLEGRO_EDITOR     DATABASE      The layer added above the TOP layer in SiP Layout cannot be deleted from database.
    ) T5 u4 {5 R( v8 C- r0 i2 I1852799 ALLEGRO_EDITOR     DFM           Refresh symbols crashing inside constraint re-enablement code! D. ~. U1 N7 X6 p5 V8 J
    1865732 ALLEGRO_EDITOR     DFM           The Thru via hole to Pad check in Annular Ring should check only the Finished hole size instead of backdrill diameter- u1 e. e% E# k3 \6 C2 f
    1862977 ALLEGRO_EDITOR     DRC_CONSTR    Differential pair phase tolerance DRCs introduced in release 17.2-2016 DML-independent flow6 }1 v% Y  a( M& ]
    1864460 ALLEGRO_EDITOR     EXTRACT       Running Extracta from outside using command window writes layer name for top/bottom layers incorrectly for SiP designs
    & G' n; p' i; i* B7 n1 a1859208 ALLEGRO_EDITOR     GRAPHICS      Pop-up menu remains on desktop when PCB Editor is minimized
    ' v: ~2 L* c0 y2 t5 t1 {+ W0 z& H1866422 ALLEGRO_EDITOR     MANUFACT      Backdrill update taking a long time
    ) V  T( Q% q. m( m2 p1 n1 G/ q1867148 ALLEGRO_EDITOR     MANUFACT      Backdrill update taking longer time to process.
    8 ?  A1 I$ @9 t1872127 ALLEGRO_EDITOR     MANUFACT      Backdrill performance issues - Additional fixes required for S034
    ( p# N: I+ a  ~* m: M2 Y4 J' f1866577 ALLEGRO_EDITOR     SHAPE         Board becomes unresponsive on Shape Update or Slide Trace) u2 n7 N' t% q+ r' w! M7 l
    1867590 ALLEGRO_EDITOR     SHAPE         The Shape to Pad clearance on multi drill oblong padstacks is not working correctly
    # ^' K: @4 F; {. A" J% ]& Z( n4 f1871902 ALLEGRO_EDITOR     SHAPE         Void issue during rotation of symbol with multi-drill padstack from hotfix S032
    * t8 q7 i! V- S8 ]1866778 ALLEGRO_EDITOR     UI_GENERAL    Unsupported prototype 'Enable_command_window_history'  is not allowing text edits using arrow keys
    ( ~. e9 _* a3 P3 T8 h3 N( S1865757 ASDA               DESIGN_CORRUP SDA hangs when trying to save design or copy page or circuitry
    ! @" t# [% w$ {$ @# U1865872 ASDA               DESIGN_CORRUP Corrupt design crashes on editing., c2 h1 I$ q/ j/ e6 Z: l' G1 r& z; A
    1867039 ASDA               DESIGN_CORRUP Design corruption issues
    # h; }  [' K. W5 ?0 J: K' l1831263 CAPTURE            OTHER         Toolbar refresh is very slow on windows 10 after installing latest windows patch
    : @  c! o8 N9 o1843595 CAPTURE            OTHER         Icon refresh is very slow on Windows 10 Professional after installing Hotfix 0294 v- p8 b' D" [& U
    1845003 CAPTURE            OTHER         Application slow to respond after running for a long time
    1 |4 ~' I: F4 n2 A1 @) V1847062 CAPTURE            OTHER         Starting OrCAD Capture redraws the toolbar icons many times.
    * Z0 _( ]9 v3 u1 A, ?1850816 CAPTURE            OTHER         Capture redraws toolbar very slowly and repeatedly, Z4 Z7 j& r! h1 u6 M/ Q
    1851346 CAPTURE            OTHER         Capture CIS redraws toolbars repeatedly* l7 Y2 W8 _& f3 e- \
    1851354 CAPTURE            OTHER         Capture slows down in Hotfix 30 as tools icons are repeatedly redrawn very slowly  G$ d5 E/ }  U! u  J4 c
    1851883 CAPTURE            OTHER         Toolbar content refresh is very slow
    ; o- L6 ^' l; t1852819 CAPTURE            OTHER         Capture refreshes toolbar again and again
    & I7 Q: r1 v  G7 S1 l1853395 CAPTURE            OTHER         Release 17.2-2016: Capture is refreshing toolbar icons many times at startup with latest hotfix
    7 _1 b& k* u  }5 S" r1853972 CAPTURE            OTHER         Capture starts and redraws toolbar very slowly: ^5 v. r. k" U
    1854735 CAPTURE            OTHER         Capture toolbar reloads multiple times' |7 v" U8 U; G1 d
    1855850 CAPTURE            OTHER         Toolbar content refresh is very slow
    " v. i0 ?" a# |1857523 CAPTURE            OTHER         Toolbar icons refresh multiple times and very slowly in release 17.2-2016
    7 T' D' a5 d8 [2 ]1 z4 l1859219 CAPTURE            OTHER         Toolbar is refreshed multiple times while starting Capture CIS; z" U- a6 ^# I9 M/ Q0 `! o
    1859626 CAPTURE            OTHER         OrCAD Capture does not work with the latest Windows 10 update' t1 e! `8 \  I3 d3 Q
    1863341 CAPTURE            OTHER         Toolbar icon refresh is very slow
    / i5 ]8 m# r$ Z1865661 CAPTURE            OTHER         Release 17.2-2016, hotfix 032: Capture extremely slow on Windows 108 `" F0 w- V4 Y# D2 ]! e" ]
    1867009 CAPTURE            OTHER         Slow graphics with Design Entry CIS on Windows 10.6 \; f- S( w% e& h$ m5 v* Z% X" D
    1869160 CAPTURE            OTHER         OrCAD Capture poor performance (toolbar related)
    % V  \2 b. _( W! }. ~0 z1869692 CAPTURE            OTHER         Redrawing of toolbars on Windows 10/ ]6 Q$ a2 h3 X- l
    1870310 CAPTURE            OTHER         Allegro Design Entry CIS redraw issue! {" n! J/ B, b; P  d
    1870367 CAPTURE            OTHER         OrCAD Capture Slow Redraw
    3 B% b: M  _+ \) _4 w  h1871382 CAPTURE            OTHER         Schematic will not open and toolbars refreshed repeatedly
    $ E- U3 l) K, O- x, @- C' ]% Z) D* [1872427 CAPTURE            OTHER         OrCAD Capture freeze on Windows 10; ~  R0 Z3 V& t" ?
    1862679 CONCEPT_HDL        COMP_BROWSER  Unable to input property value to search in Part Information Manager
    ! M& r7 B% T2 F1865039 CONCEPT_HDL        CORE          'Save Hierarchy'  of a release 16.6 design opened in release 17.2-2016 results in unexpected part changes. L' c9 _: O# f, G' H9 a
    1866544 CONCEPT_HDL        CORE          XNET_PINS added to migrate Design as DML Independentflow does not get saved in the CSA files
    0 m. ~2 h! b! g( U1849363 SIG_INTEGRITY      SIMULATION    Differential impedance calculation shows ZERO when changing dielectric constant
    ; e3 }/ B+ f) H# @1854195 SIP_LAYOUT         UI_GENERAL    After setting 'enable_command_window_history' in QIR5/Hotfix 031,  Edit - Text no longer functions
    ! |% B& e6 T' M8 s# S
    ' d! r! M9 J% r  l  C2 n# u; T5 L8 P! |. i" E3 g- Y$ T% E- S
    Fixed CCRs: SPB 17.2 HF033
    9 x% O, I" I* M4 x+ j01-25-2018
    " {# T- `' w, M( j: h========================================================================================================================================================' ^2 _' d9 z( l$ A6 ~1 d
    CCRID   Product            ProductLevel2 Title
    6 b+ Z6 \1 \' W) j- E========================================================================================================================================================  @1 [( |0 S8 n9 b. F
    1828672 ADW                ADWSERVER     LDAP connection error while trying to log in to DBeditor
    ! C2 D  {4 J) o7 N1840699 ADW                DBEDITOR      Unable to release footprint model due to older version being linked to a DE-HDL Block Model
    . O6 Q6 k7 N5 h5 ^: @2 \) c% V$ r! D1852402 ALLEGRO_EDITOR     DATABASE      Cutouts are not converted correctly when opening release 16.6 board in release 17.2-2016: {6 X9 ^. N: ?* S2 _# I
    1855223 ALLEGRO_EDITOR     DATABASE      Release 16.6. BoardOutline not fully converted to release 17.2-2016 Cutout Layer2 f$ D- C1 x1 _2 _
    1855252 ALLEGRO_EDITOR     DATABASE      Unable to open a previously saved release 17.2-2016 database
    7 t3 `: i2 B9 Y* ~0 y5 Q9 s7 }1863025 ALLEGRO_EDITOR     DRC_CONSTR    Shape voiding to Via pad with backdrill keepout is oversizing the Dynamic shape void by the backdrill keepout
    # d) c0 r' Z% V. q+ ~1854087 ALLEGRO_EDITOR     EDIT_ETCH     Sliding arc crashes PCB Editor8 @9 t; S7 r6 \% r5 c; t
    1840667 ALLEGRO_EDITOR     INTERACTIV    Choosing 'Change Text block to' from pop-up displays message 'E- (SPMHGE-150): Text font is not defined'
    - Z; Z( O3 a( B" y- X1849133 ALLEGRO_EDITOR     INTERACTIV    On choosing 'Change Text block to' on text , 'Text font is not defined' message appears
    % j% R2 B. I3 i5 u9 a1854695 ALLEGRO_EDITOR     MANUFACT      PCB Editor crashes while performing nc_route( E+ s4 i( i" j, v6 v# r' Q; z- E
    1854634 ALLEGRO_EDITOR     NC            NC Drill file is generated with half the number of Drill Holes on enabling 'Optimize drill head travel'
    . n3 j0 a, j8 w  \5 Y. `. B1856773 ALLEGRO_EDITOR     NC            Issue with Optimize Drill head travel in hotfix 031: Missing drill holes4 ^. F6 f! b6 `4 P5 R  N
    1860876 ALLEGRO_EDITOR     NC            NC route critical difference between hotfix 031 and 022: No slots found warning
    : `, O; f& x6 I5 z1758671 ALLEGRO_EDITOR     OTHER         Export parameters takes long time to export and some times the process hangs
    7 O! w$ g: u5 ^" i1040989 ALLEGRO_EDITOR     SHAPE         PCB Editor crashes while editing board outline
    + a! p% {4 Y6 r1328385 ALLEGRO_EDITOR     SHAPE         Check for missing thermal reliefs when shapes overlap, h1 W& {2 R5 o( A" Q0 _' u
    1366376 ALLEGRO_EDITOR     SHAPE         Thermal created for Xhatch shape overlapping another shape, but not created when solid shapes overlap
      F7 g( o" w0 t0 {1716436 ALLEGRO_EDITOR     SHAPE         Acute angle trim should not violate DRC.+ l% r& I7 T, Q6 v  R1 h9 v
    1822377 ALLEGRO_EDITOR     SHAPE         Setting shape parameter Acute angle trim control to Full round produces unwanted shape to keepout DRCs# z7 R) X+ h* \9 s7 x9 u
    1826436 ALLEGRO_EDITOR     SHAPE         Same net shape to hole spacing not voiding shape for cline of different net moved close to vias of same net shapes; H) O5 r- m4 n$ b# ?) e- ~3 Z
    1834510 ALLEGRO_EDITOR     SHAPE         Same Net Shape to Via Spacing does not always clear correctly
    : t0 H' _, L* D  Y1850716 ALLEGRO_EDITOR     SHAPE         'DiffPair combined void for vias added with Return Path option' does not work with fillet and pad suppression! Q8 y" P! V$ R" t
    1852814 ALLEGRO_EDITOR     SHAPE         Thermal reliefs are not created after placing modules.! T% y! X& D  M/ b$ ?
    1853453 ALLEGRO_EDITOR     SHAPE         Route keepout clipping of cross-hatched shapes needs to be corrected& g8 b8 T+ q$ r( G, C- ]& t
    1859391 ALLEGRO_EDITOR     SHAPE         Shapes are not using 'minimum aperture for gap width' for voiding after back drill update./ k. e9 Q1 W2 Q1 e0 l9 a' W! E
    1859410 ALLEGRO_EDITOR     SHAPE         Shape to Teardrop is not using same net spacing rules1 f1 c# Z- {! @8 x$ E2 G
    1825397 ALLEGRO_EDITOR     UI_FORMS      Option panel disappears in release 17.2-2016
    ' e/ q# Z3 I4 ?4 F7 P5 p9 G% V4 Z1854070 ALLEGRO_EDITOR     UI_GENERAL    enable_command_window_history prevents many aliases and commands from working correctly
    ! w1 y4 h6 g; [1855180 ALLEGRO_EDITOR     UI_GENERAL    Comma and dot do not work in funckey if 'enable_command_window_history' is set6 }! P, j1 a+ ]: o2 J# D
    1860003 ALLEGRO_EDITOR     UI_GENERAL    Icons and features missing or behaving differently in release 17.2-2016, Hotfix 031
    + I& S3 J% r' Z4 M$ \1861278 ALLEGRO_EDITOR     UI_GENERAL    Icons and menus missing in PCB Editor in release 17.2-2016, Hotfix 031
    " q; i. _3 x* `+ u: k* q+ `1862292 ALLEGRO_EDITOR     UI_GENERAL    Layout Pins icon missing in toolbar in Symbol Editor since Hotfix 0312 a' D" M9 b4 j1 X- S  B( V& T
    1793284 ALLEGRO_PROD_TOOLB CORE          Limit View (V1R, V2R, COM) for OUTLINE layer.
    + H& U! z) F) }7 j1712701 ALTM_TRANSLATOR    CAPTURE       Third-party translator shows error for missing operand0 e  T- f( b+ d$ k
    1802182 ALTM_TRANSLATOR    CAPTURE       Imported schematic has connectivity loss
    6 }6 g+ O& D5 i6 G" U" G: w& L1802462 ALTM_TRANSLATOR    CAPTURE       Hierarchical ports placed incorrectly for imported third-party design/ ]+ V* L! b8 `/ Y2 I+ m
    1823935 ALTM_TRANSLATOR    CAPTURE       Translating third-party schematics with hierarchical pages from Design Entry CIS' V5 p( C1 m# @3 Y. ~; e% K8 ~9 S
    1830570 ALTM_TRANSLATOR    CAPTURE       Third-party to Capture translation is translating only one page out of 32
    4 u8 y8 y& C3 l& E$ r2 n: T# l( a: S1839627 ALTM_TRANSLATOR    CAPTURE       Third-party translator is not importing complete schematic& D2 c7 B' E0 o! p6 k
    1846965 ALTM_TRANSLATOR    CAPTURE       Cannot translate third-party schematic( `. H. B, [, b& n* S
    1816767 ALTM_TRANSLATOR    DE_HDL        Error when translating third-party schematic to DE-HDL
    # J5 k% Y* G% n8 f" U( G3 V1845601 ALTM_TRANSLATOR    PCB_EDITOR    Cannot operate third-party PCB translation in release 17.2-2016 Allegro Venture PCB Designer license! p% o3 t  e# S, @
    1841060 APD                DIE_GENERATOR Cannot 'die text out' from SiP Layout or Allegro Package Designer. \6 Q8 \1 D" W
    1793232 APD                SHAPE         When fillet/taper not connected to a pin, voiding process incorrectly applies shape clearance values
    - G- g" X, ?- C* y. {1846541 APD                SHAPE         shape degassing does not obey void to shape boundary0 i6 X* o, ^8 G2 q( I
    1863446 ASDA               CONSTRAINT_MA A space in the name of a spacing or physical constraint results in the incorrect constraint set name& K% J" n1 k/ k1 |
    1859678 ASDA               VARIANT_MANAG SDA - When hovering over all three buttons, under Preferred Parts in the Variant info it says (Do not install)
    / B1 u5 e1 m2 |& {! q) A+ @; a1815839 CONCEPT_HDL        CORE          Allegro Design Entry HDL crashes when entering Location data manually' p' Y& E3 e, f
    1841857 CONCEPT_HDL        CORE          Unable to modify Components in non-windows mode1 ~& P6 [2 K2 z5 v# y
    1852096 CONCEPT_HDL        CORE          Creating a block using top-down approach does not generate the CSB file
    % k5 `* d2 b) c* K  E* M  {* g- C1 }1857390 CONCEPT_HDL        CORE          DE-HDL crashes on moving symbol% ]7 ~9 n0 I9 c* N
    1789070 CONCEPT_HDL        OTHER         Having folder 'allegro' in cpm root directory gives error while launching layout editor from Project Manager
    , ~5 e7 H4 m0 H, {- W1862484 CONSTRAINT_MGR     CONCEPT_HDL   Extracting an ECSet in SigXP is missing a t-point
    8 `2 l3 y: x) |4 k* H# M3 n1863045 CONSTRAINT_MGR     CONCEPT_HDL   Pin pairs deleted for a few differential pairs after upreving the design to release 17.2-2016
      r4 w$ J& l- g+ k6 r( e" N+ M5 ^1863054 CONSTRAINT_MGR     CONCEPT_HDL   Differential Pairs are treated as invalid objects on upreved design1 u/ D. l. G3 M, J" o# M9 q$ N" o
    1863094 CONSTRAINT_MGR     CONCEPT_HDL   Pin-Pairs are shown duplicated in the topology for the extracted object (Diff Pair)9 U8 }& H8 U; ]
    1831998 CONSTRAINT_MGR     OTHER         'Tools - Options' settings not saved on closing Constraint Manager* m" ]/ D! ]4 @0 c
    1855324 CONSTRAINT_MGR     OTHER         Enable the option 'Expand Hierarchy' in 'Find and Replace' dialog, by default4 f1 ^! e" t' c6 @# a" b! n
    1860847 CONSTRAINT_MGR     OTHER         'Include Routed interconnect' option once enabled, should remain enabled for that board file
    * g" R9 `3 z1 {0 K% E: x! a& n1843359 EAGLE_TRANSLATOR   PCB_EDITOR    While importing third-party PCB, many footprints do not convert, even though the log file says footprint created
    : o' }4 O$ T' G# Y1839978 SCM                REPORTS       dsreportgen unable to output reference designator from a lower-level hierarchical block if it has a single component
    0 S% Y  J& @: d- Z6 t" `1850013 SIP_LAYOUT         OTHER         Environment variable 'icp_disable_cte_auto_update' needs grammatical change
    $ |2 g  n! T- q7 L4 O9 S: P1833742 SIP_LAYOUT         PADSTACK_EDIT When creating Die to Die Via using Generate Padstacks, resultant pad stack has wrong Layers/ k2 p  K' {) r* P/ f
    1619098 SIP_LAYOUT         SHAPE         Acute angle of shape in design
    / a3 @! x; t- g6 |* C1728628 SIP_LAYOUT         SHAPE         Auto-void in dynamic shape does not disappear if object is removed) K, x& \, p, d- F0 \. w4 x
    1854592 SIP_LAYOUT         VIA_STRUCTURE Create via structure returns an error
    0 N) A, O: z3 I9 `  I
    & g0 Z. m$ s+ [3 B' [6 N/ W4 D
    " Z3 c7 J- s( MFixed CCRs: SPB 17.2 HF032
    6 `2 l0 x& u, j% K- a7 y01-13-20185 A3 W8 e" {' ~2 i
    ========================================================================================================================================================
    " a% a* }+ w2 F' n' ^4 _CCRID   Product            ProductLevel2 Title
    " _5 H, `4 ^  G) N6 ]& L) Y1 B========================================================================================================================================================8 M6 H) v, |; V# L& J* ^
    1846603 ADW                FLOW_MGR      Copy project GUI not displaying correct design name after changing the project folder name* U7 q. F5 n7 r( s, d5 Z4 b
    1831152 ALLEGRO_EDITOR     3D_CANVAS     New 3D viewer canvas is blank
      k; t4 Q/ O* h# J1805870 ALLEGRO_EDITOR     COLOR         Color file with dot (.) in the filename is not recognized for setting color from the Visibility tab! o- |/ X4 c$ R  J. S9 r, d
    1843126 ALLEGRO_EDITOR     DATABASE      DBDoctor UI is taking very long3 A0 g8 l/ j+ i4 T7 |3 {# G9 [
    1857588 ALLEGRO_EDITOR     DFM           Design for Fabrication - Aspect Ratio is not taking correct drill hole size
    6 X7 n/ o2 h" D- k' x; {1844313 ALLEGRO_EDITOR     INTERFACES    STEP output viewed in third-party tool has parts sunken into the secondary side
    : u# j  ^# A7 y* n1801301 ALLEGRO_EDITOR     MANUFACT      Export IPC 2581 fails if VOLTAGE property is attached to the nets on each side of a RF component
    ; M- v* y) P6 M1850078 ALLEGRO_EDITOR     MANUFACT      Choosing 'Manufacture - Artwork' crashes tool
    , p  t" v# r2 A' `+ s! _1844049 ALLEGRO_EDITOR     MODULES       Module deletion not removing related component information.
    + i7 T& U6 F1 u1849665 ALLEGRO_EDITOR     MULTI_USER    Shape rejected by muserver
    2 E) ]- ^, P& N1 }8 B1782831 ALLEGRO_EDITOR     RAVEL_CHECKS  RAVEL file does not load when it is located on a network with a UNC path specified
    & v! T8 N4 W) ^4 j1830442 ALLEGRO_EDITOR     SCHEM_FTB     Fail to import technology file with message for failure to read the configuration file
    & x! `& p# n( V1837391 ALLEGRO_EDITOR     SCHEM_FTB     Capture Property cannot rewrite or update constraints in PCB Editor
    + P2 Q6 i2 {/ Y+ y2 V1840643 ALLEGRO_EDITOR     SCHEM_FTB     Export physical does not work after modifying PCB cross section
    " a. Q/ E, Y- j( V% j  J! i1718165 ALLEGRO_EDITOR     SHAPE         Drill hole cannot be voided by shape
    , F3 v4 h6 P. b1 i3 c/ C1 U; W% T1753245 ALLEGRO_EDITOR     SHAPE         Update Shape retracts more than the shape to shape spacing% b( [0 E' K9 m7 D
    1827366 ALLEGRO_EDITOR     SHAPE         out of date shape is not flagged as out of date
    + O8 e$ P" R& c1828208 ALLEGRO_EDITOR     SHAPE         Shape remains out of date, but status shows otherwise/ b* G$ Z* |" W+ N4 w) \
    1832098 ALLEGRO_EDITOR     SHAPE         Skip via shorts to plane at few places even after the necessary keep-outs are assigned to the via pad-stack.# _- V5 a. p4 W5 h8 @% d
    1834281 ALLEGRO_EDITOR     SHAPE         DBDoctor creates a large number of DRCs/ a1 s8 g! r; \) ~( R" n& O
    1842121 ALLEGRO_EDITOR     SHAPE         Unable to clear the Drill Hole to Shape Spacing DRC as Pin is not able void to the shape correctly.+ \! \. b; K7 Q7 A, Y/ Z
    1846010 ALLEGRO_EDITOR     SHAPE         Changing MCAD hole to copper spacing in Analysis Modes - Design does not make shapes out-of-date
    : ?, w) o7 ]1 k1839119 ALLEGRO_EDITOR     UI_GENERAL    On some machines, PCB Editor hangs when launched with a script that uses SKILL to open a design7 B# k$ F2 A4 Z: \0 U* a  Y6 B
    1828794 APD                SHAPE         Setting Shape Fill Xhatch Cells option to HIGH, crashes the application! {, b/ X# [" M0 t
    1840748 CAPTURE            PROJECT_MANAG Capture crashes on opening or creating designs
    - h; y0 H1 A; z1785298 CONCEPT_HDL        CORE          Incorrect object access during variant load
    6 j* G$ }' `/ i7 [& H0 ]# L5 t1832119 CONCEPT_HDL        CORE          Save Hierarchy shows ERROR(SPCOCN-2010) messages but design packages without error
    ; }+ L$ w0 G8 g1 ~2 I1833036 CONCEPT_HDL        CORE          nconcepthdl crashes with a core dump when running an external script
    % M8 r$ }, B3 ?2 Y/ W. O1841545 CONCEPT_HDL        CORE          NO_XNET_CONNECTION properties added to two-pin filters after upreving to release 17.2-2016
    " t0 X& c& @# L6 U1842289 CONCEPT_HDL        CORE          Opening a schematic in release 17.2-2016 causes the .dcf file to be overwritten
    , B2 g, A1 G0 E% _1 c3 n, h1841543 CONCEPT_HDL        OTHER         DE-HDL crashes when changing a net name/page name/bit bus after installing release 17.2-2016, Hotfix 029
    1 Y; o6 d1 {) K: K6 e5 M1843791 CONCEPT_HDL        OTHER         Table of contents listing does not update for some hierarchy blocks at the top level
    # K6 K( u9 I% [1 R1850709 CONCEPT_HDL        OTHER         DE-HDL crashes on editing text on canvas in release 17.2-2016, Hotfix 030% l& x$ I( ~- V( S7 J
    1853377 CONCEPT_HDL        OTHER         DE-HDL crashes on trying to edit bus tap value on Windows 10.
      Z/ X- C$ Y4 i/ ?. r+ j1857213 CONCEPT_HDL        OTHER         DE-HDL crashes when changing Power Property1 i: C" B& q& Q8 ?
    1857214 CONCEPT_HDL        OTHER         In release 17.2-2016, DE-HDL crashes on using 'Change' for a $LOCATION text value on Windows 10/ y9 u& C) a6 H8 {
    1821982 CONCEPT_HDL        PDF           Pin number shown in PDF published from DE-HDL- y6 A$ [7 z, O: a5 N
    1848615 CONCEPT_HDL        PDF           PDF Publisher shows incorrect pin text values for parts
    0 _+ S& }; _# f3 H1845996 CONSTRAINT_MGR     CONCEPT_HDL   Confusing error message regarding 'Auto XNets Off Mode' vs 'DML Enabled'
    & e/ G0 x; j; U" C8 z5 L1854190 CONSTRAINT_MGR     CONCEPT_HDL   'Audit - Electrical CSets' hangs Constraint Manager after the design is upreved to release 17.2-2016* j3 _/ V$ v& L- M" g6 k6 u
    1854868 CONSTRAINT_MGR     CONCEPT_HDL   Match Group getting deleted after upreving the design to 17.2 and removing the signal_models
    ! V# T( q8 {5 W! f9 r6 N( q1854872 CONSTRAINT_MGR     CONCEPT_HDL   Additional Pin-Pairs getting created on the DiffPair after upreving to 17.2
    2 [* j, e& F) R' c4 M* y! a1822624 CONSTRAINT_MGR     ECS_APPLY     Cannot copy PCB net schedule from a net to other nets
    / o( }- r0 h9 w+ n; V1854883 CONSTRAINT_MGR     ECS_APPLY     Match group showing 0 length for pin pairs in design upreved from release 16.6 to 17.2-2016
    ( S4 s# {# w' A$ G, h1855893 CONSTRAINT_MGR     OTHER         SigXplorer extraction crashes PCB Editor" u1 N. i0 \" B; S) p% F4 N9 @! `
    1855917 CONSTRAINT_MGR     OTHER         SigXplorer extraction does not extract constraints unless the worksheet is opened once in CM! J  Q, y/ T- U9 O, q% V
    1855350 CONSTRAINT_MGR     UI_FORMS      Constraint Manager significantly slower in release 17.2-2016, Hotfix 031
    ' t9 f4 R: |+ J9 ~* I/ t1 N1855860 EAGLE_TRANSLATOR   PCB_EDITOR    Cannot invoke a CAD translator in PCB Editor6 f. [: n3 r2 N$ p/ r  ]% m
    1857745 EAGLE_TRANSLATOR   PCB_EDITOR    A CAD translator does not invoke in PCB Editor8 a! Q; l5 g2 f( x
    1859005 EAGLE_TRANSLATOR   PCB_EDITOR    Eagle translator is not invoking at all
    ; m! ~, P8 C# P# t. ?9 C6 a1843091 F2B                DESIGNVARI    Variant Editor allows mismatched JEDEC_TYPEs in release 17.2-2016
    $ o- o  c6 k7 A4 k+ \, ^1719059 FSP                DE-HDL_SCHEMA Termination resistors on buses not being drawn efficiently6 o( g6 N4 R. H5 _
    1823419 FSP                GUI           Net Name Template not visible in Change Net Name in Windows 10! c/ l: w: x, m$ }- ?
    1480035 ORBITIO            ALLEGRO_SIP_I Die symbols are mirrored when imported back to SiP Layout: O+ R# l7 u6 r9 G  b1 S" W
    1853331 PCB_LIBRARIAN      SETUP         CPM file not updated from PCB Librarian setup
      o* R  C' Y4 t2 }1841308 PCB_LIBRARIAN      SYMBOL_EDITOR Symbol not updated in Library View2 J: k$ ^* n7 j9 H% [; W9 \3 g
    1831269 SCM                OTHER         Blank properties of associated components are being filled with NULL
    2 X3 n" R6 G8 V1719057 SCM                SCHGEN        Pins off grid for voltage nets' u& T, w) U- k" O# \8 A- l
    1719060 SCM                SCHGEN        Pull-ups and pull-downs showing upside down in view
    " h. z  v% \. m, V+ n) G  G1732687 SCM                SCHGEN        Schematic generation deletes IO ports; says it's placing them on last page, but never places them2 H, i, _& }" x7 R
    1855932 SIG_EXPLORER       OTHER         For non-DML designs, SigXplorer defaulting to mils when PCB Editor design units and CM constraints are in mm0 t" G# M2 g6 b
    1824035 SIP_LAYOUT         WLP           SiP Layout DRC GUI not reading Tcl blocks in PVS DRC rule deck5 i$ F  Y9 t" ~. @" ?( Z0 d

    2 \! J" C3 G$ M% x: a1 e1 P
    5 a& L* V8 P" W. |: B+ I7 {$ VFixed CCRs: SPB 17.2 HF031
    . e/ O% ?. B6 ]5 y12-8-2017
    7 W/ _; L7 g, n% v7 s1 Q% d========================================================================================================================================================
    * u! {" S) t3 t- {CCRID   Product            ProductLevel2 Title1 C8 w$ j* S0 z9 v; }5 I4 p& |/ B
    ========================================================================================================================================================
    9 E3 z5 l9 R2 h: f+ s" H1746108 ADW                DBADMIN       Adding and then saving a custom rule set in rule manager results in corrupt rules.xml, G  |! M6 {: p
    1609983 ADW                DBEDITOR      dbeditor should automatically change mechanical kit names to uppercase4 M" \, q2 m6 v+ x! w
    1807139 ADW                DBEDITOR      Cannot add new properties, though the new properties were shown in dbeditor
    & h' j' U  [0 [* p1807410 ADW                LIB_FLOW      Checked-in parts not available in database& g, |0 h2 _& ^
    1797408 ADW                TDA           TDO crashes without displaying exception during check-in
    # s/ a# j0 p: `  a3 K% G1804500 ALLEGRO_EDITOR     3D_CANVAS     Interactive 3D canvas fails to show all placebounds of a .dra
    0 w; p5 j' e3 g: w- w0 W# e1810758 ALLEGRO_EDITOR     3D_CANVAS     3D Viewer represents symbol incorrectly in hotfix 025 but as expected in hotfix 024
    " Z0 s9 ^0 V6 T1795567 ALLEGRO_EDITOR     EDIT_ETCH     Route menu has same hot key for 'Connect' and 'Convert Fanout'
    ' `' |( i6 o) I# e8 w% R- _1796525 ALLEGRO_EDITOR     EDIT_ETCH     AiPT is not pushing dynamic shape to add bumps to resolve dynamic phase DRC
    , F" P( \  L2 B1818170 ALLEGRO_EDITOR     EDIT_ETCH     Fanout with Outward Via direction is shorting few pins
    ( e5 w! `8 `( a5 {$ H! i# }1712658 ALLEGRO_EDITOR     INTERACTIV    Add connect: Pin remains highlighted even after choosing 'Done'4 f! z2 i: u$ e8 H2 _6 T( ~
    1727193 ALLEGRO_EDITOR     INTERACTIV    Logic - Part List truncates device names to 64 characters though database allows longer names
    . b9 U0 G, g* R5 z1775484 ALLEGRO_EDITOR     INTERACTIV    Choosing Next with persistent snap in Show Measure disables persistent snap
    & y, T9 C! p: j' ~+ i* V1711860 ALLEGRO_EDITOR     MULTI_USER    Multi-user lock cannot be cancelled- V. U/ x" [2 f% ^  p' L! F& N
    1812448 ALLEGRO_EDITOR     NC            Crash when canceling NC Parameters dialog
    % R, b, |! {, O  o% d4 G1792987 ALLEGRO_EDITOR     PAD_EDITOR    Pad Designer does not recognize flash names longer than 31 characters1 L2 B2 q; L+ Z. Y; s
    1810958 ALLEGRO_EDITOR     PAD_EDITOR    Padstacks with offset holes
    # B* b/ O4 H8 F: c) g9 a. I, J787024  ALLEGRO_EDITOR     SHAPE         Improve dynamic shape voiding in regions/ B' z% M8 P% c5 j6 L+ |7 X
    793232  ALLEGRO_EDITOR     SHAPE         Line to Shape spacing rule outside region affects shape void in region
    0 `7 t0 g1 [% [2 K797245  ALLEGRO_EDITOR     SHAPE         Line to Shape Spacing with Region not followed
    ) C$ S" A. w2 w& s% R8 V865822  ALLEGRO_EDITOR     SHAPE         The autovoid functionality should use the true line-to-shape spacing value
    + W+ X$ h/ Z8 Z8 j8 ?' G912051  ALLEGRO_EDITOR     SHAPE         Improve dynamic shape voiding in regions' p+ T, f7 W7 b0 v5 d5 W
    965714  ALLEGRO_EDITOR     SHAPE         Region constraints are not working correctly on dynamic shapes
    5 C& a' r& ?# l968342  ALLEGRO_EDITOR     SHAPE         Shape Voiding when crossing constraint region is taking conservative value and not the actual spacing value# ]7 s# Z8 ^0 o; h, G; S
    974734  ALLEGRO_EDITOR     SHAPE         Shape Voiding when crossing constraint region takes conservative value and not actual spacing value; d$ y" k! z$ `7 F: b7 o: F
    1073908 ALLEGRO_EDITOR     SHAPE         Allow line to shape spacing in Region5 L% Y  c3 l/ n" X
    1154787 ALLEGRO_EDITOR     SHAPE         Region constraints not applied correctly to dynamic shapes: U  p& D6 x  \' Y- r8 o
    1171283 ALLEGRO_EDITOR     SHAPE         Shape Voiding when crossing constraint region takes conservative value and not actual spacing value$ [- l; z. U; y4 M& O- c+ i4 E5 q
    1181767 ALLEGRO_EDITOR     SHAPE         Allow override on line to shape spacing in Constraint Region  |' {0 B1 H( D. I/ @3 A* m
    1183792 ALLEGRO_EDITOR     SHAPE         Allow override on line to shape spacing in Constraint Region
    - ^' a) b5 c: y& v, T1186210 ALLEGRO_EDITOR     SHAPE         Line to shape spacing constraint does not follow the Constraint Region value' a6 @, f/ G2 H6 d. S
    1192312 ALLEGRO_EDITOR     SHAPE         Region constraints are not working correctly.
    3 h& i( k' n  `0 L, |2 D" k1387021 ALLEGRO_EDITOR     SHAPE         Improve dynamic shape voiding in Regions4 ^! J) n/ X) g
    1447891 ALLEGRO_EDITOR     SHAPE         Resolved constraint and actual air gap differ1 c: K/ B3 u3 P2 c( P: i+ ~
    1465383 ALLEGRO_EDITOR     SHAPE         Line to shape spacing constraint does not follow the Constraint Region8 O0 L. o0 r. M/ l
    1583144 ALLEGRO_EDITOR     SHAPE         Line to shape spacing inside the constraint region does not follow region rules* F$ i6 [, A( M# U$ ~- i. v
    1591320 ALLEGRO_EDITOR     SHAPE         Resolve shape to pin constraint in constraint region
    0 u' b! H& }* U& o1627305 ALLEGRO_EDITOR     SHAPE         Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
    ) R2 c$ F$ g. h1694552 ALLEGRO_EDITOR     SHAPE         Constraint region not working correctly
    5 u, x& l, C7 j( o0 h" C" ?6 U" D1764474 ALLEGRO_EDITOR     SHAPE         Line to Shape Spacing for Region should be used inside region instead of conservative value
    ( a; i7 f. T% t1775119 ALLEGRO_EDITOR     SHAPE         Shape voiding is not following constraint rules for dynamic shapes in a constraint region1 U! l! G6 q( `/ Y2 a) [
    1784916 ALLEGRO_EDITOR     SHAPE         Shapes are not voiding to other shapes against DRC settings, creating random DRCs.
    ! N0 L; n' o- P& d# U1793179 ALLEGRO_EDITOR     SHAPE         'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
    ' l  ^) Z( g! B* T8 n1803365 ALLEGRO_EDITOR     SHAPE         Region shape to shape constraints take precedence when shapes have multiple constraints' a2 w0 s" }1 E5 v
    1800530 ALLEGRO_EDITOR     UI_FORMS      3D Anchor menu missing when using new style OrCAD PCB Editor menu
    ! o" x4 U& T+ M1813604 ALLEGRO_EDITOR     UI_FORMS      3D Anchor View is not available on OrCAD PCB Editor menu.
    7 {0 F% h" W8 w) K& l1784710 ALLEGRO_EDITOR     UI_GENERAL    During Place Replicate and saving file with same name, the warning pop-up window does not show on top2 E4 [; x& _0 c- E% d
    1784728 ALLEGRO_EDITOR     UI_GENERAL    During Place Replicate and saving file with same name, the warning pop-up window does not show on top
    0 B) M* T& `# U4 o: t0 h; F, z4 @1721853 ASDA               CANVAS_EDIT   Movement of components results in shorts and inconsistent routing' D% ~$ B$ u9 y& Q7 n: G+ V
    1802120 ASDA               CONTEXT_MENUS Ports are selected though filter is set to Components. a3 r8 b% N" u6 }6 w1 g
    1803832 ASDA               MISCELLANEOUS Browse and select new libraries without editing cds.lib) `8 E" ]+ z% |% e. h
    1804643 ASDA               TABLE         Exception when pasting table data from third-party tool in SDA
    # ~9 d, S% x; c  }: q( R1794004 CAPTURE            LIBRARY       Diode pin numbers different in Capture in release 16.6 and 17.2-2016
    % H/ r9 b. j2 p$ L- D" o2 Z  d1735506 CAPTURE            OTHER         File menu is missing in Capture
    4 }/ ^1 d1 k0 y# I1766663 CAPTURE            SCHEMATICS    Capture crashes during part placement
    % R8 H  e- U7 E  C; i0 _1762181 CAPTURE            SCHEMATIC_EDI Crash on 'Push Occ. Prop into Instance'
    ) C  y, U! W( I/ }- l* e1786762 CAPTURE            SCHEMATIC_EDI 'Remove Occurrence Properties' and 'Push Occ. Prop into Instance' corrupt database
    ( E) t. v; `: n1 g# S# H1759424 CIS                PART_MANAGER  Unable to save the link database part from part manager2 l- f+ ~3 N" S/ ], h
    1802670 CONCEPT_HDL        CORE          Variant commands take 6 to 10 hours to run on a block' n  H5 K& s' h9 k9 @) W& J
    1816798 CONSTRAINT_MGR     CONCEPT_HDL   CM API ACNS_DESIGN returns the design name in mixed case
    $ B4 W" `$ J" o1812656 CONSTRAINT_MGR     DATABASE      Constraint Value specified at the DEFAULT PCSet/SCSet is not shown in bold blue) Z: H5 O& Q) Q; `0 B* r( ]$ D9 Q
    1635766 CONSTRAINT_MGR     UI_FORMS      Worksheet views are not changed as per input
    % B% T7 `1 ^  t& K5 u6 l1700505 ECW                PART_LIST_MAN Shopping Cart Quantity is not read or not displayed in Pulse
    ! J% |; q& j% i) J% A1797371 ECW                PROJECT_MANAG Clicking on another project sometimes takes you to the default project instead of the project you click on
    . C* S# r; ]& Q9 P7 E  y& s1 E6 B' o1843526 INSTALLATION       TRIAL         Trial installer should not check disk space in update licensing mode! T; J- `/ r; W$ F/ z
    1762148 PCB_LIBRARIAN      SETUP         Part Developer: Text not readable in Setup form3 C* }2 I2 d5 `( Z3 h  A
    1770760 PCB_LIBRARIAN      SYMBOL_EDITOR Symbol Editor does not remember the last size of the window- l  l& I% y* Z3 R% U
    1773604 PCB_LIBRARIAN      SYMBOL_EDITOR Option to switch between the new and legacy Symbol Editors5 A4 W1 f. N+ c, L8 {
    1800354 PCB_LIBRARIAN      SYMBOL_EDITOR Resistor has too many lines and looks wrong in new symbol editor
    4 a: I; E* a1 p5 h  J8 h1813346 PCB_LIBRARIAN      SYMBOL_EDITOR Resistor looks different with multiple diagonal lines in new Symbol Editor but looks normal in DE-HDL
    1 }) f9 u* t- s& d2 Y7 X4 v! C1815279 PCB_LIBRARIAN      SYMBOL_EDITOR Unable to change Grid Settings from Lines to Dots- Y9 t3 e4 k$ V: o* B% k
    1738603 PSPICE             DIG_SIMULATOR Release 17.2-2016 PSpice digital model: Delay defined by PINDLY is not taken into account* C0 y' m+ ~3 P4 f' W( r) V
    1802905 PSPICE             ENCRYPTION    Incorrect option shown in PSpiceENC syntax in usage detail& i; F* c5 h: f) n4 f6 K& X; {% T
    1765345 PSPICE             ENVIRONMENT   Custom distributions are not added to the dropdown6 W. g! {/ B& r. t0 K! Y
    1784856 PSPICE             ENVIRONMENT   PSpice ignoring directory changes for Save check point in simulation setup session
    " Z. q. q2 @/ X! _7 K+ w1817805 PSPICE             ENVIRONMENT   Incorrect result for PSpice 'Start saving data after'
      v! u6 E( u' o4 ^/ q# V1784507 PSPICE             FRONTENDPLUGI Spelling of 'Definition' in PSpice Part Search is not correct
    ; d$ V) C; N  H' e1801790 PSPICE             LIBRARIES     SAC model giving errors
    ' ?5 P! A/ g# w6 p+ U* ~; ^1738776 PSPICE             SIMULATOR     PSpice simulation stops before TSTOP& j4 @  c( p) h" \4 E
    1795950 PSPICE             SIMULATOR     Simulation cannot be completed in release 17.2-2016 but is completed in release 16.62 `3 a; K% ]2 m8 D* n. Q7 I7 }! ]/ f
    1803407 PSPICE             SIMULATOR     Getting convergence error on a model8 M% g) s  c. o+ n( M0 d
    1814759 PSPICE             SLPS          .INC file is not working with SLPS
    : j% [; ]. o3 ]) S* }. H9 [1715859 SIP_LAYOUT         ETCH_BACK     Etchback mask not overlapping each other; creating floating metal' }% ?- D8 e8 p  N( Z" j5 k8 ~* s
    1729523 SIP_LAYOUT         INTERACTIVE   When creating a bond finger solder mask the results do not match the required settings
    & S3 Y6 G" c4 ^8 R4 T1800069 SIP_LAYOUT         INTERACTIVE   Corrupt dra/psm symbol, but the reason is unclear
    9 r2 {9 `5 O$ ]1 n$ _6 J4 `1756620 SIP_LAYOUT         SHAPE         Performance issue when moving vias.
    / u8 P0 i/ i9 {$ ~, T1782928 SIP_LAYOUT         SHAPE         Shape merging (logical operation) shows error though measuring shows elements are correctly spaced
    1 ]& i& o( F3 W( M2 i6 M+ a  k" Q' V1816454 SIP_LAYOUT         THIEVING      Thieving: need thieving as a specific data type in CM to better control the filling pattern+ J( M$ z8 I! o  ~7 z& J
    1728026 TDA                CORE          Check-in should not require all child objects to be checked in specially if they are not checked-out
    # J& ^" x$ M& Q* [$ J! s& r. V1823976 TDA                SHAREPOINT    Connection to server terminates when joining a project  X  x! J$ H+ G

    ' u. d& {" Y$ N2 J! @1 y) l) O
    1 D! O7 K" W$ X! D: EFixed CCRs: SPB 17.2 HF030
    & E; k* R4 L% Z11-17-2017
    $ i9 I: a' ^  x: e. I+ R( ~========================================================================================================================================================
    ) z: @' C5 v0 z/ L& d! i- ?7 U1 n% ]CCRID   Product            ProductLevel2 Title
    8 n. P* l' g6 h+ S* @========================================================================================================================================================
    6 v* _" ]6 [6 q' f3 X* S5 q+ ^1821774 ADW                DBEDITOR      MPN is tagged Pending Purge after deletion and lib_dist
    3 ~; w% K2 l( w. R+ z% n- [" T, F1829549 ALLEGRO_EDITOR     DRC_CONSTR    Dynamic phase DRC marker displayed at the design origin+ H! D; \: e7 ]7 A" l! f) n
    1690998 ALLEGRO_EDITOR     INTERFACES    Runtime error when running PDF Publisher  W6 W/ O* G) z6 I5 L$ z7 S; q
    1805203 ALLEGRO_EDITOR     INTERFACES    Runtime error when exporting smart PDF on a large board with all film layers selected2 F: R: k! Z' h2 O' P
    1811698 ALLEGRO_EDITOR     INTERFACES    Runtime error while exporting PDF% l1 q1 ?  f$ x' g
    1823818 ALLEGRO_EDITOR     INTERFACES    Cannot map some step models) S  Q1 }# D% s9 P# N: A4 Q- j
    1750654 ALLEGRO_EDITOR     MANUFACT      Cut marks cannot be generated on cut outline.! p: i6 f  j2 l' v
    1828293 ALLEGRO_EDITOR     NC            Incorrect status returned for backdrill3 I9 R9 s/ V2 e* P. H8 q
    1825401 ALLEGRO_EDITOR     PADS_IN       In PADS library translation, pads_lib_in fails to create Placebound_Top as a shape
    4 R- N; ~5 p" |, N2 ^/ ^1825427 ALLEGRO_EDITOR     PADS_IN       Symbol drawing files (.dra) created after PADS Library translation are not getting renamed to their decals
    / B8 K7 }) k; G8 ]: O1825460 ALLEGRO_EDITOR     PADS_IN       Pins are moved from their correct locations during PADS Library Translation
    3 x8 o# T1 r7 s( N" A1831200 ALLEGRO_EDITOR     PLOTTING      Incorrect PDF output for traces* g! ?4 R* f4 C: z' C3 j6 Y
    1321314 ALLEGRO_EDITOR     SHAPE         Force update of dynamic shape generates thermal tie that causes net to short
    2 s7 {5 X) M$ x% u1647585 ALLEGRO_EDITOR     SHAPE         Void around holes is not circular but of the shape of the bounding box" P, Z, E1 Z! j0 H. _( `
    1830676 ALLEGRO_EDITOR     SHAPE         XHatch Shape not voiding properly
    % e: w' Q+ Z2 [& D1821286 ALLEGRO_EDITOR     SKILL         Using axlSetParam to set static shape clearance parameter crashes PCB Editor+ {% L# O( v; p; c) f
    1804662 ASDA               DARK_THEME    Dark Theme: Change color of selected cells in Rename signals dialog so user can see they are selected
    + u# U% N1 o; ]( c& j6 F1817486 ASDA               NEW_PROJECT   Need to save a project with a new name, 'copyprojectas' does not seem to work; o# P& f7 ^% h/ Z
    1826023 ASDA               NEW_PROJECT   SDA requires user to go into project settings window twice to add a library) M: |& J, ^  O! b( W* w1 U) M
    1830632 ASDA               SCRIPTING     SDA crashes when you type 'find -types' in the Tcl command window
    . j* }! e( h: T- Z1798864 ASDA               VARIANT_MANAG Retain default part visibility when substituting preferred part for variant1 M8 C  b' v* ]+ L1 F
    1798865 ASDA               VARIANT_MANAG Value attribute of variant is off while printing though on for default and view' i$ D. ]! p5 `- I3 B$ ~
    1798866 ASDA               VARIANT_MANAG Variant Printing: Pin numbers printed though set to off on default part
    ' p; Z. M% B, w& N! z1831836 ASDA               VARIANT_MANAG Cannot delete existing variants in design
    ( {& v- }0 W& r1 Q- ~6 b1821120 CONCEPT_HDL        CORE          SIGNAL_MODEL attached to a component is not displayed on the canvas in the Attributes form
    ! e+ O" k1 f" _! {& a  T1824714 CONCEPT_HDL        CORE          Display issue: Page border disappears when running the command _movetogrid. O, c9 {- t7 @: p% y/ J
    1822587 CONCEPT_HDL        CREFER        CRefer crashes on a hierarchical design using split blocks8 N/ L5 u4 ~# G# ^& g
    1825461 CONSTRAINT_MGR     CONCEPT_HDL   Uprevving to release 17.2-2016 adds NO_XNET_CONNECTIONS on components having custom models7 \. V" _8 j/ p- O
    1825968 CONSTRAINT_MGR     DATABASE      cmxlGetObjects returns all the aliased nets and the physical net that goes to the netlist
    " ]9 i; g' g5 g9 _, u, z& ?4 m1819622 CONSTRAINT_MGR     XNET_DIFFPAIR Discrete with NO_XNET_CONNECTION removed from topology when extracted with Routed Interconnect
    2 E% k7 P: I# K4 Z* `# o1829762 ECW                PROJECT_MANAG Pulse log in: Multiple processes triggered, generating many zip file packets and corrupting many of the packets! {' M' ~/ D& h2 K( C: u. I
    1810296 F2B                BOM           BOM includes status column,  nothing should ever be forced on a users BOM output
    9 K! m5 S0 b; B; S1824593 F2B                PACKAGERXL    PXL crashes and removes the pxl.log file from the Packaged directory
    ; w' p: |6 X5 j& `# I$ V0 i! Y1832005 F2B                PACKAGERXL    Message stating 'PXL has stopped working' when packaging design
    + T* x& V& P+ {1822912 RF_PCB             AUTO_PLACE    rf_autoplace fails for RF component containing variable
    ( S1 K! R, K( E# b, T" X1803731 SIP_LAYOUT         DXF_IF        DXF export from 'Component Geometry/Pin_Number' subclass not working in release 17.2-2016
    1 ?- f0 W8 w6 a- f- @5 Q: C+ y1825478 SIP_LAYOUT         SHAPE         When running the Shape Islands report it is listing all the Fillets as Islands' \) e; _, q4 i; `3 f2 Q% A" P
    5 X' B+ l0 F4 |

    6 q6 K' C  G0 L" AFixed CCRs: SPB 17.2 HF029
    - e5 Z" s8 W& j6 e* e, b11-3-2017& H) y; L; y) L& c' k) o
    ========================================================================================================================================================
    1 I: D: P4 M1 _4 eCCRID   Product            ProductLevel2 Title
    + K7 i, y4 m- M: y7 k: g========================================================================================================================================================# u. Y1 m: c, l8 B9 r1 d0 }
    1814597 ADW                DBEDITOR      Associate part classification is very slow in release 17.2-2016 of Allegro EDM
    5 n$ {9 p5 U* e7 f9 n; D1733482 ADW                FLOW_MGR      After installing QIR3, Flow Manager prompts with Java Help question3 S2 f) L1 E) p1 w
    1814789 ADW                PART_BROWSER  PTF shows data in old component browser but not new component browser
    ' D/ ]2 h- S" L1808620 ALLEGRO_EDITOR     DFM           Missing graphics in new drc browser.
    # |4 G' F9 E+ Q% E; K, [1814558 ALLEGRO_EDITOR     DFM           Silkscreen checks do not work if silkscreen is defined as mask in cross section
    ; A% E* o% K  U! s& _- X1807996 ALLEGRO_EDITOR     EDIT_ETCH     Route Clearance View is not using the correct spacing constraint when nets are partially routed in a region
    % R5 w+ A7 Q9 Z( p4 l8 L; Z1747929 ALLEGRO_EDITOR     INTERFACES    Cannot import logo/bmp on a .dra file+ b) z% T: ^! }) G* M6 E  d' x5 h
    1820142 ALLEGRO_EDITOR     INTERFACES    pdf_out command not supporting UNC paths for the output pdf file
    . Q$ Y( ^7 `7 q& G' N1671865 ALLEGRO_EDITOR     MANUFACT      Exceeding 20 characters in Artwork Control Form - General Parameters - Prefix displays 'Illegal Character(s)' error
    3 i  b$ w" J9 z/ L) V7 E7 O/ W! {1710032 ALLEGRO_EDITOR     MANUFACT      Adding Artwork prefix gives error for illegal characters+ Q* \7 R$ L: l. p. Y  K7 L+ h
    1714911 ALLEGRO_EDITOR     MANUFACT      ERROR: 'illegal character(s) present in name or value' while adding prefix in Artwork Control Form
    - g7 c! M( w7 X  R9 U1 W, @; P1813950 ALLEGRO_EDITOR     MANUFACT      In the drill chart, the titles 'tolerance_drill' and 'tolerance_travel' seem to be reversed
    ; [9 l, l# y# O  S' K& f1820970 ALLEGRO_EDITOR     MANUFACT      IDX_EXCLUDE and BOM_IGNORE excluding objects from IDX export
    - X# E' R2 R7 `1822045 ALLEGRO_EDITOR     PARTITION     Shape fillet becomes static shape and loses fillet attribute after importing partition
    . V% X$ V. V! P1 B# S6 \, g, j1776181 ALLEGRO_EDITOR     SHAPE         Placing via arrays around a differential pair places vias only for one net
    ( S. w9 M5 j' Z" A  ]( J1 s1817283 ALLEGRO_EDITOR     SHAPE         Allegro PCB Editor Show Measure Air Gap shows a very large number
    7 P  }5 }! t- {: u1815595 APD                DRC_CONSTRAIN Differential pair spacing constraint not propagating to physical cset nets
    9 a# |+ U3 K- `& Z1785116 APD                SHAPE         Big size die performance issue0 g* z. `. ~- E
    1811134 APD                STREAM_IF     GDS stream out with 2000 precision has sharp edges along shapes.
    8 Y$ b( p/ u, H) Y$ N1811882 APD                VIA_STRUCTURE High-speed via structure refresh fails
    % o: g% y" [9 i% a1814878 ASDA               DARK_THEME    Part Manager: Difficult to read black text on black background  Z" I1 }5 W& T
    1814889 ASDA               DARK_THEME    Change 'updating route in progress' message color: a bright orange bar in dark theme is difficult to read
    # l8 C3 T- M* P8 g0 V# w# w1817355 ASDA               PAGE_MANAGEME Double-clicking a library in project preferences library does not move the library but changes appearance
    3 K6 v0 J4 y3 ?  t; B' ]3 [" E1817964 ASDA               SHORTCUTS     User Preferences shortcut misspelled
    3 j% w, p6 Q7 k7 H; H. O+ O1820247 CONCEPT_HDL        CORE          DE-HDL crashes while saving a design1 I* l; Y* U4 r0 _3 o+ u* |" M% _
    1823187 CONCEPT_HDL        CORE          DEHDL allows editing of the locked component's refdes using change text editor  D/ I/ A* ^8 e, g8 U
    1824052 CONCEPT_HDL        CORE          Trying to edit on a group containing a LOCK component, deletes the packaging data on the schematic
    7 Y- j' D' f/ j; [1813987 CONSTRAINT_MGR     OTHER         PCB Editor crashes when Constraint Manager is closed
    : t: F9 w0 @3 {1821129 CONSTRAINT_MGR     XNET_DIFFPAIR Uprev to release 17.2-2016 adds unwanted NO_XNET_CONNECTION property to discrete symbols( j, x6 _* C$ d% o
    1814725 PSPICE             PROBE         PSpice Measurements crashes PSpice for a digital simulation
    # Q! B5 g0 v2 M& _; B) R- S1 _  x1808672 SIP_LAYOUT         INTERACTIVE   create bounding shape command options: 'Min Area' and 'Sync with shape layer'
    $ W5 C. n2 }& m  d+ k1 Y1 R1817458 SIP_LAYOUT         MANUFACTURING Error in DXF conversion after updating SiP Layout  from Hotfix 066 to 082 in release 16.6
    3 }# N; q, Z% E/ o$ q3 A; a# J# q: H* `6 p- A
    ( r& ]( H& E! q! a. R$ `) u0 z
    Fixed CCRs: SPB 17.2 HF028
    , m* q( d. b$ a2 ~10-14-20173 w$ D/ i* G" k8 m! u% T
    ========================================================================================================================================================- J. |- G7 }$ G
    CCRID   Product            ProductLevel2 Title
    4 m/ U/ X8 C" l0 j========================================================================================================================================================/ E# E3 V. ~$ A( p/ |0 y4 Q) p
    1773530 ADW                FLOW_MGR      DE-HDL hangs on importing components from another design or copying and pasting components within a design
    " J  y6 [+ o; N# l6 s' T5 N6 L1790584 ADW                FLOW_MGR      SKILL code for comparing two PCB Editor .brd files does not work in EDM in release 17.2-2016, C" S: ?* i& A4 ]: u; i: r& J  K
    1794116 ADW                FLOW_MGR      LRM fails to run on project- n; h: f5 v7 F- N# ?& t- {
    1811532 ADW                FLOW_MGR      The message for missing tools.jar should not appear in adwcopyproject.log
    & Q4 N. }" {7 Y, L1812109 ADW                LRM           Library revision manager displays errors while re-importing updated sub-blocks  j, J2 j/ }: u. y" l! ~
    1771851 ADW                PCBCACHE      Problem in packaging upreved imported block" [1 n" N. w$ e: }
    1814785 ALLEGRO_EDITOR     3D_CANVAS     PCB Editor crashes when a bend is created and then viewed in 3D Viewer
    8 Z  v2 [: q) y9 W4 ^1800131 ALLEGRO_EDITOR     DATABASE      allegro_downrev_library utility fails on Windows 10
    * z/ O' Z, H- J3 f9 {9 H' [1814607 ALLEGRO_EDITOR     DFM           DFM check for soldermask does not include Package Geometry/ Soldermask if the soldermask is part of stackup
    / F# ]4 a6 X2 i, D' S" O1813996 ALLEGRO_EDITOR     EDIT_ETCH     Add Connect crashes PCB Editor if clearance view is set to channel" Z) \% j3 ]" A9 y4 i; v+ X% W
    1810832 ALLEGRO_EDITOR     SCHEM_FTB     Error while doing Export Physical from DE-HDL to PCB Editor0 L' L: z% ?( j. B+ H
    1811785 ALLEGRO_EDITOR     SCHEM_FTB     Import > Logic > Import Directory does not resolve the relative path to the packaged folder( h) z$ Z& [7 U$ p% u
    1814166 ALLEGRO_EDITOR     SCHEM_FTB     Error message when exporting design to board using an earlier version of database
    ) k/ x0 W' m! T/ y1817891 ALLEGRO_EDITOR     SCHEM_FTB     Error message when exporting design to board using an earlier version
    & u9 [  U/ Q: l6 R9 E1818954 ALLEGRO_EDITOR     SCHEM_FTB     Error message when exporting design to board using an earlier version of database* ]7 X# ]! F" D
    1812808 ALLEGRO_EDITOR     SHAPE         Artwork is different from PCB board% P$ l/ q' C7 ~, v
    1814836 ALLEGRO_EDITOR     SKILL         Doing zcopy Xhatch pattern crashes PCB Editor in release 17.2-2016
      E4 L% d+ _9 x8 W6 D9 ]" M1772218 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor stops responding on Show Element& R) c9 {9 n5 I7 H9 c
    1778353 ALLEGRO_EDITOR     UI_GENERAL    Intermittent PCB Editor crashes on loading IDX in release 17.2-2016 Hotfix 020
    ' h' b5 C+ f; a- M8 Y) }5 [+ s1818077 ALLEGRO_EDITOR     UI_GENERAL    axlViewFileCreate disappears behind window or is blank
    9 D6 l" ?1 b& R; ~1 T3 f1807423 ASDA               NEW_PROJECT   SDA CPM file has erroneous date
    ! g. d; H8 B) O, t0 X0 ^% O1809597 CONCEPT_HDL        CORE          Problem auditing SI model in Allegro Design Entry HDL from Hotfix 025 onward, no problem in Hotfix 024
    ' \3 ?. o* h$ ]" i1810322 CONCEPT_HDL        CORE          Unable to package design if OK_NET_ONE_PIN property is set
    ( i4 p0 D! d* Q; z% ~7 Q* w3 g1813436 CONCEPT_HDL        CORE          Read-only block import issue in same session: displays error message SPCOCD-553& i9 u! W, G" Y% }' P
    1813912 CONCEPT_HDL        CORE          The response in DE-HDL is sometimes extremely slow
    * k- F; T6 O$ h) _3 Q' U# T1812506 CONCEPT_HDL        INTERFACE_DES Error messages during packaging followed by a success message though there are errors in design
    7 L7 ~5 N+ [2 C3 C! o+ l1 a1808677 CONSTRAINT_MGR     CONCEPT_HDL   Auto-generation of differential pair finds several instances of the same net5 Y; P  v  X% {4 V/ M/ |( |: Y
    1808898 CONSTRAINT_MGR     CONCEPT_HDL   Unable to resolve the ECSet mapping errors if the topology has pin of PINUSE POWER & GROUND
      I4 i/ d9 d# |: Y  ~1810320 CONSTRAINT_MGR     CONCEPT_HDL   DE-HDL - Constraint Manager:  Cannot add group to net class if a net in group is a member of the net class
    ' O0 @! d- V% ~$ M  N) \2 N: t1812459 CONSTRAINT_MGR     CONCEPT_HDL   Auto-generation of differential pairs has issues
    7 T+ U$ {6 [; N( }5 y1796234 CONSTRAINT_MGR     OTHER         PCB Editor crashes on query (ALLOW_ON_ETCH_SUBCLASS) without data type defined
    0 I0 P% A" J5 t; J9 C" n1811692 CONSTRAINT_MGR     OTHER         Constraint Manager: Set Topology Constraints - Rel Prop Delay - Pins is empty in release 17.2-2016 Hotfix 0269 @7 l1 ^7 a# T9 F
    1816311 CONSTRAINT_MGR     XNET_DIFFPAIR Extracting a differential pair into SigXplorer crashes DE-HDL7 u! @9 j& X4 I8 r' \
    1807593 ORBITIO            ALLEGRO_SIP_I Die symbol shifts when importing die from OrbitIO to SiP Layout9 H' `& P* T5 i
    1800763 PSPICE             SLPS          Error while running co-simulation in MATLAB for PSpice-SLPS demo designs2 r: k, q) R$ t7 a, @2 X
    ' R" H/ ]1 o, D5 W! f  ^. Y8 [

    ) F4 y1 E, i; }# Y  Y* x. g1 LFixed CCRs: SPB 17.2 HF027
    3 {- F0 C/ M+ i09-29-2017
    8 i, i5 w  O  a  G========================================================================================================================================================
    ; _# n6 l' [. SCCRID   Product            ProductLevel2 Title
    0 ?3 o' n) Z" @* Q! G7 E========================================================================================================================================================2 D! }! ?' [3 \% _4 k' z! U
    1795353 ADW                FLOW_MGR      Tool unable to find project in windows_project.txt1 h0 Y: N6 B/ ]# E" L
    1810386 ADW                FLOW_MGR      Error regarding not finding project in 'windows_project.txt'& p# @; h4 H. `) f. R
    1743732 ADW                LIBDISTRIBUTI adwserver -install does not give error if it cannot connect to server.
    % z0 o& I' i- A; k8 Z: K1804378 ALLEGRO_EDITOR     3D_CANVAS     Bend area issues in 3D Viewer
    ! v" {: x3 G# v3 t/ U! w1795312 ALLEGRO_EDITOR     DATABASE      Cannot unlock symbols as status is changed to View on opening design
      x' [6 `) e. b3 I2 p1803262 ALLEGRO_EDITOR     DATABASE      Donut pad With DYN_THERMAL_CON set to FULL_CONTACT has connectivity issues
    1 y' y& L/ n7 S* M1 N. g# B1802183 ALLEGRO_EDITOR     DFM           Using mouse wheel to scroll error information in DRC Browser changes font size$ n9 [; X- Z- T1 ~
    1797222 ALLEGRO_EDITOR     DRC_CONSTR    Updating DRC results in error 'SPMHDB-403'- K, d, i3 v! B' @6 e2 B
    1792163 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashes on moving components
    ) D/ l4 v) _& f  U* d5 b1806640 ALLEGRO_EDITOR     INTERFACES    Step Mapping not working in release 17.2-2016 Hotfix 025: w( Q# Y& ~9 R& J8 m7 p- R) O
    1807278 ALLEGRO_EDITOR     INTERFACES    Running 'step_export_product_asm.exe' displays 'vcruntime140.dll' missing error& v7 p' T5 w. h2 J
    1807286 ALLEGRO_EDITOR     INTERFACES    The facet file (.xml) for the STEP model 'modelname.step' cannot be found.6 O8 f1 L% I: ]* K3 R% |' _
    1808006 ALLEGRO_EDITOR     INTERFACES    Facet file for step model cannot be found1 U5 @3 u2 l1 Z3 E
    1704335 ALLEGRO_EDITOR     MANUFACT      Documentation Editor shows an error about backdrill while no backdrill was used in the design" p9 k) }# [8 j# x, `" e
    1800115 ALLEGRO_EDITOR     MANUFACT      IPC2581 Export giving error that backdrill is out of date even though no backdrill is defined in the design
    : X' U& b" a3 Y1799444 ALLEGRO_EDITOR     PLACEMENT     Via Array - Boundary placement fails with error
    6 R  _, L/ I  p: p9 `1725242 ALLEGRO_EDITOR     SHAPE         'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape% `  P5 ^/ e6 U! m
    1804129 ALLEGRO_EDITOR     SHAPE         XHatch Shape not voiding properly+ i, C1 `: T' j0 O) R& |! s3 [% O
    1805238 ALLEGRO_EDITOR     SHAPE         PCB Editor crashes while importing netlist
    , c4 e( g; n9 F, O( A1803542 ALLEGRO_EDITOR     SKILL         Using axlPadstackEdit to change drill size causes via net to change in release 17.2-2016 Hotfix 025+ U0 r" V, t; C  E
    1800774 APD                STREAM_IF     Only one pad in GDSII when running 'stream out' with the Flatten Geometry option' s# E3 q4 J7 E& b, o
    1804196 APD                STREAM_IF     Component is mirrored by X-axis instead of Y-axis on enabling mirror geometry- z5 j, f$ B9 W1 p# b4 ^4 {
    1803375 ASDA               IMPORT_BLOCK  Import HDL Block fails with message regarding Xnet states and DML independence
    * l  r' E# U% c& c0 A% F1807423 ASDA               NEW_PROJECT   SDA CPM file has erroneous date
    - m% ]! N6 S9 z# W# d1789400 CAPTURE            SCHEMATIC_EDI Capture schematic opens unannotated pages on search7 ^9 R/ D% X; r0 F6 `  Z4 L. R- ?
    1801573 CONCEPT_HDL        CONSTRAINT_MG Upreving release 16.6 design to 17.2-2016 adds NO_XNET_CONNECTION to some components
    ! K7 R1 I* s/ a0 E6 Q6 {- c* e1810586 CONCEPT_HDL        CONSTRAINT_MG DE-HDL crashes when transferring XNET properties to similar components in a read-only block, W- Y9 `- w4 V
    1794169 CONCEPT_HDL        CORE          _automodel command crashes DE-HDL if PACK_IGNORE is set" V/ q1 E" s* g7 m
    1798672 CONCEPT_HDL        CORE          Dashes in design name creates an extra design folder in worklib after upreving to release 17.2-20163 E/ c) r2 x$ F5 [: F* Y0 I) b
    1802258 CONCEPT_HDL        CORE          Locking unlocked components results in a warning (SPCOCN-3403)
    ! k/ D! R0 N. R1803019 CONCEPT_HDL        CORE          DE-HDL crashes on backannotation
    , }$ {) H9 R0 i9 T( Q  g1803615 CONCEPT_HDL        CORE          After running 'Mark for Variant', the block cannot be changed to blue
    : q" {* q; s9 R& _+ `& Y$ D2 U1804029 CONCEPT_HDL        CORE          Visibility issues when using the LOCK functionality" ?( C  B4 G* e' a3 [# d, \, l
    1806352 CONCEPT_HDL        CORE          Group Mirror is causing design corruption.- ?3 m& q) w9 s6 `. e9 [, u
    1806978 CONCEPT_HDL        CORE          Cannot mirror a group of  objects$ g' I. R3 g& M* w8 Y" ]4 z
    1810387 CONCEPT_HDL        CORE          Mirroring groups causes erratic display and may corrupt database if project is saved
    6 n$ }" Z9 x" u/ R% p$ _* V1812811 CONCEPT_HDL        CORE          Schematic group mirror not working
    3 e5 Q# P4 U4 |7 N: W% D1810401 CONCEPT_HDL        INFRA         Add Signal Name: Cannot select suggested net name
    % I* I$ ]3 ^5 U1 m1787409 CONCEPT_HDL        PDF           Minus character at the end of netname causes unexpected string concatenation during PDF Publish3 \% x- y# t  `3 I
    1800931 CONSTRAINT_MGR     OTHER         Even after removing NO_XNET_CONNECTION on parallel termination, topology extracted has duplicate capacitors! p0 ~8 @* F# }+ K/ ]
    1790106 CONSTRAINT_MGR     SCM           Cannot find the constraints file (0) in the schematic project: u, q% I% u* y, M
    1787117 CONSTRAINT_MGR     UI_FORMS      Creating bundle in Constraint Manager crashes PCB Editor4 |. Q! t4 ?( M' r0 ]$ j
    1797384 ECW                METRICS       Pop-up metrics value tool tip is translucent, making values hard/impossible to read7 M. Q  `0 Y8 ~
    1803226 ECW                METRICS       Pop-up metrics value tool tip is translucent, making values hard/impossible to read0 x6 s) O5 V+ q. ~9 V3 H
    1664059 ORBITIO            ALLEGRO_SIP_I Incorrect connectivity after .brd import" M7 Y. }, z* v. e6 W& T
    1799338 SIP_LAYOUT         DRC_CONSTRAIN Multi-threaded DRC fails with internal memory error even after setting shape_cache_size
    $ M1 ^. |) [, ^6 t7 h7 p1799499 SIP_LAYOUT         DRC_CONSTRAIN Multi-thread DRC fails
    $ c4 Q& m8 [! [5 _3 e3 `2 h1806585 SIP_LAYOUT         DRC_CONSTRAIN Multi-threaded DRC update aborted: internal memory resource depleted# t# C# r: x6 V$ l. a6 k& I- N
    1809804 SIP_LAYOUT         DRC_CONSTRAIN Error message while updating DRCs in release 17.2-2016 Hotfix 026 regarding shape_cache_size8 K4 i; |# Z3 L/ f/ h
    1788770 XTRACTIM           ENG           Translated bump / ball conductivity is wrong (PowerDC and XtractIM)
    8 Y/ {% `: L: f) T6 P7 M9 v3 b/ `6 i& v# }! j' t8 v/ V  \& w6 @

    ! g# J$ D0 \0 J1 y7 ~# N) f8 XFixed CCRs: SPB 17.2 HF0268 A0 z4 k# Z- k9 l6 |3 J3 P5 k
    09-15-2017! A& d1 e/ w& v# b. K: I$ F
    ========================================================================================================================================================) I0 u) m+ P* q- Z! k
    CCRID   Product            ProductLevel2 Title4 ~/ M+ f# Q1 `, g3 P- c* z
    ========================================================================================================================================================  |. o* ^* _1 X
    1765398 ADW                DATAEXCHANGE  Duplicate  MPNs are created when updating MPN classification properties with data exchange: d3 Z% Y7 M  r4 W( K; a* B3 I
    1780147 ADW                DBEDITOR      'Associate Footprint from Tree' does not log the information
    8 x+ l' o; s/ r1790134 ALLEGRO_EDITOR     DATABASE      Correct spelling  in Layer Function definition$ A! @# }9 K# V4 n
    1792345 ALLEGRO_EDITOR     DATABASE      Pastemask is added to bottom layer on backdrilled pins
    - `4 M  I% G* u2 Q  R. u+ c- m. b! N1792930 ALLEGRO_EDITOR     DATABASE      Uprev required for all libraries and padstacks to use release 16.6 DRA in release 17.2-2016
    9 o  c' M$ l. @/ j, b9 L1781203 ALLEGRO_EDITOR     DFA           DFA Spreadsheet Editor not starting from Windows Start menu
    - f8 U1 j% p1 `6 I+ `1797422 ALLEGRO_EDITOR     DFA           DFA Spreadsheet Editor not starting from Windows Start menu
    * u8 V) b; u/ z# \1770694 ALLEGRO_EDITOR     INTERFACES    Incremental IDX does not place unplaced components
    " M$ ~. B  x; A( H9 D- X; s0 I0 O1776791 ALLEGRO_EDITOR     INTERFACES    STEP file not displayed in PCB Editor for mapping7 \1 V9 {6 o! _
    1783515 ALLEGRO_EDITOR     INTERFACES    PCB Editor reading step model incorrectly
    4 J3 `8 W/ H3 v1 T  U7 \2 ]/ S8 L! w1781485 ALLEGRO_EDITOR     MANUFACT      Setting ipc2581attrpath results in error 'E- ipc2581attrpath: Variable not defined'
    0 H4 r2 N2 o5 s/ [& A. A. z1772713 ALLEGRO_EDITOR     MULTI_USER    Allegro Symphony Server rejects group moves
    7 G1 o# C8 j. H- u6 C1789853 ALLEGRO_EDITOR     MULTI_USER    Symphony Server rejects updates and hangs frequently: E# p! ]! v8 W
    1725591 ALLEGRO_EDITOR     OTHER         File - Export PDF crashes on the design attached! Y7 L2 D% H% ^$ _* w' V  s/ q
    1736324 ALLEGRO_EDITOR     OTHER         Export - PDF fails to export PDF
    4 ?0 p$ i" w8 E9 G5 i5 z1794071 ALLEGRO_EDITOR     PLACEMENT     The placement of component is very slow and takes around 3 to 5 minutes per component.
    ' y: h1 ~6 Z, v. h1496199 ALLEGRO_EDITOR     SHAPE         Overlapping route keepouts result in a broken shape.' k: x" D% B9 }" E1 @
    1760146 ALLEGRO_EDITOR     SHAPE         Void offset in Artwork but not in board for a particular instance only: [0 e) A/ \. q+ N4 }/ d: w
    1770372 ALLEGRO_EDITOR     SHAPE         Overlapping shapes merged in artwork shifts void causing a manufacturing short
    7 Q5 {9 o$ N2 F) y; j1793419 ALLEGRO_EDITOR     SHAPE         Unexpected shape void in artwork in release 16.6+ X2 b2 C& q! ~) x1 @
    1796666 ALLEGRO_EDITOR     SHAPE         DRCs for out-of-date shape while placing single via
    1 x" x3 [# E! \, J8 t2 V3 K6 V) C  ~$ S1786386 APD                EXPORT_DATA   Exported dra and pad files do not have right stackup  r/ r3 M, @. N% y* L
    1765673 APD                SHAPE         Shape in Cu1 and Cu3 cannot void correctly
    0 d1 W1 }& R' i# J& _' r7 X1782418 APD                SHAPE         Artwork is showing unnecessary horizontal lines- {6 n; B/ b* p8 `( |
    1778366 CONCEPT_HDL        CHECKPLUS     CheckPlus not printing logic design name( p% u6 X9 K# G; l
    1723855 CONCEPT_HDL        CORE          Cannot use Rename Signal for unnamed wire segment if the wire has a branch to the same instance, R, V  `: _/ t7 e
    1755174 CONCEPT_HDL        CORE          Unable to create XNETs on the read-only blocks
    " l% Y; E6 x: l, u# w. p! _& |3 A0 ?/ b1765533 CONCEPT_HDL        CORE          Strokes are slow to respond in release 17.2-20160 c6 f, P, y- b1 Y  o2 x: I
    1780253 CONCEPT_HDL        CORE          In Windows mode, with copy command still active and symbol on cursor, DE-HDL stops responding on pressing Delete key% |5 i: u  H& E
    1785069 CONCEPT_HDL        CORE          Warning box for SPCOCN-2251 needs to be resized and the text formatted correctly- a: D$ c' x  T
    1786030 CONCEPT_HDL        CORE          Packager fails in release 16.6 but runs successfully in release 17.2-2016
    * m5 T  j- M1 D' Y; p1788077 CONCEPT_HDL        CORE          Creating new window (new tab) in DE-HDL resets view of original window
    9 T* R2 U1 ]" g9 ?$ g$ t2 ]1788591 CONCEPT_HDL        CORE          Wrong pin number displayed after running packager- J; O2 [  @+ @$ R# r! h5 A" H
    1776774 CONCEPT_HDL        CREFER        CRefer crashes without error entry in log file3 Q8 q8 {( |" y; w5 U, y
    1328320 CONCEPT_HDL        PDF           Cannot select/search sig_name in published PDF
      J; ?9 |1 \/ t9 A1787409 CONCEPT_HDL        PDF           Minus character at the end of netname causes unexpected string concatenation during PDF Publish8 j% Q& O, g5 |6 _
    1758122 CONSTRAINT_MGR     ANALYSIS      Extracted topology for a differential pair is missing a pin-to-pin connection in the top file2 s6 |* U3 c' y( N( f- ~% T8 H& N
    1786161 CONSTRAINT_MGR     CONCEPT_HDL   Random crashes in release 17.2-2016 while working on the schematic editor along with Constraint Manager, J6 p" ^  Z) o$ ?. Q) D
    1788877 CONSTRAINT_MGR     DATABASE      Constraint Manager API cmxlImportFile looks for sub-string during replace mode and not explicit names
      q$ x6 N# [9 ]; \9 \: I- k1800263 CONSTRAINT_MGR     OTHER         DE-HDL and CM crash when deleting regions
    $ _9 x$ v* R# q% n" X1792000 CONSTRAINT_MGR     UI_FORMS      Data type of constraint not shown in GUI3 J1 ^; [3 H: B, L, v
    1744828 FSP                CAPTURE_SCHEM Button appears during 'Generate OrCAD Schematics'
    7 S& D: o' v2 S3 V- X; M$ ^8 X7 R1747568 ORBITIO            OTHER         Import of .oio file in SiP Layout takes a long time" x+ `$ P  _/ X
    1765229 PSPICE             AA_FLOW       Not able to run PSpice MC after setting Assign Tolerance/ E% Q  V' C% i. T- ~
    1770174 PSPICE             MISC          Issues with DMI Template Code Generator7 }0 j) |  ^) h4 ]! l7 V" r
    # }% e' m8 U7 u% v( K

    8 }  U( j5 M' k% \% K. s+ ~7 rFixed CCRs: SPB 17.2 HF0254 K0 h7 P; A2 R: t, a
    08-25-2017, f  }- D5 L5 `" A7 u4 _- |, y
    ========================================================================================================================================================$ J8 _( M) H# F/ ?
    CCRID   Product            ProductLevel2 Title/ L6 _* H) G: a& p9 ~: m4 n
    ========================================================================================================================================================- e# ~9 R/ `  z/ J. v4 S
    1258913 ADW                ADWSERVER     Copy project message: Unable to locate tools.jar
    * a" L. C8 R5 M/ r) x" D1760866 ADW                ADWSERVER     Metrics dashboard in Allegro EDM Configuration Manager does not show updated SPB 17.2 hotfix
    - Y% I& A  b, ~2 G$ l# U# q1055946 ADW                ADW_UPREV     Set PTF_SUBTYPE SEARCHABLE to false and default value to exclamation mark
    - _% O* Q/ Z  q8 _* {& ]4 G1508163 ADW                COMPONENT_BRO Manufacturers Part tab disappears on clicking anything other than the part number in the left tree- h. ?; k; W. E2 [" _) w9 S! _* x
    1774164 ADW                COMPONENT_BRO In release 17.2-2016 Hotfix 22, DE-HDL crashes on using Generate View
    # w* P% G1 @/ q  H. J1345018 ADW                DBEDITOR      Database Editor does not catch empty mandatory properties if no changes are made to the part
      ^- m/ Z/ x! W! K, Z- V) ^1586858 ADW                DBEDITOR      'Access Denied' Error while opening Datasheet Model using Launch Viewer in Database Editor
    ' v0 p$ C1 X5 G- V% H. P1754185 ADW                DBEDITOR      Max Height value in DBEditor is different from PCB Editor
    : x8 G2 H& v: Q1719260 ADW                FLOW_MGR      Configuration error on a fresh install of EDM in release 17.2-2016 Hotfix 014
    4 S6 z0 u4 B% s4 T5 ^1743730 ADW                LIBDISTRIBUTI .lis file error in install_model while using MLR.
    " E2 E- T; M- q/ @1757178 ADW                LIBIMPORT     back-end libimport failed, crash and existing flashmodel not found5 \: ]% E2 U7 M
    1648609 ADW                SRM           PCB Editor stops responding when launched with -s option in release 16.6-2015 Hotfix 078
    ' Y* P( n' X6 f; \0 J1731152 ADW                TDA           TDO coredumps after a new object has been checked in as minor and deleted.% q7 _. [1 Y' a( x& y
    1766998 ADW                TDA           TDO-ASA: Cannot enable the project for team design until a component is added to the new ASA/SCM design/ r+ ?* `4 q* L3 I& ?: W, |$ u
    1695240 ALLEGRO_EDITOR     3D_CANVAS     Interactive 3D View of a package symbol not showing the correct mapped STEP file attached to the package symbol; R: w( R. b, R0 k% V
    1698148 ALLEGRO_EDITOR     3D_CANVAS     Allegro 3D Viewer crashes on Windows 10; [7 r6 ^/ h( {) {: u' ^
    1738655 ALLEGRO_EDITOR     3D_CANVAS     Interactive 3D canvas crashes on Windows 10
    % K5 t$ p! Z( g# Q, d7 C1750001 ALLEGRO_EDITOR     3D_CANVAS     Interactive 3D Canvas crashes on selecting in symbol view
    + O* t$ Q8 n% Z2 b. K3 D/ Q1751796 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas shows component placed at wrong layer for Embedded components
    6 u/ P& D' s1 q1768775 ALLEGRO_EDITOR     3D_CANVAS     Allegro 3D canvas closes when Update Symbol is done and cannot be re-invoked
    % e" c3 H  Q4 s, y/ d, H1695025 ALLEGRO_EDITOR     ARTWORK       Artwork film show shorts.4 ]! c/ K% U2 Q# K9 I
    1708674 ALLEGRO_EDITOR     COLOR         Dehighlight all should disable the check boxes in the color dialog/nets
    0 O; Y* ]& w& E: \$ a1735522 ALLEGRO_EDITOR     COLOR         In release 17.2-2016, PCB Editor crashes when not being able to write the CVSettings.xml file.0 s" q% A/ l$ h5 l/ `0 V
    1764475 ALLEGRO_EDITOR     COLOR         Allegro PCB Editor hangs when selecting OK on the Color Dialog form
    + g/ f! ^& p0 i7 ^# W1718438 ALLEGRO_EDITOR     CROSS_SECTION User interface is inconsistent for the Mask Layer Subclass site file editor.( `' {  f6 b8 Z, m. X
    1765387 ALLEGRO_EDITOR     CROSS_SECTION Cross Section Editor does not retain or remove layers added/removed from Setup-->Subclasses  E$ C, z( i& t+ s6 Y" X- M
    1714910 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes with blank allegro.jrl file when a release 16.6 board is opened in release 17.2-2016 Hotfix 013
    8 d9 E; R, ^/ }+ r1769534 ALLEGRO_EDITOR     DATABASE      DBDoctor unable to delete invalid subclass
    $ V3 v* g: }  _+ K, t7 S1775705 ALLEGRO_EDITOR     DATABASE      Updating stackup in PCB Editor does not change backdrill status to 'Out-of-Date backdrills'+ M( m( ?% g6 @- F* l8 A$ J
    1778608 ALLEGRO_EDITOR     DATABASE      Rigid Flex design: Components with pads defined on the TOP and BOTTOM layers are not placed on the correct layer' [1 `* S9 w: L+ p' t* e; q
    1778644 ALLEGRO_EDITOR     DATABASE      Allegro PCB Editor crashes while trying to place dimensions3 d+ l/ O1 B" f- K% @! \
    1698695 ALLEGRO_EDITOR     DRC_CONSTR    Line to Mech-Pin DRC not displayed6 A: r: j1 u. c/ W. G+ o
    1705214 ALLEGRO_EDITOR     DRC_CONSTR    Shape to drill DRCs not getting void and 'cns_show' does not report constraint value
    % i6 T  {" a: C! ?7 K1722841 ALLEGRO_EDITOR     DRC_CONSTR    Inconsistent soldermask to soldermask DRCs on vias as compared to board geometry/soldermask
    1 k9 e6 l, R$ p/ N/ ]1736116 ALLEGRO_EDITOR     DRC_CONSTR    Shape Voiding and DRC error on layer with no hole or pad definition
    1 F! q7 Y; i- c1744248 ALLEGRO_EDITOR     DRC_CONSTR    Release 16.6 to 17.2-2016 DML Independent Flow does not resolve differential pair pin pairs Correctly
    6 R$ n! ?  e  R; C6 l0 Z. b. ^* p1776848 ALLEGRO_EDITOR     DRC_CONSTR    Negative plane island DRC reported in release 17.2-2016 Hotfix 23. L" P! ]3 E  G
    1730806 ALLEGRO_EDITOR     EDIT_ETCH     Element 'vias_allowed' is not valid for content model adding high speed via structures+ ]/ z! ?' W9 h+ H& ?
    1745332 ALLEGRO_EDITOR     EDIT_ETCH     In release 17.2-2016, PCB Editor crashes when starting Add ZigZag Pattern2 j* N0 e2 }$ j, o" L6 ?
    1765555 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashes during contour routing) e  F2 ]/ Q; |) E
    1644401 ALLEGRO_EDITOR     INTERACTIV    PCB Editor crashes on running the z-copy command
    / l  {5 K+ F$ A1657621 ALLEGRO_EDITOR     INTERACTIV    Copy cline and via cause redundant vias0 C6 ~) E/ b$ x- {& W) _6 [
    1688556 ALLEGRO_EDITOR     INTERACTIV    Limitations with editpad boundary3 r: B2 K7 ~1 E7 u% y& m
    1704901 ALLEGRO_EDITOR     INTERACTIV    Changes cannot be done when 'Design outline' is selected2 ]% C+ s3 V1 {3 ?  x' ^7 D) e
    1710731 ALLEGRO_EDITOR     INTERACTIV    The Edit > Change command does not select or change the text on a block
    ' i6 N; ^3 N' H% S9 X8 G1714855 ALLEGRO_EDITOR     INTERACTIV    Placing two objects on the Design_Outline subclass causes PCB Editor to crash
    + x. J5 y( u  {! d' F2 }" @1725736 ALLEGRO_EDITOR     INTERACTIV    Edit>Change cannot change silkscreen line to a different class, but works in preselect mode0 @+ H7 q: p4 z, X$ V  o; y
    1728004 ALLEGRO_EDITOR     INTERACTIV    Text cannot be edited if the Design_Outline subclass is in the selection box
    ) i2 ^) F/ W$ h$ |* w1 _1728794 ALLEGRO_EDITOR     INTERACTIV    The Oops command and the Esc key do not work when moving components in the Temp Group mode
    6 V* C" E# q6 E3 G1738070 ALLEGRO_EDITOR     INTERACTIV    Copying shape after Shape Operations results in error 'E- (SPMHDB-72): Current active shape must be filled first'+ G! {) ?7 c$ t
    1750696 ALLEGRO_EDITOR     INTERACTIV    Add notch angle option fails to update if changed while add notch command is active.% U. I% P+ ~, D4 f! c4 B
    1755240 ALLEGRO_EDITOR     INTERACTIV    Copy via does not work3 F/ N$ ]1 M3 B9 q; K- h
    1777416 ALLEGRO_EDITOR     INTERACTIV    Running shape operations results in database corruption) a! Y/ M& ?* X  J
    1715835 ALLEGRO_EDITOR     INTERFACES    When IDX is imported in PCB Editor, all the shapes are created on package keepout on all subclasses
    9 W) X4 _+ `) Y9 f2 g1744111 ALLEGRO_EDITOR     INTERFACES    Pads rotating 90 degree when exporting DXF file from Allegro PCB Editor/ G  e' \/ k% \6 k/ e: u  S+ Q1 ~
    1736045 ALLEGRO_EDITOR     MENTOR        Third-party import crashes PCB Editor with error stating that .SAV file will be created. ^" w/ O  P4 W7 g1 O  V6 O3 f
    1751914 ALLEGRO_EDITOR     MULTI_USER    Find Filter options get disabled while creating symbols$ O, W5 P- H& k( y6 [1 G
    1770811 ALLEGRO_EDITOR     MULTI_USER    In release 17.2-2016, axlTriggerSet('exit 'routine) causes a crash while exiting
    - K8 ~& f" B1 Z8 U) y$ X1736545 ALLEGRO_EDITOR     OTHER         Spelling mistake in description of no_dynamic_zoom variable in user preferences Editor
    : m7 M. r4 k& Y( s/ u6 A) B1761610 ALLEGRO_EDITOR     OTHER         Dynamic shape is not voiding as expected.& y& F% {: m! p' M. n
    1702535 ALLEGRO_EDITOR     PAD_EDITOR    After modifying a padstack in Pad_Editor, the Update to Design function fails to update the dra file
    6 t1 T. R4 S0 E" D& T1713461 ALLEGRO_EDITOR     PAD_EDITOR    Padstack editor default geometry not working when cell is preselected
      E2 g3 Z5 t/ y4 f  a1715702 ALLEGRO_EDITOR     PAD_EDITOR    Donut shape is lost on cutting the pad shape of the donut pad
    ! u6 x+ }7 g4 y' w) q6 q: ]1720300 ALLEGRO_EDITOR     PAD_EDITOR    Multi-drill staggered pattern: Different hole placement for first and second rows for releases 16.6 and 17.2-2016& I& f/ k+ t, ~9 i& j/ ^1 m" t& K
    1724896 ALLEGRO_EDITOR     PAD_EDITOR    Padstack Editor shows flash symbol for regular pad on selecting 'Shape Symbol'
    - e9 w" z/ {# `0 V1714839 ALLEGRO_EDITOR     PLACEMENT     Selecting an alternate symbol (alt_symbol) in a group, in the Placement Edit mode, removes the symbol from the group
    & \$ y* E: h2 o1781502 ALLEGRO_EDITOR     PLACEMENT     Quickplace by room crashes Allegro PCB Editor( J: ?; g* f2 K) ^1 C
    1699690 ALLEGRO_EDITOR     SCHEM_FTB     'view_pcb directive' no longer working as expected4 \- [9 T' h' o3 k  z6 m
    1758796 ALLEGRO_EDITOR     SCHEM_FTB     PCB Editor launched from Project Manager does not read the relative paths specified in the view_pcb directive
    , w+ i+ ]8 u$ t. d0 ^1761101 ALLEGRO_EDITOR     SCHEM_FTB     On saving a board after import logic in PCB Editor, the file is saved in the cpm location and not in the physical folder: t7 R0 i% h5 i0 x* A) u' X( P
    1761394 ALLEGRO_EDITOR     SCHEM_FTB     Working directory for PCB Editor changes after import logic
    9 s9 Y1 M3 b* X8 Y' Y1714922 ALLEGRO_EDITOR     SCRIPTS       Running script in the non-graphic mode runs the tool graphically5 g& ?# N; E4 O- U' b
    1726550 ALLEGRO_EDITOR     SHAPE         Shape failed to connect to pin
    1 V* {; _+ n' p5 U+ {! Q. k1754945 ALLEGRO_EDITOR     SHAPE         In release 17.2-2016, Delete islands  fails to add DYN_DELETED_ISLAND to voids on Windows 10 systems# z2 X6 ~  S3 _- i; a2 I3 i: p1 l
    1766280 ALLEGRO_EDITOR     SHAPE         SPMHGE-300 Polygon operation failed because of an internal error* P9 [" e) S! q* o8 A* O1 u, K5 G% U
    1768307 ALLEGRO_EDITOR     TECHFILE      Properties defined in the technology files are not being imported in a new design* M) q- X+ K' E: q
    1771584 ALLEGRO_EDITOR     TECHFILE      The tech file import command does not update user-defined property immediately
    , F8 i8 R* X+ _9 a' P8 B' R7 o5 d1730104 ALLEGRO_EDITOR     UI_FORMS      Change description  of Title bar option variables in User Preferences
    . X7 ~$ ~3 A% J9 d; F/ g* r) c1749272 ALLEGRO_EDITOR     UI_FORMS      etchlen_ignore_pinvia variable needs to be updated
    8 {+ m. I% r% N1649254 ALLEGRO_EDITOR     UI_GENERAL    Using wildcard to open padstack file generates error SPMHA1-161 in Padstack Editor in release 17.2-2016
    * A* e! P/ \: x" i  q6 D% @8 o1685985 ALLEGRO_EDITOR     UI_GENERAL    Funckey not working for Display - Measure
    ' h# b1 ~# y% u: z- U4 X1687073 ALLEGRO_EDITOR     UI_GENERAL    Show Measure command shifts focus to Search field in result window after selecting first element8 ~5 X$ M. _7 _
    1699272 ALLEGRO_EDITOR     UI_GENERAL    File Viewer not displaying HTML files correctly when 'allegro_html_qt' is enabled2 w/ ^5 X0 X% C0 a0 T3 l9 Y' X
    1711321 ALLEGRO_EDITOR     UI_GENERAL    Database settings do not change on changing color settings using the SKILL function axlDBDisplayControl()
    / j2 m9 A, g* m, I' |3 J% F1728468 ALLEGRO_EDITOR     UI_GENERAL    The Show Element window takes the focus away from the PCB Editor window
    # J+ O# R4 F/ f4 K4 Y* X+ T1733690 ALLEGRO_EDITOR     UI_GENERAL    Performance issues in Visibility dialog if called repeatedly in release 17.2-2016, Hotfix 017
    ; X2 y( d/ ]! H$ w0 y, K; a1734176 ALLEGRO_EDITOR     UI_GENERAL    Unable to sort padstacks to open in the padstack editor using wildcards
    ; W' Z; D/ j& s) K2 Q$ i/ Z1735733 ALLEGRO_EDITOR     UI_GENERAL    RAVEL checks slower in release 17.2-2016, Hotfix 017: {& ^  C$ j( H- l1 v1 @9 `
    1737545 ALLEGRO_EDITOR     UI_GENERAL    axlVisibleSet is slower in release 17.2-2016
    * F* }/ r, i. k( V( l( j3 K1744655 ALLEGRO_EDITOR     UI_GENERAL    SKILL code with axlVisibleSet slower in release 17.2-2016 compared to 16.6
    ' F' L" A4 c' N2 b8 x1759380 ALLEGRO_EDITOR     UI_GENERAL    axlLayerPriority API changes layer visibility and colors- [1 r" D. G( p2 Y. ^
    1775071 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, dialog boxes are not displayed in the right order on using SKILL
    + O3 O/ \- g! D+ G7 A/ n& U1708554 APD                GRAPHICS      MCM shape lines are almost short and different with DXF and Gerber files
    7 g: K# ^+ l( f7 c6 V1678824 APD                SHAPE         Updating dynamic shape fails to void all elements on layer L2.+ @8 R0 i: f6 W. L9 J* w
    1742335 ASDA               COMPONENT_BRO Libraries missing from new Component Browser  Z4 |  {! j  r/ H* `
    1779777 ASDA               CONNECTIVITY_ SDA: Net name and physical net name are different
    . H& |2 [% u9 d& D4 n: `1721919 ASDA               CROSSPROBE    Cross-probing a net from the .brd file highlights the entire bus in the schematic: }, D. H4 Y9 {& S6 R6 C
    1714313 ASDA               EDIT_OPERATIO Filter does not work correctly in the Change RefDes form- F; @% e+ l" q; g7 I
    1730809 ASDA               FORMAT_OBJECT Image transparency slider does not update the number in the combo box correctly5 }; R& U- v, x
    1747397 ASDA               GRAPHICS      Pop-up DRC descriptions are too small and cannot be read
    1 o9 A2 c, Z3 h# m6 c7 M2 O. C1640061 ASDA               HIERARCHY     Incorrect message received when invalid characters are specified for subdesign suffix
    . k5 N$ q' x9 r6 G$ J7 I1723535 ASDA               MISCELLANEOUS Clicking in the Command window should place the cursor at the last line to avoid editing previously run commands& ~. m$ ^1 Q6 N, s- k
    1699936 ASDA               PAGE_MANAGEME Page gaps created while moving pages
    8 W& ~: d  z+ `" A1737180 ASDA               VARIANT_MANAG Deleted variants are removed from the variant.lst file but displayed in SDA
    % l$ m) n* F3 L1763247 ASDA               VARIANT_MANAG Changes in Variant Editor are not reflected on the schematic page.
    ( a3 I7 a. }' B4 p5 ]& C- H1733971 CAPTURE            CONNECTIVITY  Auto connect to bus not working in the attached design6 [. B5 o- c3 l  ?9 |3 Y% w, S
    1236010 CAPTURE            DATABASE      Capture is very slow in processing designs.& e3 d$ H1 o. B4 V1 `( [
    1518560 CAPTURE            DATABASE      Large schematics are slow to respond
    : q: A+ e* b7 _3 P+ H+ f( A% i$ I1705592 CAPTURE            DATABASE      Capture hangs when switching between schematics that contain nested netgroups
    / b/ _6 B  d% }0 J- P1770687 CAPTURE            GENERAL       In release 17.2-2016 Hotfix 021 and 022, selecting Help - Learning PSpice throws Java Script error. l$ A! q" b' [3 T; n  I
    1692435 CAPTURE            HELP          Version Info Window is empty7 c& D6 J. K; }5 m  U/ S7 {+ [+ U
    1767374 CAPTURE            NETLIST_ALLEG Capture crashes on canceling the netlisting process
    5 {7 u$ r% F3 {9 D: w& x1719613 CAPTURE            OTHER         Moving a wire in OrCAD Capture CIS or Allegro Design Entry CIS results in design crash$ B* H* v. A$ e5 ]! C9 e0 b& Z
    1746663 CAPTURE            OTHER         Capture slows down significantly in release 17.2-2016 Hotfix 017 and 018
    : `. Y- i  }- e- f' p1709179 CAPTURE            PROPERTY_EDIT Unable to delete unwanted properties associated with Ground and VCC nets.2 ?' Q$ c! p/ r+ J9 }! T3 ~
    1714121 CAPTURE            SCHEMATIC_EDI Mirroring and moving a symbol resets the position of a newly added pin property  \. ~, x4 Q! g2 o$ b# Z
    1729861 CIS                OTHER         The 'Refresh Part Types' icon is alternated with 'Refresh Symbols From Libs' icon  M; [1 r! P/ U6 g0 o6 }' S, W6 l8 u
    1333600 CONCEPT_HDL        COMP_BROWSER  Sort the sections numerically in Part Information Manager
    8 P4 |, u( A& q  m- r/ u1 H, k1758761 CONCEPT_HDL        COMP_BROWSER  Incorrect Version showing in Component Browser in 17.2
    . p; T: E) H6 P$ N) U* ~, G1769591 CONCEPT_HDL        COMP_BROWSER  Modify Component / Project Information Manager (PIM), parts take longer to load in EDM
    ! u/ w  M' v6 I# N4 y7 p1479711 CONCEPT_HDL        CORE          Mirroring symbols causes alignment issues6 x& G4 F# t2 f9 T0 H- x- D1 z! n
    1696208 CONCEPT_HDL        CORE          Display issue with the grid visibility after a save hierarchy/ x% u" I6 d4 N4 g( ]
    1698802 CONCEPT_HDL        CORE          Pin number overlap with the pin stub when the component is mirrored.- C- I3 p" }  O- x) @3 p
    1708917 CONCEPT_HDL        CORE          nconcepthdl crashes on a design with a core dump! a: l$ I: `* |" j7 C( ~
    1744815 CONCEPT_HDL        CORE          Deleting a page crashes DE-HDL
    $ |) f! Q1 m) r1751863 CONCEPT_HDL        CORE          'Move' does not move body but only properties of selected part
    1 H8 R% J( |3 B1 H2 o2 C  X1763556 CONCEPT_HDL        CORE          Component Alignment and other graphical feature not working in Windows 10
    0 J& ?/ C* x* E1725121 CONSTRAINT_MGR     CONCEPT_HDL   Audit report of ECSets reflects some gaps in certain columns0 O- G2 e* F1 w; X) B
    1758740 CONSTRAINT_MGR     CONCEPT_HDL   Extracted topology does not populate the gather control used in the ECSet
    9 X, N7 C4 d; P8 V( S/ e1759580 CONSTRAINT_MGR     CONCEPT_HDL   Class to Class assignments are incorrectly displayed in the 'CSet Assignment Matrix'
    - [$ M( N9 i6 `5 C, r* X. |0 `1759590 CONSTRAINT_MGR     CONCEPT_HDL   Unable to create bookmarks in Constraint Manager( C! j% H" q- Z
    1764597 CONSTRAINT_MGR     CONCEPT_HDL   Copying constraints from a SKILL-defined CSet copies the automation flag/attribute ('A' in UI), as well.
    $ C0 b1 j' V& C( j1 f* ?( g1771427 CONSTRAINT_MGR     CONCEPT_HDL   Decimal units specified in the precision settings are not applied correctly
    . ]' {) J- J/ ?: j9 Y. u1 t9 x1700402 CONSTRAINT_MGR     DATABASE      Parallelism violation DRC not reported until cline is moved
      O: k1 e0 V/ `" `. f0 O1700370 CONSTRAINT_MGR     OTHER         Constraint Manager: Expanded nodes collapse on restart. ^) z8 T' k. n0 ?1 F. T
    1735636 CONSTRAINT_MGR     OTHER         Inductors are extracted as resistors in the topology- G! f6 E+ j4 @% {9 B, Q5 A9 A
    1776917 CONSTRAINT_MGR     OTHER         Creating advanced formula causes the tool to crash
    ) b/ E. v  @# P$ Z% ^1 ^1762979 CONSTRAINT_MGR     TECHFILE      Constraint Manager does not retain values after importing tech file* [- D+ _) w& G- [' C
    1699275 CONSTRAINT_MGR     UI_FORMS      Constraint Manager: Dialog boxes opened from the File – Import menu show files and folders in incorrect order! y0 n: e& h" ^0 G8 \' J
    1699312 CONSTRAINT_MGR     UI_FORMS      Typing *.* in the File name field does not display all the files in the Import Constraints dialog box
    9 l# ]) k( N+ j4 @2 b1742134 CONSTRAINT_MGR     UI_FORMS      Editing a cell from any of the constraint set in Constraint manager is filling other cells that should not be selected* w( V3 I' G5 a5 }: C0 [
    1755576 CONSTRAINT_MGR     UI_FORMS      Constraint Manager: Physical CSet filter not working correctly2 z/ V) s! y8 ~, L8 v0 e( h( w
    1775333 ECW                DASHBOARD     Activity Log is not accessible to ECAD_Integrators if they are not part of the project team
    ) u# c5 Z! E$ w: b3 g1749220 ECW                OTHER         Remove 'Role' column from Users web parts* P+ i* I, R' ~! d' W
    1716527 ECW                TDO-SHAREPOIN Allegro Pulse: Mismatch between metrics with components on schematic and components in layout
    5 e5 H, H% n) m1724195 FSP                SYMBOL_EDITOR Device pins are not correctly aligned after being moved in Schematic Symbol Editor
    , [. l& p* f+ a1 _! ]1725479 INSTALLATION       DOWNLOAD_MGR  Download Manager error prompts user to close downloadmanager.exe3 L, P! ~  U1 y% y6 A
    1738952 PCB_LIBRARIAN      SYMBOL_EDITOR Pin table must allow for Copy/Paste of Rows+ h% m8 f9 s+ k- Q8 w
    1638740 PSPICE             FRONTENDPLUGI Set minimum height for the search field in PSpice Part Search
    7 o. l  w+ K3 n1699822 PSPICE             FRONTENDPLUGI Set minimum height for the search field in PSpice Part Search
    - n, J  r# ~7 Z1652265 PSPICE             MODELING_APPS Cannot place PWL source from PSpice Modeling App( x  P' [6 j/ W2 L! Q
    1685967 PSPICE             MODELING_APPS Getting error when trying to place PWL source from PSpice Modeling App( y+ ^$ X: m; ~) O# k8 k
    1716313 PSPICE             MODELING_APPS PSpice PWL Sources not working correctly in release 17.2-2016 Hotfix 0146 `/ ^! U+ A# @* K$ j/ O6 q
    1738747 PSPICE             MODELING_APPS Inconsistent file type for PWL part in modeling application and source library
    : e" Z$ E+ R8 a  N1762202 PSPICE             MODELING_APPS PSpice modelling app Tcl issues5 p2 L+ d+ p1 @4 o" _8 a, J
    1736605 PSPICE             SIMMODELS     BSIM4.6 model parameters incorrectly handled by simulator5 H& D- m% F3 i- \/ H9 |2 W
    1442623 PSPICE             SIMULATOR     Bias points are nor correct in attached circuit
    2 T1 ^6 M: M- ~4 d9 [: m& |- j1618815 PSPICE             SIMULATOR     Bias Point calculation appears incomplete1 V9 h0 l) w0 }1 ]2 B
    1723039 PSPICE             SIMULATOR     PSpice crashes when curly braces are specified for the ETABLE parts
    3 L" v" m# X3 r- E5 B4 ~1782353 SIG_INTEGRITY      SIGWAVE       SigWave crashes when opening .sww file in release 17.2-2016 Hotfix 023& G$ Y5 W( y& l1 W
    1745940 SIP_LAYOUT         DATABASE      Cutting a part of a tapered cline does not remove the connectivity on the dangling cline
    * ^* h; d8 {) [" W1780072 SIP_LAYOUT         DIE_ABSTRACT_ Export->Die Abstract File causes a crash
    ) U& o. M7 \5 u. d' g- ?! C1736396 SIP_LAYOUT         SYMB_EDIT_APP 'No such child' error message when deleting pins in symed) H. H$ _+ A9 Q( ]; U. a
    1769728 TDA                CORE          Default policy file needs to be fixed& g0 G9 {: n  k
    1735682 XTRACTIM           GUI           XtractIM translation is incorrect: adds anti-pads
    % w( [4 D" V. b9 T9 K; ~4 `3 Y- j7 \

    ) |& s* \; G+ dFixed CCRs: SPB 17.2 HF0245 O% V& {7 A7 u
    07-28-2017
    3 N. \, _1 Y0 x, N& {! O4 |, C1 i$ Y9 f========================================================================================================================================================
    7 d) ^) m: Y# D; F- sCCRID   Product            ProductLevel2 Title4 O5 @3 I$ t( ^/ R6 F& @9 f
    ========================================================================================================================================================- I' ~2 Y, d  X& f8 H# f- z; S
    1762143 ADW                COMPONENT_BRO Part placed using the 'Add' button does not populate 'PART_NAME' property8 C7 O2 K- [0 ~5 A1 I) Z
    1765790 ADW                PART_BROWSER  Fail to extract component part number and footprint information
    4 Y9 D& c8 r& B- l5 U1757719 ADW                TDA           TDO and Windchilll Work Group Manager out of sync at times& b2 |7 r5 a+ y# ~
    1760607 ALLEGRO_EDITOR     DATABASE      Value for number of decimal places changes in Pad Designer in release 17.2-2016) L) `4 N+ N% A. G
    1775160 ALLEGRO_EDITOR     DFA           Loading DFA spreadsheet crashes PCB Editor in release 17.2-2016
    4 E( B' Z2 @- B% Y2 v1 ]1765984 ALLEGRO_EDITOR     OTHER         Cannot view System Info
    5 A# F. j+ Y% [; _! j6 J1729350 ALLEGRO_EDITOR     REPORTS       Net loop is not listed in report
    9 |3 n2 Q; W7 l4 D# S0 F1725242 ALLEGRO_EDITOR     SHAPE         'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
    6 x8 }, }# c) Y" t% _7 g1754402 ALLEGRO_EDITOR     SHAPE         Illegal arc radius error (SPMHA1-85)$ n% i6 p/ w0 m2 M5 A3 ?( ?' b% U
    1762888 ALLEGRO_EDITOR     SHAPE         Border line missing for some crosshatch (xhatch) shape voids
    % h. w- O$ t/ H' j' A# A8 @, }. O1769188 ALLEGRO_EDITOR     SHOW_ELEM     'Show Element' with the 'Groups' option used on certain modules crashes PCB Editor
    & y+ N) p. @& B1767690 ALLEGRO_EDITOR     TESTPREP      PCB Editor crashes when running automatic Testprep( Y) r; f+ ~" U% y/ \( ^9 N
    1737337 ALLEGRO_EDITOR     UI_FORMS      Pinned Show Element window closes when opening new design in release 17.2-20168 ]4 k$ H" \. R: U# `" V) l: K
    1736642 ALLEGRO_PROD_TOOLB INTEGRATION   Cannot change accuracy to 4 for 'Change Width' in Productivity Toolbox2 k. P" p: o( {
    1685216 ALTM_TRANSLATOR    CAPTURE       Third-party translator placing symbols off grid+ \  }  W) F4 A4 @! G! w3 K
    1738679 ALTM_TRANSLATOR    CAPTURE       Connectivity loss in imported schematic
    7 W9 S+ v% _( v1738705 ALTM_TRANSLATOR    CAPTURE       Connectivity loss in imported schematic& l. ?9 q; N. g8 @. ]0 D) |
    1748583 ALTM_TRANSLATOR    CAPTURE       Crash on importing design using third-party translator
    5 T4 Q  A' f$ R1679310 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator should fix off-centered connections. c4 W0 e- M: `' K% W- c# `
    1686845 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator does not place parts after successful translation3 e/ C6 W4 i# K( K
    1723141 ALTM_TRANSLATOR    PCB_EDITOR    Placement outlines are rotated in third-party translator
    0 C$ C" a7 V  _( c& W5 d1723164 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator creates board with missing data: vias, traces, and so on
    9 r5 _$ H, u4 G) h2 B1723190 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator changes design origin1 S) {( E! a7 F6 C: O
    1750496 ALTM_TRANSLATOR    PCB_EDITOR    Third-party board with arc tracks not correctly converted to arc clines& A/ n' ?. h2 t- S) ~6 s% ^
    1769624 APD                DATABASE      Attempted symbol delete crashes APD; u0 V2 Y/ y1 D+ Y
    1727206 APD                SHAPE         Merging two shapes results in an incorrect shape/ F' S$ J( @( c- z' F: n
    1707756 ASDA               VARIANT_MANAG Scrolling in Create Variant closes tool
    6 t9 d5 `/ s# G) g2 h1753699 CM                 RELEASE       installDebugger() does not work in release 17.2-2016 as SKILL kit is not installed
    + U9 Q/ t5 [, b# @1741534 CONCEPT_HDL        CORE          DE-HDL freezes when selecting a net that contains many connections
    ; @  z3 Y, y. r3 F9 f1752687 CONCEPT_HDL        CORE          The move command changes the connectivity of the schematic1 ?, \( W' d" J2 @# X' W0 Y2 P
    1763525 CONCEPT_HDL        CORE          Genview crashes when generating split symbols: q0 v- R# U* {2 k
    1766797 CONCEPT_HDL        CORE          Schematic not refreshed after using the clear xnet overrides feature# ~( b7 U3 W4 `4 y
    1770852 F2B                PACKAGERXL    ERROR(SPCOPK-1138): A hard location was found on instances of different physical part types
    2 s/ Q0 h1 ?5 c' c3 K# T: a. p1754473 FSP                DE-HDL_SCHEMA Provide an option to generate symbols with custom attributes
    , j3 s1 v% e) f1748106 FSP                OTHER         Create protocol from existing protocol error message needs clarity
    8 t8 i$ _; C/ N, j+ S1 b) a1724201 FSP                SYMBOL_EDITOR Unable to change 'Pin Direction' in symbol editor
      m0 o& y. y* I1772429 ORBITIO            ALLEGRO_SIP_I Import - OrbitIO: Translator cannot create bundle in PCB Editor5 Q8 y, u/ _$ G
    1725759 SIG_INTEGRITY      OTHER         PCB shape/plane capacitance! Y: W- W' c+ g4 z
    1760924 SIP_LAYOUT         DIE_STACK_EDI Package height of die .dra file reset to 110um when placed( I' p9 M5 J( B* ^0 X' q
    1764385 SIP_LAYOUT         MODULES       Embedded components are unplaced in created modules (.mdd)
    ; n* f; d5 W) P1 y1733679 SIP_LAYOUT         OTHER         'metal density scan' does not use select window
    4 ?1 R1 v( H1 z$ J0 U3 {5 l1763707 SIP_LAYOUT         OTHER         SiP Layout exits with error message in release 17.2-20163 r% F* X' G7 t; d, J0 E. i$ q
    1763515 SIP_RF             DIEEXPORT     Virtuoso writes incorrect width for 45 degree path segments in XDA file
    ) U, c8 [( y$ T3 }8 e4 Z0 T1772397 TDA                DEHDL         DE-HDL crashes if license is not available for team design$ D$ E, K7 R3 L2 ^6 y* t2 }0 {; E# E

    & V3 H2 _% M; B+ y, C4 N
    * ]% Q1 D" j' {- MFixed CCRs: SPB 17.2 HF0231 }9 h& i% G$ z/ L+ [
    07-7-2017
    % M( j' _. h; G7 t8 q! k1 m, Q2 p========================================================================================================================================================
    9 _1 z4 Q2 g8 ~8 PCCRID   Product            ProductLevel2 Title
    , y+ p0 W/ M/ k5 J5 W9 H========================================================================================================================================================
    # ^# A3 ^0 a' u  ^- h  l1703281 ADW                ADW_UPREV     Design_init needs to support the -cb command# g/ f$ {& p+ S" }
    1762238 ADW                COMPONENT_BRO DEHDL crashes without reason
    . L& l0 E9 G7 U! t1759467 ADW                DBEDITOR      DBEditor does not recognize that 1.10 is a higher version than 1.9
    1 E8 k9 J. V* \7 J  r+ J1731459 ADW                FLOW_MGR      Cannot open LRM from Flow Manager( ^) S! g% ^' e' A% e. x5 o
    1731460 ADW                FLOW_MGR      Cannot open LRM from Flow Manager
    2 }' B0 J! Y% a8 c) X5 G& @: e! n# q1757443 ADW                LIBDISTRIBUTI Blank PHYS_DES_PREFIX in PTF file: Q# ~. q3 g) @2 j# P0 W
    1752126 ADW                LRM           cache not getting updated with std models when moving from 16.6 to 17.2
    : z, ~$ R" v  }1754444 ADW                LRM           Update Standard library in LRM causes an error, "Cannot proceed with update as don't have permission to delete."
    7 O' M8 s- u/ e1 p: l9 X6 \1715861 ADW                SRM           symbolrevchk.par has incorrect variable name for SRM to ignore the tool version
    * j6 J6 i- X% @7 E* e+ i1628403 ADW                TDO-SHAREPOIN Objects remain checked-out after multiple failed 'check in hierarchy' attempts* M3 ~) e; C3 v1 `
    1759250 ALLEGRO_EDITOR     DATABASE      Flex-rigid placement does not move bottom pads to nearest layer" o# v- I) {6 K' w" F
    1762782 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes when creating artwork7 ^1 R: T: x! v
    1746665 ALLEGRO_EDITOR     DFA           Cannot scroll in DFA Constraints Dialog if the DFA constraint file is read only6 i/ t! {1 E& O
    1750084 ALLEGRO_EDITOR     DFA           DFA spreadsheet disappears from the DFA library if hyphen is present in the name
    ' u7 R7 D7 m  }+ l  J1697155 ALLEGRO_EDITOR     GRAPHICS      Position and size of Show Element and Measurement windows not saved in PCB Editor
    ; c7 g0 ]2 A4 D3 k/ G1734282 ALLEGRO_EDITOR     GRAPHICS      Placement of reports and pop-ups not retained in PCB Editor
    & E7 B3 `$ L- y+ K2 I( z$ w1740863 ALLEGRO_EDITOR     GRAPHICS      Show Element and Measure windows do not retain position
    . I2 I# y' k1 p+ x1749687 ALLEGRO_EDITOR     GRAPHICS      Position and size of Show Element and Measure windows are not saved in PCB Editor in release 17.2-20169 u- N4 K3 x0 {
    1764124 ALLEGRO_EDITOR     SCRIPTS       Replaying recorded script file crashes PCB Editor3 |/ ~: x" w2 q# t
    1762888 ALLEGRO_EDITOR     SHAPE         Border line missing for some crosshatch (xhatch) shape voids& P8 u' G0 ^, T
    1763619 ALLEGRO_EDITOR     SKILL         Incorrect text block name when extracting text parameters using SKILL
    ; h1 |& {8 v) C& e! f1685826 ALLEGRO_EDITOR     UI_GENERAL    Reports when opened from Status Form disappear behind PCB Editor canvas when clicking on canvas
    & \5 F, q0 C8 j3 z6 W1733552 ALLEGRO_EDITOR     UI_GENERAL    Although F1 is defined as an alias for another command, pressing F1 opens help
    : e- E, F5 \+ l% l8 L( y5 _1735098 ALLEGRO_EDITOR     UI_GENERAL    axlUIYesNo displays garbled text when customized for Chinese in release 17.2-2016
    ! q( d. q+ }3 U7 r' u- ?2 L& }1753430 ALLEGRO_EDITOR     UI_GENERAL    'Tools - Quick Reports' opens only one report at a time: P, T* A3 X, f  i3 B
    1754283 ALLEGRO_EDITOR     UI_GENERAL    Call multiple reports from a function key
    . d7 O/ m# e* s' H- d, q: A( A1742822 APD                STREAM_IF     Component pins are not mirrored properly when mirror geometry option is checked and component is mirrored at 90/270. A2 I9 e0 d; Y! L& e; k7 x% p
    1762284 ASDA               COPY_PASTE    Copying testpoint crashes tool and eventually the operating system  w' X9 ~/ T# K- r" T
    1655057 CONCEPT_HDL        COMP_BROWSER  ADW Part Manager and Component Modify hangs' w8 I4 ?$ P6 c( p( u7 s  i
    1689740 CONCEPT_HDL        COMP_BROWSER  Bad response time using Dehdl component browser7 n$ b* \9 P* g: l" R
    1735332 CONCEPT_HDL        COMP_BROWSER  Sort in mathematical order Symbol list in Component Browser7 ^5 j6 ]( ^8 q5 p7 b
    1739197 CONCEPT_HDL        COMP_BROWSER  Part Information Manager can`t sorted symbol version/ J2 [# T, g' L( X  V1 N! n  a- c
    1764605 CONCEPT_HDL        CORE          Signal added from the console should be 'Left Aligned' instead of 'Center Aligned'. e  W3 a9 a' G4 v2 |: o3 E% l6 C
    1761706 CONSTRAINT_MGR     CONCEPT_HDL   cmDiffUtility has a typo in the usage statement: q/ I# k0 v( J8 D! y% b5 k
    1758426 ECW                DASHBOARD     Behavior of 'Apply Label' for Dynamic and Status labels should be same in TDO and DE Webpart0 l6 c3 z1 C) b* V
    1764096 ECW                PROJECT_MANAG Renaming project using the ETD window randomly hangs the edit window, refreshing bring backs the page$ z) [6 C( ^; o/ G4 S, o
    1764070 ECW                TDO-SHAREPOIN Join Project: Multiple entries shown for workspace/project with multi-hierarchical structure
    / d: h5 r2 N* H8 ]& V1754473 FSP                DE-HDL_SCHEMA Provide an option to generate symbols with custom attributes
    ; O8 `) V' J+ F, L( x. B  m1724124 FSP                DESIGN_EXPLOR Provide Tcl command to filter data in Design Connectivity Window
    ( F; J# @$ l7 c+ [0 Q: Z+ i1726548 FSP                OTHER         Unable to open FPGA system planner if username/log file path has Cyrillic letters1 s9 \5 I4 Q* c5 d1 ^
    1719133 SCM                SCHGEN        Voltage symbol not getting placed for some of the voltage nets
    7 n, u( r6 |/ O: \$ J6 \6 h8 D6 B" e1680989 SIP_LAYOUT         ARTWORK       Artwork film set-up: Match Display including invisible layer$ I* B" I/ `1 G$ a
    1732218 SIP_LAYOUT         DEGASSING     Shape will not degas as needed - not all voids degassed3 L- Y, S0 m6 x3 r" d5 D& O
    1763280 SIP_LAYOUT         DIE_ABSTRACT_ SiP Layout does not recognize width of segment when importing .xda- z) I! H5 w( {" [
    1762992 SIP_LAYOUT         OTHER         Saving a design after adding a solder mask layer in the cross-section crashes tool7 U" [1 V( B6 B' N  s3 [; Y1 q+ i
    3 }/ I: V, f6 W* ~5 U
    $ J8 i, y8 P. d) t; w
    Fixed CCRs: SPB 17.2 HF022
      L: w) T  F  M8 s2 \06-16-20176 i, x7 l1 y2 J+ L! x# n
    ========================================================================================================================================================" l$ u& n% |! I" y# A
    CCRID   Product            ProductLevel2 Title, {3 j, e3 w! t/ V; y
    ========================================================================================================================================================( e9 D. N% V8 w
    1755789 ADW                DBEDITOR      Checking in HSS Block returns 'Failed to create archive'
    1 d4 s7 v0 ~0 N, h- t3 r1731459 ADW                FLOW_MGR      Cannot open LRM from Flow Manager
    2 _# M' \1 M% _1 \' X6 n0 B1731460 ADW                FLOW_MGR      Cannot open LRM from Flow Manager
    8 b1 Q7 m/ b# I$ b2 ~6 u1744081 ADW                FLOW_MGR      Error regarding configuration file when trying to open Workflow Manager1 G/ g; p- [6 R) X8 a1 ?
    1756727 ADW                LIBIMPORT     EDM Library Import fails with java exceptions when merging classifications
    7 e, z3 n/ E4 O* h) q2 J& B( S1743763 ADW                SRM           Find filter is grayed out when Allegro PCB Editor is opened from EDM Flow Manager
    $ v  `7 r5 N- f  g1748399 ALLEGRO_EDITOR     DATABASE      In release 17.2-2016, end caps not visible for certain clines in PCB Editor& Y( s/ J" a5 m, y" g- T# {, Y
    1748522 ALLEGRO_EDITOR     INTERACTIV    A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it
    7 z: v& O" H2 N4 S# V2 G1734983 ALLEGRO_EDITOR     INTERFACES    Secondary step model does not stay mapped after drawing is reopened( w% e5 [$ v' H
    1753704 ALLEGRO_EDITOR     REFRESH       Refreshing symbols crashes PCB Editor5 T6 \3 N  f3 L: C4 E0 E
    1493721 ALLEGRO_EDITOR     SHAPE         Voids on negative planes are not adhering to constraints! ~+ \" W* ]. L) b* P% P! T4 `4 o
    1711242 ALLEGRO_EDITOR     SHAPE         Route keep out leads to partly unfilled shapes with gaps
    $ E$ E0 Z7 P, b7 z* a  f1726865 ALLEGRO_EDITOR     UI_GENERAL    Pop-up Mirror command does not mirror at cursor position- u6 o. x0 p: F2 Q/ t$ X
    1752987 ALLEGRO_EDITOR     UI_GENERAL    axlUIViewFileCreate zoom to xy location not working while in user created form.
    3 ~8 ?) ~# S, O( q* Q1755638 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run
    $ ]. ^6 f: h2 K( J6 n" I* N1719792 ALLEGRO_PROD_TOOLB CORE          Productivity Toolbox Z-DRC hangs or crashes PCB Editor
    ) ?' I# w5 a1 O# R+ a1624869 ALTM_TRANSLATOR    CAPTURE       A structure file is required to translate a third-party schematic to OrCAD Capture
    - f" v- s$ v3 p& }, y1707416 ALTM_TRANSLATOR    CAPTURE       Missing components and pins in the OrCAD Capture schematic translated from a third-party tool* i+ G+ _1 Q! T) H+ Z
    1708825 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate the schematic* a: P8 j% T" L0 u3 n3 U5 A
    1719200 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate all the pages of a schematic
    ) c/ d# c( ]0 A* S6 T1546070 ALTM_TRANSLATOR    CORE          Third-party to DE-HDL schematic translation fails/ T7 J2 q1 L1 }2 r% e+ Z
    1700508 ALTM_TRANSLATOR    CORE          Third-party PCB translator does not work in release 17.2-20168 r; n" _/ y# N3 q# h
    1699340 ALTM_TRANSLATOR    DE_HDL        Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor
    ' }, |$ K5 V, t( v1 R! O9 q+ U: F1630379 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator is not importing clines and vias/ t7 T" M5 ?" h
    1708615 ALTM_TRANSLATOR    PCB_EDITOR    All items of third-party PCB not imported in release 17.2-2016& ]2 R. }' _0 C/ c0 y% v7 e7 L
    1758296 APD                DXF_IF        DXF OUT: Rounded rectangle pads mirrored incorrectly
    9 K8 N2 d7 ?( {( z4 C1756040 APD                IMPORT_DATA   The 'die text in' command ignores values after the decimal point
    ' }( m. A' K. K, s1727206 APD                SHAPE         Merging two shapes results in an incorrect shape6 z+ I3 G" v' W4 g: `
    1753682 CONCEPT_HDL        CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL" m: x, m1 G+ X- S  s
    1721334 CONCEPT_HDL        CORE          dsreportgen not able to resolve gated part on schematic
    8 T0 y/ ~! w1 L7 P$ m* {# a1747559 CONCEPT_HDL        CORE          Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)! }+ v+ S) F9 h6 s7 P: l
    1749644 CONCEPT_HDL        CORE          In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes
    " b+ _% X/ Q- U' `1746910 CONCEPT_HDL        GLOBALCHANGE  Global Component Change unable to identify part data when using schematic pick option: E: @/ v- ]! s; d/ w; \, O/ J7 H; p
    1743572 FLOWS              PROJMGR       Project Manager displays incorrect values in Project Setting- k: B) J( e  l, z
    1724124 FSP                DESIGN_EXPLOR Provide TCL command to filter design connectivity window" i9 ]( q4 r3 J) O: y
    1719105 FSP                GUI           Tabular sorting not working in FPGA System Planner
    / o" t5 @* Z& Y# P4 n; T/ z1755750 PCB_LIBRARIAN      GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor0 d. l/ n5 y9 T! a5 p6 o# y# v2 |
    1722993 PCB_LIBRARIAN      IMPORT_CSV    Part Developer crashes while importing part information stored in a .csv file2 v5 C$ }1 x" u+ J# ]
    1758856 SIP_LAYOUT         3D_VIEWER     Correct the spelling error in the 3D Viewer Design Configuration window' o0 B1 x' ?8 x9 }
    1755179 SIP_LAYOUT         ARTWORK       PCB Editor crashes when creating Gerber files
    / N7 v) u' F; L) c/ \1 }2 w1743511 SIP_LAYOUT         MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check
    $ ?5 b/ l8 c) d
    & \9 o. P5 h+ o6 C! k* |, H3 u
    ) ^( p. \& O3 S( H, tFixed CCRs: SPB 17.2 HF021& v& b! K9 i6 K% J" b; M. ]
    06-3-2017
    5 [8 w4 o3 w$ o( P5 W6 I========================================================================================================================================================" C) q/ x$ Y/ p8 ^  B+ H4 x' ~/ Q6 |
    CCRID   Product            ProductLevel2 Title2 Z2 t# u, d' V. W
    ========================================================================================================================================================
    0 @% o. m  N0 S6 c1401318 ADW                DBEDITOR      Bulk Edit - Previously modified cells do not turn blue when selected
    1 J( s/ ^! S5 L- b1 R0 |! t% {1621446 ADW                DBEDITOR      Bulk Edit - sorting highlights incorrect cells to mark them as changed/ A# r- }* G& y% _3 z! K! h: K7 C5 o
    1743997 ADW                LIB_FLOW      Match file for standard models is incorrect6 |( V! p+ l; Z- f+ ^
    1746052 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes when applying no drc property
    7 l( @) `6 n9 U0 E; ^1736067 ALLEGRO_EDITOR     DRC_CONSTR    Interlayer checks not reporting DRCs between cline and mask layer2 K0 w9 C: F9 X2 S# z6 k* n! x
    1738587 ALLEGRO_EDITOR     EDIT_ETCH     Line width changing on slide for ETCH - Conductor (Not on a NET)' f3 `- p+ t) r
    1745277 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashes on using the slide command
    9 E1 ?- c3 }3 a  @1747942 ALLEGRO_EDITOR     EXTRACT       Fabmaster Out does not export arc in pad_shape
      N+ @- w- G' o1737202 ALLEGRO_EDITOR     GRAPHICS      Setting the variable display_raster_ops  Z1 o4 C9 Y1 v$ \6 N7 e5 N
    1744042 ALLEGRO_EDITOR     GRAPHICS      Unused pad suppression is not working on few nets3 U: w3 ^1 S* \, c
    1703848 ALLEGRO_EDITOR     INTERFACES    IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty
    , i/ o; W  G5 f2 U8 [1743899 ALLEGRO_EDITOR     MANUFACT      Glossing dangling vias crashes PCB Editor
      [+ f4 i# p, g5 Z1744467 ALLEGRO_EDITOR     OTHER         The 'logical_op_new' variable is not displayed in User Preferences Editor7 v$ D2 U/ e$ S4 X3 l  K; C
    1748520 ALLEGRO_EDITOR     OTHER         TDP fails to load on an empty database
    2 }  ?' R6 Y( c, m: R1748581 ALLEGRO_EDITOR     PAD_EDITOR    Padstack Editor crashes when changing default pad geometry
    3 {+ M4 p- q3 n9 n# C8 C. x* j* @1751469 ALLEGRO_EDITOR     PAD_EDITOR    Padstack Editor crashes/freezes when browsing for a shape symbol2 {/ h' D9 l; T, m- i% @/ p1 v& j* z
    1725948 ALLEGRO_EDITOR     SHAPE         Shape differences after conversion from release 16.6 to release 17.2-2016' Z" G+ u: ]; p
    1729306 ALLEGRO_EDITOR     SHAPE         Seting shape_rki_autoclip variable causes no void to be generated
    & f+ A: S6 l& I, ^6 o7 {$ h% b6 }4 R1698876 ALLEGRO_EDITOR     UI_GENERAL    Tabs are large and text is compressed in release 17.2-2016, Q, w: t4 H9 Z# ^- y( K- O$ I1 D& j
    1698883 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors. ^1 u: G: B, y% t5 o# d2 h
    1707933 ALLEGRO_EDITOR     UI_GENERAL    axlUIMenuFind not locating menu as per x_location9 y) w) H1 ?) I/ t/ j" q
    1741460 ALLEGRO_EDITOR     UI_GENERAL    Right-click, context menu options grayed in some cases after choosing Edit - Copy
    1 d5 S0 y5 l( t8 W) _2 s1747588 ALLEGRO_EDITOR     UI_GENERAL    Interacting with PCB Editor by sending messages is not working: _% f: Z7 x9 o2 H
    1747488 APD                EDIT_ETCH     Route connect is improperly affecting existing routes in locked high speed via structures1 Y& ?6 J* I. a+ @( v
    1750182 APD                STREAM_IF     The stream out settings are not saved+ f& F9 `1 t3 P. x6 |4 o
    1752067 ASI_SI             GUI           Links to differential waveforms do not work in Sigrity SI report
    - f3 [! s/ b: m, m, k3 u* s1752131 CONCEPT_HDL        COMP_BROWSER  Symbol view in part manager doesn't match the symbol version
    + z+ L. q* s8 V! Y1 s$ k& E4 ?1754116 CONCEPT_HDL        COMP_BROWSER  Default Symbol selected is n°2 instead of n°1 in component Browser4 \9 H& z. K0 O- i  k( X9 Q
    1754949 CONCEPT_HDL        COMP_BROWSER  Part Information Manager displays preview window with the wrong symbol and missing footprint
    # H6 J4 i; b! ]! P2 l) p1721334 CONCEPT_HDL        CORE          dsreportgen not able to resolve gated part on schematic
    " {/ `! r. t! }7 r7 @1750916 CONCEPT_HDL        CORE          DE-HDL crashes when trying to uprev a project in release 17.2-2016' x: ~: u! ]" ~: g
    1711487 CONCEPT_HDL        INFRA         Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design% t$ R. Y- a% K5 D
    1746915 CONSTRAINT_MGR     CONCEPT_HDL   Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow, d/ y3 V% l7 n4 K
    1743523 CONSTRAINT_MGR     DATABASE      Suppress warning pop-ups from the constraint automation script
    ' g: u( c# j6 M1746941 CONSTRAINT_MGR     UI_FORMS      'Go to Source' from DRC tab is not working in release 17.2-2016" v0 ]. X) Q. x& m
    1753010 ECW                METRICS       Metrics not getting collected due to old license in use
    8 L& `" ~# A7 v1713052 FSP                GUI           Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance
    # o% `- @6 U4 v9 H1719099 FSP                GUI           Net naming wrong after building block
    2 A2 k4 `  M$ A2 C/ p$ `0 h1719105 FSP                GUI           Tabular sorting not working in FPGA System Planner3 }5 U9 Y! K* G! u8 R" J8 h, ~# Y
    1720479 PSPICE             ENVIRONMENT   Probe window does not open consistently on Windows 10 systems3 k  ]3 P. \3 S: g$ E) V$ L
    1723411 PSPICE             ENVIRONMENT   Probe window does not open consistently on Windows 10 systems* ?" ~# r0 G  s& x4 `3 O
    1746628 PSPICE             ENVIRONMENT   PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016
    6 V  g) F2 u' a! m: e. k6 ]5 N1745976 SIG_INTEGRITY      GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing
    . m1 \5 B) m1 W2 v1690820 SIP_LAYOUT         PLATING_BAR   Cannot add fillets to pads with plating bars in release 17.2-2016
    & Q1 G" O% B+ m& l8 F% c1725042 SIP_LAYOUT         PLATING_BAR   Creating a plating bar removes dynamic fillets! f0 G% Q$ x5 d# b
    1747534 SIP_LAYOUT         SHAPE         Moving fiducial crashes SiP Layout8 s) u4 n9 Z  A: p0 l) R( ^2 ]
    8 s) Z+ Q: b' M1 y- c8 ^) `
    + q4 f. ]( t5 D- w
    Fixed CCRs: SPB 17.2 HF020
    ! }& O3 g8 [# r; L9 y$ L# @) Y05-21-2017
    ) x2 ?( G. _3 f/ r% o3 h: {========================================================================================================================================================) S. w' E6 t7 U; D/ N% C
    CCRID   Product            ProductLevel2 Title
    * @$ X) q( p+ f7 A========================================================================================================================================================
    " F) l2 H( ]5 ^. A1737443 ADW                DBEDITOR      Revising the schematic model classification for one category causes all parts in the library to be revised6 B- k4 R8 t( o' J
    1734123 ALLEGRO_EDITOR     3D_CANVAS     Interactive 3D canvas crashes Allegro PCB Designer in 17.2 S016
    4 d. M! A! E( i6 |! i  Z1742084 ALLEGRO_EDITOR     DATABASE      Running DB Doctor on DRA files with custom pad shapes resets some of the custom padstack shapes in release 17.22 Z' B& y+ x5 f' V
    1739397 ALLEGRO_EDITOR     INTERACTIV    In release 17.2, running the SKILL function axlImportXmlDBRecords causes Allegro PCB Editor to crash7 S  o3 }2 P' f& J0 ~
    1724588 ALLEGRO_EDITOR     MANUFACT      Backdrill Route keepout suppressing existing Route Keepouts
    2 x( g  j: C1 {- I1740036 ALLEGRO_EDITOR     MANUFACT      Generating the cross-section chart does not provide information about the overall board thickness
    % J5 R; `* L9 z4 H; L1743726 ALLEGRO_EDITOR     OTHER         IDF file export: In release 17.2, only one design outline is exported as against multiple board outlines in release 16.6
    : d% o4 p) Y2 `, C! z, F1744467 ALLEGRO_EDITOR     OTHER         The 'logical_op_new' variable is not displayed in User Preferences Editor# ]1 M  H' r/ r$ Z  E# z
    1729350 ALLEGRO_EDITOR     REPORTS       Net loop report is not working.
    ; ^6 }7 m" S  y4 \" J4 D1713014 ALLEGRO_EDITOR     SHAPE         Incorrect behavior of donut shaped pads at certain rotations# }. f+ P4 y* x0 P/ e' X
    1739870 ALLEGRO_EDITOR     SHAPE         The artwork is different from the PCB in release 17.2 Hotfix 17
    & `# Q. |+ l9 ]  v% h) l1698869 ALLEGRO_EDITOR     SKILL         PCB Editor crashes when trying to open another .brd file after running SRM on first .brd file8 Y6 k4 ^3 V! S
    1739307 ALLEGRO_EDITOR     SKILL         axlCNSDFAExport fails after first run+ c3 \- Q# z- k2 V7 _9 {9 W
    1743385 ALLEGRO_EDITOR     SKILL         SKILL APIs for STEP model mapping are not available in release 17.2 Hotfix 17 or 18" C2 ]1 A1 ]" }9 Q8 `& d
    1685826 ALLEGRO_EDITOR     UI_GENERAL    Reports when opened from Status Form disappear behind PCB Editor canvas when clicking on canvas
    . w" ]  X5 E) ~8 |( O5 x1687797 ALLEGRO_EDITOR     UI_GENERAL    Cannot open two HTML windows, one after the other, while using SKILL function% \  P) r- k' O2 Y$ |# Y8 @
    1696229 ALLEGRO_EDITOR     UI_GENERAL    Setting the 'allegro_html' environment variable in User Preferences Editor overwrites existing popup text windows" a+ v. @  w3 J5 J
    1708636 ALLEGRO_EDITOR     UI_GENERAL    In SPB 17.2 release, keyboard focus automatically shifts to the newly opened dialog box( E/ F7 `5 J  p7 Y  i
    1711367 ALLEGRO_EDITOR     UI_GENERAL    Launching two report windows using SKILL is not working in 17.2
    0 z+ V+ {8 X+ v8 Z1742856 ALLEGRO_EDITOR     UI_GENERAL    Allegro PCB Editor crashes if Project Manager is open for a design in release 17.2 Hotfix 189 L- Z% z# M' P# t& Z1 a
    1729519 APD                SHAPE         shape degassing does not generate all voids to cover entire shape5 `& B- y! A9 I8 z- M3 ^
    1711375 CONCEPT_HDL        CORE          Copy-paste of schematic between two instances of DE-HDL is not working as expected# O* r2 ?$ c  q* @
    1737230 CONCEPT_HDL        CORE          On the Linux platform, copying of schematic objects does not work between designs of releases 16.6 and 17.2
    2 l( C! S# P) h; S- e' K8 ]" R6 I1741375 CONCEPT_HDL        CORE          Inconsistent behavior of the Move command when moving a symbol6 o% s2 B+ j( x; c
    1743992 CONCEPT_HDL        CORE          Inconsistent behavior of the Move command when moving a symbol
    0 r8 Q. m8 L9 N0 S! c0 N1736093 CONSTRAINT_MGR     CONCEPT_HDL   Incorrect topology extraction and mapping errors related to MUX parts! |' Q5 e; D: k; G$ W5 `# k, i$ c
    1743518 CONSTRAINT_MGR     CONCEPT_HDL   Lag observed in expanding and collapsing the net classes in Constraint Manager7 z" w) E9 c3 Q. s
    1730159 FSP                ALLEGRO_INTEG FSP diff engine does not read PF Thevenin connections in FSP
      S" b- v9 Z' U! J# V# o4 J$ N" j1664070 ORBITIO            ALLEGRO_SIP_I Display pads of SMD components on correct layer8 F) r* Y1 P. v3 C
    1709319 ORBITIO            USABILITY     OrbitIO issues an error about Device template while importing brd with Bundles/ Q$ h+ d% f5 }  b, n- e$ r
    1741150 PSPICE             ENVIRONMENT   Need a way to prevent the 'pspSimSetting.js' file from being overwritten by a hotfix installation in 17.2# B3 F6 t2 m" ], N
    1735354 PSPICE             SIMULATOR     Access to custom nom.lib is not working as expected
    8 a, F. b( {2 ]6 A1716523 SIP_LAYOUT         COLOR         Tool crashes on using the PageUp, PageDown, and Tab keys in the Color dialog box.4 T" Q. f6 `$ h! `. y
    - r! i0 Q# B6 G

    # s0 s2 \# b7 l8 T# MFixed CCRs: SPB 17.2 HF019
    6 J5 U1 j7 ~: x1 ]3 i0 H. W05-6-2017, e# E8 K& W6 x4 O/ P) B& ]
    ========================================================================================================================================================2 L( r4 l9 u4 X3 R+ q" O, I
    CCRID   Product            ProductLevel2 Title
    0 i7 t" f/ v, Z========================================================================================================================================================( D3 t1 `! z& n1 E
    1701785 ADW                ADWSERVER     Getting 'Unable to locate tools.jar' error while using 'Copy Projects'
    ) ~' s- N: f# N) o/ i# F. b1706782 ADW                ADW_UPREV     Design uprev failed with error 'ERROR (FM-107): Failed to run adw_uprev'
    . k& k1 G) w8 z$ _; x1508159 ADW                FLOW_MGR      Flow Manager 'Open Last Project' option points to a deleted project: ]8 @  E. ]+ O% C4 l4 T
    1690903 ADW                FLOW_MGR      Flow Manager library project list empty after 'Remove From List'0 S7 ?8 |$ @. Q3 H
    1705224 ADW                LIBDISTRIBUTI Cannot migrate Library Footprint Models having subdirectory to release 17.2-2016+ k* O) x, q( k& [3 G; ], V; s
    1672037 ALLEGRO_EDITOR     EDIT_ETCH     Add ZigZag Pattern crashes PCB Editor7 J1 `% O  O3 A5 c
    1695711 ALLEGRO_EDITOR     EDIT_ETCH     In release 17.2-2016, Fiber Weave Effect - Add ZigZag Pattern crashes in Windows 105 K  r8 n# I5 _! Q$ ?& R1 l
    1706522 ALLEGRO_EDITOR     INTERFACES    DFX import displays error message '*Error* eval: undefined function - cloneID' but imports outline
    ' `. z# H7 F* n* d% C1716336 ALLEGRO_EDITOR     INTERFACES    DXF file is not correctly imported into PCB Editor
    " |! y( }6 d# m# T1720290 ALLEGRO_EDITOR     INTERFACES    Incorrect rotation of padstack after dxf import
      y" t- u! I" N. S$ J1724683 ALLEGRO_EDITOR     INTERFACES    DXF OUT: incorrect Rounded/Chamfered rectangle pad rotation
    , {  ]- K+ ]8 j; i1732587 ALLEGRO_EDITOR     INTERFACES    Format/content of ipc356 files exported in release 17.2-2016 different from release 16.6
    # v7 {6 l0 U+ D4 g" w9 x( r/ f1737516 ALLEGRO_EDITOR     INTERFACES    IDX Import works differently for placed and unplaced parts
    . d1 n& ]% T! `" Y3 }1715152 ALLEGRO_EDITOR     SCRIPTS       Clicking Layout in Project Manager fails to load PCB Editor and gives message 'Word too long'$ f% t2 a& V7 {" m
    940699  ALLEGRO_EDITOR     SHAPE         Update shape to smooth fails to void a few clines.5 Q  y" }8 v/ |
    1706581 ALLEGRO_EDITOR     SHAPE         Dynamic shape void clearance errors with vias7 w- U7 Z+ k3 P$ g) ]; o
    1638300 ALLEGRO_EDITOR     UI_GENERAL    Version information set in $cdsversion truncated on title bar for some tools
    " A" ?$ Q0 y4 n4 Q6 j! c1697732 CONCEPT_HDL        CORE          Pasting a signal name results in warning (SPCOCN-922) if the wire is too close to the edge of the page border
    * X/ k5 s& ~* O. x+ I6 P1729510 CONCEPT_HDL        CORE          Changing the name of a split block adds pages that are part of the page gaps
    + s5 f& z7 |" E. l: g' B1 G1721065 CONSTRAINT_MGR     CONCEPT_HDL   Physical import errors on changing plane to conductor in stack-up3 j$ m" G2 F  _, c: C1 p! e
    1734875 CONSTRAINT_MGR     OTHER         'Create Spacing CSet' crashes tool from existing CSet context and grayed out in design context
    1 B' a$ R4 N: }$ m, w5 c  `1 x) `- S1473104 ECW                PART_LIST_MAN Pulse does not filter capacitor values correctly
    . z! N/ ^- b, J2 [& |- t% P1736580 PCB_LIBRARIAN      SYMBOL_EDITOR Grids are not displayed correctly in Symbol Editor9 W1 z& H+ p1 x4 X
    1738955 PCB_LIBRARIAN      SYMBOL_EDITOR Need ability to edit Symbol Properties
    " j) @4 n, N0 V1 Q1735215 PSPICE             FRONTENDPLUGI PSpice part search customization CDN_PSPICE_ODBC_SRC environment variable is not working5 p% L+ f7 a7 e* }( z) A0 X; F7 ~
    1733198 PSPICE             PROBE         Probe crashes when exporting trace expressions with multiple plots to CSV files
    7 }  Z8 ?& V  t; ^- R/ [1737060 SIG_INTEGRITY      SIGNOISE      signoise fails for the AllegroSigrity_HS_Base_Suite option in release 17.2-2016 and release 16.6-2015
    , d2 N+ m5 t; s4 c: f1707443 SIP_LAYOUT         WIREBOND      Moving bondfingers violates spacing constraint
    ' j  K$ E" \7 h) R9 ~% }3 @  C8 s+ J; J# e+ O
    7 |  y* r; O2 X% J
    Fixed CCRs: SPB 17.2 HF018# h7 ~/ c$ A" a9 Y! I4 b
    04-23-2017
    / C/ r7 E& B/ D8 D1 z/ m========================================================================================================================================================% W6 Z; g: e; x
    CCRID   Product            ProductLevel2 Title
    & o& \0 h8 F3 J, L* d) E========================================================================================================================================================
    7 |7 X  Q; R; ~  [+ z1721773 ADW                ADW_UPREV     adw_uprev updates all versions in history log to the new version. Should only insert note about uprev.
    1 Q- e: g0 X0 Z& [: H7 m; Z1684346 ADW                LIBDISTRIBUTI lib_dist_client fails for new release 17.2-2016 design server- f; J9 P5 s! \! u4 s
    1696632 ADW                LIBDISTRIBUTI lib_dist_client fails on release 17.2 Designer Server having release 16.6 Master Server
    % T0 v8 n+ u* _$ i% E- R1705224 ADW                LIBDISTRIBUTI Cannot migrate Library Footprint Models having subdirectory to release 17.2-2016
    - F( R5 q1 X" V7 T9 U' ?2 L/ B1721017 ADW                LIBDISTRIBUTI adwserver -install fails intermittently during Master Library Server or MLR distribution
    8 a! k) D* ]' s( ]1711373 ALLEGRO_EDITOR     COLOR         Cannot interact with Allegro PCB Editor when Color dialog is open
    # j4 \# T6 z- H/ s4 I  |! l, p1710772 ALLEGRO_EDITOR     DATABASE      Mirror command not working on zones+ X5 N& y. c% c& D2 O) x3 p8 R# \6 ?
    1725621 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes when moving a group of components or clines% y* N- p. h( |! O, n. z. t; G) U, e
    1699796 ALLEGRO_EDITOR     EDIT_ETCH     AiDT fails and reports there are no timing constraints even when propagation delay is set5 s; a2 W& p7 E# b- t" `' m' A  T$ n- [
    1726483 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashing when converting corners to arcs
    , ]: B$ u+ E1 p( h: m, s1726678 ALLEGRO_EDITOR     INTERFACES    IDX copper layer export does not export all pin pads, a1 y1 D# w8 w. [3 Z) ?7 q8 L0 q
    1691036 ALLEGRO_EDITOR     MANUFACT      Fillet not centered on trace1 Q# Y; [2 c% U$ d2 N5 N! d
    1732304 ALLEGRO_EDITOR     MANUFACT      Countersink does not have drill figure on NCCOUNTERDRILL-1 subclass; r4 J$ b6 L  L4 u# H
    1719564 ALLEGRO_EDITOR     OTHER         Cannot open PDF published in release 17.2-2016 in third-party software( |, a" U7 f% w+ j$ i
    1723065 ALLEGRO_EDITOR     OTHER         PDF out does not print the outline correctly" E$ y; L1 T$ [$ Q
    1729247 ALLEGRO_EDITOR     OTHER         Cannot delete shape on Route Keepout layer
    $ a5 R) ]4 @  M5 ?1722747 ALLEGRO_EDITOR     PAD_EDITOR    Option to enable 'Connect by Touch' in Pad Editor
    $ N: H; D. s5 e1 [. ?1731643 ALLEGRO_EDITOR     PAD_EDITOR    Changes to secondary drill are not saved on padstack update
    - E6 r! _+ {' w6 ?; m( Z1727303 ALLEGRO_EDITOR     REPORTS       The 'Shape Dynamic State' report has changed to 'Shape Dynamic Status' in release 17.2-2016
    3 m% P* x4 Y% U* F& h% Z1695879 ALLEGRO_EDITOR     SHAPE         Dynamic shape priority error creates shorts.* A. J5 W( w+ o
    1713014 ALLEGRO_EDITOR     SHAPE         Incorrect behavior of donut shaped pads at certain rotations  X' o7 o1 U# e" @
    1588769 ALLEGRO_EDITOR     UI_GENERAL    Alt+key shortcuts are not available in release 17.2/ ?/ }" C' J1 T% }) r) r6 y
    1602563 ALLEGRO_EDITOR     UI_GENERAL    Shortcuts to menu items not working in release 17.2
    6 T, w( h* {, S) ?2 s0 P, [1603776 ALLEGRO_EDITOR     UI_GENERAL    Alt key not working with menu commands. H: w8 {0 f( [3 b
    1611516 ALLEGRO_EDITOR     UI_GENERAL    Keyboard shortcuts have no response
    " Z# C& U- P2 D% C1647271 ALLEGRO_EDITOR     UI_GENERAL    Preselection is not working for docked Find window6 {$ u7 }; v. s7 P* I
    1650044 ALLEGRO_EDITOR     UI_GENERAL    Keyboard shortcuts are not working properly in release 17.2
    # ]* a% K0 M: ^* i6 e1651912 ALLEGRO_EDITOR     UI_GENERAL    Inconsistent response when using the Alt key( c3 Q' I4 D/ R7 X
    1679964 ALLEGRO_EDITOR     UI_GENERAL    Many dialog boxes are blurred in Allegro PCB Editor/ S- u' r& o# X/ R  e
    1692416 ALLEGRO_EDITOR     UI_GENERAL    Underscores in menu commands denoting shortcuts are missing in release 17.2
    1 X3 w0 {& g8 N* P3 s+ d1693055 ALLEGRO_EDITOR     UI_GENERAL    Reports with html links end with an extra > at the end# {) z' p! a/ G4 h& g" T
    1693968 ALLEGRO_EDITOR     UI_GENERAL    Batch process that uses SKILL is taking too long to process files and generate reports
    - y* e! W" r" O1 \1698840 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016 Waive DRC report, selected coordinates of a Waived DRC remain blue; y& n+ ^6 M3 J9 a, i1 o2 d" p
    1703065 ALLEGRO_EDITOR     UI_GENERAL    Menu shortcuts do not work as expected+ |* `- M7 T: H7 i3 |( V$ p3 n' u
    1707547 ALLEGRO_EDITOR     UI_GENERAL    Release 17.2: The Alt key function is not working in PCB Editor
    / V  h+ ~' {0 w1709280 ALLEGRO_EDITOR     UI_GENERAL    Alt+Function key not working in release 17.2.
    ) L' r. `2 b% ?$ O% `) Q1711203 ALLEGRO_EDITOR     UI_GENERAL    Color does not change for selected coordinates in reports and Show Element
    . Y2 z0 h% q* M( G1711724 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, custom interactive menus stop responding when invoking another custom command
    3 I& H9 A% ?  }5 K# f9 ~1715613 ALLEGRO_EDITOR     UI_GENERAL    With undocked Options window there is a mix up of entered text and funckey  q/ g5 ?7 {7 R3 l
    1719301 ALLEGRO_EDITOR     UI_GENERAL    Selected coordinates do not change color in reports and Show Element$ Z# b: q7 F" E2 o4 o# Y
    1724197 ALLEGRO_EDITOR     UI_GENERAL    Short cuts and hot keys not working in PCB Editor in release 17.2-2016
    % _+ }; ~* `6 q" Q" B1728724 ALLEGRO_EDITOR     UI_GENERAL    Funckey is not working in release 17.2-2016; {4 g5 z+ R( }; f- \. {
    1673703 ALLEGRO_PROD_TOOLB OTHERS        Design compare not reporting the Top and Bottom layer differences$ r+ e( a. T. [) w, I
    1704474 ALLEGRO_PROD_TOOLB OTHERS        When using Productivity Toolkit - PCB Design Compare, 'Override undefined width' is incorrectly applied
      t, A7 t/ b  h( M1571035 ALTM_TRANSLATOR    CAPTURE       Circles in third-party schematics not getting translated into Capture' {2 @6 B, a# L+ f! v# _- u
    1588911 ALTM_TRANSLATOR    CAPTURE       Capture crashes when translating, project and libraries are empty& e+ A4 N5 O3 [* e
    1589394 ALTM_TRANSLATOR    CAPTURE       Schematic getting shifted off the page after translation  ?; x" w1 ]" C% s8 T& p
    1631294 ALTM_TRANSLATOR    CAPTURE       Errors while translating third-party design when original design is in metric units* x% [$ y: U, @7 {1 C2 F
    1663176 ALTM_TRANSLATOR    CAPTURE       Only first sheet of design getting translated from third-party schematic into Capture" n( l" y3 R9 D* y
    1694363 ALTM_TRANSLATOR    CAPTURE       Capture is unable to translate third-party designs
    / X: W( h) n  [3 A5 b2 r8 _! t1539739 ALTM_TRANSLATOR    CORE          Capture crashes on importing a third-party project
    % O8 a8 |1 ?5 @! x$ S1542860 ALTM_TRANSLATOR    CORE          Capture crashes on clicking Translate after selecting a third-party design
    6 o+ O* r( Y4 F( O1551642 ALTM_TRANSLATOR    CORE          Unable to import third-party schematics into Capture5 C# Y0 |. a' k4 n0 J! g9 ~6 x# j/ R
    1572929 ALTM_TRANSLATOR    CORE          Footprint names getting altered during translation
    2 ~7 F8 ]3 g3 K* M5 T( Z1568436 ALTM_TRANSLATOR    PCB_EDITOR    Unable to translate third-party layout data into PCB Editor
    3 l+ @8 E0 q7 _- j4 G/ `& h8 P1629256 ALTM_TRANSLATOR    PCB_EDITOR    Getting empty symbol and devices folders when importing into PCB Editor, K- @; [. U1 }8 {2 ^: d/ i# m
    1664120 ALTM_TRANSLATOR    PCB_EDITOR    Import from third-party to PCB Editor is not translating data correctly
    / B6 P. e) K+ M( F7 u6 G: S# }9 G1701537 ALTM_TRANSLATOR    PCB_EDITOR    Import does not complete and reports errors+ q" ^! x; U, \
    1698706 APD                DIE_GENERATOR When using Compose Symbol from Geometry, circle from DXF cannot generate to pin
    : U1 u9 o3 Z( x. q" s" y6 F( Y1 J1714528 APD                DIE_GENERATOR Getting 'illegal pad pointer' warning when creating die from geometry
    . E: G& V6 U$ I1714532 APD                DIE_GENERATOR Compose Die from Geometry creates incorrect pad shapes( z; H) }8 g$ a, g
    1734310 APD                MULTI_USER    Symphony server mode malfunctions when die layer present.
    9 h9 r# g7 J6 N; O! t1725506 APD                SHAPE         In release 17.2-2016 Hotfix 015, void is not generated in Artwork for BC7 layer causing short
    7 J. o  n: M# F5 @- o& T1724395 APD                WIREBOND      Running axlBondWireDelete returns error message
    7 g5 L$ d, Q6 b* t* P9 v9 R' w% ^1726609 ASDA               CANVAS_EDIT   Paste should not be allowed in the Current Refdes column of the Change Refdes form
    ; @8 [# S6 R8 ]* [7 a1719754 CONCEPT_HDL        ARCHIVER      Path stored in the compressed file starts from /home instead of the current working directory
    8 X! F( a9 Y1 Z$ r6 u2 L; z  j1726570 CONCEPT_HDL        CHECKPLUS     Checkplus crashes on Windows 102 m: l2 K) V, B0 ?6 W+ X0 u; Z" i
    1697977 CONCEPT_HDL        CONSTRAINT_MG Differential pair disappears when it is packaged
    4 S8 r9 y# Q% [" t6 D* j0 T; w1679575 CONCEPT_HDL        CORE          Page numbers are duplicated in Hierarchy Viewer when editing page names* o0 ]8 k. ~( u7 e! G
    1697732 CONCEPT_HDL        CORE          Pasting a signal name results in warning (SPCOCN-922) if the wire is too close to the edge of the page border9 b' p' B/ K/ c" \0 |
    1711564 CONCEPT_HDL        CREFER        CRefer crashes while processing a hierarchical design containing subdesigns
    * |1 |1 j% Z  S2 D8 _, |1730736 CONCEPT_HDL        OTHER         Crash on generating BOM from design
    / {5 e. M8 ^5 U1 P) ]# ^& `4 d1608350 CONSTRAINT_MGR     CONCEPT_HDL   Name of buffer model is not passed from Constraint Manager of DE-HDL to SigXplorer
    / @7 R1 F. ]* b) g1715803 CONSTRAINT_MGR     CONCEPT_HDL   Extract a net from constraint manager to SigXplorer, the models assigned are not displayed in SigXplorer
    1 R* `7 X, N, C. P& ~1718073 CONSTRAINT_MGR     CONCEPT_HDL   ECSet mapping errors on an upreved design in release 17.2: Pins in XNet and CSet do not match: }; x+ Z% T/ a0 z+ O8 C
    1720886 CONSTRAINT_MGR     CONCEPT_HDL   SigXplorer does not extract assigned model from the schematic
    ; }# [/ o9 A+ _% u- |1718514 CONSTRAINT_MGR     ECS_APPLY     Extracted topology does not use the PINUSE overrides specified on the canvas
    ' e$ Y6 E6 H& o9 A, {; N1722306 GRE                CORE          Boards with Total Etch Length constraint only should not include z-axis when budgeting pin pairs9 q/ w. e4 V5 F
    1710049 PSPICE             SIMULATOR     Functions are not taking parameters in correct order- o7 f2 p; ~& z! p2 R, i) b' q
    1693021 SIG_INTEGRITY      OTHER         PINUSE is not updated correctly at model assignment with specific steps
    4 V$ t* z" u; R' j/ j. G0 Z1730854 SIP_LAYOUT         SYMB_EDIT_APP Cannot delete all the die pin from a symbol using the Symbol Edit application mode
    , l8 {+ `, k% c! W, u
    9 N2 ?0 e; R2 J  U4 [7 e
    , r: K% [' R* D4 [$ ~$ H9 q: H) X6 N. JFixed CCRs: SPB 17.2 HF017
    + S$ K" U! T5 A+ e4 \, d' x+ s04-13-2017" W. h0 i8 |3 g6 r
    ========================================================================================================================================================# M5 k) W+ I- q
    CCRID   Product            ProductLevel2 Title
    " Q5 ]" A1 k% U4 ~========================================================================================================================================================
    " B; L" n6 u3 `+ A# r3 `( ^1732877 ALLEGRO_EDITOR     SKILL         The 'axlXSectionGet' function fails in release 17.2 Hotfix 016
    % Z2 ?( \# W7 x
    % F& q. a0 P! ~5 X9 @( B8 J" I/ `* F2 m( i
    Fixed CCRs: SPB 17.2 HF0160 {$ n! P7 F- {
    04-6-2017
    ! q2 }8 N# n6 M7 K! w# y6 A1 |2 K========================================================================================================================================================; ^) O- J% Y' M: Z
    CCRID   Product            ProductLevel2 Title) z$ W- K: u( }
    ========================================================================================================================================================* g5 }  ~& h) J+ ^4 p
    1673128 ADW                COMPONENT_BRO Directive is saved in project CPM# t( ^& e8 T: X' u& M+ k
    1673510 ADW                COMPONENT_BRO Lifecycle status color column is not sorted correctly in Component Browser search results3 g3 ^; R) R0 {( Q
    1604734 ADW                DATABASE      Parts displaying non-key properties and values in the Component Browser in ADW: N; w1 k$ {/ M& c6 S
    1142957 ADW                DSN_FLOW      No Help available for schematic design verification; H5 H& i: k5 z- b' f+ ^- n, }$ {
    1609186 ADW                DSN_MIGRATION ADW Design Migration utility should handle ADW board reference projects and manage atdm.ini
    0 B- @9 K1 F; ?' f1591757 ADW                GENERIC_UI    Running 'Create Test Schematic' in ADW Flow Manager results in Error SPCOCN-1736
    7 j1 c5 H8 I( i5 {' y: }1588111 ADW                LIBIMPORT     Library Import fails with Java errors while processing .csv files  U! M  B* c+ ?1 E2 f
    1642367 ALLEGRO_EDITOR     3D_CANVAS     Component height is not correct in new 3D Viewer! e/ ^( m& g: d' d5 y5 r9 B
    1642668 ALLEGRO_EDITOR     3D_CANVAS     The new 3D canvas does not show STEP model of the drawing (.dra)& O/ j/ m$ _" @2 Z& A9 v
    1653247 ALLEGRO_EDITOR     3D_CANVAS     New interactive 3D Viewer shows wrong placement
    . W8 D, a1 b+ {% o  c& P5 `1658275 ALLEGRO_EDITOR     3D_CANVAS     Components on the bottom side are shifted in the new 3D view
    5 Q; d. d1 ?8 S8 f6 [1639244 ALLEGRO_EDITOR     ARTWORK       When importing an artwork, a sub-folder is created with the value of the ads_sdart environment variable
    # V& Q5 n* Q3 r6 t# Y* i5 s( S1658173 ALLEGRO_EDITOR     ARTWORK       ARTWORK: Value of Scale factor for output.
    ) ?7 M) g: Z+ z1 w/ \1661760 ALLEGRO_EDITOR     ARTWORK       Import artwork to Design Outline layer does not give error in Allegro prompt.4 m# z' L4 X5 G) ]6 |6 M
    1667778 ALLEGRO_EDITOR     COLOR         Add option to set FORM mini dehl_retain_color to NO2 n4 N6 G) v' E; m" N
    1669462 ALLEGRO_EDITOR     COLOR         Changes made to the Visibility tab are not reflected in the Color Dialog window5 d7 H5 i! f4 H/ J  T, g0 m8 U
    1641265 ALLEGRO_EDITOR     CROSS_SECTION The differential impedance value for a layer is not getting updated5 ]9 ?0 u1 y9 b- r& }' t' _$ l
    1648149 ALLEGRO_EDITOR     CROSS_SECTION Getting warning when calculating impedance in mixed stackup' \/ m& n5 N) B' p
    1671441 ALLEGRO_EDITOR     CROSS_SECTION Enhancement request for cross section dialog box
    $ L- C; l+ U, t, Q1 q  o# @1673320 ALLEGRO_EDITOR     CROSS_SECTION Diff impedance calculation fails6 ]( n: l' X2 O; f5 V/ e) N' ~8 g
    1690021 ALLEGRO_EDITOR     CROSS_SECTION How to keep settings of expanded/compressed columns in the Xsection- I" [1 q0 b5 ~9 X: A
    1703831 ALLEGRO_EDITOR     CROSS_SECTION Calculation of Diff Z0 fails in flex designs6 t* Q2 `+ `) X+ v' @2 }: m& Y
    1711484 ALLEGRO_EDITOR     CROSS_SECTION ShowAll Column does not retain its status
    9 c+ U1 q% T0 E4 d1672841 ALLEGRO_EDITOR     DATABASE      ERROR(SPMHDB-153): Table corrupt; current/maximum mismatch9 h; k/ h2 o8 v/ C9 u. x8 |
    1673613 ALLEGRO_EDITOR     DATABASE      COVERLAY_TOP not present in the Non-conductor section of Color Dialog window
    4 F+ T1 M% E# H! k7 Z1688123 ALLEGRO_EDITOR     DATABASE      Drill Plating Issue# `& q3 O6 k1 c, L( F
    1701995 ALLEGRO_EDITOR     DATABASE      When upreving a 16.6 brd to release 17.2, lines drawn on OUTLINE are translated to CUTOUT and not DESIGN_OUTLINE3 e* x$ a! G  |8 i/ f
    1710772 ALLEGRO_EDITOR     DATABASE      Mirror command not working on zones) h8 X6 \# \$ B$ v2 M
    1713335 ALLEGRO_EDITOR     DATABASE      Defining Adjacent_layer_keepout_above and/or Adjacent_layer_keepout_below and then saving the .dra file giving error  k3 t7 t8 }7 l7 A  b  P
    1693289 ALLEGRO_EDITOR     DFA           File - Save As script does not save the DFA file$ o6 Z4 o4 c, p0 J
    1644004 ALLEGRO_EDITOR     DRC_CONSTR    Unreported DRCs from dynamic copper to line and dynamic copper to SMT pin
    , {8 |$ L- n) E# X# M6 o+ p4 g1651425 ALLEGRO_EDITOR     DRC_CONSTR    The .brd file crashes when moving text controlled with minimum metal to metal constraints
    2 g  q5 D: Y1 F/ J  W% B1 w1663494 ALLEGRO_EDITOR     DRC_CONSTR    Reported Mechanical Pin to conductor spacing DRC constraint value is incorrect leading to false DRCs: A" b2 N) |& a% n6 K
    1687049 ALLEGRO_EDITOR     EDIT_ETCH     Create a Via Structure disconnects nets: w5 l1 t( i1 T; Y3 M. X
    1704296 ALLEGRO_EDITOR     EDIT_ETCH     Asymmetrical fanout created for BGA Quadrant style
    # k2 k  `- |9 }) ]* l1686873 ALLEGRO_EDITOR     EDIT_SHAPE    Merge static shapes deletes both the shapes selected.- W, T$ ~9 s' |5 u4 p0 O9 X! e' G6 }
    1629925 ALLEGRO_EDITOR     GRAPHICS      Errors reported and no layout data drawn in PCB Editor in release 17.2 Hotfix 003 on Ubuntu 14.04# L7 ~0 h  a- I& t  m" O
    1628895 ALLEGRO_EDITOR     INTERACTIV    Shape Edit mode: An error message is required when attempting to edit a Shape with the FIXED property
    7 v! d- a, g+ E# U; ^/ f4 P; J( x1666379 ALLEGRO_EDITOR     INTERACTIV    Place replicate is not working on the attached test case
    ! J6 [! y6 V7 @8 ?* @7 K$ T3 a5 {5 C1668282 ALLEGRO_EDITOR     INTERACTIV    Grid display incorrect for repeated grids
    ' g, s; `6 d6 Y# E- z# X! C1675531 ALLEGRO_EDITOR     INTERACTIV    Design Entry CIS: Cross Probing with PCB Editor and Constraint Manager is not working
    4 o) l4 z* n( y- _/ z1694470 ALLEGRO_EDITOR     INTERACTIV    Update description of variable padstack_nowarning_display
    : I4 f* @! B5 w, v+ g; x1696855 ALLEGRO_EDITOR     INTERACTIV    Mixed grid setting is not displayed correctly on Define Grid screen.
    2 ]0 C- t! U8 [9 s: m  U4 i1698192 ALLEGRO_EDITOR     INTERACTIV    Deleting and replacing a component causing database corruption in Hotfix 0090 F( h  A% w4 f1 O
    1703671 ALLEGRO_EDITOR     INTERACTIV    An error occurs when defining grids with zero increment value
    ) D. u5 w: _8 s( {5 x1703812 ALLEGRO_EDITOR     INTERACTIV    Crash during move when using the 'snap pick to' option set to symbol origin
    ! s4 l; i$ {3 X0 u& q# {' f9 W. ~1719276 ALLEGRO_EDITOR     INTERACTIV    Setting variable grid for 'All Etch' displays an error in the Define Grid form0 d5 k+ p" @0 @6 I0 Q$ I5 R
    1663422 ALLEGRO_EDITOR     INTERFACES    Shape loses group membership after importing through sub-drawing
    $ ~# N0 t! V8 J7 s5 w; o8 ?" y1637959 ALLEGRO_EDITOR     MANUFACT      Thieving uses different clearance values around the route keepin." b1 i# }( D/ P2 c# b
    1716431 ALLEGRO_EDITOR     MANUFACT      Test points generation stops due to an error' B3 l* P% B6 N% i& `! }& s
    1641994 ALLEGRO_EDITOR     OTHER         DB Doctor: Incorrect spelling of 'eliminated' in the log file messages% W. S, b: U0 r4 u- ?6 ^
    1660496 ALLEGRO_EDITOR     OTHER         SiP Layout crashes when trying to generate abstract level view by using export chips and connectivity* b: g. u& Z% x% {# s4 {
    1685464 ALLEGRO_EDITOR     OTHER         The 'alias ~S save' command is not recognized when set in the local env file
    1 M, _& \4 q2 A, K: H0 H1696486 ALLEGRO_EDITOR     OTHER         STEP export results vary between releases 16.6 and 17.20 a6 V' W1 l0 k" E' \
    1706623 ALLEGRO_EDITOR     OTHER         axlBackdrillGet crashes for invalid argument
    8 [1 [7 R& V) ~5 F8 t1586957 ALLEGRO_EDITOR     PAD_EDITOR    In Pad Editor, selecting a pad geometry is not showing up in the Design Layers tab0 {: D3 W+ I! z2 }2 `" ]! i
    1610984 ALLEGRO_EDITOR     PAD_EDITOR    Geometry set in tabs not read, only initial value set in Start page is used
    . ~8 B  z5 _! Y# g' I% z9 ?1614015 ALLEGRO_EDITOR     PAD_EDITOR    Padstack Editor in release 17.2 does not auto fill geometry in design layers
    + m$ v- r- O! V$ U+ B1636012 ALLEGRO_EDITOR     PAD_EDITOR    Keepout should not be allowed if antipad is not defined for outer layers
    4 f6 \4 q5 p7 A9 T  Y: A1641973 ALLEGRO_EDITOR     PAD_EDITOR    Padstack Editor: Path to the previously opened .pad file is not seeded in the File - Open dialog on a fresh launch
      s- I/ x7 C. V; w3 C1642789 ALLEGRO_EDITOR     PAD_EDITOR    In release 17.2, 'Units' and 'Decimal Places' in Padstack Editor are not updated as per the .pad file
    % a9 }& s9 i* |2 w+ M9 b& b1646914 ALLEGRO_EDITOR     PAD_EDITOR    The 'Save' button is grayed out in Padstack Editor0 M8 [+ D  F; t3 P
    1657553 ALLEGRO_EDITOR     PAD_EDITOR    No possibility to specify Padstack Editor default library path at invocation) Q  |: |( M! f4 k
    1657609 ALLEGRO_EDITOR     PAD_EDITOR    Changing Tolerance field in Padstack Editor does not activate the Save button0 u" o, X# w3 S8 z
    1662225 ALLEGRO_EDITOR     PAD_EDITOR    Padstack editor dialog message doesn't match available options0 L% [4 A. V" x# [* n
    1667062 ALLEGRO_EDITOR     PAD_EDITOR    Padstack editor does not retain the decimal places from the previous session  {7 M7 u, N  D1 b3 c4 _
    1672774 ALLEGRO_EDITOR     PAD_EDITOR    Pad Editor graphics appear to show offset incorrectly/ Q* E' ^3 Y1 \/ P9 X/ I4 q. o
    1674157 ALLEGRO_EDITOR     PAD_EDITOR    Update Symbols does not update Pad Type Information; Y: y3 T% l  p+ Z
    1675438 ALLEGRO_EDITOR     PAD_EDITOR    Drill hole size warning for the SMD pad/ d3 r+ \' }( H% f# [# v
    1684376 ALLEGRO_EDITOR     PAD_EDITOR    Pad Editor issues with settings, such as decimal places, layers, and so on3 ?! l( i1 R6 B2 I3 t: E9 |
    1690376 ALLEGRO_EDITOR     PAD_EDITOR    Variable padstack_nowarning_display fails to suppress warnings  y8 G- |( b( y" d$ r# l4 m+ g
    1694649 ALLEGRO_EDITOR     PAD_EDITOR    Change&nbsp;Cancel button to No in warning generated when&nbsp;updating padstacks in design layout: E: D& z# v+ Q0 Y; y  ^9 H
    939242  ALLEGRO_EDITOR     PLACEMENT     Cross probing between Capture and PCB Editor is inconsistent# c/ g2 T8 \* t9 l* Y
    1103945 ALLEGRO_EDITOR     PLACEMENT     Place Replicate Create does not include the etch connected to pin) K' j+ ~6 u6 n1 q6 c# z/ `& ~
    1233019 ALLEGRO_EDITOR     PLACEMENT     Allow cross probe object selection apart from highlighting during place replicate1 r- W  {9 _/ y) Z6 S
    1643078 ALLEGRO_EDITOR     PLACEMENT     PCB Editor flags an error message when a module is placed at a specific angle
    # ]/ z, ]1 U# V2 Z1696932 ALLEGRO_EDITOR     PLACEMENT     Inconsistency with Snap pick to when selecting Segment Midpoint' w4 B* B" F+ z0 D
    1654500 ALLEGRO_EDITOR     REPORTS       In release 17.2 Hotfix 006, display of Netin (back anno.) report fails when variable ads_sdreport is set/ V# i& l( S# N; @/ Z7 s
    1643992 ALLEGRO_EDITOR     SCHEM_FTB     Export Physical fails with the 'netrev.exe has stopped working' error
    # ~* r4 Y+ L* @4 S# h& Q1653400 ALLEGRO_EDITOR     SHAPE         Dynamic shape does not void a via.
    ( R5 ~! k( M4 ?1 j; G1 B1668262 ALLEGRO_EDITOR     SHAPE         dynamic shape does not void custom route keepout with arc
      f  o. v. x5 R2 a( j: {; t1682569 ALLEGRO_EDITOR     SHAPE         Variable 'dv_squarecorners' not working correctly.2 g1 _) F$ u( K7 I* d% z$ f) N
    1696240 ALLEGRO_EDITOR     SHAPE         SKILL error when merging polygons
    % A2 P5 T7 G" L: r- x1 X1709968 ALLEGRO_EDITOR     SHAPE         In release 17.2, DB Doctor reports error in shape when no error was reported in release 16.6 for the same shape) U& ^' ]2 B" M  ~
    1632505 ALLEGRO_EDITOR     SKILL         In release 17.2 Hotfix 004, PCB Editor crashes after SRM update and save7 E5 [* _. E) D4 `
    1651701 ALLEGRO_EDITOR     SKILL         Cannot set the etch factor value in the cross-section using the axlXSectionModify() SKILL command" \8 m9 b; ^' ~' d9 u. }2 G" h
    1658419 ALLEGRO_EDITOR     SKILL         PCB Editor crashes after running SRM
    6 u; H3 F4 D- z+ B) m8 J1658948 ALLEGRO_EDITOR     SKILL         axlIsLayerNegative() is not working in release 17.2% x+ q  n2 w0 q; {
    1670956 ALLEGRO_EDITOR     SKILL         axlIsLayerNegative() always returns nil
    8 x. Z! `4 }0 K' }" ~- y. t1687239 ALLEGRO_EDITOR     SKILL         Problem with SKILL function axlCNSGetPhysical - incorrect parse string
    7 G) k! @6 l8 l. Z1692345 ALLEGRO_EDITOR     SKILL         The axlGetParm documentation example for deleting an artwork record is incorrect.
    / I6 M7 A% r( o1 R+ ~1707878 ALLEGRO_EDITOR     SKILL         Object rat_t does not work with axlDBPinPairLength.6 K0 `2 I8 D2 M: u, L
    1598061 ALLEGRO_EDITOR     UI_GENERAL    Adjust menus to allow side by side view: M& @8 M! \2 U! o5 ?. q
    1599901 ALLEGRO_EDITOR     UI_GENERAL    Color Dialog box is not updating according to visibility tab.( _; w. ?. x2 {9 Q& P0 G, I( t
    1602563 ALLEGRO_EDITOR     UI_GENERAL    Shortcuts to menu items not working in release 17.24 }4 F" R% A  o+ l
    1603776 ALLEGRO_EDITOR     UI_GENERAL    Alt key not working with menu commands& o; h+ `- H, D. d
    1611516 ALLEGRO_EDITOR     UI_GENERAL    Keyboard shortcuts have no response5 ?$ \! a, B$ G
    1614763 ALLEGRO_EDITOR     UI_GENERAL    Cannot scroll to the bottom of an undocked command window in PCB Editor7 o: \3 Y+ U0 N1 `- k$ A
    1619873 ALLEGRO_EDITOR     UI_GENERAL    Command Window scrollbar does not reach its end
    % q- y, |2 h; b6 I# C" k8 G# R1624617 ALLEGRO_EDITOR     UI_GENERAL    Dialog box title under Setup > Outlines > Design Outline... Design is misspelled as "Desgin"4 i7 n# i; W7 N! y! o' O2 p
    1631646 ALLEGRO_EDITOR     UI_GENERAL    Visibility pane not retaining the correct layer view
    6 T+ w7 I7 q7 O' d1637062 ALLEGRO_EDITOR     UI_GENERAL    The last line of the floating command window in release 17.2 is hidden behind the command window frame* C* r9 L1 z0 ~
    1642645 ALLEGRO_EDITOR     UI_GENERAL    Cannot scroll to the bottom of an undocked command window in PCB Editor
      N' ]2 D. ?. |+ K1645335 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor crashes in Hotfixes 004 and 005 if ODE and Allegro Manufacturing options are installed
    5 l0 ^1 A* [+ c3 ?8 E1647520 ALLEGRO_EDITOR     UI_GENERAL    PCB Editor crashes after installing release 17.2 Hotfix 005- x" m; G% t3 d
    1647541 ALLEGRO_EDITOR     UI_GENERAL    Release 17.2 Hotfix 005: PCB Editor crashes immediately after launch+ E5 |" V. c+ [; l7 q
    1650044 ALLEGRO_EDITOR     UI_GENERAL    Keyboard shortcuts are not working properly in release 17.2
    8 l, r, B& Q, k8 F' j7 m1651912 ALLEGRO_EDITOR     UI_GENERAL    Inconsistent response when using the Alt key
    1 ^* s' s# ^0 E+ ]. T) [6 G8 k* p1652423 ALLEGRO_EDITOR     UI_GENERAL    Using the F1 key does not display the help document
    ' w# P0 U8 ~. [4 p2 @" |9 s8 |1654600 ALLEGRO_EDITOR     UI_GENERAL    Spelling Mistake in "Design Outline" dialog box, Setup->Outlines->Design Outline, misspelled as "Desgin"
    1 D3 R; ~5 o) {/ u  b1654777 ALLEGRO_EDITOR     UI_GENERAL    Reports UI does not work properly when writing a report file.+ |) C+ ~2 R$ i7 |( W+ ~9 Y0 w. P
    1655500 ALLEGRO_EDITOR     UI_GENERAL    Visibility selection ignored after color change- l% [' I0 M& g) u2 u
    1655514 ALLEGRO_EDITOR     UI_GENERAL    Artwork Film is available in the View section only after you restart PCB Editor# A8 x; w; G) V
    1663819 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2, SKILL function, axlOpenDesign(), does not work as expected
      _9 c8 P, \7 P( H9 g: W1671334 ALLEGRO_EDITOR     UI_GENERAL    Design outline is not shown in 'World View' window- S  I) h% c2 O; e- h$ p) k  H
    1672148 ALLEGRO_EDITOR     UI_GENERAL    Add option in release 17.2 to change the placement of the Find, Visibility, and Options tabs similar to earlier release" O0 B9 p/ f) u/ W* c
    1679418 ALLEGRO_EDITOR     UI_GENERAL    On choosing Edit - Move, the 'Symbol pin #' box is obfuscated
    " `% o  ~- C6 Z1679761 ALLEGRO_EDITOR     UI_GENERAL    Choosing Edit - Spin hides 'Symbol pin #' partially+ Z( Y0 z0 ~. b8 U$ p4 \7 o
    1686887 ALLEGRO_EDITOR     UI_GENERAL    Hyper Text no longer selects coordinates for easy copy0 C5 U( i7 [* x( j# K: f
    1687286 ALLEGRO_EDITOR     UI_GENERAL    In 17.2 Hotfix 009, the Static Phase meter shows up in the middle of the screen instead of the lower-right corner
    ( ^* P+ ^) |+ E) D  W/ c1692416 ALLEGRO_EDITOR     UI_GENERAL    Underscores in menu commands denoting shortcuts are missing in release 17.2
    1 B# T9 c; n3 A* ~1693968 ALLEGRO_EDITOR     UI_GENERAL    Batch process that uses SKILL is taking too long to process files and generate reports
    ( G, J. {7 I, U% ^# M$ t1702420 ALLEGRO_EDITOR     UI_GENERAL    Unable to maximize&nbsp;reports viewer&nbsp;in 17.2
    6 M  b1 K7 A- k# v& [$ }' i1 N1703065 ALLEGRO_EDITOR     UI_GENERAL    Menu shortcuts do not work as expected. g% d7 ~# K: ?) o. Z( f
    1703107 ALLEGRO_EDITOR     UI_GENERAL    Scripting using regional settings for decimal separator: x0 M! S. s! `2 N2 ?8 `; n
    1707547 ALLEGRO_EDITOR     UI_GENERAL    Release 17.2: The Alt key function is not working in PCB Editor/ D& [& a7 ^( h, Q  y" Q
    1709280 ALLEGRO_EDITOR     UI_GENERAL    Alt+Function key not working in release 17.2.
    ! s) D6 e, P% g+ i" g- K& u9 G1639896 ALLEGRO_PROD_TOOLB CORE          MFG collector does not move files to subdirectories
    : ~1 f4 W& n& b* t8 n! {2 c( X1608804 ALTM_TRANSLATOR    DE_HDL        Translation issues in symbols with multiple physical pins mapping to a single logical function- P) Z6 S7 Z" o: b# W
    1658525 ALTM_TRANSLATOR    DE_HDL        Invalid characters in pin names
    - o6 ]  s, ?. `$ [( w0 p% ^" g5 n1658536 ALTM_TRANSLATOR    DE_HDL        All cell names should be generated in lowercase letters
    8 O2 M8 Y8 G  R2 u1609962 ALTM_TRANSLATOR    PCB_EDITOR    Errors reported during design translation
    : @3 |$ e" {; s: H1661562 APD                DRC_CONSTRAIN The wrong space calculation on finger to trace& ^/ ~! N+ J! U) n" l
    1682398 APD                SHAPE         Deleting islands causes out of date shapes
    / Z1 D5 Z5 M. b3 o$ K. x1638112 ASDA               CANVAS_EDIT   Unable to rename multiple selected buses using the 'Assign Name' command- Z; W9 V7 k: H& g3 b$ m
    1645571 ASDA               CANVAS_EDIT   Various routing inconsistencies with synonym bodies on the canvas. g4 V6 W5 i0 f) K
    1656336 ASDA               CANVAS_EDIT   Presence of illegal characters in the net name removes the entire net name
    & I; J+ E9 g5 g" f+ K. k" L! n$ i1667176 ASDA               CANVAS_EDIT   Unable to add the port symbol in a specific scenario% F9 Z; U: t7 ]' t/ g# ~
    1641473 ASDA               CONSTRAINT_MA Importing a tech file into SDA makes the tool unresponsive
    3 R+ p/ A6 f7 Z6 m1661350 ASDA               CONSTRAINT_MA Unable to create physical & spacing class from the docked CM6 L2 R1 s; r/ p2 g- a/ |  U
    1645557 ASDA               IMPORT_DEHDL_ Importing a DE-HDL design into SDA adds the COMMENT_BODY attribute to nets0 ]$ J7 \( {8 N4 N  S; x3 L8 N* f5 x
    1652753 ASDA               MISCELLANEOUS Tcl command window should display correct casing for autocompleted command
    ; `- a' ^- T: Q& P; o& M1654973 ASDA               MISCELLANEOUS If there is a casing mismatch in the Tcl command name, correct command is not picked from the list4 |8 @% I: m( T6 F
    1652718 ASDA               PAGE_MANAGEME Page numbering on the page border does not update correctly when pages are moved, added, deleted
    & J1 e2 K/ N# w$ i0 Y1699454 ASDA               TABLE         In the table object, cursor skips a cell on the first use of the TAB key  O+ T: I0 {7 _  o; `" {4 A
    1702702 ASDA               TABLE         Copy-pasting table objects to a new page fills the headers and rows in black
    7 r( d- C2 @2 T& Y9 _1668877 CAPTURE            ANNOTATE      Using Ctrl+drag does not preserve the reference designator value# ~' p! T# q; E: N7 I, Q
    1665454 CAPTURE            NETGROUPS     Incremental copy for alias does not work anymore.3 p8 C7 q1 M& X8 a+ d- |, G
    1634598 CAPTURE            OTHER         The ‘OrCAD_Capture_CIS_option’ license not released even after selecting another product option5 x- Q- R/ |& S8 c; f
    1636090 CAPTURE            OTHER         Capture crashes after switching from release 17.2 Hotfix 003 to 004 due to some Tcl files9 O  ]- G- b# a4 y: O5 o" I
    1650029 CAPTURE            OTHER         Crash while archiving a newly created PSpice project without adding simulation profile
    " O2 x( c' j, N; |" y& Q" G; |1659602 CAPTURE            OTHER         Saving CIS BOM via TCL command window
    % v( @- X0 g0 P3 T( p' o2 [9 p1678715 CAPTURE            OTHER         Capture.ini [WebResourcesMenu] is not working in release 17.23 g3 y. e- A/ |; g
    1619449 CAPTURE            PROJECT_MANAG Search not working in a PSpice project7 e. w% t6 n* x, p9 O* ~, {. F8 M3 d
    1670133 CAPTURE            PROJECT_MANAG Start Page showing wrong Software Version
    1 ?. }% s5 n% x. g3 i% y9 A1670766 CAPTURE            PROJECT_MANAG autoreference does not work properly
    3 h$ `! `; N4 ^2 t* w7 G* }5 w- _1676095 CAPTURE            PROJECT_MANAG (SID:22758) OrCAD Capture Start Page reporting wrong hotfix installed3 t* D" s5 p/ Y" x- U8 f9 m
    1658315 CAPTURE            TCL_INTERFACE Inserting text with double quotes is not working as expected in PDF created from Capture
    " p- _% |+ @6 J0 B& A% J1642601 CIS                OTHER         Design Entry CIS: SQL server password is required each time the tool is launched  t9 T9 e+ [6 P) ^- @2 s9 I1 ~
    1712279 CONCEPT_HDL        CONSTRAINT_MG Differential pairs are dropped from Net Classes when upreved to release 17.2-2016
    3 E5 x6 u! D, e+ e3 B# ~1665449 CONCEPT_HDL        COPY_PROJECT  Copy project fails with error COPYPROJ-77" B; ~! `5 v; y) ^5 ^
    1661778 CONCEPT_HDL        CORE          Advanced Find will not find pins with the SIG_NAME property attached/ s1 l/ [  K# h; ~* d- W* e3 F
    1666084 CONCEPT_HDL        CORE          All user-defined properties are not listed in the Customize columns in Variant Editor2 {7 Y" h" Q% Z% Y/ O( R; l4 N2 f( x
    1667043 CONCEPT_HDL        CORE          Incorrect information in cpm.log file
    + p8 O! f: B  W1670659 CONCEPT_HDL        CORE          SIGNAME text off grid when pasting copy using ctrl+v.% \2 v! {. L8 w3 o+ K
    1697732 CONCEPT_HDL        CORE          Warning (SPCOCN-922): The object is being placed towards the left edge of the schematic. Ensure that the objects are pla3 I* Q3 V( C4 y! u+ s) R
    1697955 CONCEPT_HDL        CORE          Rename Signal places sig_name at an incorrect position for an unnamed net2 Z, ]  e8 v& j: `& p
    1711635 CONCEPT_HDL        CORE          The arrow keys do not work as expected in Windows mode, H6 o9 |" V6 n& ^6 e. v
    1713091 CONCEPT_HDL        CORE          Difference in the behavior of 'Add Signal Name' in DE-HDL between releases 16.6 and 17.20 v/ F, k, K' a- D$ i% j% D
    1708820 CONCEPT_HDL        OTHER         In a board cache flow, component bodies are missing when importing another board cached flow project.# X2 V/ o  `6 J8 I' {
    1639928 CONSTRAINT_MGR     CONCEPT_HDL   The '-filterFile' argument is not recognized when cmDiffUtility is run as a command line operation6 T# t' q; k" z4 E
    1657048 CONSTRAINT_MGR     CONCEPT_HDL   Unable to navigate through the search results in the CM Reports
    ' Z; O- m, i- v, F8 }% X1718073 CONSTRAINT_MGR     CONCEPT_HDL   ECSet mapping errors on an upreved design in release 17.2: Pins in XNet and CSet do not match
    : T  M( M7 `' G# J7 v; F" C; w1 F) T1717336 CONSTRAINT_MGR     DATABASE      Netclass members change during logic import; it's a toggle switch
    : L4 H3 I$ J" P, e9 i$ l1718514 CONSTRAINT_MGR     ECS_APPLY     Extracted topology does not use the PINUSE overrides specified on the canvas
    1 l* j+ ]" ?: K! X1682885 CONSTRAINT_MGR     INTERACTIV    Constraint Manager worksheet switching does not work correctly in Linux
    . Z1 Y+ U- D, u' N% p5 q* h' I7 e1669523 CONSTRAINT_MGR     OTHER         Select is disabled in Constraint Manager when a command is active in PCB Editor
    : ]+ `% B3 W3 T* }1670802 CONSTRAINT_MGR     OTHER         Selecting a list of nets using the shift key does not work in Spacing and Physical domain
    0 s7 m" {& m7 ^, {3 G1670922 CONSTRAINT_MGR     OTHER         Title of the Layer Remove window is Constraint Manager
    & R+ I" y* k8 g& n1678235 CONSTRAINT_MGR     OTHER         Select option grayed out in Constraint Manager if a command is active in PCB Editor, `/ B$ w1 x* J/ ^0 Q) j/ G
    1680917 CONSTRAINT_MGR     OTHER         In release 17.2, nets cannot be selected in Constraint Manager when a PCB Editor command is active
    # G' r" g" Q, g8 }5 N6 I1691125 CONSTRAINT_MGR     OTHER         Highlight command no longer selects the net in CM
    6 X! p2 _( j+ A& R0 Y5 o1703791 CONSTRAINT_MGR     OTHER         Cross highlighting and assigning color to nets between PCB Editor and CM does not work/ e( l2 @% k: X, e' D' v* w0 v
    1649603 CONSTRAINT_MGR     UI_FORMS      Expand and Collapse commands do not work when multiple objects are selected
    # O; z. q# ?4 d4 r+ w8 V1654931 CONSTRAINT_MGR     UI_FORMS      Expand, collapse only works on one of the multiple selected objects.1 e. @! P7 ]8 |4 }* W5 u
    1668794 CONSTRAINT_MGR     UI_FORMS      Incorrect via name shown when filtering via list
    1 i( a( K  l' H7 i! v1678305 CONSTRAINT_MGR     UI_FORMS      Unable to use the CM worksheet customization (wcfx) from the CDS_SITE area- U4 M- Q" x, S
    1679909 CONSTRAINT_MGR     UI_FORMS      Incorrect layer order getting saved when defining BB vias in Constraint Manager PCSet
    - v1 |( p0 ~- T: a. I1 [1691906 CONSTRAINT_MGR     UI_FORMS      Display Issue: When you use the filters, the horizontal scroll bars are duplicated# w% y8 h* i& x: w) p6 k) b6 x
    1677893 ECW                INTEGRATION   Integrations list update is not working as per scheduled time
    3 h; ?3 K6 E; H7 z1652707 ECW                METRICS       Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart
    # S, b6 v- M0 g' P% d: r9 g1654512 ECW                METRICS       Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart
    ; K  r$ h8 u- s  v% s8 I1668953 ECW                METRICS       IE11 Swedish only: Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart( d( f0 J) m) ^8 D4 T9 ]1 b. {6 R' ^
    1677443 ECW                METRICS       Queued up metric packets on Pulse server are not processed if there are any packets related to a deleted project
    1 Z; e5 u) O! l  B- i4 w% \1663676 F2B                PACKAGERXL    Physical net name (PNN) errors in the log file
    * B* @7 ]: b2 o0 K: \4 L% [2 Z3 c1669583 GRE                DETAIL        AiDT always fails push when there is a connect shape attached to the cline being tuned
    0 ~" P% X; n, X3 m8 ]1686350 INSTALLATION       SPB           InstallDiagnose fails to repair some errors0 j9 ~; ~* g* z$ w
    1672369 PCB_LIBRARIAN      EXPLORER      Cannot create a New library build in Library Explorer.
    : ], I3 G# h1 n6 o+ a1631034 PSPICE             ENVIRONMENT   When simulating the design in release 17.2, Capture crashes but works with release 16.6
    ; o$ t2 D* G7 n. A' q# w% a8 R- A; Q1648284 PSPICE             ENVIRONMENT   PSpice project crashes when a design is opened in release 17.2
    ( U; P3 A, V+ N$ q1663336 PSPICE             MODELEDITOR   Ibis translation not supporting paths with spaces$ K7 ]3 Z$ m3 J9 }2 R6 p$ l; U2 t
    1679376 SIG_EXPLORER       OTHER         Topology created in OrCAD PCB SI license cannot be reopened with the same license$ W# {9 \* P4 ^1 K2 F1 a
    1666484 SIP_LAYOUT         CROSS_SECTION On converting a design from release 16.6 to release 17.2, a Dielectric thickness of ‘0.2032’ is added to another layer.# i% L1 y+ ^! C. C: A& C* O
    1687988 SIP_LAYOUT         DIE_GENERATOR 'compose die from geometry' does not retain the user-defined padstack name
    ; K  u/ g; y$ `4 p5 F$ I3 i1 [  G1715016 SIP_LAYOUT         DIE_GENERATOR Using Die Text-In wizard to replace a die reconnects wire bonds to the wrong die in stack-up, [$ d( u1 ^# j5 f) y3 Z, i3 ^
    1620601 SIP_LAYOUT         MANUFACTURING Need the ability to create LINES with round end caps in the same way as the LINES appear in the database5 R2 E" s  B; H! ^! f
    1705963 SIP_LAYOUT         PADSTACK_EDIT Pad Designer: "None" changing spontaneously into "Circle 0.000" in a pad stack definition and unable to save
    0 c) B1 f" z* u# Y, ?/ z+ K0 r3 j, R( W1713767 SIP_LAYOUT         REPORTS       Reports in release 17.2 for the Verilog Port Name are adding incorrect data that was not found in release 16.6# r0 L2 h* m9 y5 c; Q" m
    1696218 SIP_LAYOUT         SKILL         SiP Layout crashes on reassigning nets
    6 b$ N. V- R! q- X2 H$ [/ J# z% v1695885 SIP_LAYOUT         UI_GENERAL    Visibility Tab check box: unchecked "All" disables access to "Shp" check box, Z& ]$ `% e7 S
    1639838 SIP_RF             DIEEXPORT     Enhance the error message, SIP-1507, to include that overlapping pins within tolerance are included during die export; `& n- q5 [0 M# ^6 ^- r. B
    1653894 SIP_RF             DIEEXPORT     Redundant error message for die export, when view name is other than "layout"
    " b! w' z$ u- W1681332 SIP_RF             OTHER         Running die export causes Virtuoso to crash
    3 ]5 c. E) P8 d) `6 D1679336 SPECCTRA           LICENSING     Min/Max Propagation Delay cannot be routed by PCB Router using OrCAD PCB Designer Professional
    ' l" Z8 Q6 e8 `6 ?# J. a/ Z! _) x* R

    $ O! x$ ?' z# F  a# d8 l' m5 EFixed CCRs: SPB 17.2 HF015
    # o3 N5 F; z2 `8 K1 @03-16-2017
    4 I. C8 K3 j( b4 M========================================================================================================================================================
    ' f- h. g( o) P+ l# OCCRID   Product            ProductLevel2 Title
    6 _1 ?) r5 h# ^; b========================================================================================================================================================
    + W' l. Q' |$ Y( d1653366 ALLEGRO_EDITOR     INTERFACES    Unable to attach step model to symbol$ F7 o2 y' ^$ L1 o$ b, J
    1671760 ALLEGRO_EDITOR     INTERFACES    Step package mapping window unable to display step model* G5 }* f% h. z$ G% O8 ]' x0 @
    1706879 ALLEGRO_EDITOR     MANUFACT      Trace gets moved to dielectric layer after using the Gloss function$ ?: x, I1 t- q3 s- C& Y8 G7 b$ g0 ]
    1708685 ALLEGRO_EDITOR     MANUFACT      Incomplete ncdrill holes data in drl file& y% v+ P& i4 q8 G1 {" H
    1712057 ALLEGRO_EDITOR     PAD_EDITOR    Changing text size and restarting Padstack Editor results in incorrectly scaled forms
    1 r$ A& @/ e' ]7 `- M/ W7 s1709335 ALLEGRO_EDITOR     SCHEM_FTB     Cannot import netlist from attached design
    $ E( X6 m# U2 h% c  z9 ]- N1687329 ALLEGRO_EDITOR     SHAPE         Shape is not voiding uniformly when component is rotated in 30 degrees
    9 T+ l: r0 u! R3 n: m' l1698539 ALLEGRO_EDITOR     SHAPE         A thin shape is left when dv_fixfullcontact is enabled.
    - I% z$ R: t& y4 h+ O3 |& a- ?1620210 ALLEGRO_EDITOR     UI_GENERAL    Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously+ J+ e4 A9 Z- G5 f9 X4 P" B3 l8 I
    1687819 ALLEGRO_EDITOR     UI_GENERAL    Change in Region and Language settings of Windows impacts decimal character in Padstack Editor( c9 N' \; [4 C8 a2 M
    1699326 ALLEGRO_EDITOR     UI_GENERAL    Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not. H6 i" y5 g$ ]
    1711341 ALLEGRO_EDITOR     UI_GENERAL    Incorrect pad size in Padstack Editor when the German regional settings are used
    ( o* c0 z1 e6 Z! D" K3 x1712496 ALLEGRO_EDITOR     UI_GENERAL    Padstack Editor shows incorrect values when using comma and 3 decimal places
    % a7 l6 g8 D9 o' q. H1714744 ALLEGRO_EDITOR     UI_GENERAL    Using comma instead of dot as integer separator results in incorrect diameter value- ^# N2 W% g( B9 O# `! ]( I! o
    1715714 ALLEGRO_EDITOR     UI_GENERAL    If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
    # F7 P, s0 A, X) W, D$ }% x; n1713292 APD                WIREBOND      Allegro Package Designer crashes when adding wire to a die pad
    , n  {$ }3 R5 {) @) ]1710973 ASDA               PACKAGER      Unable to export Allegro SDA project to PCB Layout
    / m& Y, Y8 b* [! ]7 f1698697 CONCEPT_HDL        COPY_PROJECT  Copy project corrupts the .dcf file; `8 \7 Q, Z! m
    1705401 CONCEPT_HDL        CORE          Alignment issues while pasting signal names in 16.6 Hotfix 084, _8 b$ v6 [2 f, V/ A; ?
    1707116 CONCEPT_HDL        CORE          SIG_NAME is placed on non-grid position
    6 |: W% u  G$ o# m6 v7 L1710486 CONCEPT_HDL        CORE          Rename Signal places sig_name at an incorrect position for an unnamed net( d* }: q, q2 {; p& N; G
    1667786 CONSTRAINT_MGR     XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer0 S  L2 N( p. }
    1709508 SIG_INTEGRITY      REPORTS       Allegro Sigrity SI crashes when running a reflection simulation& @& G+ C2 x# A$ t+ Q$ A' V
    1710097 SIP_LAYOUT         DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
    0 C% G8 t  m2 J+ A6 U0 h* J1712964 SIP_LAYOUT         SYMBOL        SiP Layout crashes when using Renumber Pins in Symbol Edit application mode
    % x+ u/ I% }7 \0 a7 i. y
    : ~) [3 q" M, N2 p
    8 L, x, q# k1 z. ?: R8 Q# AFixed CCRs: SPB 17.2 HF014
    # [/ S  B, F9 n- C03-4-2017
    ' \! u; z' e9 r: ~  J4 E, C========================================================================================================================================================
    ( X- V2 N5 n0 t! ]7 sCCRID   Product            ProductLevel2 Title
    - e, b$ s$ s9 {' T% E  H========================================================================================================================================================! A* @. h3 H8 W! }$ J
    1691828 ADW                COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships
    / \1 T' A0 C) a1700963 ALLEGRO_EDITOR     DATABASE      Running the 'slide' command results in the cline segment losing connectivity* h4 ~# _" l( m& X
    1685502 ALLEGRO_EDITOR     INTERFACES    The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-2682 n3 V1 j( y# m# ^
    1644643 ALLEGRO_EDITOR     MANUFACT      The NC drill legend does not match the drill customization data
    $ G& I7 d% q: D% z/ L1 f; R6 Z( l' R1700557 ALLEGRO_EDITOR     MANUFACT      DXF output does not contain drill figure data$ t, ^" e6 _3 }# q
    1660252 ALLEGRO_EDITOR     NC            NC Drill file generated with errors: ?) y! v% J! K& `
    1677775 ALLEGRO_EDITOR     NC            Merging of drills not retained in database.9 a) m$ E' A) {8 U
    1701554 ALLEGRO_EDITOR     SHAPE         Shape spacing clearance is not updated unless the shape vertex is deleted
    # W1 `: d0 s6 \/ g1 W1704669 ALLEGRO_EDITOR     SHAPE         Route Keepin is not getting created at a specific location
    ; k7 H5 n+ m# y/ O) O1 ~3 `; ?- p1685995 ALLEGRO_EDITOR     SKILL         All film sequence numbers are returned as 0 when using the SKILL function axlGetParam
    6 E6 ~1 s. a7 F  {9 E; \1621336 ALLEGRO_EDITOR     UI_GENERAL    Changing the color visibility does not refresh the screen color immediately8 a8 w& |+ W; `2 s
    1668817 ALLEGRO_EDITOR     UI_GENERAL    Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6! L$ g# g4 h) W, ?3 w
    1671268 ALLEGRO_EDITOR     UI_GENERAL    Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one
    & P' j2 W* w" B4 K1690691 ALLEGRO_EDITOR     UI_GENERAL    Reports not generating if the 'allegro_html_qt' environment variable is disabled
    - t; D4 t0 T: f3 k, c3 v8 E, a1709903 ALLEGRO_EDITOR     UI_GENERAL    Toggling layer visibility does not change the display until the mouse pointer is moved
    % g& M. ~+ ~" V8 Q1647596 APD                EXPORT_DATA   Allegro Package Designer crashes when trying to export board-level components& @) M  y1 Q/ N) h) f5 j" }
    1688035 APD                OTHER         Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers
    ; U* E! K& y6 z# e0 z0 |' `. h: i0 l( t1690777 CONCEPT_HDL        CHECKPLUS     Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase) Y* t( A8 w/ \
    1695987 CONCEPT_HDL        CORE          $PN placement in DE-HDL during part development is not following mouse placement8 c) Z% F. b3 ?, h, t
    1700873 CONCEPT_HDL        CORE          With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message2 W& o; F3 @" g3 H+ n1 \* d
    1702703 CONCEPT_HDL        CORE          Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011! H# T( g+ x" s9 {2 ^# m' K
    1705999 CONCEPT_HDL        CORE          Signal naming is not working correctly in SPB 17.23 p$ p6 i" E$ }( S, U
    1677489 CONCEPT_HDL        CREFER        CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers0 x$ T  d2 s; d2 Z5 }
    1698259 CONSTRAINT_MGR     CONCEPT_HDL   Unstable $LOCATION property in release 17.2-2016
    - C2 b! B5 M+ Q7 s! m9 x) B1702537 CONSTRAINT_MGR     CONCEPT_HDL   ECSet mapping errors reported after removing the signal models on an upreved design
    ) H" L  B0 g! b& V1703981 CONSTRAINT_MGR     TECHFILE      Importing a technology file (.tcf) results in packaging errors
    9 G% p  T. [4 E9 d6 F9 W1673115 ECW                INTEGRATION   Import from external data sources (Integrations) truncates input values to 128 characters+ m, m# y1 d6 b5 G3 S
    1699395 FSP                FPGA_SUPPORT  Selecting a QSF part name in the FPGA Properties window crashes FSP
    * A/ R) O$ i) z; {5 m' G1704353 INSTALLATION       DOWNLOAD_MGR  Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'/ r! o/ O* P5 M6 G! x$ m
    1705265 INSTALLATION       DOWNLOAD_MGR  Problem installing OrCAD Library Builder from Download Manager
    $ z; f" P. R9 S7 T" r9 Q  ~1 ^9 G$ B1646635 PDN_ANALYSIS       PCB_PI        PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script
    ' ]1 {! I4 O, Q9 a, ]; I  Q# s6 h9 d
    8 q& ]0 R$ G7 c; F. B( n; W. J
    8 |8 I4 k- ~1 u7 `. ^( oFixed CCRs: SPB 17.2 HF013$ B+ Q& x- ]# H  R2 J& B
    02-17-2017
    - t$ g% R6 P' N2 `========================================================================================================================================================
    4 a; N9 ~) P6 I3 w4 kCCRID   Product            ProductLevel2 Title4 c, ?0 ?. c1 t7 ]6 q" E; N
    ========================================================================================================================================================1 G% @) a& U/ A! j  m9 q
    1567741 ADW                COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm
    " u8 i3 p6 \" [$ a- n( V1697109 ALLEGRO_EDITOR     ARTWORK       Artwork not showing padstacks for the soldermask layer
    / }/ g" a( ^. K- H9 c, Y5 v% G1682297 ALLEGRO_EDITOR     DATABASE      Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
    2 m2 W5 j3 S: r9 J, I1697309 ALLEGRO_EDITOR     DATABASE      PCB Editor 17.2 uprev changes NC pins from non-plated to plated! r! q2 L5 U" |
    1698624 ALLEGRO_EDITOR     DATABASE      Opening 16.6 board in 17.2 converts non-plated holes to plated5 B- {* J2 f* U
    1697092 ALLEGRO_EDITOR     OTHER         axlDBViaStack crashes PCB Editor session and corrupts the board
    7 |4 g  f# U7 r2 ^2 ~# i  c1687819 ALLEGRO_EDITOR     UI_GENERAL    Change in Region and Language settings of Windows impacts decimal character in Padstack Editor3 H9 d1 K/ w2 E: x5 [
    1696637 ALLEGRO_EDITOR     UI_GENERAL    Padstack Editor uses Region and Language settings for the decimal symbol% i+ s3 ?( d) |# g
    1699326 ALLEGRO_EDITOR     UI_GENERAL    Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not2 F6 y$ k4 r; w  B( p. C4 D
    1616138 ALTM_TRANSLATOR    PCB_EDITOR    Board file imported from third-party tool to PCB Editor has the shapes but not the components2 Z! K+ ~$ a: N9 @9 p6 G
    1666020 ALTM_TRANSLATOR    PCB_EDITOR    Board converted from a third-party tool to PCB Editor has missing components% u( K" w# p0 i- x  h$ X: j8 z
    1690448 CAPTURE            CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets( j" ?3 W( |: `9 _% x1 ]
    1690455 CAPTURE            CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets
    ! y6 P( r  S) Z. S$ X1684180 CONCEPT_HDL        CORE          Message should indicate that the user needs to reload the design after setting SET STICKY_OFF
    + @3 E* m! J- r) l6 h1695987 CONCEPT_HDL        CORE          $PN placement in DE-HDL during part development is not following mouse placement
    9 x5 U9 \( g& l6 v! O* N1688287 CONSTRAINT_MGR     DATABASE      PCB Editor crashing while adding a net to a net group.8 p$ O) |8 F& _* K. w* `: `- m
    1675013 ORBITIO            ALLEGRO_SIP_I Failed to import brd file. t, t9 O! q' P% ?: a& ]
    1698968 SIP_LAYOUT         3D_VIEWER     3D viewer shows keepin and not design outline.
    ! a: o5 i' l+ U1699884 SIP_LAYOUT         ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker
    9 P! U3 s9 B/ d& c- m- {& v/ Y  d1689969 SIP_LAYOUT         DIE_EDITOR    SiP Layout crashes when moving dies using relative coordinates
    % `+ A3 A; l8 F0 b* J6 E1696239 SIP_LAYOUT         DIE_EDITOR    When using the Die-stack Editor to move and stretch wires, SiP Layout crashes
    . j; D8 ?; K- U1695372 SIP_LAYOUT         REPORTS       Running the Metal Usage reports fails on the Primary side.& c  G8 Z0 o3 t" Z9 S) N7 j

    / H- R/ V) x/ ^0 D: v" N% U0 V6 d7 g. f$ N' E' r
    Fixed CCRs: SPB 17.2 HF012
    ' S& E; Y, ^4 ^3 ^& c2 R/ s& J02-3-2017
    9 J" ~/ F% g" O% b===================================================================================================================================# A8 l5 B/ f1 X! H7 t( Y7 c3 `
    CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
    * L/ V6 e+ z, X- T; i- H===================================================================================================================================7 [- t9 R# z# v2 A0 D8 w( R
    1659641 ADW            FLOW_MGR         Documentation Editor does not invoke when a .brd file is opened from EDM Flow Manager* L! E/ i7 W  s  b8 ?; T
    1661632 CONCEPT_HDL    OTHER            Page skipped in DE-HDL when navigating using the Page Up and Page Down keys4 {7 Q# [8 z# E) W# x/ k, t- g
    1668325 ALLEGRO_EDITOR SHAPE            Updating shapes to smooth creates erratic voids.
    . J6 ~) X/ b  m( ^1 Z6 O+ F) B7 l( y1670082 CONSTRAINT_MGR ANALYSIS         Inconsistency in Constraint Analysis Modes - Electrical in OrCAD PCB Designer Professional 17.28 r: H3 h* X5 L7 ?! P* U; \: K# e' h
    1674231 ECW            METRICS          Re-upload for local metric packets that failed on first attempt is not working when Pulse server name contains dots; _, M; S/ A# a3 T% w% p
    1674338 APD            SHAPE            Shape is not clearing slivers that are smaller than the 'Minimum aperture for gap width' of '18 um'% z# t, z% Z* W' B; N7 ]
    1675677 ADW            DBEDITOR         DBeditor Issue-Searching by using the Properties method
    3 Y" D$ M: n* w$ K2 w5 R, T1677489 CONCEPT_HDL    CREFER           CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers5 H: @8 i0 d9 U
    1679351 ALLEGRO_EDITOR REPORTS          Missing Fillets Report is not showing missing fillets on the bottom layer+ q0 l% L) O4 ~& Y9 n2 l
    1681002 ALLEGRO_EDITOR OTHER            17.2 STEP output fails to produce an output similar to 16.6
    2 f* E0 G0 f- U) x1682287 ALLEGRO_EDITOR EDIT_ETCH        Auto-interactive Delay tune (AiDT) rips lines that have been routed) Y  p" Z( n5 \) p( P) M( {
    1682900 ALLEGRO_EDITOR PLACEMENT        Moving a symbol by snapping to segment vertex with 17.2 Hotfix 009 crashes PCB Editor- n$ n6 i7 l- P
    1684117 CONCEPT_HDL    CONSTRAINT_MGR   Property deleted from Constraint Manager is not getting updated in the DE-HDL canvas% B5 S$ Z8 l. D1 [0 o9 e2 |0 g( t2 A
    1686803 ALLEGRO_EDITOR INTERFACES       PCB Editor crashes if the 'ipc2581_group_drills' variable is set.4 P8 q2 c* m$ z5 A3 i1 n
    1687816 ALLEGRO_EDITOR PLOTTING         Export PDF Vector text option does not work
    # ^9 A2 x3 N$ ^1688287 CONSTRAINT_MGR DATABASE         PCB Editor crashing while adding a net to a net group.
    ' l% d, u6 B, o! O, I1689881 ALLEGRO_EDITOR DFA              Record and replay script for loading DFA spreadsheet not working
    & m  c' U8 y# M/ s/ x1690958 ALLEGRO_EDITOR SKILL            SKILL command axlDBDelLock is not working as explained in the documentation
    7 O0 Z& m& p) v0 J! ], ?! ?1692166 APD            DATABASE         DB Doctor returns 'ERROR(SPMHDB-252): A corrupt database pointer was detected' for a specific design
    6 I8 c1 g9 A1 L1 z1693431 ALLEGRO_EDITOR SKILL            Running axlXSectionModify and axlXSectionSet results in warnings and corrupts multi-zone cross-section
    : H0 f: W" f1 z+ x0 a) R. _1693719 ALLEGRO_EDITOR MANUFACT         Incorrect suppressed holes information in the drill file created
    + z0 T6 \3 N7 [; S! _8 g1693846 ALLEGRO_EDITOR MANUFACT         PCB Editor crashes when running the gloss command# @/ m+ \* W% J! d( S% X
    1694151 CONCEPT_HDL    CORE             Rename Signal for unnamed net added the sig_name at the incorrect position with small text size.0 ~* w. j- a9 \1 Z
    1694867 ALLEGRO_EDITOR SHAPE            Void is deleted by the shape merge command. {5 |& m# h* Z" d) s2 D% N
    1695131 ALLEGRO_EDITOR SKILL            PCB Editor crashes when using the axlSpreadsheetDefineCell SKILL function
    ! Z5 _( v# H- m- r4 v: Y% U
    9 @% x, m; O. [6 R1 k
    6 l, P( B( x" v& I2 ]) d* `: \Fixed CCRs: SPB 17.2 HF011
    8 r; l/ t7 j( z1 `/ t2 O3 l01-20-20176 T' v. c3 S* Y1 }3 O4 A' d* Z
    ===================================================================================================================================4 ^$ X1 P' E" ?9 \/ B" d
    CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
    0 T9 c% \5 C! X4 N===================================================================================================================================4 O4 s. `, ~0 U( T0 P* ]
    1618986 CONCEPT_HDL    CORE             Information required about the DONT_FORCE_ORIGIN_ONGRID directive
    $ w! [" u6 a% W- `1629696 PSPICE         PROBE            After successfully exporting traces to csv, PSpice crashes on a subsequent attempt to export traces0 T1 u2 Q) _9 F( j1 ?, ], v
    1667213 CAPTURE        NETLIST_ALLEGRO  Tools - Create Netlist stops responding on Windows10+ S: K0 E8 p, V+ Z5 a
    1667599 APD            OTHER            Wire Bond operations taking longer than expected to complete
    9 r' Z- f6 |& b0 q& j1667678 MODEL_EDITOR   PARSE            Signal model assignment creates ESpice models that do not pass Model Integrity checks
    ! ?, i& N, W! r$ V. W+ q' Y2 E2 z7 i) N1670120 ALLEGRO_EDITOR UI_GENERAL       In 17.2, the Static Phase meter shows up in the middle of the screen instead of the lower right corner! T5 H& F/ S+ p0 T
    1670927 ALLEGRO_EDITOR DRAFTING         Using zcopy to create a Route Keepin results in database errors% R- P2 l2 |2 P+ e+ W# ]
    1675359 ALLEGRO_EDITOR ARTWORK          Subclass ETCH/WIRE is added to artwork definition though the visibility of 'ALL Layers' is turned off! |3 s: C3 s/ u, ~2 ?
    1675619 ALLEGRO_EDITOR MANUFACT         Differences observed in IPC-D-356A between releases 16.6 and 17.2/ M" G3 `! C& h. H% n" U
    1676161 ADW            FLOW_MGR         Opening a project in SPB 17.2 flags the 'Operation load JNI code failed' error
    % B/ |9 U8 N. M# N0 ]/ S1677405 CONCEPT_HDL    OTHER            When moving a wire with a dot, the dot is not removed directly
    - ?4 [6 S- n. o1678061 PSPICE         SLPS             Simulating an SLPS co-simulation with a Fixed-step solver with a value smaller than 1E-4 results in a crash/ w& b: c4 \! j; Q# [& E' s
    1679347 PSPICE         SLPS             SLPS crashes when co-simulating without opening OrCAD Capture or PSpice3 I. Q% |# U# V- _; w" Y- }
    1680113 ALLEGRO_EDITOR SHAPE            Irregular void created on dynamic shapes
    / E6 _4 I; J$ \( K3 b- B# t1680802 ALLEGRO_EDITOR DATABASE         A 16.3 database locked with disabled export of design data should be view only in 16.6
    ' i7 j7 i" g7 [4 I$ L1681129 ALLEGRO_EDITOR DATABASE         Match Groups in the DE-HDL design are not getting transferred to the board file( p) ]. D3 b% X% l9 X# T
    1681514 ALLEGRO_EDITOR UI_GENERAL       Opening the Dynamic Shapes State report hangs PCB Editor in 17.2 Hotfix 009: g2 @' k/ Y/ E5 ]. \, }
    1681727 CAPTURE        NETGROUPS        In 17.2, Capture crashes when closing a design that has assigned Netgroups7 z5 {8 N4 M3 `4 P# \7 Q8 j! N
    1682297 ALLEGRO_EDITOR DATABASE         Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
    , f7 X% K, c. h- ?( q1682447 CONSTRAINT_MGR CONCEPT_HDL      Extraction issue on differential pairs in the given design
    ) E3 [6 \2 g+ ?" B% Y1682454 CONSTRAINT_MGR CONCEPT_HDL      Design with NO_XNET_CONNECTION property on parts is exported to PCB Editor; many other components get the property
    9 \" W+ K5 T6 T0 q7 T' I1682469 CONSTRAINT_MGR CONCEPT_HDL      Creating a CSet from an existing CSet leads to invalid CSet names in Constraint Manager connected to DE-HDL
    ; t$ ?% o' Q5 U8 j1 i6 G, }3 K. |( F1683919 ECW            TDO-SHAREPOINT   Site Minder integration for login from TDA not working after SSL certificate update% N# S2 ]/ f/ y# J2 _8 H
    1684111 ALLEGRO_EDITOR SHAPE            Dynamic Shape not voiding overlapped static shape; {  w3 ?; i0 \
    1684508 ALLEGRO_EDITOR AUTOVOID         Allegro PCB Editor stops responding when deleting a via9 s6 ]+ M" o) Y- y! }- b
    1685540 ALLEGRO_EDITOR OTHER            If text is attached to an object, the object is also printed in the PDF
    $ w! E1 N2 W. K8 o+ S1685810 ALLEGRO_EDITOR PAD_EDITOR       In 17.2, Padstack Editor does not save adjacent layer information for BOTTOM pads* A* m0 n( a' q0 s5 s) G9 o  q
    1685986 ALLEGRO_EDITOR PADS_IN          PADS Translator-generated output shows incorrect unit for the soldermask oversize option
    + S! }( U  ]4 Z' K; h) h1686127 ALLEGRO_EDITOR SHAPE            The void of shape missed in artwork.
    ' Z% V- p( k8 z4 G9 L; ^1686791 ALLEGRO_EDITOR OTHER            Searchable property unavailable on bottom layer pins in the generated PDF
      O$ o1 j1 A0 ?8 q; h. Q5 ~( M. Q9 w4 p1 ~6 L4 C

    , R, t2 B  y$ F/ |. f( e6 p/ P2 vFixed CCRs: SPB 17.2 HF010
    3 i% s" [, q& l2 a5 [8 ^& {01-6-2017 1 c4 E4 |2 _0 t# I0 o- \' H  q$ \
    ===================================================================================================================================
    % E+ B! k- H/ w1 m3 n1 gCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
    6 P/ G  B3 o) d( Q===================================================================================================================================4 `% S1 F" F+ b
    1524700 F2B            DESIGNVARI       Variant file cannot be loaded
    / Y' z9 ^% ^5 g# H0 w0 u1597787 CONCEPT_HDL    MARKERS          Save As in Marker dialog causes DE-HDL to crash  G. f. Q6 |6 c. O
    1599843 CONCEPT_HDL    INTERFACE_DESIGN Moving NG causes extra elements added to it to move# X9 `7 t, y9 n1 ^
    1620017 F2B            PACKAGERXL       Packager Fails with ERROR(SPCOPK-1053) when $PART_NUMBER property for components has a value
    . T  F5 L) y6 e: _4 i1632977 CONCEPT_HDL    INTERFACE_DESIGN Connectivity error when moving NG members% V) |1 C$ \, M- k; w" |$ \
    1635941 ALLEGRO_EDITOR INTERFACES       Shape created by IPC 2581 for negative film is not same as the shape on board3 E- q* }! m9 Y7 q
    1656357 CONCEPT_HDL    CORE             Pasting a signal name across pages causes the name to overlap with the wire segment
    # J: T! @$ ~, g0 a: M( E9 J1657346 CONCEPT_HDL    PDF              Wire Pattern set to two-dot chain line in a schematic appears as a solid line in the PDF output( X& t. Z5 J( l3 S  N4 D$ x
    1658048 ALLEGRO_EDITOR COLOR            color_lastgroup is not working in SPB 17.2& }% _; m: U3 W4 M- m$ V
    1658874 CONCEPT_HDL    CORE             'Insert (n) Pages' command does not work when the CONFIRM_WRITE directive is ON
    % y7 p5 x7 J- ?  [1659030 RF_PCB         LIBRARY          Offset is not calculated from the center if using negative values for input pins when placing MSOP symbols
    " i4 ?5 Z7 G! ^$ [4 B1659097 CONCEPT_HDL    CORE             Mouse stroke fails to be enabled on startup with left mouse button (LMB)6 `2 l1 q5 a* Q2 }7 s
    1659532 CONCEPT_HDL    CORE             About Import Design command with the CONFIRM_WRITE directive9 t# H" O: N  V) d
    1659929 CONSTRAINT_MGR UI_FORMS         Using wildcards in filename for Import Constraints does not work in 17.2( H6 n1 l: N" s* g
    1660200 ALLEGRO_EDITOR UI_GENERAL       Move by Sym Pin # edit box is obfuscated+ [/ G9 N$ K. D, R+ t9 w
    1662821 ALLEGRO_EDITOR OTHER            Cross section chart does not show stack vias in 17.2
    # @7 L( m1 u7 g; p' F5 F: ]8 Z- U1663641 CONCEPT_HDL    COPY_PROJECT     File - Copy Project in Project Manager creates two designs if there are dashes in the design name
    ; C9 [9 f6 |" `' l: E* T& E+ J1665652 ALLEGRO_EDITOR SHAPE            Critical fillet and shape issues in 17.25 D- _4 ?4 n# A8 A2 Q( Z4 C$ r
    1665918 CONCEPT_HDL    CHECKPLUS        Error (100) Program Internal Error 'Create_flat_node' with checkplus run6 D% H) i9 G3 C9 m2 n9 ~3 O+ |
    1667056 ASI_PI         GUI              Power Feasibility Editor does not list capacitors connected to selected nets/parts- b2 J7 l  M' [  x- w$ p4 q
    1668137 ALLEGRO_EDITOR SCRIPTS          PCB Editor crashing when running Script Replay
    8 k& @( n+ s4 K4 d1669651 CONCEPT_HDL    CREFER           CreferHDL values are invisible( A% C! x  K7 ^* P8 y& V
    1669707 CONCEPT_HDL    CORE             Pin numbers not visible on the canvas after replacing a part with the same symbol but a different part property0 M. i' n0 M$ S  d5 N+ O
    1670339 ALLEGRO_EDITOR OTHER            Small shapes defined on the mechanical symbol Board Geometry - Outline are not converted to the Cutout subclass.! S  G7 c* S& a. |
    1670564 ALLEGRO_EDITOR MANUFACT         Exported Gerber file cannot be imported in brd  a3 J/ x0 D. K4 {
    1670687 ALLEGRO_EDITOR NC               nclegend.log reports missing columns which are present in the NC Legend8 t/ v5 T/ P  u
    1670811 PSPICE         AA_MC            AA MC Plot settings options9 l0 I4 b1 I8 \: X" r, f1 B% `. u( a- N0 Q
    1671428 ALLEGRO_EDITOR UI_FORMS         Display origin checkbox position changes in Step Mapping dialog& F( ]: x6 X! @
    1671728 CONCEPT_HDL    CORE             Option requested to reload preferred_projects.txt without re-opening DE-HDL7 _8 g# r% U0 h9 `/ D* {8 N# h
    1671901 ALLEGRO_EDITOR UI_GENERAL       Toolbar and menus are locked or greyed out5 E/ O) {3 M! M' ~, s
    1672477 ALLEGRO_EDITOR DRC_CONSTR       DRC generated by Dynamic fillets
    ; n. G- h8 v6 \/ p$ Y8 J! n1673499 ALLEGRO_EDITOR DATABASE         Drill table title issues of backdrill designs in 17.22 B4 B, k9 N% J5 V
    1673681 ALLEGRO_EDITOR UI_GENERAL       F1 for Help not working in PCB Editor 17.2, g: P" {' P8 o
    1675499 ALLEGRO_EDITOR DATABASE         Running the Gloss command causes PCB Editor to crash...
    ( Z& ^# {$ s% l5 W: s  C9 ?1676480 ALLEGRO_EDITOR MANUFACT         Creating Variant Assy_Bot Drawing showing Variant Assy Top Drawing0 K3 b7 N* M7 e% M
    1677431 ALLEGRO_EDITOR DATABASE         Get ERROR(SPMHA1-141): Invalid sector row. Contact cadence customer support when opening DRA File
    4 q9 f  p' `. L# ^* z1 p5 z1677651 CONSTRAINT_MGR CONCEPT_HDL      DE-HDL crash on design after successful packaging
    # J" X  u( n) p% D  h, k1677672 CONCEPT_HDL    CORE             Whitespaces in URL links are not resolved correctly on Linux with Firefox( @* ~5 X8 }! I; Z. x6 f, U2 j5 m
    1680837 ALLEGRO_EDITOR SHAPE            Updating the shape makes the shape disconnect from Thru pins of same net
    + U; F  u% C+ D  @1681059 ALLEGRO_EDITOR SHAPE            Shape Voiding using DV_SQUARECORNERS environmental variable does not always produce voids with square corners.
    $ |1 E. @- P7 _% J9 w6 a: q# @0 o1682312 SIG_INTEGRITY  LICENSING        Allegro Sigrity SI/PI Product Choices window is blank after installing 17.2-s009 hotfix
    * Z5 R: c, b( a2 f! f* J& ~  d
    9 H8 I* H/ s: I) y& s( e* d& o8 f) Y4 E+ r0 z- S  r5 p
    Fixed CCRs: SPB 17.2 HF009
    , e: _2 v  x" _+ T12-8-2016
    7 u# }8 Y' H; R: n8 l===================================================================================================================================
    0 \# T0 \! H5 A  ^% NCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
      W2 _' \1 P* x- q===================================================================================================================================
    1 r  \8 ?) r# \5 W1212577 PSPICE         MODELEDITOR      IBIS translation fails without any information in log file
    ! M; |2 v6 D3 T7 p8 I1311687 PSPICE         MODELEDITOR      Timeout error while translating IBIS model
    % R( Z- x/ t$ q6 Q: x* `: a1327174 PSPICE         MODELEDITOR      Log file should list error details during IBIS Translation
    ; y' V" I" ], g  e1499665 ALLEGRO_EDITOR INTERACTIV       Offset Move depends on move setting.
    # V1 ]* R9 }- L; ?1516093 ALLEGRO_EDITOR PADS_IN          Pads library translator does not translate slot orientation
    6 i# ^, }; f! n- e2 n; {1565795 ALLEGRO_EDITOR UI_GENERAL       Search does not work in the Defined Variables window$ @6 h' n+ o+ u3 M
    1568817 ALLEGRO_EDITOR UI_GENERAL       Padstack editor not accepting comma as decimal separator with system locale set as LANG ru_RU.UTF-8% w1 H! F+ ]) X  R, j
    1569272 ALLEGRO_EDITOR PLACEMENT        Get the error message 'E- (SPMHDB-394): Placement cannot be completed ... 'after creating Place Replicate circuit; M$ X) j" z. p4 I8 i" B
    1577379 CONCEPT_HDL    CORE             Packager-XL gives different results when run from DE-HDL and ADW Flow Manager4 {3 v: O5 ?) [% W4 |9 n- r
    1578523 ALLEGRO_EDITOR PAD_EDITOR       Library Padstack Browser does not refresh preview
    9 L9 M8 }7 e: z! |1578533 ALLEGRO_EDITOR PAD_EDITOR       New Padstack Editor does not automatically update the geometry
    0 Q# Q3 y% I5 Q: Z) J1581129 CONSTRAINT_MGR UI_FORMS         Unable to dock the Electrical worksheet in Constraint Manager
    6 b" l9 m9 t$ m0 R' r" t( c/ o1582103 ALLEGRO_EDITOR PADS_IN          PADS Library Import creates additional filled shape not present in source data) m4 @: g3 ^# D- {0 _4 {
    1591027 ADW            LIBDISTRIBUTION  Library Distribution redistributes previously distributed models& o4 J0 q# |1 C1 P/ U9 v. j0 p
    1592026 CIS            VIEW_DATABASE_PA View database part does not work from schematic pages of an externally referenced design
    0 `: G) S( y2 q1593389 CAPTURE        GEN_BOM          Include files in Tools - BOM not working
    . t! `/ a4 A! K8 i, z5 C6 G1593404 SIP_LAYOUT     EDIT_ETCH        Slide command moves via toward the object# _' t; `/ s; i
    1595872 CIS            PART_MANAGER     Capture CIS Part Manager PCB Footprint update case-sensitivity issue- Z) a* v! ?5 E) }9 j$ A
    1596955 ALLEGRO_EDITOR EDIT_ETCH        Scribble mode is not working as per expectation.
    & L! U% ?3 q. R1 }5 `1600936 ALLEGRO_EDITOR INTERACTIV       Pin DataTips differ between 16.6 and 17.2! z- g$ T  v7 @# y% F8 |2 @( C" D
    1605961 ALLEGRO_EDITOR COLOR            Wildcards not working in the Filter Nets field of the Color Dialog window. `# Y( x4 S5 p! E' v5 G
    1606392 ALLEGRO_EDITOR PLACEMENT        Filmmask not shown when component is attached to cursor
    * f+ e) s: u% c" z$ C. g4 H3 X1607016 ADW            TDA              TDO crashes after LRM update during check-in hierarchy$ g2 ~& q4 [5 P
    1608059 CONCEPT_HDL    CREFER           Removing crefs from top-level design also removes .csb files from lower-level blocks
    " \6 Y1 ?' [) @) R- f2 @1608278 CAPTURE        OTHER            Crystal Reports: User is prompted for ODBC password to create a BOM report6 @) Z& q" T6 Q5 c
    1610377 CAPTURE        PROPERTY_EDITOR  Discrepancies between the NET_SPACING_TYPE property (or any other property) text and the actual property- C( M( s+ y8 A7 U
    1610456 ALLEGRO_EDITOR DATABASE         Strip design and selecting user defined subclasses results in database corruption.
    ; N1 P3 p8 X. [3 d: K" R! b1612793 CONCEPT_HDL    OTHER            Pattern-based auto-distribution of split symbols not working if there are spaces before commas
    0 \( H# x. c: e! y# d2 M4 \1613442 CONCEPT_HDL    CORE             Signal names are not horizontally centered when the wires are added using different methods. r0 I) y& [: H2 V
    1613559 ASDA           IMPORT_DEHDL_SHE custom variables from the BOM Tables are not getting imported, [$ H8 a1 T* s, g7 A; ~. M  k
    1614093 CONCEPT_HDL    CORE             Import Design window has artificial 64 char limit for path - prevents access to some locations
    / ~; V+ E2 Y  I3 q1614372 CONCEPT_HDL    EDIF300          OFFPAGE symbol is exported as PageBorder in EDIF300 schematic* ^+ Z) u/ D( e4 Q# h
    1615075 APD            LOGIC            Netlist-In wizard fails to import the net names, but gives a successful completion Info message$ M1 g+ G1 I  b$ X
    1616131 ALLEGRO_EDITOR PLACEMENT        While placing a module, the Mirror command in the right-click pop-up menu is not working! i% t% t0 j- }! c6 H+ p, {* F" V
    1617377 ALLEGRO_EDITOR UI_GENERAL       Visibility pane does not retain the correct layer view
    6 l; M; \4 }0 `( c; E# I1617404 ALLEGRO_EDITOR UI_GENERAL       axlUIMenuChange does not work as expected in 17.2
    ( d3 ~0 A4 P$ m+ L* u. h! o1619412 ALLEGRO_EDITOR INTERACTIV       Script to create new padstacks from existing padstack is putting in wrong values for a regular pad# s& F/ x; j# c5 u2 e% _; G8 H
    1621842 ALLEGRO_EDITOR PLACEMENT        mechanical symbol without placebound will not place in QuickPlace
    1 b& R' M3 x5 r( T/ K& n! L9 X3 L1621874 ASDA           PRINT            Print - Save as PDF uses the default printer options only" g  w& ?" [& \8 y
    1621887 ALLEGRO_EDITOR INTERACTIV       Getting a 'Could not satisfy the snap condition' message when using the Snap pick to option
    , K9 B0 ^: l4 w' }* F: Z7 f1622680 ALLEGRO_EDITOR PADS_IN          Import PADS fails with the 'ERROR: *NET* section found. Translation of netlist is not allowed.' message
    7 Q% ^% [; w2 d' U9 G6 d" f- P: s1623832 ADW            COMPONENT_BROWSE Incorrect part placement on schematic in Design Entry HDL 16.6-S073) G6 T1 ?+ w- l3 h% T
    1624813 CAPTURE        GENERAL          The Value property is always left aligned when placing a symbol on the schematic1 A' _& ?. V) x
    1624953 ALLEGRO_EDITOR UI_GENERAL       Custom views in 17.2 do not return to original+ J! B: o! |8 Y
    1625000 ASDA           CANVAS_EDIT      File - Save Project does not provide any indication of saving or progress bar
    5 c; U" e: {( j1625163 CONSTRAINT_MGR OTHER            There is no status for the analyze command in the Constraint Manager in 17.2
    " y# Y+ `2 P7 d: V& {# P6 ]5 ^9 S1626647 PSPICE         ENVIRONMENT      Capture crashes when loading a design with two hyphens in sim profile name
    , R" z& p7 f$ t; E3 e' ]/ }) W1628357 CONSTRAINT_MGR OTHER            Constraint Manager shows differences if exporting and importing constraints on the same board.
    % o3 n4 _0 p' o8 Z# ^# d1628409 ALLEGRO_EDITOR PAD_EDITOR       Pad Stack Editor does not remember last used directory
    / J0 [" m: l$ y1631443 CONCEPT_HDL    ERCDX            ERC reports warning due to lower-case value of some properties in chips.prt
    % O6 C' F5 V) o+ u1 J1632195 SCM            OTHER            'No known page border found' error in cref.log) y0 Z% {8 ^0 [9 e1 k  N7 [
    1632365 CONSTRAINT_MGR OTHER            Select command is disabled in the right-click pop-up menu from Constraint Manager in SPB 17.2" `; d# I; K2 O" F3 N7 i) ~' K
    1632462 ALLEGRO_EDITOR 3D_CANVAS        3D View (new) and PCB Editor crash when checking collisions( G+ O- ~  ~' j8 p+ R
    1632590 ALLEGRO_EDITOR 3D_CANVAS        PCB Editor crashes when 3D View is open and more 16.6 boards are opened
    & C' e0 O) f6 I* Q* G  s. f1633433 CONSTRAINT_MGR UI_FORMS         Expand - Collapse feature for multiple objects not working correctly
    / H- S! i  V4 d  x& z' x1633454 ADW            TDA              TDO crashes if DAO throws an exception% c( i$ e( o1 ?% i* k
    1633526 PSPICE         AA_PPLOT         Spaces in Simulation Profile cause error in Parametric Plotter' m0 Q8 c8 V& M9 u% I6 I
    1633608 ALLEGRO_EDITOR COLOR            'Retain objects custom color' should not enabled as default.
    & n, [# ], W; o1636216 ALLEGRO_EDITOR 3D_CANVAS        Interactive 3D canvas (Unsupported prototype) is not mapping step model when assigned to device) `* L) A% H' }; ]1 S
    1636899 ALLEGRO_EDITOR 3D_CANVAS        The new 3D Viewer is not taking the Package Height set on the PLACE_BOUND layer into account when displaying it.
      }( `: l/ o8 C8 E1638185 CAPTURE        DATABASE         Opening CIS database locks all part libraries none of which are open
    / ~- V4 c9 D8 q" O9 b1639409 ASDA           CANVAS_EDIT      Handling of MAKE_BASE property from DE-HDL designs imported into SDA
    * r( c2 ]: N1 w1639541 CONSTRAINT_MGR OTHER            PCB Editor 17.2 crashes when making changes in Constraint Manager2 B$ `, e! m  L- J  p
    1639613 APD            STREAM_IF        The stream out command has created sharp angles in the GDSII output file5 m2 Z0 M$ }+ ~2 P
    1640061 ASDA           HIERARCHY        Incorrect message received when invalid characters are specified for subdesign suffix' ]0 @6 \5 @/ k) l$ X: ?4 i) x
    1641118 F2B            DESIGNVARI       Some DNI parts are not identified in the variant view due to the BLOCK
    , ?% N6 ?. h3 f6 U: H7 m' z3 K8 t1641410 ASDA           CONSTRAINT_MANAG No errors or issues reported when incorrect topology is applied to a net or an Xnet
    # e2 R5 J  H( c( S2 ^1642891 CONSTRAINT_MGR CONCEPT_HDL      DE-HDL crashes randomly while working on Constraint Manager+ Z! L. K) Y# J* Z
    1643003 CAPTURE        PROJECT_MANAGER  Start page shows latest as S004 after installing S005
    8 Y1 q: y! d9 o+ _3 _2 q2 U0 h1643532 ALLEGRO_EDITOR OTHER            Strip design command fails to delete symbol text in the attached design
    5 f! X5 a, p1 `) z; V, e1645529 ASDA           CONSTRAINT_MANAG Unable to delete the diff pair from the nets
    - w" |# E1 S" I$ u0 v0 `  O& k+ x1645639 CONSTRAINT_MGR CONCEPT_HDL      DE-HDL crashes when the XNET_PINS property value has a trailing comma character
    7 B/ v/ I) V2 V1646354 CONSTRAINT_MGR CONCEPT_HDL      Cannot select Design Instance/Block Filter from the View menu in Constraint Manager6 ^7 b0 b" B( X  C) L
    1646612 PCB_LIBRARIAN  CORE             Generate Symbol option crashes Part Developer
    4 ^9 Q& C7 P2 F1 r" `5 I8 k1646932 ALLEGRO_EDITOR MANUFACT         Manufacture - Auto Rename Refdes keeps defaulting to Use Default Grid even if another is chosen
      [2 Y- E1 s$ v( L1647190 APD            REPORTS          'Sorted by Bond Finger' report shows incorrect wire bond connection
    ; p# z9 M! u  L, ]$ i" F1647673 ASDA           EXPORT_PCB       Two Physical folders are seen after installation of QIR
    # b2 z( |$ D; c' I( l8 Q1647729 ALLEGRO_EDITOR SKILL            axlFillet returns t when fillet is not added.
    9 R0 Y7 i: q$ ^, {( |# g0 C1647779 CONSTRAINT_MGR OTHER            'Software Version' in the cmDiffUtility viewer does not show the correct version
    6 L1 ]8 T9 n" O6 X2 ~; R9 o1647843 ALLEGRO_EDITOR ARTWORK          Misleading information in command window when artwork import fails
    * }6 k/ p8 ]5 I" v' P. ]( \2 O1648575 CAPTURE        OTHER            Suppress warning setting must be written in capture.ini file
    & }( H$ U! S# }! g1649060 CONSTRAINT_MGR CONCEPT_HDL      Rename dcfx to dcf process results in error in log file and dcf not updated" @5 O5 k2 Q( n# f- s
    1650106 ALLEGRO_EDITOR 3D_CANVAS        3D canvas rotates mirrored components in unmirrored angle$ Q* o$ r0 v3 s5 |
    1650238 SIP_LAYOUT     WIREBOND         When performing 'Adjust Min DRC', the reference bond finger should not move." V! R3 A. o8 i9 {* i, s" Z
    1650734 APD            SHAPE            Shape on L1 does not flood properly
    , Q& n; _( ~# d& X5 x- B6 f1650793 CONSTRAINT_MGR CONCEPT_HDL      Conflict of XNET_PINS definition between the chips and the SIGNAL_MODEL is not handled correctly
    : H& [$ q# y  c3 M) U1650801 ALLEGRO_EDITOR SCHEM_FTB        Running Export Physical with Update PCB enabled in Project Manager crashes netrev.exe2 s1 }/ ^# C6 j" c0 O
    1651011 ALLEGRO_EDITOR 3D_CANVAS        Interactive 3D viewer shows mechanical symbol mirrored
    + Y6 y- n5 d  [5 [  U' b& e1 {& I1651063 ALLEGRO_EDITOR CROSS_SECTION    Cross-section preview is incorrect
    & t. E' j! ~) K" L5 O0 F* E6 \1651066 ALLEGRO_EDITOR DATABASE         Pins not connecting even after running the Tools - Derive Connectivity command1 F! m/ s# ^5 C7 N4 t; S5 Y
    1651700 ALLEGRO_EDITOR SKILL            Running axlXSectionModify() on a layer removes the value of the material. z$ t. |) H" ]2 m! V8 i( K4 p1 u
    1651925 ALLEGRO_EDITOR ARTWORK          Searching for a macro in the artwork data file: Count for the macro does not match the actual count in the output) P$ q; ]: `2 C1 \6 l9 A
    1652230 CONCEPT_HDL    CORE             The master.tag and vlog004u.sir files are not created in the entity directory on saving symbols; Z% k! i+ a2 {. y4 c& @) d$ L4 _( V
    1653080 CONCEPT_HDL    ERCDX            Difference in results from SPB16.6 in 'erc.rpt' when logic_data is renamed as worklib in SPB17.2 on RHEL6.5
    6 y) z0 W( s! `' {2 r. j1653422 ADW            LIBIMPORT        Classifications not linked to a Part Number or Cell Model are removed during Library Import
    / r* [9 V5 Y& r: I, q; p! Z# P1 k( ?% m1653526 ALLEGRO_EDITOR DATABASE         Via padstack keepout is not displayed on the canvas when pads suppression is enabled.
    # `4 \3 q( |- i- [7 \7 x* i1653951 ALLEGRO_EDITOR CROSS_SECTION    Cross Section Editor changes lost despite selecting No to the 'All changes will be lost ...' message
    + N9 o0 [) I) G  F! l$ [1656224 ADW            FLOW_MGR         Copy Project wizard no longer allows dashes in the 'Name of new project folder' field8 F4 o' p* ^) P8 n
    1656581 ALLEGRO_EDITOR OTHER            PDF generated for layer with shape shows undesired voids if film is mirrored and Filled Shape is not selected
    % ?9 H: @+ D# O2 _1656608 APD            REPORTS          Incorrect calculation in the metal usage report
    - x" i4 ]% j$ q9 `4 K1656726 CONCEPT_HDL    CORE             Interface command always disabled in the Wire menu
    7 f, s1 \% l% \! s+ b6 l. I1656841 CONSTRAINT_MGR UI_FORMS         Incorrect layer information is displayed in the Edit Via List dialog when a filter is applied
    # ]/ _& [  Q  I' z9 H3 P1657220 ALLEGRO_EDITOR SKILL            axlXSectionGet() returns Primary list of layers and not All stackups, U' x. V* d7 N# ]" Q1 I+ o
    1657257 SIP_LAYOUT     EXTRACT          When using extracta, custom layer names not getting retained
    ! M. \# o7 X( ~1 O# o1658440 ALLEGRO_EDITOR PAD_EDITOR       The location of a drill in the .pad file is different from the .dra file
    8 y1 D$ H1 i% M' u. J. z4 f( `1658445 CONSTRAINT_MGR CONCEPT_HDL      When DCF file is converted to ASCII, no further updates are allowed.
    8 Q3 t; J* v/ N# v9 s$ D1659473 SIP_LAYOUT     WIREBOND         When moving wirebonds they are jumping instead of sliding: Z& C; r* e( s3 ^  F" h0 g
    1659498 ALLEGRO_EDITOR INTERACTIV       Unable to turn off line on Etch Wire for Jumpers( _& h, F: g2 H6 A  b8 n
    1659644 CONCEPT_HDL    OTHER            Predefined nets are not listed if 16.6 design is being opened in 17.2: m2 M. w7 d# i( g+ s
    1660475 CONSTRAINT_MGR UI_FORMS         The CTRL+V shortcut is not working in the Export Constraints window in Constraint Manager 17.2
    ! C/ F$ ^( X' z5 L) z+ {( y1660492 ALLEGRO_EDITOR UI_GENERAL       PCB Editor crashes when using multiple desktops on Windows 10
    + r! V5 L! R% j, n1 K1661133 CONSTRAINT_MGR ANALYSIS         PCB Editor crashes if comma is used in the Value field for Analysis Mode1 v4 o, X8 T3 j! [& D' h1 p, j: P# H
    1661307 CONSTRAINT_MGR CONCEPT_HDL      Prevent creation of diff pairs on VOLTAGE nets
    6 }9 i& N% {- ]. M. N8 t  a6 ?1 a& E1661357 ALLEGRO_EDITOR EDIT_ETCH        PCB Editor crashes when using Route - Connect
    . f1 W) |3 \" q$ F1661874 ASDA           DESIGN_CORRUPTIO Unable to delete the ZERO part from the schematic page' \0 |+ E  X  E6 Z
    1662799 ADW            SRM              Mechanical symbols are not being displayed in the Mechanical tab of Symbol Rollback Manager
      D0 i+ N2 ?$ s, l5 E, C' h1664797 SIG_INTEGRITY  GUI              Unnecessary coupled interconnect models were generated during View Waveform.  ]3 H- h; u  A9 s& ?" P
    1664858 ALLEGRO_EDITOR EDIT_ETCH        PCB Editor crashes during Auto Interactive trunk route.
    0 i! D& k/ {& x$ k/ w7 L1664911 ALLEGRO_EDITOR OTHER            PCB Editor freezes after DRC Update is performed
    / V% m7 z! e- F1666329 CONSTRAINT_MGR OTHER            SCM Import Physical process crashes cmfeedback4 r6 O8 z! S1 R5 h
    1666551 ALLEGRO_EDITOR ARTWORK          Import Artwork, Mirror option separates imported artwork to different XY locations
    & ]( w$ g( a' h2 C) \. N1666723 ECW            TDO-SHAREPOINT   TDO login is not working with Site Minder because of incorrect characters in the Site Minder login form HTML
    4 z+ c& y& V2 i' P1667068 ALLEGRO_EDITOR SHAPE            Update shape removing the shape voiding( n5 l6 {* j5 O6 a3 `
    1669828 F2B            DESIGNVARI       Variant Editor crashes on Windows 10 T540 P laptops but works fine on Windows 10 desktops/ [7 |$ d2 G# O3 F: U/ \
    1670221 ALLEGRO_EDITOR DATABASE         Non-recoverable corruption error is reported when saving the board after adding a layer
    ' ]* v) v$ v* r& z- y1 l1672134 ALLEGRO_EDITOR ZONES            TDP needs FIXED component override
    . h7 X# @8 V$ C+ @8 v" |# @5 G' g2 @% z: E

    % ~8 q# Y+ K1 L9 h9 }. y* R. zFixed CCRs: SPB 17.2 HF008
    ' I0 o8 T$ y9 y7 C7 x6 T) ?$ h! Y10-29-2016
    9 U# ^* h* @/ O===================================================================================================================================3 X# c5 L5 f0 C% D" s; `5 ]
    CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
    5 I+ l. d- ?. c+ X. g/ D===================================================================================================================================+ M; L* t* \: \1 y8 s1 k, c
    1644406 ALLEGRO_EDITOR SHAPE            Alternate symbol placement results in illegal parent identifier error+ K' ~# i& N; i3 O' @& P
    1647098 SIP_LAYOUT     OTHER            SiP crashes on symbol copy and rotate
    6 H$ F: e+ f% A3 @2 B1647154 APD            OTHER            Disconnected Clines not working; f; ?" l8 d8 S
    1648817 GRE            IFP_INTERACTIVE  Allegro PCB Editor stops responding on adding netgroups to a nested netgroup
    3 X; ?. \% B4 {1 m5 m6 s+ H) Q- r1649829 CONCEPT_HDL    CORE              A delay is observed before the sub menus of the File and Tools menus appear
    6 E: K$ a+ @, H. z8 p5 s' m) a1652930 ALLEGRO_EDITOR OTHER            Command-line version of switchversion not working0 C- b# Y" C" R+ p
    1653109 ASDA           DESIGN_CORRUPTIO SDA not pulling latest library information for part
    " l* Y0 c( B: w( x: E1655377 FLOWS          PROJMGR          Project Manager crashes on Windows 10
    $ u# V1 A4 h8 `9 H% o, F- M- U: S, q  F5 q! j. K/ O# J6 Y1 L- F

    - N3 W2 {# A* H: [* JFixed CCRs: SPB 17.2 HF007
    4 r0 r& H% w& I+ C" U; E3 P# @10-20-20163 F" i$ T% t3 Z1 ?! e  l
    ===================================================================================================================================
    ( j; G* M. ]9 B( a+ qCCRID   PRODUCT        PRODUCTLEVEL2   TITLE" e8 ~+ W9 `% a$ E  n0 Z4 ~1 l
    ===================================================================================================================================
    # G- d& W, |3 W' W# o6 G5 {1582276 CONCEPT_HDL    CORE             Need the ability to delete an image placed on the DE-HDL canvas+ k5 |  G; ?: w. w: }0 E: F5 U; y- T
    1594101 CONCEPT_HDL    CORE             No error or warning issued on specifying an incorrect unit for voltage
    * m+ i# n% v$ A  @# M$ n1611293 ALLEGRO_EDITOR UI_GENERAL       If the Command window is floating, it cuts off text from the bottom half of the last line.' e% |1 e6 |8 l8 V; j' g7 {
    1611652 ALLEGRO_EDITOR UI_GENERAL       New artwork film not appearing in the drop-down list for Visibility Tab
    ; F! e/ A( g) M1618205 ALLEGRO_EDITOR UI_GENERAL       New Artwork film added is not updated in Visibility - View" [" E0 g3 N8 G2 Y1 o* \. \
    1631114 CONSTRAINT_MGR OTHER            SKILL functions axlCnsPurgeAll and axlCNSDelete delete spacing constraint sets but not deleting names
    , @/ P: m# V7 t( f5 |# U5 |6 }1633726 ALLEGRO_EDITOR UI_GENERAL       Visibility tab not dynamically updating the view list when artwork film changes
    , m) F& t) H- u' Q) [, {1636404 CONSTRAINT_MGR CONCEPT_HDL      In 17.2 QIR1, DE-HDL Constraint Manager allows users to enter invalid voltage units
    - c7 A2 h: t0 U1 A1636864 ALLEGRO_EDITOR UI_GENERAL       Domain Selection for Visibility does not work with Hotfix 004 unless you save and reopen the board file  V% E& v; h, q; B
    1638251 ALLEGRO_EDITOR DATABASE         Unplated hole changed to plated hole after uprev from 16.6 to 17.2 version: D1 x8 {- ~4 u7 B! t; z
    1639483 ALLEGRO_EDITOR EDIT_ETCH        Manually routing discrete components with incorrect constraints causes PCB Editor to crash
    ' u# b9 ~. \) o1641435 SIP_LAYOUT     IMPORT_DATA      Need SiP Stream mapping layer count to match Virtuoso stream layer mapping count9 z% C* H- E# X
    1641483 SIP_LAYOUT     WIREBOND         SiP Layout - Modify the wirebond report generation for Start and End height when using a DISCRETE class footprint
    . S( }8 K$ v2 z; p; |0 g! V1644131 F2B            PACKAGERXL       Option needed to package a DE-HDL design with ptf errors into a board file
    5 y4 C% t$ ~! G. [* M" p4 s/ R3 E) B1644807 CONSTRAINT_MGR ANALYSIS         Unable to set electrical constraints modes with the OrCAD PCB Designer Professional licenses
    . S0 e0 |. h1 D4 j0 P1646228 ALLEGRO_EDITOR UI_GENERAL       Running the axlUIMenuInsert command to add a submenu after running the axlUIMenuFind command crashes the tool
    ! k  W3 Z: {, P2 W. _1647402 PSPICE         PROBE            Unable to print on Windows 10 as no plots are displayed in the Probe window
    1 R9 r# O# Q' d! W  d7 f" F# e1648183 ALLEGRO_EDITOR INTERFACES       Allegro STEP Export: Using the 'step_3D_copper' variable, pads not exported in the same plane as traces and shapes
    " K2 g, U2 t1 x  P. V1 Z1649222 APD            ASSY_RULE_CHECK  Allegro Package Designer stops responding on running the Acute Angle Metal DRC
    $ \  o$ [  E; @1 J, n
    ; y! t5 _; a9 g) X. K
    + \' {" u3 J! d1 M' w: zFixed CCRs: SPB 17.2 HF006
    ) O. k3 F6 n  r/ S8 I$ o" y9 ]10-7-2016) D& {4 h8 t7 {! O1 k" I
    ===================================================================================================================================
    . X8 l7 J( S) o- |7 V+ e( Q7 A4 JCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
    : M& B3 u! z4 E( @4 W" ?===================================================================================================================================8 i5 [5 A" p5 R1 Z
    1585203 ADW            DBEDITOR         Optimize check-in of footprints with multiple padstacks
    6 E3 `' F9 {4 T) N) L- G1607954 ALLEGRO_EDITOR SHAPE            Dynamic Shape not updating correctly
    8 C; |5 q* T0 A1618173 ADW            SRM              SRM does not automatically run when a .brd file is opened from EDM Flow Manager in 17.2 Hotfix 003
    " Z' Y: b$ Q0 Q6 L; R7 h1618832 ADW            SRM              SRM marks parts as updated even when they are not updated: M" n9 a& F6 g# x+ U6 `
    1623823 SIP_LAYOUT     WIREBOND         NO_WIREBOND property is ignored by Add/Edit Non-Standard  e, w" J4 g* ?; q+ l" d. T
    1626001 ALLEGRO_EDITOR SHAPE            Shape to route keepout DRCs reported for dynamic shapes in the attached design
    % }' W( \+ V7 k) v5 b8 L, W  R1626546 SIG_INTEGRITY  FIELD_SOLVERS    Extra RL elements in via spice circuit model generated by Via Model Generator. }; G2 z# r9 p  y/ I7 o; Q
    1631792 SCM            OTHER            The NC net has re-attached itself to another net, RIGHT_LEFT_N, in the design, U/ L3 h4 \+ j" @6 L8 |
    1632223 ADW            LRM              Checking in a hierarchy causes a crash+ T: R+ {! N5 l9 y
    1632844 F2B            DESIGNVARI       Part is simultaneously defined as Pref and DNI in Variant Editor with no error9 v/ f" V* ]; m' i$ @
    1633647 ALLEGRO_EDITOR MANUFACT         Variant issue: Create Assembly Drawing command not creating filled shapes for keying pegs in attached design  Y8 F0 J% g* N0 r, w2 w; N' P
    1633707 ALLEGRO_EDITOR DATABASE         Cannot remove Route_Keepout associated with a pin+ ]) w# i; |1 ]8 `8 o$ U2 r
    1634392 PCB_LIBRARIAN  OTHER            Launching Library Explorer without -proj option crashes the tool. Y, @; r$ V1 c$ O
    1635049 CONSTRAINT_MGR CONCEPT_HDL      DE-HDL crashes when trying to create layer set from Constraint Manager
    / `4 _! P% J2 ^/ e) U1635593 ORBITIO        ALLEGRO_SIP_IF   Importing  .sip file reports undefined argument error while processing shapes
    + i2 s) b' C: H1 m( W$ ?) y1635858 ALLEGRO_EDITOR ARTWORK          Get 'WARNING: Null REGULAR-PAD specified for padstack' messages in log file when generating artwork for all layers
    ! n# y6 u* P. X+ U' H! F# ^1636097 ALLEGRO_EDITOR ZONES            Technology Dependent Packaging footprints not updating in the design$ d2 H+ b8 G9 x6 \, Y7 `
    1636185 ALLEGRO_EDITOR ZONES            Import Placement not placing TDP footprints in zone" h. m) q4 X- e- m% T
    1636867 CONSTRAINT_MGR OTHER            Millimeters shown as mils in the Analysis Modes dialog box- w1 I6 q9 o& ]3 }
    1638094 SIP_LAYOUT     OTHER            Cross Section Editor not seeing updated information
    0 l3 W7 G+ A0 d! w2 B1639845 ALLEGRO_EDITOR INTERFACES       Step file not generated when board is exported to a folder with special characters in name
    3 m1 i" ~) P. f( j! O1640611 APD            SKILL            Launching XtractIM from SiP Layout with the attached design crashes both SiP Layout and XtractIM
    $ j  x! l: ]% [+ x2 J1641339 ALLEGRO_EDITOR INTERFACES       DXF_IN does not show all the subclasses available in the design# G0 A! U; j3 r! m/ \  `
    1641879 XTRACTIM       GUI              XtractIM crashes on extracting a SiP design if 'SI Ignore' is selected for a die stack layer in Cross Section Editor8 o4 p  |( Y' k% p9 \9 y" i
    1642012 CONCEPT_HDL    CONSTRAINT_MGR   Schematic-defined net groups without any members cannot be deleted in Constraint Manager
    ( _4 X: r1 I0 k4 h4 }8 z+ w2 Z1642015 CONCEPT_HDL    CORE             Pin exists on block but no corresponding port exists in the underlying schematic
    2 ]8 Y4 b) C# T& W: A& k, T5 M1642597 ALLEGRO_EDITOR OTHER            Importing .tdp file: Footprints not included in the .tdp file are updated in the design
    & z3 s! L) V" }: G3 B( h' w1643557 SIP_LAYOUT     DIE_GENERATOR    Die Text files will not update the design  ?+ w1 ?0 u( i8 J1 m) T& f
    1646086 ASDA           IMPORT_BLOCK     Importing a DE-HDL design into SDA results in error 'IMPSHT-42 Alias cannot be created'
    , W' Z9 L9 I; D+ t% v8 u1647580 ASDA           IMPORT_PCB       SDA-File Import from PCB Editor has duplicated RefDes on schematic.: s* o  w) T5 b9 `

    - T6 L' M5 j; G: P' M3 H; Y8 L
    ' g. e' F4 v6 ?% }% J' TFixed CCRs: SPB 17.2 HF005
    ) |& S: Z' ?( N09-10-2016
    ' ~1 b3 l. [8 l4 `===================================================================================================================================9 u8 V2 e3 x, n* J9 g! C* Z/ C
    CCRID   PRODUCT        PRODUCTLEVEL2   TITLE9 b1 C4 ]2 U3 S9 W
    ===================================================================================================================================; ^9 e! e9 R; }$ w1 g6 u! R" `, s
    1496199 ALLEGRO_EDITOR SHAPE            Overlapping route keepouts result in a broken shape4 f* @' K  l8 B7 ^) o
    1519972 ALLEGRO_EDITOR DRC_CONSTR       Dynamic phase DRC at incorrect location& N0 U: k4 l7 t9 M
    1521940 ALLEGRO_EDITOR DRC_CONSTR       PCB Editor not recognizing the correct pin pairs of the differential pair
    / w  S/ w" V( D0 `# m1536713 ALLEGRO_EDITOR INTERFACES       File - Viewlog still checks for brd2odb.log file
    & E5 u! C4 m" e3 `1568912 RF_PCB         BE_IFF_IMPORT    Route keepouts can only be imported once
    4 n+ q7 C- L4 }1586846 RF_PCB         PLACEMENT        Get an error while manually placing RFCOMPIB part3 P" _% O; P& T( ]0 [2 Q
    1588769 ALLEGRO_EDITOR UI_GENERAL       ALT+key shortcuts are not available in 17.2* ~- n0 e' T0 k( u" Q, {4 \
    1589396 ALLEGRO_EDITOR UI_GENERAL       Need option in 17.2 to change the placement of the Find, Visibility, and Options tabs
    2 }, @8 V9 {. w+ x1593258 ALLEGRO_EDITOR OTHER            Adding German letters to database diary deletes all the entries8 `, c$ g# a- G7 G; V) S. @( `
    1597413 SIG_EXPLORER   SIMULATION       SigXplorer crashes when simulating with a via that was added to the canvas( I7 |# t' r, U$ I% V, P1 @
    1599680 ALLEGRO_MFG_OP ALLEGRO_INTEG    Documentation Editor crashes on opening a specific database
    * ?' ^8 f* H4 H0 O! q8 @+ c& U1606682 ECW            ADMINISTRATION   ECWBackup and ECWRestore fail when data is 1GB or more' \) i; E- l5 }
    1607250 ALLEGRO_EDITOR DATABASE         A board file created in release 16.5 crashes when opened in 16.6 Hotfix 69
    % g  W' }7 _4 Q- N9 P- Z% _1607565 ALLEGRO_EDITOR SYMBOL           Default values are not consistently converted when adding pins after changing units.# B& |& r- ?9 p& j- a" ]
    1607956 ALLEGRO_EDITOR OTHER            Unable to generate the model index file from the command line using mkdeviceindex
    ! |. G9 u6 G. _! G' N7 Q0 @, U  q1609794 ALLEGRO_EDITOR UI_GENERAL       PCB Editor: Shortcut keys to menus are not available in 17.2
    - E: Y8 i& ?' x; {( B2 P6 z! S1609817 CONSTRAINT_MGR CONCEPT_HDL      DE-HDL crashes on opening project
    $ f& n' `5 i8 L, H1611446 ALLEGRO_EDITOR SHAPE            Inconsistent break in shape when creating voids in a design in  16.6 Hotfix 69) P* l- z# H, x0 @- N1 J- X5 p
    1613512 ORBITIO        ALLEGRO_SIP_IF   Unable to read the OrbitIO database file (.oio) in SiP Layout
    5 d/ M* p0 I3 p( O: \; ]1619610 ORBITIO        ALLEGRO_SIP_IF   Some mechanical pins appear rotated by 90 degrees when imported
    * H" H) [; T3 \5 B1 q3 l1620814 ALLEGRO_EDITOR PARTITION        Etch and Via are not imported with the partition
    7 O6 k9 j% O4 \$ v8 k1621390 GRE            CORE             Design Crashes during the Spatial Planning phase
    . `5 B  ^% a; f! \; U& m1623112 ALLEGRO_EDITOR OTHER            SPB17.2 switch release is unable to identify 16.6 release when 16.6 is installed in All-Users mode9 D) K* U5 j6 E& z
    1623113 ASI_SI         GUI              Aggressor waveforms are not displayed in waveform viewer after crosstalk simulation/ h. t" L  [) P5 @  ~
    1623231 CONCEPT_HDL    CORE             Unable to make the Attributes form part of the standard display in DE-HDL
    5 Z% B& z2 F+ Y9 V1623666 APD            OTHER            Incorrect vector pin syntax appears in the chips file written using 'RF Module - Export chips & connectivity'/ I5 |8 o: j  G" \
    1623888 CONSTRAINT_MGR CONCEPT_HDL      Ambiguous and inaccurate mapping errors reported when an ECSet is applied to a differential pair object" L+ K4 K6 \$ a7 e
    1623904 ALLEGRO_EDITOR SCHEM_FTB        Logic import fails, but no error mentioned in the netrev.lst file
    + X: E: X9 r* T, v' ?1623935 ALLEGRO_EDITOR SKILL            On running the SKILL function, axlSectionModify, Shield and Etch Factor are not updated, ]. S$ K3 C' b+ u$ F' ?/ Q
    1625610 ALLEGRO_EDITOR SHAPE            Modifying a shape boundary leads to other shapes losing their voids
    * z, ?# ]3 e5 n7 e* K1626716 ALLEGRO_EDITOR UI_FORMS         Z-Copy menu is not available with OrCAD PCB designer Professional license* J6 O% H  O5 x9 A8 y3 N
    1628403 ADW            TDO-SHAREPOINT   Objects remain checked out after multiple failed 'check-in hierarchy' attempts$ F8 ~* `4 X7 K. c6 k
    1630458 ORBITIO        ALLEGRO_SIP_IF   Import OrbitIO Database file (.oio) in SiP: Bill of Materials report does not include standard dies) V0 S# N+ Q* I5 b0 G! L. R
    1632504 CONCEPT_HDL    CORE             DE-HDL core dumps during Save Hierarchy on Linux0 ~$ }- t0 g) A8 Q, K
    1633581 ALLEGRO_EDITOR PLACEMENT        On mirroring a part, the cursor moves to the origin of the board5 R. |# m# I3 B
    1633601 ALLEGRO_EDITOR PLACEMENT        Place - Via Arrays - Boundary command: Via arrangement pattern deteriorated in Hotfix 004
    + J( a+ Z9 c" A6 D# k5 ?; I
    4 c5 x5 k" G8 i9 h
    5 l/ {! `/ o6 ]5 aFixed CCRs: SPB 17.2 HF004
    $ R2 X/ s# P5 U4 R+ r08-14-2016" l5 w# j4 t- a
    ===================================================================================================================================
    $ }( W9 ]. D' A0 i: YCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
    ( w! P; `$ c) ^  u===================================================================================================================================
    ' n6 [+ j3 y2 L' ]# x2 X* A908816  CAPTURE        SCHEMATIC_EDITOR Few graphical operations are active even when a page has been locked9 M2 f0 e9 K" a; J' W
    1213923 ADW            LIBIMPORT        Cannot delete parts in the Library Import project (XML)1 m6 u$ p( A) `
    1250476 PCB_LIBRARIAN  LIBUTIL          con2con does not check for PACK_TYPE value set to question mark$ B# v$ k  x4 U0 _; Q
    1306441 APD            OTHER            The Minimum Shape Area option in Layer Compare uses an unspecified value
    5 q( A0 }' K: G. {1322242 ALLEGRO_EDITOR INTERFACE_DESIGN Using Add Connect with the Replace Etch option causes PCB Editor to slow down for certain constraint nets
    , q$ Y5 T' O, J3 Z1326716 ADW            DOCUMENTATION    Dataexchange documentation correction needed8 _( q) }2 s" M: {  o+ B
    1356948 APD            DEGASSING        When using the Degassing tool on shapes the size of the file becomes very large$ o- U8 M! d% D, Q
    1376510 ADW            DBEDITOR         DX output ERROR after Property Display Ordering of Part Classification.
    , c$ Q5 ?( g) H, O# o9 N: _& p# ~1408218 ALLEGRO_EDITOR MANUFACT         Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
    : y- Y1 o# X( Y  j% Y5 r. @1410485 CAPTURE        SCHEMATIC_EDITOR The 'Autowire - Connect to Bus' menu command and the 'W' keyboard shortcut are enabled on a locked design
    , O* ]2 @% l5 K: @9 p1413248 CONCEPT_HDL    CORE             Import from another TDO project makes the block read-only
    4 w* J; x: ~! D+ i4 w4 l1413287 ADW            LIBIMPORT        Library Import converts all Attributes to uppercase when reading CSV
    5 |) V$ A6 ^* V% y1417429 ALLEGRO_EDITOR INTERACTIV       Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
    ' y4 }1 [7 ~" m9 q1417442 ALLEGRO_EDITOR INTERACTIV       Spin via stack and only part of the stack spins
    0 S9 V8 a' X1 _' y4 P" n1430251 ALLEGRO_EDITOR PLACEMENT        Quickplace placing symbols outside of a polygon shaped room
    1 j4 U: d5 D8 C1440509 ALLEGRO_EDITOR PLOTTING         Ratsnest does not follow the RefDes position when plotting the BOTTOM layer with the Mirror option
    & A7 ]0 g; Y- i9 Z1441086 PCB_LIBRARIAN  OTHER            Changes made to a package with sizable pins generated from the 'sym1' view are not saved( Q4 o, ^% q) U) @
    1443339 PCB_LIBRARIAN  PTF_EDITOR       ALT_SYMBOLS syntax in PTF file not checked
    6 x3 c. M0 K' W) ?3 c1444144 ALLEGRO_EDITOR DRC_CONSTR       The 'add taper' command generates line to line spacing DRC+ ^% r: d% S; u; o
    1451766 CONCEPT_HDL    COMP_BROWSER     License error message should indicate which license is required1 Y3 ~7 U( a/ Y: Z
    1451977 CONCEPT_HDL    PDF              Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set, E5 `$ R( `% q, x% v" {5 D
    1457138 CONCEPT_HDL    CONSTRAINT_MGR   devices.dml: difference in content generated by _automodel add command and Constraint Manager launch' @  O4 f2 c/ c; ~  S
    1458439 F2B            PACKAGERXL       The Packager pstprop.dat file reports false conflicts in net properties  F. g6 }8 z5 g" Q8 [/ j
    1464865 CONSTRAINT_MGR ANALYSIS         For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM
    1 t) Q: \& n! x3 s1464948 PCB_LIBRARIAN  VERIFICATION     The errors/warnings do not match between the various tools
    * [8 F: N8 _2 A, D1467826 CONCEPT_HDL    PDF              PublishPDF from console window creates a long PDF filename" l; S- J( y9 Z4 N
    1470106 ALLEGRO_EDITOR MANUFACT         silkscreen program cuts auto-silkscreen lines excessively
    / P2 Q" I! E0 b! e1471287 CONCEPT_HDL    CONSTRAINT_MGR   Pages imported from other designs with different units should inherit the source constraint units2 X, B- J; ~9 w  i1 @' U7 _
    1472046 ALLEGRO_EDITOR OTHER            Gloss routine, 'Via Eliminate' - 'Eliminate Unused Stacked Vias' is not removing unused microvias from the stack* C- c# a* H; ^( A% j) T+ Q
    1472414 ALLEGRO_EDITOR SCHEM_FTB        netrev changes pin-shape spacing rule in constraint region8 a( h/ o# V( Q9 d( m. x2 H
    1472444 ADW            ADWSERVER        Multiple errors in adwserver.out after SPB054/ADW47
    % e; O: O6 W! S  h, m, p1473056 ALLEGRO_EDITOR ARTWORK          Gerber export has additional phantom data not on design
    ' g$ v, P( f& o% S/ K1473900 CONCEPT_HDL    CORE             DE-HDL stops responding when a hierarchical block with variants defined inside the reuse block is enabled
    ( M! M4 o* U4 \7 x3 h- R3 @1474020 ADW            DBEDITOR         Unable to modify schematic classification when a part is checked out previously by another librarian1 J8 h* r5 z& F8 H$ |4 ]+ s
    1474066 ADW            DBEDITOR         Bulk edit performance lags when parts included have a large number of properties) {9 T" |& A8 t, z' d6 ?
    1474764 ALLEGRO_EDITOR PLACEMENT        In Hotfix 56, the 'place replicate create' command does not produce desired results if a fanout is marked7 x) D* `& ]; V  v: F3 _
    1474894 ALLEGRO_EDITOR PLACEMENT        Place replicate fails to include vias when the module is applied to other circuits.
    9 D* \; ~. T* G  ~& O+ X1475650 ALLEGRO_EDITOR OTHER            Using Outlines - Room Outline gives WARNING (axlRemoveNet): No match for subclass name - 'BOARD GEOMETRY/__EPB_SCRATCH_'7 v( x& j2 O- w# r7 c
    1476528 ORBITIO        ALLEGRO_SIP_IF   While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown
    8 H6 s* z( T$ z. _1476920 CONCEPT_HDL    OTHER            Genview consistently fails in some indeterminant manner.% v7 b7 J3 s( u/ U
    1477369 CONCEPT_HDL    INTERFACE_DESIGN A significant number of problems are reported when running genview with port groups* |/ R3 F4 |) f& i
    1478111 F2B            DESIGNVARI       Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release$ l7 d# ?# Y9 T$ I) `
    1478200 GRE            IFP_INTERACTIVE  PCB Editor displays the 'Low on Available Memory' error when updating shapes and then crashes
    3 }. l' d) R" T+ x# L# |3 j1478680 CONCEPT_HDL    CORE             Unable to move components in a schematic using the arrow keys
    5 P' g  s! ?! V  P3 a1479135 F2B            PACKAGERXL       Hierarchical design reports conflicts when signal names change through the hierarchy
    4 D4 ~; K1 _0 j9 E; v3 R1479153 CONCEPT_HDL    CORE             File - Save Hierarchy flags an error and does not update subdesign xcon: }8 ]" F& Q. L3 j  }
    1479227 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy% K. T2 A- q* f6 C/ u( ]
    1479454 CONCEPT_HDL    OTHER            DE-HDL issue: locked DIFF_PAIR property is editable
    7 X! k1 B3 d# c+ S$ Y7 g1479569 PCB_LIBRARIAN  OTHER            hlibftb fails with error SPCOPK-1053
    , b( k' G% Q/ r) i3 m# q1479785 ORBITIO        ALLEGRO_SIP_IF   BRD file is not loaded in OrbitIO3 j# y! \/ N5 \
    1480005 ADW            DBEDITOR         The DBEditor or DBAdmin GUIs do not allow the same characters in Property as LibImport CSV Files
    " Q  o6 z7 J5 [1480367 SIG_INTEGRITY  OTHER            Differential pair extraction SKILL error
    * E( S$ b3 n7 q1 x4 R1480499 ALLEGRO_EDITOR PARTITION        Cannot delete partition
    # `5 D, e0 C% C: F, I$ ]0 |+ G1482544 ADW            DBADMIN          Hierarchical Preferred Parts List (PPL) is not functioning correctly
    ( v0 ~4 J7 q' K+ }# T6 Z3 @. z1483136 ADW            COMPONENT_BROWSE Error flagged when searching a property value with parenthesis or comma in Component Browser in the ADW mode5 j0 @8 Z% d1 p6 Q4 {
    1483617 ALLEGRO_EDITOR DATABASE         Delete islands command crashes database with filled rectangles* f1 Z5 o/ J" M0 K/ O$ m. B$ z
    1484100 SIP_LAYOUT     INTERACTIVE      SiP crashes when copying and rotating a symbol
    " {) n6 m" p% }# A! B0 M6 t: @1484781 CONCEPT_HDL    CORE             Three different Hierarchical Viewer issues# X2 f! g/ x7 O% X4 P' T, _
    1485059 PCB_LIBRARIAN  CORE             Part Developer pin attributes are randomly marked as read-only1 _* A9 K2 J$ E& N" D7 U* a5 E
    1485931 ALLEGRO_EDITOR INTERFACES       Errors generated when importing IDF in an existing board file
    3 E1 J* z. P. w8 N1485960 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule is crashing the project5 R) V8 }; n* d: o: M
    1486086 ALLEGRO_EDITOR ARTWORK          Cannot generate artwork.
    - c( ~, Q, g% u" h9 }. v+ N: P: i1486378 ALLEGRO_EDITOR PARTITION        Unable to delete orphan partition as it is not listed in workflow manager.
    5 P" C/ Q7 u- Z6 M5 s- O1487085 CONCEPT_HDL    CONSTRAINT_MGR   Import Physical with the Constraints only option reports problems
    # I9 N+ B' G# g* R% D  L2 u. \1487125 ADW            COMPONENT_BROWSE Results not displayed in Component Browser for parts with no associated manufacturer parts7 s: ?% I0 [. E
    1487265 CONCEPT_HDL    CORE             Replace command in Windows mode shows incorrect behavior. k7 B; Q& p) J0 @! ?
    1487496 ADW            DATAEXCHANGE     DX changes checkout ownership when override action is set to remove existing relationships, \! j# |  M% r' G0 b8 W
    1487656 ADW            LIBIMPORT        Pre-analyzing a project reports false warnings& F' w9 G/ K- s9 }# N1 z* o
    1487733 CONSTRAINT_MGR OTHER            Export Physical takes more than two hours to update PCB Editor board( C8 d: k- N8 p; }1 K
    1488753 CONCEPT_HDL    CORE             Import sheets in a design with no change in models: CM_VALIDATION_ON_SAVE variable is triggered
    3 X% J1 ^3 }! _; D- g1488758 CONCEPT_HDL    CONSTRAINT_MGR   Disable Constraint Manager launch if CM_VALIDATION_ON_SAVE is set and the database goes out of sync% v8 b! ]/ H7 V' f* v
    1490299 SCM            OTHER            Allegro System Architect does not update revision properly( A7 b/ V7 J8 [7 B
    1490744 ALLEGRO_EDITOR SKILL            axlChangeLine2Cline changes line to cline and places it on the TOP layer! t$ \; O, ]3 c4 l# ^$ ^5 t# K+ [
    1490924 F2B            PACKAGERXL       Save Design/Export Physical is resetting Via constraints
    ' W! [1 S7 X# O1491351 ALLEGRO_EDITOR OTHER            Create Detail for bond fingers on a custom layer not working; y9 V& F, r( _9 v5 A, H# a
    1492013 CONCEPT_HDL    CORE             Stale PNN properties not cleared from schematic on packaging design (backannotation)/ e. @6 k( V2 y- O
    1492595 ALLEGRO_EDITOR MANUFACT         Dimension character substitution help is wrong
    # R  Z+ E; h3 e5 ]/ O& I1492703 CONCEPT_HDL    OTHER            'Global Property Display' not working for symbol edit, j9 f" r2 c& n0 {, w# p
    1492777 ORBITIO        ALLEGRO_SIP_IF   OrbitIO crashes on importing MCM8 k6 ~  m' Y4 ~7 t1 ]
    1492901 CONCEPT_HDL    CORE             Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL& M# ]% v4 i* y7 U1 j" e- U
    1494194 CONCEPT_HDL    CORE             Random display of the 'PHYS_NET_NAME' property in hierarchical designs* F3 H0 O2 l4 X/ }% D, h
    1497597 ALLEGRO_EDITOR DATABASE         Show Element on pin shows wrong drill size+ ~' g% h+ O* I3 t$ s$ n: W! [2 S
    1497956 CONCEPT_HDL    CORE             ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root- }. O, o. H, n  D  U; X2 i
    1498234 ALLEGRO_EDITOR ARTWORK          PCB Editor fails to create artwork and no error is listed in the log file, [7 n8 {6 n5 _# N2 z/ {
    1499363 CONCEPT_HDL    CORE             Custom attributes under variant management stopped working in Hotfix60
    , u8 }* p# h* ]; \0 x  m1500422 ALLEGRO_EDITOR SKILL            SKILL function, axlTriggerSet, results in PCB Editor crashing at launch6 a! \" O% ?* `8 [- x2 t
    1500725 CONSTRAINT_MGR CONCEPT_HDL      Unable to clear pstprop.dat file conflicts; j9 m5 ?) Y7 E5 @7 s' u7 q
    1501093 SIP_LAYOUT     OTHER            Package design variant shows wirebonds connected to a die which is not part of the variant
    ) g) T3 l' y4 d0 p! n1501165 F2B            DESIGNVARI       TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out3 m% H6 J) b; ^1 |2 J
    1501294 ADW            COMPONENT_BROWSE Some tabs missing after the migration to ADW ISR 053 with SPB ISR 060
    1 N- a1 w/ S/ l" h1501974 F2B            PACKAGERXL       'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL5 a4 v0 d; J6 P2 ~# r
    1502282 ADW            CONF             Configuration Manager: Clicking 'Set up or Manage Company & Site' gives an unclear message
    ; D% Z3 F; \4 I3 x. g1502782 ALLEGRO_EDITOR SCHEM_FTB        Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings' j, o4 }6 r) p* B1 d4 }" w/ O
    1504093 ASI_SI         GUI              View Topology and Waveform buttons overlap when Signal Analysis window is resized
    5 n) K$ Y1 T' |! r% {& l) h, [1504767 CONSTRAINT_MGR SCHEM_FTB        Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
    ) a! @' d: p8 b5 L$ ?+ [' `* B1506110 ALLEGRO_EDITOR DRC_CONSTR       No DRC shown when a text on etch layer is overlapped on mechanical pin
    : o2 k$ e$ H, K; r/ i1506654 CONCEPT_HDL    INTERFACE_DESIGN On moving, Netgroups break
    7 i: O" U' z5 s6 h% `: ~. e6 h1507497 ADW            COMPONENT_BROWSE Switching rows in Component Browser does not change the graphics of the symbol
    6 N9 w9 Q9 m# Q5 U; N3 c% @1509184 ALLEGRO_EDITOR DATABASE         BB vias in mirror have terminal pads suppressed by artwork0 ?) f2 w& b1 m& H: }3 i. H- M
    1510387 FSP            EXTERNAL_PORTS   Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
    ! W; B3 @9 Z: b1 k! A) k1510570 ADW            DATABASE         ERROR: Cannot check in block model because the part with instance id used in the model is not available in the database
    4 F6 m2 S5 C, S* R1511180 ADW            DBEDITOR         Database Editor: Incorrect message about a schematic mode displays when associating a footprint to a part number$ I. C  z. u! D5 a/ a( i
    1511397 SIP_LAYOUT     TECHFILE         Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
    6 z( B( e3 J, j% f9 f/ s3 k+ e1511744 ALLEGRO_EDITOR OTHER            Allegro PCB Editor removes property from component instance
    1 ^1 P. ]6 Q+ V" t( F1 U; U1511761 SIG_INTEGRITY  OTHER            Allegro PCB Editor crashes on running the cns_show command.# X: z- Y4 I; T* o
    1511947 ADW            DSN_MIGRATION    Command line arguments of the 'designmigration' command are not working. v; M& P1 x- k- t
    1513085 CONCEPT_HDL    CORE             NC symbols in the schematic are being renamed to NC_1 in pstxnet.dat and are routed as one net in Allegro PCB Editor5 A6 w4 @) O/ K' o0 q
    1513092 ADW            DBEDITOR         Create Footprint Model name is not working properly if it already exists in the local flatlib- [; [7 t4 b4 t# Y, D, R
    1513737 ADW            CONF             DesignerServer from a different network domain does not show distribution data
    , G6 L( ]$ x: U$ l! p0 J1514469 CONCEPT_HDL    CORE             Unable to get rid of an underscore from the PHYS_NET_NAME property! j: E7 E. R+ R! g) i/ ]
    1514942 SIP_LAYOUT     CROSS_SECTION    AIR no longer permitted in stackup in 17.0
    : M1 t' K8 i) {& S/ U1515318 PCB_LIBRARIAN  IMPORT_EXPORT    Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly
    3 x. m1 ~& T' Z% [( @" Y" ?1517351 CONCEPT_HDL    CORE             Genview does not update an existing split symbol
    ! s7 P2 b$ `& G5 ?# f1517388 ALLEGRO_EDITOR SHAPE            DRC error reported as PCB Editor fails to read the void for a via2 t' G6 r: X9 h* \1 o/ ~% r
    1518032 CONCEPT_HDL    SECTION          Error SPCOCN-2009 displayed even when the user has not manually sectioned the design. X0 J9 S; D3 E- |5 s6 P  j& i1 E  V9 a
    1518724 PCB_LIBRARIAN  PTF_EDITOR       PTF Editor is not saving changes/ ]5 }, h% q: _: R  R/ K
    1519040 ALLEGRO_EDITOR DATABASE         Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.( u/ d  `0 D2 Y% p' e
    1519518 CONCEPT_HDL    OTHER            Genview does not generate split symbols5 U% s0 @1 s: C6 P
    1519623 CONCEPT_HDL    CORE             Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas7 j. O& G4 t+ ?/ {
    1519910 CONCEPT_HDL    INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
    5 b6 D9 I  [1 Z* F7 ~1519946 CONCEPT_HDL    CORE             Renaming a net leads to loss of constraints associated with the net0 {+ U$ d$ p- |
    1519987 ALLEGRO_EDITOR SCHEM_FTB        In Hotfix 61, constraints are lost on importing a netlist
    1 i3 M9 H' b# [7 [2 b1520207 CONCEPT_HDL    CORE             Genview crashes after renaming ports- R6 j8 W5 m2 E: p  M
    1520727 CONCEPT_HDL    CORE             In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
    # _1 b9 Z4 O& |4 `  w1521174 SIP_LAYOUT     DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor
    - Y# ]) }( D7 y6 w2 Z7 ^1521871 CONSTRAINT_MGR CONCEPT_HDL      Constraint Manager launched from DE-HDL allows space in the name of layer sets
    3 S9 n3 w, }5 }/ J5 g1522831 APD            OTHER            axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.4 ?% E5 v  Z* N/ j# [) z& r- I) L% k2 W
    1522900 ORBITIO        ALLEGRO_SIP_IF   Padstack shape distortion after translation to OrbitIO from SiP Layout design* p1 d0 G, n, ?6 }8 D5 f% b
    1523237 ALLEGRO_EDITOR SKILL            SKILL function axlDBGetExtents() causing PCB Editor to crash
    / t5 ?% `. x0 I8 K: J1523426 ALLEGRO_EDITOR DRC_CONSTR       Dynamic shape not adjusted based on keepout; DRC generated
    $ M7 q0 n& p4 j% z+ G! E1524875 F2B            PACKAGERXL       Packaging using csnetlister fails, while manual packaging of individual blocks works fine, `% p8 n& c) D& S6 e
    1525432 CONSTRAINT_MGR OTHER            User-defined property not being transferred from DE-HDL to PCB Editor# }  D* d9 J8 M
    1525883 ADW            DATABASE         Invoking libimport on an existing DB should verify that the 'libimp_su' variable is set correctly# P9 N* Y1 h1 c. K, y# }) }; }
    1525948 F2B            PACKAGERXL       Reference designators assigned by the Packager tool are not correct' b: O7 y6 q8 k3 c( b6 |1 \
    1526914 ADW            LIBIMPORT        Cannot import to new library database! d3 |, k5 [6 l, Y: y4 i
    1527321 ALLEGRO_EDITOR SCHEM_FTB        Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63) x, p; R% `' l% z7 d# o, U
    1528075 CONCEPT_HDL    OTHER            Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
    * R+ a3 [( J6 E8 \9 q6 _$ V: O1528235 ADW            DBEDITOR         Running rule 'Validate Classification Property and Property Values' results in property mismatch error
    # |& [2 s+ E5 h7 ^4 l# L3 C& n+ f) S1528254 CONSTRAINT_MGR CONCEPT_HDL      Import Logic with the 'Overwrite current constraints' option is deleting some attributes
      p3 O6 C8 _: k( Y8 G9 X) @4 R; z/ b1528398 ALLEGRO_EDITOR SCHEM_FTB        Netlisting of pins with NC property results in error; C5 s! P5 c- |5 C
    1528479 ADW            LRM              LRM crashes when opened on a lower-level block in a hierarchical design
    ) A  W2 F1 h) {' a; \- j; q3 z: C1528894 ADW            DBEDITOR         Lack of PTF_SUBTYPE in the classification prevents the release of the part; y1 E; D* t; X( k* h0 r3 W/ d3 i
    1529178 SIG_EXPLORER   OTHER            When an ECSet is created from a net, values are not transferred correctly for PinPairs4 w1 V; B0 Y1 z6 W* o% D; p/ K
    1529209 CONCEPT_HDL    CORE             When adding a component symbol version, the More option does not show all the versions1 I! B! U! a, ]1 r4 Z( c2 {6 S
    1529720 CONCEPT_HDL    COPY_PROJECT     Running ADW copy project does not update the 'master.tag' file! g: k6 m* i9 H
    1530445 ALLEGRO_EDITOR EDIT_ETCH        PCB Editor crashes when 'Add Connect' is used* I! Z! d4 {1 F. l+ p" u& Y
    1530707 CONCEPT_HDL    CORE             Request to recover a 16.6 design after DE-HDL crashes
    + L+ u+ a4 l. A8 z2 [: ^) q& `4 Z1531425 CONCEPT_HDL    CORE             DE-HDL crashing while trying to add a NetGroup
    / B( I. u! X& F% Z2 c  p1532865 CONCEPT_HDL    CHECKPLUS        Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr! O( t; U" H( g& x1 S/ m
    1533543 ADW            DBEDITOR         Component Browser free text search returns 2 parts when only 1 exists
    8 Z$ b9 G) i: l3 u$ u. n0 P1536273 CONSTRAINT_MGR CONCEPT_HDL      Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue. a4 v/ T, O1 _) a
    1537055 CONCEPT_HDL    CHECKPLUS        Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties. D" D) S+ V# J8 z
    1537339 CONCEPT_HDL    INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
    # v) {- r5 M/ K: Q7 h1537521 FLOWS          PROJMGR          Do not allow project creation if there are spaces in directory or file names on the Linux platform
    1 K9 \1 \6 U$ p# U1539077 ALLEGRO_EDITOR SYMBOL           PCB Editor crashes when choosing 'Layout - Renumber Pins'1 l" t4 b; f- l& |% N0 D% s' M
    1539227 CONCEPT_HDL    CORE             Renaming a page from the hierarchy browser crashes the schematic editor.
    . Z' d* U0 G& R4 u1539997 ALLEGRO_EDITOR SKILL            PCB Editor crashes when the axlStringRemoveSpaces() command is run4 [, n* W& t; i' z1 e2 s- W
    1541532 SCM            SCHGEN           Generate Schematics crashes with 'Out of Memory' error7 t) \. m+ I4 T, S6 ?9 T+ X* G
    1541680 CONCEPT_HDL    DOC              A dot (.) or period in design name created 2 separate design folders in worklib
    7 M! f, R! e: k* k$ X' W" f& K2 ^2 ^1542817 ALLEGRO_EDITOR DATABASE         Import Netlist not getting completed on specific board  y% j$ Z$ h! V6 s7 x
    1542949 ASDA           EXPORT_PCB       The Export to PCB Layout form: The file name specified in the 'Output Layout File' field is not accepted9 X0 J! v0 H5 m/ l+ z
    1543537 ASDA           NEW_PROJECT      While creating new projects, the new folder name is not visible clearly in the explorer
    . ~$ I( Q4 C- c# X) f1544060 SCM            SCHGEN           Generate Schematics causes Allegro System Architect to crash* s' L/ \# I) ?  O+ [
    1544633 APD            STREAM_IF        The 'stream out' command causes Allegro Package Designer to crash
    / W, W) P5 A4 v  w8 p! x  n1544698 ALLEGRO_EDITOR PLACEMENT        'place replicate' does not add clines and vias to fanouts if fanouts are marked
    9 q' j  |3 h  E0 B2 w1544856 ASDA           CANVAS_EDIT      Edit > Find places the process (UI) behind the SDA tool.
    / n/ e0 P# k$ S. r) @2 _1545136 ALLEGRO_EDITOR PLACEMENT        All fanouts are marked as part of one symbol instead of the symbols they attached with; G1 v1 [7 P) d7 J# s3 R" @
    1546062 ADW            TDO-SHAREPOINT   Failure to launch TDO Dashboard, need to update error message with more useful information( D6 K* \$ n$ N# J/ J9 k& I
    1549105 APD            OTHER            'Stream out' fails with message: 'Request to terminate detected. Program aborted'& T% F2 I0 y, H
    1549658 ADW            TDA              An unmapped network folder in the Team Design Authoring option results in an error
    # W  N% l7 z1 y1550052 ALLEGRO_EDITOR PLACEMENT        PCB Editor crashes when copying symbols
    % B: Y, i% ~; g* C1 D) @/ Z5 l1551635 CAPTURE        TCL_INTERFACE    GetSelectedPMItems returns error for design cache objects
    1 V" A( g9 g0 |: [5 A1553027 ALLEGRO_EDITOR UI_GENERAL       PCB Editor canvas stops responding for tasks such as resize and workspace switch( s7 N/ O( h' q; b! z1 s+ h
    1555246 ADW            DBEDITOR         Part Copy As does not copy AML and reliability model relations.
    / c" B8 E; u( G  s; p7 J, i1555254 ADW            DBEDITOR         Text in Free Text search box is removed if it loses focus
    4 k& [! f" @6 j) C1557542 ALLEGRO_EDITOR OTHER            DXF export creates strange result for donut-shaped polygon
    , C1 y6 T4 d" @+ u4 t+ K& f9 X1573039 ALLEGRO_EDITOR INTERFACES       IDX returns control to the general interface prematurely during an incremental IDX export
    . `& q0 _" G- L' ~. k1580571 ADW            DBEDITOR         XML files continue to appear in flatlib even after the padstack/footprint models were released2 E; j$ A+ F- s* m/ r* }) U' ], H
    1580580 ADW            LIBDISTRIBUTION  The .lis file contains references to old models even after they were purged., m2 H' w/ r, r7 P6 {, n3 T# A
    1582064 ALLEGRO_EDITOR UI_GENERAL       User-defined menus not working in PCB Editor 17.2
    ) q, K; h( Z, e+ s1582628 ADW            TDA              When one user takes an update of physical object while the other user is still checking in the object, TDO crashes. L$ g4 N. P/ w
    1582856 PSPICE         MODELEDITOR      Getting 'ERROR: [S2C3471] Base part library does not exist when Export to Part Library', though olb is created
    ' O" D( ^6 ]. I: p! o# L1584719 TDA            CORE             Caching errors are flagged for a board-ref project during block update
    # g! {! t7 g" j, m8 n1587045 CAPTURE        IMPORT/EXPORT    Unable to import PDF file
    # {! p' \0 ~; C5 K/ f& Z& `1587259 ALLEGRO_EDITOR UI_GENERAL       axlUIMenuFind not working correctly for the 'bottom' option
    . I$ Z( _. r  K- h; Q; A' `1588736 PSPICE         MODELEDITOR      The Model Import wizard displays 'Invalid configuration' message when a .lib file is opened in Model Editor& x% H  ?2 T: A* z$ V  s) f
    1588742 PSPICE         PROBE            Browse icon is missing from PSpice File - Export - text! a! G1 g; X) ~, j1 |. Z, P
    1590006 ALLEGRO_EDITOR UI_GENERAL       PCB Editor 17.2 crashes when multiple browse windows are opened4 U6 M* M$ p8 n0 C+ Q
    1590597 PSPICE         PROBE            Problem with the adaption in the Probe Window icons- b3 g3 q8 }; j! k# y
    1591264 ALLEGRO_EDITOR UI_GENERAL       Film order in Visibility View is sorted alphabetically and does not match the manufacturing artwork3 l1 v  q, j, Q9 J9 q& @/ U% M
    1592089 PSPICE         MODELEDITOR      Cannot get the PSpice DMI Model DLL while using PSpice DMI Template Code Generator
      \: L* [: I6 G) I" {1593436 ADW            DBEDITOR         Cursor does not automatically move to the model name cell when creating a new model
    ) L7 u; M6 i: ]9 L2 ?: r7 D1594076 TDA            CORE             TDO crashes on concurrent check-ins when one of the blocks was not modified.
    + W, s/ o- S+ A2 F" C+ J2 G2 y1595987 ALLEGRO_EDITOR PLACEMENT        Subclasses not getting updated in Placement Edit mode
    0 e& H: O% {- j4 u( Z1596162 ASDA           IMPORT_DEHDL_SHE Importing sheets from DE-HDL imports the block as well0 n1 P( U5 u4 F/ j" E% D5 r
    1597000 CONCEPT_HDL    INTERFACE_DESIGN Renaming a NetGroup does not work if several segments of the NetGroup trace have the same netnames assigned.% m* O- a9 Y5 o5 W- E' ]4 b- C
    1597406 ALLEGRO_EDITOR SHAPE            Dynamic Shape does not void the traces and voids open areas) }( X2 \  H0 Q7 x
    1597957 ALLEGRO_EDITOR PLACEMENT        Quickplace: placed and unplaced counts not getting updated4 Y( i* o% d; N6 t8 T  A0 F" J" R
    1600194 ALLEGRO_EDITOR DRC_CONSTR       'drc update' gives a different DRC count each time the command is given in a multiple-cpu system9 j1 N) p5 O5 M9 w3 L
    1600800 ALLEGRO_EDITOR GRAPHICS         LINUX 17.2 operation of Update DRC is not the same as Windows – graphics not updating1 D+ s: ~3 }) _% p7 A2 [
    1602605 CONSTRAINT_MGR OTHER            OrCAD: constraints not getting saved$ N5 Z- }. h/ F- E- |2 F
    1602801 SIG_INTEGRITY  OTHER            Dielectric Warning message when opening SiP tool.$ q( `$ B8 u" I
    1603377 PSPICE         ENVIRONMENT      Running simulation with the 'At Markers Only' option does not generate the .dat file( A) [# D  C/ k: [! [- f" O; D- c# \6 ^1 T
    1604166 CONSTRAINT_MGR CONCEPT_HDL      Audit ECSets does not work from 'Referenced Electrical CSet' column header
    4 w4 {( n$ b$ b4 C1604741 ASDA           CANVAS_EDIT      Tcl console changes the present working directory when you open Project Preferences and close it.8 p8 n0 @$ l# B+ K- y
    1605310 TDA            CORE             Join Project wizard: Random crashes in the Team Design Authoring option
    $ J7 n- ~4 j8 C1606861 CONCEPT_HDL    CORE             DE-HDL crashes on Linux during the Generate View operation( W  E/ {+ y" }1 t& T
    1606917 CONSTRAINT_MGR CONCEPT_HDL      Importing tech file in DE-HDL Constraint Manager is creating a duplicate 'DEFAULT' cset0 J1 [2 K# d7 m$ @+ A4 P  Z
    1607157 ALLEGRO_EDITOR INTERACTIV       Edit - Change allows lines to be copied to Cutout subclass, but that subclass requires closed polygons
    $ ^$ m# i9 t' \" E0 l, C1607330 CONCEPT_HDL    CORE             Variant view schematic PDF corrupted with attach_props set
    # ?3 p/ O; h) U/ I; n& z! [/ {1607568 ALLEGRO_EDITOR NC               PCB Editor shows wrong drill legend for Top-to-Top drill
    ' A/ t7 _$ u  ~/ d0 V1607986 CONCEPT_HDL    SKILL            cnGetSetupProjFilePath: The SKILL routine does not deliver the full qualified path and name of the project in 17.2. t# j( H1 \: d" {7 ?& K4 F" v( S
    1608524 SIP_LAYOUT     MANUFACTURING    The Display Pin Text tool fails in the 16.6.073 version with a parseString error.
    ( J. \/ r. [0 c3 G$ i1609400 ASDA           CANVAS_EDIT      The 'Assign Differential Pair' right-click pop-up menu command should be grayed out when a single net is selected8 V4 d$ o  s7 c; ^7 D
    1609809 ALLEGRO_EDITOR UI_GENERAL       Crash in Allegro PCB Designer version 17.2-2016 on Linux2 L- n- R/ V' Q$ G4 g
    1609856 ALLEGRO_EDITOR ARTWORK          Embedded paste and soldermask showing up in both top and bottom gerber files." ?. d- N% e3 c* d9 L" ^
    1609922 CONCEPT_HDL    INFRA            Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only
    , Y+ ]8 ?" F, B* A1611226 ALLEGRO_EDITOR SYMBOL           PCB Editor gives a crash message while saving a flash symbol4 t" ?5 D3 x2 R& i$ n7 t7 {
    1612108 ALLEGRO_EDITOR OTHER            Netlist Import is crashing with the .SAV message.
    : x$ N- f2 b9 I$ n1613123 ALLEGRO_EDITOR SKILL            DrillType for Oval Slot should be 'OVAL_SLOT' not 'OVAL SLOT'" w0 u3 e2 F' G% Z' w! c& G
    1614000 ADW            LIBDISTRIBUTION  Library distribution (lib_dist) does not complete; lib_dist.lck cannot be deleted when Configuration Manager is running
    7 P- s. q* Y7 ?1 s- q6 B2 B/ o1614667 SIG_INTEGRITY  SIMULATION       Different results from Probe in Allegro Sigrity SI and SigXplorer
    2 M7 j) M& S- _) `# A) f1615601 GRE            IFP_INTERACTIVE  Delete Bundle then try to delete plan lines results in fatal error
    ; r3 t' Z9 {" Q. C/ Y! Q; a1616235 ORBITIO        ALLEGRO_SIP_IF   oio2sip import does not map layers correctly
    ) S8 Y& g: J; u8 |( P9 A& u- j0 ]1616540 SIP_LAYOUT     DRC_CONSTRAINTS  Same net DRC Line-to-Line reappearing after dyn shape update
    . U9 F4 V- U4 l3 Y8 [% x4 I+ m5 o1616733 ALLEGRO_EDITOR INTERFACES       'genrad output' no longer working in 17.2. Gives the Error 'extracta process failed. Command terminated'
    1 s9 `) S- q6 t& U. ]/ J' H1618751 ASDA           DRC              Zero Node Net errors flagged when DRC checks are run, though RETAIN_ZERONODE_NET is set to 'NO' in Site CPM file
    , @" M: R+ m$ F1618797 ADW            FLOW_MGR         Flow Manager cannot execute a specific command in 17.2.
    / G& k! @* B' J6 Q2 B) k; ^1618930 CONSTRAINT_MGR INTERACTIV       Hovering over row column cell causes the application to go into a not responding state.
    7 T  `9 b4 t, A8 u* P5 f1620350 ASDA           EDIT_OPERATIONS  Pin number is lost on updating the version of a connector pin- J5 Z, E' D, o6 D% s
    1621963 ASDA           SELECTION_FILTER Selection filter: Pins in the symbol used in connectors are not selected
    : F: z' @2 E5 N2 ]- Q1622715 CONCEPT_HDL    CONSTRAINT_MGR   Extracting an XNet crashes DE-HDL! [8 g$ y; q' d7 |1 L
    1625209 ASDA           IMPORT_PCB       File Import from PCB Editor shows board differences
    & s$ \5 `& h* a5 {4 R  @$ O( u4 I- a* |: |5 \6 v

    - V1 e+ k9 G. I( @Fixed CCRs: SPB 17.2 HF003( O- \2 X- Q% y% G# V
    07-28-2016! Y: h8 E' \$ [: C4 b# S$ }/ C
    ===================================================================================================================================' |! X9 y; k" F* w- ]4 s8 L
    CCRID   PRODUCT        PRODUCTLEVEL2   TITLE8 @7 E2 }7 ]) P6 Q; a
    ===================================================================================================================================
    : ^( x+ s+ T$ H0 r1423889 ALLEGRO_EDITOR EDIT_ETCH        AiDT gets poor routing result
    + T' W4 T6 c( ]. |; B, l, h& j9 w2 E1461626 CONCEPT_HDL    CREFER           Cross-references shown to the same pin on different block instances though the signal names differ
    0 I* M1 l$ V: n' Y2 p: r+ q1 `* r1472456 CONCEPT_HDL    CORE             The design connectivity (XCON) file and design data are not in sync3 m# G* ]4 P7 h% L. u2 T9 f
    1546151 CONCEPT_HDL    CORE             Add port, Genview, move pin on block - the pin name disappears0 ]& i  H2 w9 O3 W( {
    1547356 ALLEGRO_EDITOR EDIT_ETCH        AiDT gives different results in ISR S034 and S066
    . ~* ^$ N! _9 v& a. x. E4 G1560102 ADW            FLOW_MGR         Flow Manager: None of the eval commands working
    / r  N6 Y- R4 \" Q+ d( _  e1570032 ALLEGRO_EDITOR GRAPHICS         3D Viewer shows flat LED for a specific design
    + `" d1 \4 a3 \3 J6 u1574676 ORBITIO        ALLEGRO_SIP_IF   Updating the OrbitIO database with a modified .sip file gives errors
    ( X/ L( j6 Q% \) B: R" A1578876 ADW            ADWSERVER        Component Browser crashes when trying to show details of a part number
    1 T* L& r+ d0 A2 C4 w1580744 F2B            PACKAGERXL       Running Export Physical results in error SPCODD-1148 U! O. t& o( C% r7 B
    1582863 CONCEPT_HDL    CORE             Generate View creates non-existent ports
    % q" ?7 t% Z/ k/ n6 Y  I/ w" r3 k1584317 CONCEPT_HDL    CORE             Provide an option to open pxl.log from the Design Sync window when packaging does not complete successfully
    ) c& B5 a# j. ~1587018 ADW            FLOW_MGR         User is prompted to specify the flow name each time the project is updated
    $ j0 p0 b/ A0 K5 F- ]1587157 CONCEPT_HDL    CONSTRAINT_MGR   pstprop.net reports conflicts on nets with VOLTAGE properties
    & w% @  D5 s% I1 D1587498 CONCEPT_HDL    INTERFACE_DESIGN Need the ability to tap individual bus bits
    3 J' a: H7 v# i6 j+ q3 k1587718 ADW            LIBIMPORT        Library Import - The Pre-analyze tool does not report errors
    : ]( X' Z' r* M% L- E1588197 ALLEGRO_EDITOR INTERFACES       STEP export fails when External copper is selected on Windows 10
    + h- h" _& R$ t$ P1588786 ALLEGRO_EDITOR OTHER            strip_design reports 'Design has been corrupted'8 G1 d- Z9 i8 N; _1 {
    1589252 CONCEPT_HDL    CORE             Search results zoom into the page origin instead of the selected components. S+ T; n! {- K/ y' m
    1589318 ALLEGRO_EDITOR DRC_CONSTR       Via to SMD Fit DRC reported between embedded pin and via which do not share layers& q/ H" l: f7 N+ s9 }7 r
    1589979 ADW            FLOW_MGR         Design Name change does not reflect in Flow Manager in the same session of a project
    : x; P& f! p9 L2 o) N/ d1590538 CONCEPT_HDL    DOC              Open Archive: Some observations on the random behavior8 j4 B3 u. Q6 z6 y& }9 Q2 C
    1590639 CONCEPT_HDL    OTHER            Importing a design in DE-HDL results in a crash
    : S# B+ i! l$ r1590651 CONCEPT_HDL    INTERFACE_DESIGN DE-HDL: Duplicate NetGroups created in Interface Browser and Constraint Manager
    7 ]8 R2 z/ R5 M) _# y2 I1590720 ALLEGRO_EDITOR INTERFACES       Exported Text Size Parameter file does not load names into the text table2 t- u1 `5 p. y
    1591070 PSPICE         PROBE            PSpice crashes when using the Trace - Measurements - Evaluate command
    - }- ^7 U) B" q8 n# D8 J/ Q1591223 CONCEPT_HDL    CORE             Variant information for lower-level schematic not displayed, L. j( b& c  ?+ v1 K
    1594240 CONCEPT_HDL    ARCHIVER         Archiver is not able to change the permissions of the cells archived
    9 d! x8 Y. L1 ?1594416 ALLEGRO_EDITOR PAD_EDITOR       Padstack Editor crashes when you create a new pad& K# K- @# e1 t/ p
    1596615 ADW            DBEDITOR         Unable to search parts: Component Browser did not launch; Database Editor did not return search results# P( I  \9 R, G/ ?
    1596780 ALLEGRO_EDITOR SKILL            PCB Editor crashes after doing SRM update and save" h, X: L  _3 l; w1 a: P
    1597153 F2B            DESIGNVARI       ERROR SPCODD-53 in Variant Editor' J! i; o% X$ A; [( F  v, i5 _; \
    1597385 F2B            DESIGNVARI       Some 16.5 variant DNI parts appear in 16.6 as X-OUT and some without X-OUT or DNI& j$ b+ U" e6 _. E' w4 y7 q/ b& n
    1598629 F2B            PACKAGERXL       Export Physical crashes after flagging error SPCOPK-1458
    * \: v3 i1 L! y- C/ t$ G5 b0 p1599452 ALLEGRO_EDITOR ARTWORK          Import Artwork with Mirror option does not import pins or shapes: H2 F. u; r0 A( g7 g  C
    1599744 ADW            FLOW_MGR         Flow Manager: Commands associated with some of the buttons not working$ ?" F6 L0 w' Z
    1599950 SCM            OTHER            Adding the GND net to parts/pins takes a long time.9 o+ B4 G' v0 {( [
    1600226 RF_PCB         AUTO_PLACE       Fail to auto-place RF group% W/ v  J0 }) Y
    1600618 ALLEGRO_EDITOR DRC_CONSTR       Casing of property names is affecting results when working with Physical Constraint Set
    $ }, J- F) S6 O2 T6 r* I1600914 ALLEGRO_EDITOR INTERFACES       Exported PDF has unfilled shapes despite enabling the 'Filled Shapes' option
    8 `* A" ?# g+ H( Q1601165 ALLEGRO_EDITOR DATABASE         Thermal Relief is not added for Rounded Rectangle pad7 @* D# L# j# s4 z
    1601281 ALLEGRO_EDITOR OTHER            STEP model link gets corrupted with SKILL axlLoadSymbol
    0 ^' a; _2 j0 j( |- d; v1601282 ALLEGRO_EDITOR OTHER            Export Libraries will not export device files when there is a space in the folder name.
    2 Y( n& _. Z, j" K( C) L" q1602514 PCB_LIBRARIAN  METADATA         References to some primitives missing in block metadata;TDA errors reported for missing parts after joining a project
    8 Q% t; r: a, @/ w. I1602823 SIP_LAYOUT     WIREBOND         SiP crashes when using the Add Wire command
    - |& M! `0 Y6 f; D  ~' ~' r1602955 ALLEGRO_EDITOR SHAPE            Shape to Route Keepout DRC not reported for attached database
    * G. [' x! u' K4 [5 b1 c+ P1604223 CONCEPT_HDL    CORE             Tool stops responding after error SPCOCD-553: Connectivity Server Error
    / ~3 h1 S. Z8 |7 j0 `1604746 ALLEGRO_EDITOR OTHER            In 17.2, layer data is getting changed when importing extracta files into other thirty-party extraction tools, _/ s2 J  E4 `8 m
    1605322 ALLEGRO_EDITOR TECHFILE         Generating tech file in 17.2 takes much longer as compared to 16.6
    / Y" t" f' H, p. v) [; ~8 F: f8 c4 {" D* ^1 L9 a3 g

    7 ^7 e9 b1 `# L& Z% D2 N3 ?2 P' [Fixed CCRs: SPB 17.2 HF002) E( W" h7 Q" S
    06-31-20166 O3 Z/ f: G, ?+ e8 I2 S
    ===================================================================================================================================4 T- b/ @/ w/ E; {0 _
    CCRID   PRODUCT        PRODUCTLEVEL2   TITLE/ n6 j3 u4 P8 |2 W& I( [
    ===================================================================================================================================
    : ~$ K0 A" u1 i+ f. i4 I* H1452838 CONCEPT_HDL    CORE             Apparent discrepancy between Bus names and other nets: J, ~" n. W9 [# c- j$ e
    1469146 ADW            LRM              Packaging error reported after updating the design using LRM
    $ B, V+ D. a/ |+ r! |9 z) _1481802 ORBITIO        ALLEGRO_SIP_IF   Import of an OrbitIO file to an existing SiP file offsets the results incorrectly7 w) q/ {' A" |1 B" c6 G; x4 C
    1518957 APD            SHAPE            Shape void result incorrect
    4 G" P4 x2 \$ u& z1519155 ALLEGRO_EDITOR OTHER            IPC-2581-B Negative Plane Error
    7 K9 A* \$ w% I" `1524947 SIG_INTEGRITY  SIGNOISE         Custom Stimulus is not recognized correctly in Allegro Sigrity SI or PCB SI.
    - A5 e; a8 X7 C  E8 T1532162 CONCEPT_HDL    CORE             The Rename Signal command does not update split symbols.
      \0 }4 t: [5 Q+ J7 J1 _1543997 CONSTRAINT_MGR OTHER            Import Logic is overwriting the constraints in the attached design.& p1 K6 w3 m# j) ~. _2 w( `
    1544675 ALLEGRO_EDITOR OTHER            Export Libraries corrupts symbols if paths do not include the current directory (.)
    + w, y! x4 r% Z8 a' A1549097 CONSTRAINT_MGR XNET_DIFFPAIR    Show warning message if differential pairs are created for nets with voltage properties- N1 J, L6 Z; ?8 d$ z! c/ B
    1551934 ALLEGRO_EDITOR SKILL            axlBackDrill command is not analyzing new layer set when application mode is set to 'None'- Q5 i& K9 ?3 d$ B' b( ]4 \
    1554919 ADW            LRM              LRM does not find PTF data for cell 'res' in the reference library/ O/ y9 R, {. g& q3 {4 b: @4 p
    1555009 CONCEPT_HDL    INTERFACE_DESIGN Unable to rename a NetGroup./ X4 j8 }1 D5 H; u
    1559136 ALLEGRO_EDITOR EDIT_ETCH        Cannot connect floating clines to vias with nets
    0 N  l. L2 P2 S0 N* R1559552 SIP_LAYOUT     ORBITIO_IF       device offset in oio2sip translation
    8 H/ `( V7 m5 c0 M/ Q6 y) B+ b1560301 CONCEPT_HDL    CORE             DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
    . D  t- g& _0 N2 e; G1560804 ALLEGRO_EDITOR OTHER            Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
    0 u* c1 M" c& A5 t% O* W2 B. d1561501 ORBITIO        OTHER            OrbitIO stops responding when refreshing a design in SiP Layout3 A- T0 R2 K. ~' p2 L
    1564036 CONCEPT_HDL    CORE             User-defined custom variables are not getting populated in the TOC
    8 I. |7 C6 n# A0 ~% S1564545 CONCEPT_HDL    OTHER            Signal model property deleted from an instance is not deleted from the instance pins+ U# P3 j9 J$ {3 P3 l
    1564552 CONCEPT_HDL    CORE             Find Net should zoom to the nets on schematic canvas( j5 [4 I3 m) q/ V/ I' n2 b
    1566119 CONCEPT_HDL    CORE             Right-clicking the schematic to add a component does not show all the schematic symbol versions: ]- Z3 u9 d/ I! o
    1566848 ALLEGRO_EDITOR ARTWORK          Board Outline artwork is incomplete  `# y. [! T8 z% i5 {+ R
    1566942 ASDA           MISCELLANEOUS    Several extra files in the /tmp/ folder on Linux7 S! w* W2 D; p7 u: b5 S; ]3 z; y
    1567290 ALLEGRO_EDITOR MANUFACT         Import Artwork fails to import a shape.5 ^2 K2 R0 ?# g0 f2 U
    1567587 ALLEGRO_EDITOR MANUFACT         Extended tool name in header of drill file is not correct0 o; m- p; I4 Y) _  m( w7 M+ }
    1569056 CONCEPT_HDL    CORE             Opening the same drawing in multiple cascading windows view displays non-existent artifacts
    $ _2 i9 ~: E! ^2 s, R+ g$ d, d1569087 ALLEGRO_EDITOR DRC_CONSTR       Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'
    . n: x) v) X" w) M, x1569147 CONCEPT_HDL    CORE             The signal name auto-complete drop-down list is not displayed correctly2 X1 S: N! ~2 M1 h
    1569394 ALLEGRO_EDITOR SKILL            axlPadSuppressSet( 'on 1 '(via)) not working on SPB17.2/ G  H# c( a# ^  o. P; G) s
    1569924 CONCEPT_HDL    CHECKPLUS        Checking in a large BGA into ADW results in an error related to negative signals+ {% W  ^  {, ^4 Y
    1570398 SIP_LAYOUT     DATABASE         Diestack layers cannot be deleted if there are unplaced symbols in the design5 {! j7 V3 i5 P1 j* {5 I, n
    1570419 CONSTRAINT_MGR CONCEPT_HDL      Need to add a customized worksheet custom property weblink in Constraint Manager4 x0 n% _- W: v: O0 I' g
    1570624 APD            ARTWORK          Artwork file has missing voids on a layer and is causing a short) p6 ?& D! ?5 ^8 V6 S+ C( {2 B
    1570678 F2B            DESIGNVARI       Variant Editor: Error when adding an RSTATE property) N0 d5 ]: ]7 W# R
    1571113 CONSTRAINT_MGR DATABASE         Reports generated from cmDiffUtility show the differences in mm units only
    1 w8 s" F$ e3 {1572593 ALLEGRO_EDITOR ARTWORK          ARTWORK: 'Draw holes only' option does not match display
    : G9 A- X2 e# m& t2 o, N1573127 CONCEPT_HDL    COPY_PROJECT     The CopyProject functionality creates an incorrect 'view_pcb' directive value
    + z2 z2 Y9 G: a" n; B0 O1573205 CONCEPT_HDL    CORE             dsreportgen is unable to resolve the physical net names (PHYSNET)
    2 a: E, Q$ Q6 D; v" _# m1573625 CAPTURE        PROJECT_MANAGER  Toolbar customization is reset when Capture is re-invoked in SPB 17.2
    " r7 R& ?# v9 }7 o6 \3 a. D0 \1573755 ALLEGRO_EDITOR CROSS_SECTION    Changing a layer's type is also changing its material in Cross Section Editor
    + W; H  [, U' l/ o( J1573970 CONCEPT_HDL    ARCHIVER         archcore fails to archive the project CPM.arch file9 x5 s( T: C8 B3 a# P
    1574381 CONCEPT_HDL    OTHER            Packager crashes on repackaging a design with RefDes related advanced settings
    1 u  B; U8 u/ [+ K1576100 ALLEGRO_EDITOR SYMBOL           Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'
    2 K( E& S+ b. D$ B" N% g4 k4 B. m1577381 CONCEPT_HDL    CORE             ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure
    $ W$ D% c9 K/ x2 V1580103 ALLEGRO_EDITOR DATABASE         dbstat of 16.6 does not recognize 17.X files
    6 x5 T1 `( F# |& L8 m1580891 SCM            REPORTS          Dsreportgen crashes in different scenarios
    ! Z  M9 G( r$ L' I% u' t7 E1581254 SIP_LAYOUT     CROSS_SECTION    Cross Section Editor crashes when adding a layer! R6 ^5 Z: C6 P
    1584957 ADW            FLOW_MGR         17.2 Flow Manager, JavaScript - Tool Launch Error
    ; A$ k& U& N4 C9 r  y+ Z& r1588823 ADW            FLOW_MGR         Flow Manager: In 17.2, using back slashes in the UNC path results in problems in working with the tool
    5 G8 v2 H5 R9 D! f2 r2 P0 w5 o1590064 ADW            LRM              Allegro EDM Flow Manager - An empty LRM dialog opens on design load in 17.2
    . c! b( P# A4 f* M+ |+ l
    ) a$ L& s. Y% h2 ^0 X0 A# n
    # H6 _3 p/ a. Z0 XFixed CCRs: SPB 17.2 HF001& _; f0 m- _: V; m
    05-06-2016
      S# {( Q- P, h( T===================================================================================================================================
    % v" ^- M# B. |4 Z# j" dCCRID   PRODUCT        PRODUCTLEVEL2   TITLE. G! }! O4 B: V# c. ^5 J+ H
    ===================================================================================================================================( t* o7 C/ T9 r* {
    1272355 F2B            DESIGNVARI       Property changes on replaced component shows incorrect result in BOM output% u0 |" G/ r* J1 A% z; m
    1482953 ALLEGRO_EDITOR DATABASE         Part change disassociates parts from Group$ i, Y/ j! g: |/ n
    1484075 ALLEGRO_EDITOR PADS_IN          'pads_in' imports ASSEMBLY_TOP  and PLACE_BOUND_TOP outlines that are defined as shapes as lines, z" c+ F9 B! l8 ~3 E; n: C
    1488909 ALLEGRO_EDITOR DRC_CONSTR       Test Via causes net scheduling verification to fail# k! M  m/ f) V2 T4 E6 U* w
    1498389 SIP_LAYOUT     DIE_GENERATOR    Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
    $ D2 b  M: o! d+ |/ t% m1499515 ADW            COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser) P& p; Q- X3 P: K5 T) T. i8 s& R
    1506672 ALLEGRO_EDITOR INTERACTIV       In the attached board file, when using Replicate Place, some shapes are missing from some layers4 |% D+ j# I9 r9 G" m
    1522411 FLOWS          PROJMGR          License selection should persist on invoking Layout from Project Manager' \$ D; l! L" }$ _
    1523532 F2B            PACKAGERXL       Adding subdesign names in the 'Use subdesign' or 'Force subdesign' sections hangs for more than a minute
      S3 U. R- F$ G$ B& F  C, m1525783 CONCEPT_HDL    CORE             '\BASE' scope does not work for SYNONYMed global signals: x1 H( v- O+ K4 l- e8 Q! w
    1526729 SPIF           OTHER            Exporting a dsn file causes PCB Editor to crash in the interactive and batch modes
    ) t# k% b0 d3 w$ ^1529846 ALLEGRO_EDITOR SHAPE            Some shapes are not generated in the artwork$ O* s$ I' ?- f) J
    1537499 CONCEPT_HDL    CORE             Adding the same version (already placed) with the same split block name should not be allowed' Q6 l% _  ^. u4 y; w9 h% J
    1541589 ALLEGRO_EDITOR INTERFACES       STEP model incorrectly shown in 3D viewer. Shows pins as angled.3 H0 V/ B8 L9 @- X9 I# {
    1542334 CONCEPT_HDL    CREFER           creferhdl leaving lock files in sch_1 folder# p6 w& I( K9 z6 Q7 |) S
    1542722 ALLEGRO_EDITOR INTERFACES       IDX export: RefDes and PART_NUMBER missing for mechanical symbols. J* y2 _/ ~- [& K; _
    1543410 ADW            LRM              LRM shows confusing part status; reports that update is needed but clicking update does not work: l( }: M2 J* P/ [( h" B4 J
    1544614 ALLEGRO_EDITOR SKILL            Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
    4 s2 S- P9 z6 N  s$ N1545370 APD            OTHER            Pads in .mdd file getting placed on different layers as compared to the design
    ! h% ]' C+ W4 c  X. A' m: G1545909 ALLEGRO_EDITOR UI_FORMS         Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license
    $ E0 K; ]8 D; g! O* W9 i( i0 {1546141 ALLEGRO_EDITOR SHAPE            Shapes missing from Artwork
    # j" X) a$ \: T! ?/ `4 U" |1546877 CONCEPT_HDL    CORE             Align Left on wires fails with incorrect error message4 L7 ]! D' y% [; M: S7 x
    1547224 CONCEPT_HDL    CORE             Lock the 'PATH' property once it is assigned by system
    3 n1 m6 `4 e1 h1547584 SIP_LAYOUT     OTHER            SiP - Design Variant: Delete embedded layer if not selected/ b4 D! ^; W4 j- S: ^5 `8 Q
    1548116 CONCEPT_HDL    CORE             Some versions of Technology Independent Library do not appear when adding a symbol
    ' \) S. }) Q! l$ ]; |1548151 ALLEGRO_EDITOR INTERFACES       Exporting a step file gives a component rotation mismatch in the *.stp file) F. P4 w' @, j4 e
    1548421 F2B            BOM              Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report% J4 o  \. U/ u% F9 N
    1548978 ALLEGRO_EDITOR MANUFACT         Shape not voiding clines4 \/ s/ A. K+ E7 y
    1549662 ALLEGRO_EDITOR OTHER            Import Parameters Path fails if parampath does not have the current directory (.) set
    ) v' }3 V! h0 Y) {3 ?) V1549836 CONCEPT_HDL    CORE             Tools - Customize - Keys - Reset does not reset keyboard shortcuts" A% ]& m! G& m9 ^$ t) ?
    1550941 PCB_LIBRARIAN  PTF_EDITOR       PDV Part Table Editor new column sorting causing problems
    . G$ B' R3 w, i2 J% y1551713 ALLEGRO_EDITOR DRC_CONSTR       Hole to Hole DRC between via and pin not shown% `/ W# {/ Q( X  ~& P0 e1 N
    1553950 ALLEGRO_EDITOR SKILL            Executing axlUIControl(pixel2UserUnits) crashes PCB Editor  t5 e8 u2 M$ h$ B4 x; _3 b
    1554333 CONCEPT_HDL    CORE             Changed connectivity error when aligning ports attached to NetGroups
    , U* l/ g( ~0 A  n' F! s# x1555092 SIP_LAYOUT     DEGASSING        Degas offset is not working with hexagons. j! h, @7 U2 s8 S0 K/ ~0 z! L6 z
    1556261 ALLEGRO_EDITOR DATABASE         DBDoctor crashes with the error 'Illegal database pointer encountered, Exiting DBDOCTOR.'
    : k& y# _  _8 @- l3 y8 R  r0 d2 D1557716 APD            OTHER            Stream out fails with request to terminate detected - Program aborted
    3 v9 j( O0 d2 `9 V8 U1559951 SIP_LAYOUT     SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor - Refresh co-design die
    2 D4 }) M! G' ]8 ]. b2 Q1560197 CONCEPT_HDL    CORE             BOM-HDL adds extra characters to subdesign_suffix when generating hierarchical BOM0 s8 T1 {  o. F
    1561077 ALLEGRO_EDITOR INTERFACES       Beta - IDX User Layer export fails on Linux2 M# w6 G+ j. V. y  s
    1562537 ALLEGRO_EDITOR MENTOR           Using mbs2brd in 16.6 gives a fatal error
    7 a2 f- M+ E; G: K, s, s1564203 ALLEGRO_EDITOR ARTWORK          Cannot generate negative artwork) H6 z: f& C1 W( T, W, \

    点评

    哇塞,大佬都整理过了啊。。。牛牛牛!!!  详情 回复 发表于 2019-11-8 16:08
    牛!不是一般的牛!  详情 回复 发表于 2019-11-5 15:24
  • TA的每日心情
    开心
    2025-7-2 15:09
  • 签到天数: 995 天

    [LV.10]以坛为家III

    3#
    发表于 2019-11-5 15:24 | 只看该作者
    lilacbear 发表于 2019-11-5 14:06/ F) E, U  ~3 m' U3 [! V
    Readme for SPB Release version 17.2
    9 R/ @! V: ]1 h0 X' e3 q7 `' {+ O3 g/ a! o8 n+ z
    Copyright (c) 2019 Cadence Design Systems, Inc.
    5 f! W( j  V6 Q. z1 L3 D
    牛!不是一般的牛!" ?' s" m" T8 V1 g5 ]/ o
  • TA的每日心情
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    2022-6-29 15:11
  • 签到天数: 378 天

    [LV.9]以坛为家II

    4#
    发表于 2019-11-5 16:01 | 只看该作者
    终于翻到头了

    “来自电巢APP”

  • TA的每日心情
    开心
    2022-5-6 15:29
  • 签到天数: 34 天

    [LV.5]常住居民I

    5#
     楼主| 发表于 2019-11-8 16:08 | 只看该作者
    lilacbear 发表于 2019-11-5 14:06# [( t. J: Q8 S$ j( C5 R
    Readme for SPB Release version 17.23 y6 U* {# x! y7 y0 g+ L# l

    ! G2 O+ y5 G& j9 z$ LCopyright (c) 2019 Cadence Design Systems, Inc.
    . D8 m- Q8 N* {
    哇塞,大佬都整理过了啊。。。牛牛牛!!!
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