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Readme for SPB Release version 17.2
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Copyright (c) 2019 Cadence Design Systems, Inc.
" g) f# G" {( {9 IAll rights reserved worldwide.2 j# W9 ]0 G* r- X
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2 J7 b3 a6 ?- i4 J+ O$ E+ G9 yFixed CCRs: SPB 17.2 HF060- @$ B6 N8 P' C( e$ Y0 g1 g1 h
10-11-2019( ^# Y$ M2 `+ T1 M
========================================================================================================================================================
" d5 }& m: {2 s" `CCRID Product ProductLevel2 Title
) T6 H8 Q1 Z9 m/ o2 j========================================================================================================================================================
E q+ j: c3 b2137594 ADW DBADMIN EDM is not allowing to modify step model/ l! R! o; @2 x, @! j" |3 ^) @
2115805 ADW DBEDITOR 'BOTH' in ALT_SYMBOLS prevents correct generation of part_table.ptf u- E7 N0 \& a' V; G& ]/ G( r- Q* e
2135452 ADW DBEDITOR DBEditor poor performance in high latency networks
" h# v' K. X* {2142315 ADW LIBDISTRIBUTI EDM Library Server stops often and adwserver.out file is extremely large, more than 1GB
: d L) U2 A: h2155396 ALLEGRO_EDITOR DATABASE Netlist error when importing from Capture CIS; e# `2 F7 v/ L; c% _0 ~
2118231 ALLEGRO_EDITOR DRC_CONSTR Crash during DRC: DBDoctor exits with error 'Illegal database pointer encountered'
8 ]7 ~& H, W3 d& D0 e1 J7 x2150923 ALLEGRO_EDITOR DRC_CONSTR Via at SMD fit DRC not detected with rounded rectangle pads* c; R8 G" z7 k3 p# c. Q5 y, u
2140441 ALLEGRO_EDITOR EDIT_ETCH Drill hole to line DRC while sliding but 'Allow DRC' is not selected in the Options tab( C$ e w' {( ]' ~* c; w
2141329 ALLEGRO_EDITOR INTERFACE_DES Error message (SPMHSY-49) displayed on running 'Tools' - 'Database Check'
- B: ^5 f4 C: ]1 l8 W; j2126562 ALLEGRO_EDITOR MODULES Create Module File / Place replicate assigns incorrect netname* m" F; e$ ~0 ?5 I1 x) X% s
2150410 ALLEGRO_EDITOR SCHEM_FTB netrev.lst is created in the wrong folder
- E+ n* T4 c. ~ K& g0 ]2136158 ALLEGRO_EDITOR STEP Update STEP Mapping Data Only should be seperate Menu/Command.- l) D S% p, Z4 B0 n" H
2137801 APD VIA_STRUCTURE High speed via structure instance not adding properly+ f2 l- A% C% V
2145072 CONCEPT_HDL CORE Error on choosing 'Enable Hierarchical Variant'& a# T, c) Y+ Y/ [
2124843 PCB_LIBRARIAN CORE Prompt displayed for license choice marked to be used as default/ J2 ~8 j. `+ d% D
2141656 PCB_LIBRARIAN CORE Part Developer pop-up option 'Edit' for symbols displays an error message9 E O( K5 V6 i) }7 t+ ~
2125794 PCB_LIBRARIAN SYMBOL_EDITOR Part Developer new Symbol Editor: cannot move inverted pins that contain circle and dot0 D, g; O0 M" o
2161864 PULSE R2PLM Second publish with CPM-derived item number and cadName set to $NUMBER causes 'an item is not unique' error
8 Y/ `1 U* C4 \( W$ o, e* J' t1997911 SIP_LAYOUT ORBITIO_IF Support keepout translation between OrbitIO and Allegro layout/physical editors1 F" n" v* X. e0 a! w- Y
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Fixed CCRs: SPB 17.2 HF059
( H& K0 n. b5 w k& j09-13-20192 F7 N) y( s0 c+ @1 `
========================================================================================================================================================
9 v! @( V* J: s. K* j9 U6 NCCRID Product ProductLevel2 Title( h. ^3 {: S, l* K
========================================================================================================================================================
/ J, y$ k7 |/ Y; ` R% s) B$ J- T% _2112454 ADW DBEDITOR Icons in DBEditor do not start applications after renaming a model
, C N, z: z+ Y2 c" |* }9 X2120548 ADW LIBIMPORT Missing alternate footprints from vault area after library import.
" K/ D" } O" a1 A+ H2143314 ADW PART_BROWSER Component Browser does not start after installing HotFix 057 of release 17.2-2016 S7 j+ c$ A; b0 T7 z: m
2122302 ALLEGRO_EDITOR ARTWORK Coverlay details not being output to Artwork data as per the visibility/ W& N- T" S% {! q: V% ]2 G( z
2135521 ALLEGRO_EDITOR ARTWORK Artwork dimensions do not match Allegro PCB Editor5 v) e3 ~3 m$ i% b6 N* ?( g
2054584 ALLEGRO_EDITOR DATABASE Through hole mechanical pin in zone area without Soldermask Top still shows a pad on Soldermask Top
C$ @8 P9 z! P' A, c% a2111444 ALLEGRO_EDITOR DATABASE No soldermask for mechanical holes within zone
' @4 l2 L: r, |+ P( y2115596 ALLEGRO_EDITOR DATABASE Unused Pad Suppression removes pin connected to shape using Net_short property
$ w, s7 s( [# _: f- o, s5 P2135436 ALLEGRO_EDITOR EDIT_ETCH Allegro PCB Editor crashes when routing with VOID_SAME_NET property on cline' P+ e( m4 ~& B
1825020 ALLEGRO_EDITOR INTERACTIV GUI ( Quickplace ) not adjusted to current resolution
# r7 ?' ?8 v! a2 C0 E' `1949705 ALLEGRO_EDITOR INTERACTIV Quickplace GUI not adjusted to lower resolution% X0 U" j. p0 P& v% q$ P
2023090 ALLEGRO_EDITOR INTERACTIV Dialog boxes do not fit vertically on the screen2 g* l" ~$ c% s% l9 t+ m# l# a/ W
2109940 ALLEGRO_EDITOR INTERACTIV Quickplace pop-up window does not fit vertically on the screen1 H) W" f% W( f4 J- b" A" V
2136823 ALLEGRO_EDITOR INTERACTIV Cannot resize or move dialog box to access buttons: I) p2 y' w5 t3 D# W. x! V2 S; ]; d, k
2116748 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets
+ w( O$ s/ T# X5 u2138977 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to HotFix 057; {9 Q' t! F( L5 e
2132628 ALLEGRO_EDITOR NC Improve the User Preference description for BACKDRILL_OVERSIZE_OPTION# B7 i2 y6 c( P5 i4 Z5 I
2152244 ALLEGRO_EDITOR SCHEM_FTB Netrev.lst is written in the package folder
; C \/ E6 ? C' d- Y4 |( F# n2152493 ALLEGRO_EDITOR SCHEM_FTB netrev.lst is not created in the correct folder - error displayed for neltist import- p5 e8 r( E0 E6 \# F5 ?" U
2104559 ALLEGRO_EDITOR SHAPE PCB Editor crashes while performing shape operation 'andnot'- _* _: j) l" [) a
2108207 ALLEGRO_EDITOR SHAPE No Void Overlap option is not working in AMB9 p8 J7 h& c- h7 ^% C
2125571 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes for a RAVEL rule7 R' p6 B$ |& Z& j* ^# W2 _+ K
2140707 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes on creating dynamic shape
$ h$ M3 Y8 z* h$ g2078434 ALLEGRO_PROD_TOOLB CORE Shield Router - cline end caps treated differently than cline-segment end caps7 a$ u0 | O/ u0 Y7 k! w. g" s
2101020 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC with multiple net classes: script selects only the last two classes in a group q W6 l7 X( [" E
2029279 CAPTURE SCHEMATICS Slow response when selecting parts in schematic1 Z- o, J, |8 j: C- {* _) @
2039931 CAPTURE SCHEMATICS Slowness in OrCAD Capture when ITC is enabled
4 ^8 l1 e, i9 Z& E8 c# k# k) i2106942 CAPTURE SCHEMATICS Inter-tool communication needs to be disabled to resolve the lag issues in Capture
: P8 M' L7 G: ~# |. h& c) E6 T: x2131683 RF_PCB ROUTING PCB Editor stops responding on using RF - Add Connect6 Q1 C9 j2 D) B
2126505 SCM OTHER Thevenin Termination dialog displays resistors incorrectly( O9 {7 `- S/ T; f2 y/ N& I3 n
2102383 SIP_LAYOUT WLP Advanced WLP Non-standard fillets not working properly: fillets not added8 A$ f/ H6 T- h& y7 }' e
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Fixed CCRs: SPB 17.2 HF0588 N4 h" S& s& f H7 |( O" r
08-16-2019* B ]1 z: z5 u n
========================================================================================================================================================
3 w6 M; n, g9 x2 g- B9 I; L3 tCCRID Product ProductLevel2 Title
2 |, q. F o& W, D( |========================================================================================================================================================
7 K* a6 `! @( W# a: S8 S$ m2113265 ADW LIBDISTRIBUTI Various DB operations take too long, rebooting server seems to fix the problem: f, G; O" A) s6 V: U* ?: }
2122941 ADW LIBDISTRIBUTI Lib_dist execution taking too long to run, Capture CIS DBC File appears to be taking the most of the time+ o: F) j" Q2 W0 H$ N; G) d
2127319 ADW LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250)
% i9 s6 K2 t# U& P8 n2 i! [2107578 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Canvas shows split layer
/ [# w1 u9 |3 w9 w5 R. X; L$ C2099538 ALLEGRO_EDITOR EDIT_ETCH 'Glossing - Via Eliminate' shifts traces to another layer
, s/ p S( O# o) v1 O2031883 ALLEGRO_EDITOR INTERACTIV Sub-Drawing: clipboard origin point is not set correctly0 ^' e9 V: f, w9 ]( Q' v
2100433 ALLEGRO_EDITOR INTERACTIV Pad Edit displays error for extents (SPMHA1-69) if pads are at 90 or 270 degrees
) r( u$ h& i1 r. i1 n2 H1 d: _2127239 ALLEGRO_EDITOR INTERACTIV Exporting a query result changes the working directory
$ g* ~3 l( x7 R i. b2117160 ALLEGRO_EDITOR MCAD_COLLAB Error encountered when importing IDX file into MCAD tool in HotFix 056
& H8 T! D4 h# Q2117427 ALLEGRO_EDITOR MCAD_COLLAB IDX files exported from HotFix 056 cannot be read in MCAD tool (the same files from HotFix 055 can be read), ^& d& ~% R( U0 J
2117839 ALLEGRO_EDITOR MCAD_COLLAB IDX file created from release 17.2-2016 with Hotfix 056 is not readable in MCAD tools1 d1 y2 `2 D& m5 Q) X' a I
2118019 ALLEGRO_EDITOR MCAD_COLLAB Export IDX is not working in Hotfix 056 but working in HotFix 055 i* k0 t2 m" D
2106425 ALLEGRO_EDITOR NC Disable undersize regular pad and oversize soldermask pad for start layers
0 v8 T0 b6 A# U1 _! B2126766 ALLEGRO_EDITOR REPORTS Cannot generate reports and export ODB on board& H' T' f ^1 M$ g+ }0 Y( K8 c
2107849 ALLEGRO_EDITOR SHAPE PCB Editor stops responding on updating shapes: k4 Y- F5 H/ r3 h
1778109 ALLEGRO_EDITOR UI_GENERAL Constraint Manager exits on doing 'Undo' in PCB Editor
5 R7 |2 }+ ?4 \+ ~2064092 ALLEGRO_EDITOR UI_GENERAL Allegro Constraint Manager closes on clicking Undo in the layout editor( i* h7 s* G. ~' q: m. T7 R$ r
2093341 ALLEGRO_EDITOR UI_GENERAL Show Element incorrectly displays in report window on a single line if an HTML Report is open when show element runs$ y% K R& [+ M9 r" s; Z b) [
2110909 CONSTRAINT_MGR UI_FORMS Cannot type dot (.) in DFA Table of Package to Package Spacing in DFA of Constraint Manager.
( b' P7 a Z! f: U6 i' ^2096846 INSTALLATION ADW Component Browser does not open if adwservice.exe is not added to the Windows firewall exception list b Y. O7 {$ t. B* M
2128118 INSTALLATION ADW Unable to connect to Component Browser." r. G/ g& H2 j$ A
2116749 PCB_LIBRARIAN OTHER Cannot open Part Developer with a Venture PCB license (PA3810) v a0 y/ Y; M Y( p6 G, T3 ~
2115302 SIP_LAYOUT IMPORT_DATA Performance issues with die text in and pin use codes, function utcle pwrgnd, N v4 \. M1 u9 u9 l! W9 w7 V
2103784 SIP_LAYOUT MULTI_USER Symphony Server rejects the move void commands on a specific shape instance3 A2 M0 \2 V1 X2 S0 R0 W) Z2 Q/ z
2096239 SIP_LAYOUT STREAM_IF Database fails to create stream out file
" _' M4 f1 S# p; X' B4 j2 o; X" ?, O2117572 SYSTEM_CAPTURE EXPORT_PCB System Capture crashes with multiple Export to PCB Layout
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: t" e: q, x5 ?7 K6 RFixed CCRs: SPB 17.2 HF057
3 }, [! D; g* S# L+ c9 l" a0 D4 X+ [07-19-2019
' E2 F6 j: w2 U; R1 ?========================================================================================================================================================8 C. E; U7 p3 R' l: u/ X* F) b4 Z
CCRID Product ProductLevel2 Title
: F: ^( v4 ?9 T Y) I. M========================================================================================================================================================8 C8 E& X7 h# i" Y2 z
1920958 ADW ADWSERVER Designer server will not start due to corrupt inr file+ A$ s& U* b; u f1 `2 X$ W1 r
2039243 ADW LIBIMPORT libimport ignores footprints generated by Library Creator due to changes of attribute names2 o# R& w% F% y3 v. D E
2113226 ADW PART_MANAGER System Capture stops responding while importing DE-HDL sheets
8 r# A L4 [5 i+ o* x2 s2035942 ALLEGRO_EDITOR ARTWORK 'Create Artwork' is slow when all films are selected
' K% F* R4 @" K! l5 o2096958 ALLEGRO_EDITOR DFA Cannot launch Constraint Manager after assigning CSet and closing1 ]% K% }0 Z6 I% R t7 Z$ b
2087181 ALLEGRO_EDITOR DFM DFM reporting false positive hole to hole with stacked microvias
; ]* s) ?- \4 s4 Y' J2099400 ALLEGRO_EDITOR DFM Placing a mechanical pin on a cutout causes PCB Editor to crash
. O8 ?, C: T; u. Y/ F5 j. v2067214 ALLEGRO_EDITOR DRC_CONSTR Constraint Manager crashes for design linked board' N) [$ y. C! y
2097464 ALLEGRO_EDITOR MULTI_USER Design data lost if network connection drops in Symphony
5 }3 v; e- g4 x' j* G) w' {. w2108211 ALLEGRO_EDITOR MULTI_USER Error: Update #1 (Perm shape) was rejected by server8 m8 e K! |) `) l, o+ Q) [
2117154 ALLEGRO_EDITOR MULTI_USER Error message needed for Symphony for client disconnections W! k- G' g7 u- P ]
2100149 ALLEGRO_EDITOR REPORTS Error message (SPMHDX-9) for too many field names while generating dangling via report
! u( ^7 _" c6 i8 l. f2101932 ALLEGRO_EDITOR REPORTS PCB Editor internal error (SPMHDX-9) for too many field names when running BOM report
4 W+ e0 }( U" {. D2111449 ALLEGRO_EDITOR SYMBOL 'Layout - Renumber' results in error
( ]- D' P0 ^" q3 c& z/ C1 q2102177 ALLEGRO_EDITOR UI_GENERAL axlDMBrowsePath returns incomplete information
* Q5 G9 `$ r; L/ k6 t; t B- U2105342 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding for 'Show Element - Find - Symbol Type' on a particular board
6 h% T* [+ J1 n2 I& {( L; t% J6 w2085443 APD ARTWORK Gerber lacks precision required to void some vias for a design in artwork output: need warning' H* H- r* O; E6 c& K; k
2080118 CONCEPT_HDL CORE Getting error after adding offpage to bus and assigning a new value to $sig_name
% t1 T' Q& d, A$ l, ^2099438 CONCEPT_HDL CORE Genview allows dragging group of signals in split symbol distribution form8 k: ^ U; X% D/ m" Z k( M2 r7 I
2108289 CONCEPT_HDL CORE Variant data is not in sync with the packaged data9 U& M: f' [/ a
2087217 CONCEPT_HDL OTHER Variant back annotation will not work if there is a double quote (") in the description field of a part1 d) x( L. t) Z5 s$ w3 }5 u+ _- O P- h4 U
2107430 CONCEPT_HDL PAGE_MGMT Insert page is not working
# g% P, I2 f P8 f2063875 CONSTRAINT_MGR OTHER PCB Editor crashes on deleting match group without closing Constraint Manager6 o: n3 p0 u* L8 N6 d
2103729 F2B DESIGNVARI Cannot enable hierarchical variants for block! p u8 k9 v$ g* |( c& X
2099076 F2B PACKAGERXL Package fails for 'Save Hierarchy', but succeeds for 'Save': ^. c# ~/ J* O( _- y
2081132 INSTALLATION SPB Part Information Manager cannot connect to EDM server after upgrading to HotFix 053) H8 K0 r$ w% p5 b3 A
1599964 PSPICE ENVIRONMENT Version Info displays 'OrCAD Version Viewer MFC Application has stopped working', g2 C: H& r! @" b& G( P1 e9 L
2045497 PSPICE SIMULATOR 'Illegal Parameter Value in File' error when loading Monte Carlo parameter file7 f1 y( q: b' G2 I# z7 W
2025997 SCM TABLE Copy-Paste Broken in Physical View8 `- {1 n* w! U, a, ^" E: z& _" ^" j* B
2102652 SCM TABLE Unable to copy the Associated Components Ref Des values to Excel' |4 P" w+ i- V" W
2054225 SIG_INTEGRITY SIGNOISE Cross Section Editor bug after changing the impedance value in Analyze - Preferences
( a3 o+ O: s# _2 }& l/ A2100075 SIP_LAYOUT DIE_ABSTRACT_ Refresh co-design die running slow6 l. l o1 b' v+ {; M3 S: Z
2106312 SIP_LAYOUT DIE_ABSTRACT_ Die abstract I/F to bring into SiP Layout and OrbitIO power/ground and signals not designated as RDL
4 h- ]# s9 I3 _: g* d2106314 SIP_LAYOUT INTERACTIVE Large design causing severe lag in Windows Server machine
4 x% m* n7 k/ ~+ a& G P2101622 SIP_LAYOUT MULTI_USER Symphony Server rejects the slide commands when tapered trace option is on
/ @! y, `6 _( T, i2 P2107897 SIP_LAYOUT WIREBOND Design stops responding when running Wire Bond Auto Spread in HotFix 055
}$ s# w& E" ~% R" Z' Y; y2104885 SIP_LAYOUT WLP Advanced WLP: Metal Density Scan, scan area in report is incorrect
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1 d) }, L" u/ F* X7 aFixed CCRs: SPB 17.2 HF0561 p7 [0 ]) z# W( V6 j! l i* T
06-21-20193 M' g2 b* o# w( i z6 C
========================================================================================================================================================
% ]5 J3 C" x1 t, H# O6 { hCCRID Product ProductLevel2 Title
( l: D% P0 x# g C n7 V/ e9 g6 p========================================================================================================================================================0 P- T1 E- k6 W }1 j5 R: f2 Y) Z. L
2086463 ADW PART_MANAGER System Capture cannot add components when accessing remote machine via Citrix
8 [1 a9 W, V) g2092868 ADW PART_MANAGER Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not to flow from pstchip5 D: T: R/ X2 q9 X
2092872 ADW PART_MANAGER Import DE-HDL Sheets stops responding
- C9 b( {) D3 g0 j H5 f2088975 ALLEGRO_EDITOR 3D_CANVAS Bending in 3D Canvas causes PCB Editor to crash3 f: d' }5 @/ K4 T! G2 x' _
2088577 ALLEGRO_EDITOR COLOR Export color nets does not write all the nets in param file
' {% N" s: y8 A2 r3 t; j2028867 ALLEGRO_EDITOR DFM False DFF Trace to Thru via pad spacing DRC
. a' x) t- N6 d% w2037361 ALLEGRO_EDITOR DFM Soldermask features drawn with a line do not DRC to pin, via, or shape soldermask features
4 r! ~! P" h0 x0 s u* |2077913 ALLEGRO_EDITOR DRC_CONSTR When running a simple SKILL command, the tool will run for a very long time( n A8 ^; }( L# Z* C1 [: I
2079642 ALLEGRO_EDITOR DXF Drill symbols are rotated in exported DXF in release 17.2-2016
3 z9 @ }0 y ~, ~2083493 ALLEGRO_EDITOR MANUFACT Manufacture - Cross section chart is not readable for rigid-flex designs/ N- _9 v% s$ c: O7 S
2073607 ALLEGRO_EDITOR MCAD_COLLAB IDX_IN batch program to allow a batch update of an .idx file
, B1 I) h0 I* U _2095632 ALLEGRO_EDITOR MULTI_USER Design server on Symphony stops responding and cannot be closed or downloaded
( g, W! A9 R9 a- o& j2098221 ALLEGRO_EDITOR MULTI_USER Symphony Server Manager allows connection to databases deleted from the project area4 }# E, L$ e' I! a# ]. G6 w
2087315 ALLEGRO_EDITOR NC Backdrill exclusions raised on pins of a component
+ u0 v/ Q* I, p" U1947929 ALLEGRO_EDITOR OTHER The 'show measure' function crashes when measuring pin to pin distance" w \0 U% w' Q$ C
2091932 ALLEGRO_EDITOR OTHER Unsupported Prototypes command missing for the OrCAD licenses
+ d3 i9 m; c6 m4 ]' p3 W3 ~2089470 ALLEGRO_EDITOR REPORTS Summary report shows the exclamation character (!) in the middle of numbers and words. b1 h# Z/ {/ ^" Q, e
2067324 ALLEGRO_EDITOR SHAPE Netin crash during third-party Netlist import
' w+ O+ M+ c) |+ }! |; m4 K2075191 ALLEGRO_EDITOR SHAPE Delete islands in the design: update out of date shapes and Database Check& \6 ?2 b3 {( k6 z* G& F) |
2090604 ALLEGRO_EDITOR UI_FORMS Undo/Redo UI grayed out when invoking Color192
. Q' ^9 |' y4 z+ B( m2043825 ALLEGRO_EDITOR UI_GENERAL Custom toolbar settings are not retained upon restart of Allegro PCB Designer
2 J' v2 L% H( M2 O) V' j2 U6 \2090185 ALLEGRO_EDITOR UI_GENERAL UI setting in INI file not retained; z" X' U$ A1 T d C
2090517 ALLEGRO_EDITOR UI_GENERAL Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane
- k# n1 w% E. }' r; d2092436 ALLEGRO_EDITOR UI_GENERAL RefDes length of input string for Modify Design Padstack is limited to 20 characters' a) `2 c1 m2 Z9 R8 [: O2 \
2099070 ALLEGRO_EDITOR UI_GENERAL UI setting not working properly, Icons missing after restart.
/ X( @" \! w G: t4 Q2088484 APD DATABASE Some objects (Vias and Cline) cannot be modified (edit, delete and slide) in the mcm database
# F$ }8 g0 D4 G$ T6 i! v1951623 APD DEGASSING Shape Degassing fails with specific Void to Shape boundary value
- C% ]' |3 v1 F+ [' E2081363 APD DEGASSING Cannot degas for specific shape4 D& i5 {( }; a7 V( [; c
2083498 APD WIREBOND Cannot wire bond from a diepad to another diepad on the same component
3 q# y) ?7 j/ I0 s# d: Y0 j* E2086589 CAPTURE NETLIST_ALLEG The generate the CM enabled files from the command line using pstswp.exe.2 D# A. Y3 s- B( l3 ~
2098248 CAPTURE NEW_SYM_EDITO Ignore pin is not working for individual pins in Edit pin spreadsheet when edited for all pins
( z- Z [5 b0 G# d1773047 CIS PART_MANAGER Pin numbers and names for DNI parts will get disappeared in variant view mode if they are relocated in part editor
$ X. z- l! v. Q# c2003818 CIS PART_MANAGER Pin name and number of 'do not stuff' parts are not visible in the View variant mode/ B8 b6 T! H2 S- ]# `: V, F
2076265 CIS PART_MANAGER Variant view pinnr/pinname disappears9 d1 G; L- n! H* B$ Y
2076282 CIS PART_MANAGER View variant does not show pinnr and pinname2 c: V& Q2 G, `
2083394 CIS PART_MANAGER No pin names and numbers on variant view for specific parts
& t6 v6 k- Z; V. x* p/ G. j" ~2090027 CONCEPT_HDL CORE Cut and move of split hierarchical symbol to another page results in error due to lock or write permission issues7 B$ ] N% O. Q( y9 `
2071355 ORBITIO ALLEGRO_SIP_I Dummy nets creation in die after performing Merge Updated SiP) d3 c( E9 F, w0 Q% w( N8 L
2067703 PCB_LIBRARIAN OTHER PDV crashes immediately for vector pins if MSB is lower than LSB
U) ] f h, Q8 ]2041348 PCB_LIBRARIAN SYMBOL_EDITOR Grid setting change cannot be saved in new Symbol Editor
$ q1 I# f2 K" v+ \" R) w0 U2041365 PCB_LIBRARIAN SYMBOL_EDITOR Improve copy drawing objects in new Symbol Editor% r! x& n- a; O1 G. G1 T
2067931 PCB_LIBRARIAN SYMBOL_EDITOR New symbol editor grid issue: documentation grid spacing value changes
; y" V2 @) v2 u" F5 G: H$ X7 p& U2093849 PCB_LIBRARIAN SYMBOL_EDITOR Symbol font text and appearance different when placed in Schematics, d- ~! D) w. `& H2 [6 Y
1919298 PSPICE FRONTENDPLUGI Capture crashes on archiving project6 B6 B3 N" k5 B( `6 o4 L& C
1953001 PSPICE FRONTENDPLUGI Archive project causes Capture crash.! B5 f9 t6 o% k: d& N7 |* Z# \
2035572 PSPICE FRONTENDPLUGI Crash on archiving project
: v: E" J( |) r' K& B2041286 PSPICE FRONTENDPLUGI Archive project crashes when using lib as global.
) U# z- _ g! `+ n3 E9 M9 a% f2081796 PSPICE FRONTENDPLUGI 'Archive Project' crashes Capture in release 17.2-2016, HotFix 0531 l% f& M. q1 S) `
2106017 PSPICE FRONTENDPLUGI Capture crashes when archiving PSpice-enabled project7 s$ B7 Z5 B1 f9 q" A8 Q
2051450 PSPICE PWL PWL Sources application: pop-ups and messages when browsing and placing source/ h/ ]6 f4 v) }
2090021 PSPICE PWL Modeling Application - Sources - PWL Sources Dialog is not properly displayed
; J* l9 G; J4 U. e7 a& L/ v K3 w2094548 PSPICE SIMULATOR Model undefined error on TL494
0 B# p6 j0 s" H4 F& F! b ~% |2058018 SCM PACKAGER Reference designator mismatch in 'exportsch' schematics and board file
7 K: c( w* U8 ^. T1955868 SIP_LAYOUT STREAM_IF APD/SiP Layout: Export rounded features as circumscribed and not inscribed polygon in GDS' B. p+ i; s' V$ Z
2081914 SIP_LAYOUT STREAM_IF Release 17.2-2016: GDSII stream out drops shapes9 G' F$ F- @6 f+ t
2013647 SYSTEM_CAPTURE CANVAS_EDIT Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections) \0 Y8 C4 |/ Q' T7 N. T9 d8 b: O* m
5 P) c6 T7 L4 K
" W. |; e2 W3 Q/ z! [* A0 J
Fixed CCRs: SPB 17.2 HF055( [3 w ?! f+ W2 K6 _
05-24-2019% u- j5 k' u/ b5 \6 \: G' b! a2 {/ I
========================================================================================================================================================
+ R8 K$ \' f O3 c7 ~ a1 c9 Z& fCCRID Product ProductLevel2 Title( t4 @7 l6 N/ [4 Q- X+ e
========================================================================================================================================================' S. p! i+ z$ ]5 X. o1 y
2078057 ADW PART_BROWSER Symbol Graphics preview is not available in the Designer Server- y& I3 S, m! v% X6 S
2092863 ADW PART_BROWSER Component Browser is not displaying the symbol & footprint preview2 Y$ }# K& v: U e
2076339 ALLEGRO_EDITOR 3D_CANVAS Floating parts on bending a board in 3D Canvas with HotFix 053
1 R4 h4 b# y1 f8 ?2051075 ALLEGRO_EDITOR ARTWORK Incorrect Gerber import in Allegro PCB Editor8 j& U# B7 I: x% }5 X
2073407 ALLEGRO_EDITOR DATABASE axlDeleteByLayer deletes fixed shapes# O: i" w* y/ b3 H
2079117 ALLEGRO_EDITOR DATABASE Release 17.2-2016: Board file saved in HotFix 049 cannot be opened in HotFix 014% p! a( x$ P! G6 ^. @; @
2079204 ALLEGRO_EDITOR DFM Enabling option to update analysis mode and run DesignTrue DFM wizard causes PCB Editor to exit
1 W! N! z/ P% l" t& B$ ]. i2082394 ALLEGRO_EDITOR DRAFTING Angular dimension not owned by the same parent symbol in the layout are not deleted on moving object7 o X5 o/ n- w. b
2067916 ALLEGRO_EDITOR INTERACTIV Place replicate module bounding box does not move with circuit after module is updated
& X B3 ?* _; |7 X. O2068449 ALLEGRO_EDITOR MANUFACT Stackup chart and table shift slightly from original location on re-generation in Allegro PCB Editor release 17.2-2016
9 }, x' i: l7 X- u( f2065820 ALLEGRO_EDITOR MCAD_COLLAB Selected objects deleted from the design on clicking Cancel in IDX Flow Manager Import. a) O3 Y* _* K* r+ ^7 ^. P- _& J9 h
2080164 ALLEGRO_EDITOR MCAD_COLLAB IDX outputs two sets of masks
# a/ Y( W2 w! F1 E1 q/ F2081955 ALLEGRO_EDITOR NC Artwork file error for via size
! h- k. f! z4 j* A4 s2045061 ALLEGRO_EDITOR PLACEMENT Setting PSMPATH: axlSetVariableFile() does not update Place Manual but User Preference Editor does
8 c* y: V1 `4 V( j. E- v# x3 K* t& x2049949 ALLEGRO_EDITOR PLACEMENT Get import errors and cannot place some parts if user-defined option is turned on for netlist import+ f2 b0 P6 d, ]7 S0 x# a
2069289 ALLEGRO_EDITOR PLACEMENT Cannot place part because attribute definitions are incompatible for the 'DESCRIPTION' attribute (SPMHDB-154)
5 g) q1 F5 \9 v6 Q7 V+ t7 F& [% s2056573 ALLEGRO_EDITOR SCHEM_FTB Import Logic takes a long time when checks are turned on- X+ Z$ s0 K- r; L' z0 p
2076452 ALLEGRO_EDITOR SHAPE Shape Degassing crashes if 'Inside Shape' is selected
/ |8 ]' I2 J: x" ^) n2076873 ALLEGRO_EDITOR SHAPE Symbol Editor stops responding on editing shape with a .dra file
1 |3 p% J. m: P1 U0 y1 F1788703 ALLEGRO_EDITOR SKILL axlPadSuppressSet does not work when 'none' switch is used; r: p! P7 C* \3 e
1955127 ALLEGRO_EDITOR SKILL axlPadSuppressSet( 'off 'none ) returns a warning message and does not work per the documentation
) u: R5 w" t* O& i+ `# P0 N$ ^. d2031711 ALLEGRO_EDITOR SKILL Syntax error related to allegro.ini shown if allegro.ilinit loads INI on startup' u7 ~$ i( `$ F$ l
2062527 ALLEGRO_EDITOR SRM RF elements are shown in Symbol Revision Manager
4 {: Y' q! y, K4 e2 K2 w2074249 ALLEGRO_EDITOR TESTPREP Testprep re-sequence causes PCB Editor to crash if 'Labels with Net Name' is selected
" D! \9 { U* H6 P- T- y3 C$ u2070534 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox bar code generator is creating corrupted shapes in the database# i% W A- D4 U
2046278 ALTM_TRANSLATOR CAPTURE Third-party import fails. A5 B; X& d; l2 U$ \
2052399 ALTM_TRANSLATOR CAPTURE Third-party CAD translation stopped with error message9 E: H! N, |3 q+ b/ h
2005087 ALTM_TRANSLATOR DE_HDL Cannot translate third-party to Allegro Design Entry HDL
& B% @/ N, _' c4 }4 n3 D4 M& ~/ a$ R1922222 ALTM_TRANSLATOR PCB_EDITOR Third-party translation converts to board with unconnected nets+ p2 R9 e" K8 ]9 M9 Z
1987263 ALTM_TRANSLATOR PCB_EDITOR Third-party board file: copper not imported2 m6 e. V! M$ ^0 |
2017988 ALTM_TRANSLATOR PCB_EDITOR Third-party to Allegro PCB Editor import issues with routes, constraints, size, and accuracy4 f" |" R Q1 c% e1 R" H" G
2021300 ALTM_TRANSLATOR PCB_EDITOR Third-party translator does not show any results on PCB Editor canvas
8 j% n- t% n2 K, d: z! U1890675 APD DIE_EDITOR Mirror Geometry is Mirroring the symbol from TOP to BOTTOM Layer in SIP file
; M4 r+ `2 b! U" ~* [, ~2064219 APD DIE_EDITOR Applying mirror geometry results in mirroring: moved from TOP to BOTTOM layer) X0 a7 }" o3 S) r% ? ^
2086574 APD OTHER Duplicate layer text shown on the vias
3 Z# Z+ z5 ]8 ], A1 e# q1 ]5 {1948169 CIS CONFIGURATION Auto Symbol Refresh Checking not working for shared folders' W R) @3 i! g7 v8 N/ `
2025385 CONCEPT_HDL CORE Hierarchy Viewer expands/collapses randomly after clicking the '+' or '-' symbols' e4 \. e2 |6 Z7 D! w8 b( w
2050010 CONCEPT_HDL CORE Copyproject does not properly copy the variant files
5 s3 v) @* X r/ j+ f: ~% R7 L* E2063457 CONCEPT_HDL CORE DE-HDL: very slow rendering on some systems9 `7 @$ ?4 j T. U0 h
2076312 CONCEPT_HDL CORE Getting 'Variant out of sync' warning when creating BOM for a design with no variants2 z/ T% I5 y. ]# @) r
2083650 CONCEPT_HDL CORE Lower-level signals are appended with _1, _2, and so on
# h. K1 d: E% H+ u5 R2 X2083651 CONCEPT_HDL CORE The physical net names still do not sync with the assigned signal name; t) P: l( Y% j& w
2056736 CONCEPT_HDL GLOBALCHANGE Global Property Delete does not operate on the entire design unless the top-level page 1 is open/ Y* Q5 Q- l0 F' E: W5 k6 f
1955357 SIG_EXPLORER OTHER Signal explorer invocation with OrCAD PCB Expert Suite license
$ p+ q5 ~/ X% G {1 {$ n+ ~! h/ b2079071 SIP_LAYOUT SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die
* j+ ?( b; B6 \: t2081884 SYSTEM_CAPTURE CANVAS_EDIT Symbols take a long time to move, and results in DRCs and broken connections; C6 S& i$ ]$ J1 t7 P0 Q
1942542 SYSTEM_CAPTURE IMPORT_PCB System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks r8 o( ^' Q- {/ ?, C* o2 h/ c
2071303 SYSTEM_CAPTURE MISCELLANEOUS cds.lib file is picked up from wrong location
" y) y5 i. @- K0 B$ R" K' ~2058979 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture prevents a project from opening by putting a single quote at the end of a line in CPM file Z- X( M7 `, t; ?& B3 p6 i
2088210 SYSTEM_CAPTURE OPEN_CLOSE_PR The 'enable pspice' entry in CPM file is occasionally corrupted
( d% @3 G& L7 X0 D# P; w; S! ^- d. m1 Y. |/ X+ Z$ E* f! @3 t7 X
. _5 W/ c/ o$ _+ w0 ?5 c; J1 x
Fixed CCRs: SPB 17.2 HF054
' f9 X5 h/ _% {' A8 M' Q( d04-26-2019
+ `8 ]1 ~/ N" \8 F* S' y% I========================================================================================================================================================4 s3 e [- G& J
CCRID Product ProductLevel2 Title
5 Y& U- y( Z" b4 T& Z========================================================================================================================================================
" ^6 M! A) }4 J. ?1 q2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes4 b- y, Q' h% i
2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property
6 u* R' w* i1 X. e) J% S1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser
6 C! O, ]/ P i _# W5 v2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache
& ?6 }. H8 S& L- O' D2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
; H6 b; d! }* y' ?2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design& t6 ]: S. L. N9 _9 G
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object5 ^2 J5 x! N4 q" |; M' C- o
2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas2 Y) L# t) H/ u
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation5 S# Q3 k# a- ~$ u1 \
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded, d8 e/ Z4 F2 l, p: T @
2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off o& p/ y/ l5 z* H
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set3 _& B8 }. M7 Y/ H. L- W0 @
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
# n% E0 `# R, l- s0 {; b8 s* Z2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements
$ J0 `, i, X( h- D$ B2 j5 H! S% O# T% j2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin
" t7 W+ k5 D M6 _2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element
1 F( a4 ?: k9 r8 f5 s2056497 ALLEGRO_EDITOR DATABASE Place manual is slow
9 v/ u2 v, ?. A2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error# \. N& y! t n: m
2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code0 { h$ n; r1 g7 ]% |$ u3 C7 D
2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016& e/ ]. w2 s0 m$ R
2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
. U. Q0 j7 Y% a2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets
8 D4 s/ f( E; K, A3 v2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.
/ ~) a1 [4 p* U6 E' \; P6 l0 W2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.1 p% Q) X o" d, Q
2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'+ L2 Y9 K# Z/ J: E) @
2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations$ i1 g) {- Z4 H2 b
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
- u9 ~/ D6 f* y0 y9 U4 T2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill' _- s. r+ p8 d
2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets2 G* {0 K4 i x% t {& o Z
2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor P0 t2 l4 C8 F
2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias
1 n* K9 t# I5 O# y8 \2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor
* u! [1 l* }' U& J% ~2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable1 V, B4 e: C2 v% B1 j' T0 H% O0 m/ C: r
2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components
# H% { S( r5 ]% K% o2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report
! F" g7 h: l7 p; a2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL
6 O2 [2 a) D& ^0 p$ h( l1 ]% p2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window% x p9 a. h y$ I( D# u, j
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update9 V& d( c( E: N5 t5 @
2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'
4 A( M5 D" U# N I2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape- v1 A/ {& c! V( c* j
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present, w% ~0 D( g* g! P3 i2 i: B
2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes* `) F* X, p3 x; v! r' i5 [
2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'
9 r" T, x9 N7 k3 ?) N; ^2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
! _ @; B2 `: @5 S- Z9 ^2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash) r0 X. x2 `2 y
2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.
+ V) x. o2 _$ G3 r1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New); F& C+ I# Z p9 m' C
1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
' c1 b. f6 p0 O, E' D# u( N: g2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
9 g# t6 d3 t( |! u2 f2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design1 @/ [5 i9 l0 l r
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas" N9 X' a6 Z( D4 n. i
2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice
8 I. B" ?- a# U/ N v2 M! x2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html2 N* Z0 i9 H% B5 u7 n( j$ O3 V
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden6 W7 ]0 A% [2 y/ P6 I, ?
2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.6
. Z6 d6 a9 D( w2050674 APD PARTITION Cannot remove C-Point from a partitioned design7 o, |% g% `3 G! a, x8 a' |1 w
2068814 APD WIREBOND Bond wires cross on auto-separate: \2 K x8 @ v8 Q6 c
1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open
$ W' p( W$ B( m% P! D1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
1 s: {* d$ L6 Y; {2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL
$ c6 |7 P5 m5 d6 @ ?2 ~$ I2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
6 w0 Q( F* c8 I% O6 |: H2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved- h0 e# o0 `* e( P* Y9 \
2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix5 D3 s. z9 j& J! u2 u
2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager
/ u* r7 v/ T+ j0 F5 G1 l. E6 q6 f2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps
% _: }/ H7 R: D; [: G+ o u! t! Z2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM
% j) v2 D& y4 K& k$ o. V2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties7 b3 M0 o" G8 W( k4 b4 Z' w
2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor. o- g; d# x1 l
2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses5 Q5 H% l6 C$ I
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor: G5 Z V$ `; T+ O
2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.6 @5 Y8 E ~0 ]2 M( r7 w! P
2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma `) c" H/ l+ t" A7 `/ k
2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.
; V! }% b8 ?/ T5 Y2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character3 ~8 o! l) f' Z8 C4 k
2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped
& B7 D$ [: W' X* [2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties
9 B+ S3 H. X' s J6 D4 O1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated3 E" d4 J9 n' m. C8 p& @# [
2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated) _+ i- S# P9 M/ ]8 f; h! a- G' X
2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated
4 b2 G( Z0 V/ g$ s8 d4 V1 |2038021 PSPICE FRONTENDPLUGI Bias display is not updated9 l: S! w% v9 M7 K
2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open
5 R) G$ m3 W$ G- T3 u8 Z' V2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component
, j+ b& A( N9 {* @7 m2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks
C( N: }* E' b/ j! d, o2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
) Y' P1 C* `+ A3 _2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign
) K9 r$ t. T- Q5 F/ b2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed
' b ^2 a" Y$ F, H9 ~8 M2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'
3 S# i, W! A5 U- R- ?# n2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
) R" B4 \9 {3 x& w- [2 f' C2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
' Z; s2 {$ Y& w* }6 \7 L1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
- @+ w( X( `; S! q; z- C- j2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files3 s0 l6 v4 A ^4 u% t E
1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed., ], z7 w$ o' b1 }, q0 v' }& v( E
1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session) ~1 t; {' g& p( a$ I+ _' `
1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name3 n7 k k U3 F% n
2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written& p# q0 n4 ?# y5 M* `
1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping4 u# C! m% ]/ q$ T9 t: @7 b0 M s
2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor/ N9 ] q9 W, [5 {6 c
1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste; ]$ p) w+ Y" y( \+ P8 m: P3 T+ D
1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position' B0 g& B+ _8 `( J! F' Y
1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM
2 s# O! k$ U5 O, e4 \4 c( y1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range
2 e2 H/ e( A' t m) Y, Y8 m/ b2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.
% S+ }- o [0 |! H/ i2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF
7 y* O- [. S+ Q, u- U5 e+ h1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
0 Y& g% ]# e7 S. Y( M1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
# h* R1 g0 ~& y3 z7 ~3 o1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project
7 t! @1 N( y" R' [/ W& Y" O1 a- W1 P- r6 l) n. s& ?& M
4 @+ Q4 k2 W$ {* Z( ^2 r' d
Fixed CCRs: SPB 17.2 HF053' a- J- N4 z9 Z5 L4 r( S& q& a
03-30-20193 o, Q4 U& [7 B
========================================================================================================================================================+ m# d) G/ K/ ~& n
CCRID Product ProductLevel2 Title
, T- l0 o- R) T7 q========================================================================================================================================================0 n. Z( L u) {) n$ o; [
2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right' B' z* B) M. B" o' I/ _
2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag
, k8 z' V6 ]( p# t8 M3 `2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
. l0 y' N3 m1 d2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
; X0 ?: L" [# Z; P2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error( H$ l0 T# @6 F5 ~
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object3 ?! C5 S: y# B$ j0 ]
2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer
0 q5 ~. B) x2 K1 }& v, s2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down
* [4 E; e' R/ J: C) z3 Q5 q+ q1 Q2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
& u- ?2 i4 c U/ F' u0 j2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation: p3 e4 S( C. R$ A8 a4 L1 z
2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned
, M2 e4 D# u/ w1 L. g; E# t2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
% L+ S. b8 ?) G. l; d/ S2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone( r5 v2 Z I- C- d: R
1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.) t# k* _) q7 t
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization+ R: k {8 m6 u7 J9 I8 a1 l
2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack" N: t: O: i, \% x+ r- i7 e
1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols
- C) F& V% b& \8 C: C& t1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines
3 E+ B# }! o& x% u5 ]0 F1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.
5 J; p2 t4 p4 V4 q4 D1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types
, g& R) a- _, X. X$ ^) \2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.; k+ O- f9 h+ h6 u, _0 x% r
2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
! y" p6 q; j% m j2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation6 X- J7 P: k3 n6 Q+ k3 n- F i
2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design0 P7 v, N3 D3 Y k2 @
2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column1 Y! o! D& X: J6 N6 i; j. z
2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.
$ {. b) O/ r+ C. N" U2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table
9 h6 L! _) V5 I! v5 H4 o2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data: P9 J+ I3 u: o) P; {: e
2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value
9 ^: i: c/ p4 f2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added9 `/ U5 l. r% M
2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created! r' s9 k4 t) y5 g
2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev
2 @, ~7 b4 ~. ^( V2 R' f# _2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
, Y5 h; H ^5 g. `2 B: j s2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding
/ b% v) P2 \( c3 x2 r2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
5 S z, m0 C% q: n2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.- z/ L* p5 J7 V$ N
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present* w2 W/ x2 G# C R
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.$ E7 o# f$ |" V: s( E. ~
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
e# H; k/ N: E1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint* |5 l+ k* n7 s( K# W
2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB* Z+ Y5 y; h( l
2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash
]2 L0 x: `5 q( g2 Y& w0 _7 O6 ~2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas! Y' z/ M/ o3 S
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
) I' P; u$ \+ z' i/ ^2 J2 w1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash
7 M( @7 @: A! b+ d4 B2 C1699433 APD EDIT_ETCH Field solver runs when not expected
7 s* ^4 k8 E w" E& B3 I1937159 APD EDIT_ETCH Routing clines takes long time
/ ^ L$ J9 R4 ]$ J$ u' C) [. _7 V2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region0 p2 g/ \% L% N E/ ]7 Y# S
2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051
0 R# j3 Z9 i( o& x; U6 t) h2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture
@" g( E- d7 S2 m/ X8 {2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved! Q: j9 c) z: {8 g1 ^% k* _5 @
2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project
$ Q9 Z" ^5 Y; R0 I1 ~ l2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification; ?; y5 l1 u* R+ ~- Q
2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM' J* R; i6 K5 W
2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source' Z/ b! p8 O. L5 I# `
2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol
7 M! C& o5 ?, o. i8 }7 ^4 p2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks# m6 `* V2 i1 A$ `# O) n4 C
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
" P' G+ S1 o- Y ]" s2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library
, _# }! ?+ j9 n1 m% w# W- U5 e M2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
$ N( s" Y1 b% I0 A1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error% W' l% S+ y% [% [' x
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled) g3 `) W' M; e4 L& S9 ~/ U
1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components2 f" Z2 M: b# Z) G. C1 l
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names. W; E2 y3 U5 W( x6 W1 k) Y
2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character
) M# M* D3 Q. F, A: r1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
5 }+ Z5 x- u/ F% O- N- `: ] Q1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option, a( t1 ^! ~3 W& H4 K' Q5 j
1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped3 O$ E4 z: Y6 w4 Q; L1 `, z" S& d
1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical: ?5 w, _) x P6 x
1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names8 ?0 s1 }3 r. @6 n1 E
1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas
/ J: c2 A: R1 Z" {1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
8 H3 l' H5 @3 Z9 U9 C1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast c* v0 @9 u- k8 K% C Z( b
1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently+ j( y0 m; @' D7 B* {% w& m
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page* n9 R4 x% R# B; M0 b% R) ~
1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI
" v3 R7 B s2 |% C4 L, l. C1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created2 t' P8 m. h7 K ] i! M2 p+ W
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
: i. u+ k+ s# k z1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it' Z8 g0 w& W7 q( F
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL
/ q4 k2 a$ J O5 L1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture* J1 a% Y8 I* W2 u1 J
1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message
% o+ Z* q, G- v4 ^% D3 z1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor
5 Y7 o. y. W H5 }" o2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder
' z9 N: T, _3 ?, x: t1 j1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
% \$ w! V# p1 q* O+ j2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component
: B# Q0 k% ?( l$ z# d; U1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES
+ K$ X" o! I+ p1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option5 _) M6 j: P o" n8 c
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor. I9 n* a- N7 a8 F2 f$ n
, D A4 R: | a: F4 p, b- l( a
1 Z6 |$ m( Q+ [* h0 q" o% o c
Fixed CCRs: SPB 17.2 HF0521 ^2 h+ B8 f2 u# j+ N6 }7 b
03-01-2019, T) ~5 x) p% q
========================================================================================================================================================
' m/ l" k# x, F( jCCRID Product ProductLevel2 Title
W) y- B3 k9 L& R7 d========================================================================================================================================================4 j) E7 R7 `2 Y8 t6 J: k
2020429 ADW ADWSERVER Incorrect adwservice status on Linux' N0 b6 n" |; t# c3 M1 ~8 p
2034815 ADW LIBDISTRIBUTI Cannot mark classification obsolete because it is associated to objects in the database
# U" O& G# i$ }+ M4 R2015461 ADW PART_BROWSER New Component Browser should read the mapping of symbol and associated package as it results in error PKG-1005
( K& j7 f9 |* k% U2049380 ADW PART_BROWSER System Capture Import HDL not importing complete PTF File data
" B0 W) k& z1 d1948608 ADW TDA CUSTOMVAR directive value in project CPM was not updated by TDA UPDATE command.
' { Y8 I: X' o$ W/ f1992662 ADW TDA Custom directive added to the cpm file not updated after check-in
; D6 h( F8 |) D1 a* e1733129 ALLEGRO_EDITOR COLOR 'Display - Highlight', double-click permanently highlights symbol3 y# ] f; g/ o5 m1 O2 `; d
1861938 ALLEGRO_EDITOR COLOR Changing layer color changes layer visibility0 I# @6 p5 K. h! ^
2034753 ALLEGRO_EDITOR CROSS_SECTION Allegro PCB Editor crashes when a cross-section technology file is imported in Overwrite mode, u2 t, H( e% N2 f! C
2036895 ALLEGRO_EDITOR CROSS_SECTION Replay script error during import of tcfx Xsection file
5 ~$ S. x5 o2 k7 h( w1929360 ALLEGRO_EDITOR DATABASE Via color is inconsistent on Vias with color assigned; W" e9 a+ T, i5 T7 I- ]8 y
1984203 ALLEGRO_EDITOR DATABASE Drill holes not displayed correctly in the Zone area% Z' ~$ g' n+ @( }6 V
2013596 ALLEGRO_EDITOR DATABASE Assigning net name on Vias does not change the Via Color to that on Net Color automatically
, n# j# U* p/ Z2025798 ALLEGRO_EDITOR DATABASE Assign net to via changes color of the via to the default color
+ H$ g7 i. u h% z2 n2032678 ALLEGRO_EDITOR DATABASE Unable to delete layer on design
& G, `5 i" ^9 U: V2032725 ALLEGRO_EDITOR DATABASE Dehighlight removes color assignment from color dialog+ _5 w& x( r# `; ~! q) m h7 y
2029542 ALLEGRO_EDITOR DFA Interactive Placement with Manufacturing Package to Package spacing
4 V' P+ {& I( U9 D9 u+ ~2020548 ALLEGRO_EDITOR DFM Cadence DFM Customer site cannot Submit Request% i4 R' n1 {# [7 z1 H% q( o
2020566 ALLEGRO_EDITOR DFM Error when sending Design True DFM Rules Request) T+ u( y8 a3 J _3 X! b. [
2030179 ALLEGRO_EDITOR DFM Allegro PCB Editor .brd file will not save after routing using Automatic Router
; P9 v6 t$ n3 D! N2052907 ALLEGRO_EDITOR DFM The Submit Request button for DesignTrue DFM Rules Request does not work8 C! T E1 V( r) K6 m* h
1928915 ALLEGRO_EDITOR EDIT_ETCH PCB Editor constraint status bar does not match Constraint Manager data when z-axis delay is turned on.
+ s+ E& a U& k; l# F6 q1932165 ALLEGRO_EDITOR EDIT_ETCH Arc slide behavior with clines at odd angles: notches on slides
3 g8 L5 d3 a8 ~$ [" P% ?4 T1943901 ALLEGRO_EDITOR EDIT_ETCH arc segment incorrect on slide.
% t; b( e. _; V O; T0 l2031055 ALLEGRO_EDITOR EDIT_ETCH On drawing cline the width on a Layer is larger than defined constraint
( G m9 f9 u. Z1 `1877891 ALLEGRO_EDITOR GRAPHICS Allegro PCB Editor crashes when started from EDM for projects without a board file or empty master.tag file
/ E, y8 j8 W0 U/ @$ W2 p. z2040689 ALLEGRO_EDITOR NC The decimal digits of a rotated oval padstack do not match the Drill Chart.
, M9 `7 I) L; N/ d8 {4 `! Z- t2028105 ALLEGRO_EDITOR PLACEMENT Delay in moving a large count pin symbol
% |7 {6 {! J" X2019027 ALLEGRO_EDITOR REPORTS Information shown in the Report Viewer is not correct.
& x1 o/ Y* W, t$ w2022461 ALLEGRO_EDITOR SHAPE Abnormal termination of thieving function in Allegro PCB Editor( R- b3 K* q( G. b
2032048 ALLEGRO_EDITOR SHAPE shape void difference from hotfix 026 to 048: need square corners for full round6 m9 |* X+ K- e
2040138 ALLEGRO_EDITOR SHAPE shape_rki_autoclip affects the overlapping shape boundary
/ R8 ^) B% n {* \8 ?! u/ k2040259 ALLEGRO_EDITOR SHAPE Same net shape and cline adds shape void around cline# w9 i5 l, y3 J6 i+ S
2031468 ALLEGRO_EDITOR TECHFILE Cross section import (.tcfx) not working correctly.
3 U: ], V3 R0 E! J2006425 ALLEGRO_EDITOR UI_FORMS Option to disable 'Create a New Design' window in OrCAD PCB Designer6 |, M& ~' x2 Y# R* G& o- j
2007451 ALLEGRO_EDITOR UI_FORMS Option to suppress 'Create a New Design" window for File > Open in OrCAD PCB Editor from hotfix 048
4 K* a' J" E8 O2009314 ALLEGRO_EDITOR UI_FORMS Existing scripts that open OrCAD PCB Editor not working in hotfix 048
8 z& H. F6 G' {2 c7 Q2021476 ALLEGRO_EDITOR UI_FORMS PCB Editor is slow when using the command 'add connect'
: o1 l$ }' r$ t2039462 ALLEGRO_EDITOR UI_FORMS Hovering over Default symbol height in Design Parameter Editor does not display a description5 X$ x. S8 {. ] d
1808054 ALLEGRO_EDITOR UI_GENERAL Illegal value in axlFormSetField crashes PCB Editor
( o1 C3 x& \2 X! z. X Z1822679 ALLEGRO_EDITOR UI_GENERAL 'Symbol pin #' field is truncated on rotating components in the Placement Edit mode
" J3 Z* v/ x+ C$ `$ _; g1856438 ALLEGRO_EDITOR UI_GENERAL Script recording messages not displayed in the PCB Editor task bar when using the script window.
8 c" u" j1 e5 M9 F9 u, x& j1879078 ALLEGRO_EDITOR UI_GENERAL Running PCB Editor from command prompt with '-product help' should list all products and options
- A, T: Z! q$ W- } d6 ] E1944225 ALLEGRO_EDITOR UI_GENERAL Cannot close log file window till we close report dialog box+ E: n1 o$ C5 y t; T
1967708 ALLEGRO_EDITOR UI_GENERAL New Command Window Shows Last Command in UI \6 q2 D5 Y$ B
1968380 ALLEGRO_EDITOR UI_GENERAL Write all open editing sessions in MRU
- C2 n' d, E q9 F) g1982138 ALLEGRO_EDITOR UI_GENERAL axlFormListDeleteItem(fw field -1) not deleting last item of a list m, `# o; f0 {
2003054 ALLEGRO_EDITOR UI_GENERAL Grids not shown when 'nolast_file' is set0 g; ~2 m% N2 }( S& c) G
2010760 ALLEGRO_EDITOR UI_GENERAL Pressing tabs is selecting only vias and not selecting clines in PCB Editor in hotfix 048
1 g. i2 x; ]( V3 }2019120 ALLEGRO_EDITOR UI_GENERAL Tab key is not working when there are two objects on top of each other F& e) v- A9 _4 O1 n3 b
2029248 ALLEGRO_EDITOR UI_GENERAL Colorview load is not working when using absolute path
6 l9 G4 y2 J4 l/ I) i2030985 ALLEGRO_EDITOR UI_GENERAL The view of the PCB is offset after closing and opening the board.
0 z) ^- R4 g$ R2037968 ALLEGRO_EDITOR UI_GENERAL Tab key will not cycle between cline elements.' z! O1 u" n+ M
2015766 ALLEGRO_PROD_TOOLB CORE Advanced Testpoint Check does not work5 h! u0 a; A8 h7 g" @6 E) b
2023356 ALLEGRO_PROD_TOOLB CORE Edit new session does not work in quick symbol editor tool box S8 b2 l/ A5 `" o
2017162 CAPTURE CONSTRAINT_MG Cannot apply ECSets in Constraint Manager-enabled Capture, O4 H( Y$ w( R- k2 X
2026777 CAPTURE CONSTRAINT_MG Cannot apply electrical CSet (ECSet) in Constraint Manager-enabled Design Entry CIS
& O. v5 d) _$ H( v+ a2027545 CAPTURE CONSTRAINT_MG Getting error (ORCAP-40320) while creating ECSet. R! V; J1 X7 {
2012967 CAPTURE OTHER Capture license is loaded slowly in hotfix 048
, \$ }! p, e. Y; a: b- l2010093 CONCEPT_HDL ARCHIVER Archive .zip file keeps the whole folder hierarchy and not only the project hierarchy
2 m( t7 Y% }1 K( Q- j- I" H I2040431 CONCEPT_HDL EDIF300 EDIF300, Schematic Writer, crashes in release 17.2-2016
$ y* R7 Z7 J0 w1 x8 s# v$ n6 G8 g2034077 SIP_LAYOUT DFA DRC is not catching all Shape minimum width violations
$ m, {+ S+ D! d* F- w- C- \9 m. U2034094 SIP_LAYOUT DIE_ABSTRACT_ [VSDP-RDL Exchange] some traces are lost in SiP Layout
, D$ O) v4 G; B0 `& v( ^; b" J2037462 SIP_LAYOUT DIE_ABSTRACT_ Cline Segments are lost on saving and re-opening the design in next session( @7 u4 W% Z' K
2025321 SIP_LAYOUT IMPORT_DATA compose symbol from geometry defaults need to change due to performance
" V4 ^: O' `6 b3 G4 E0 Q8 i2017759 SIP_LAYOUT PLACEMENT Placing a die creates extra place bound and puts pin numbers in the wrong place, causing future netlist import failure
; t' s; U& g* I" P5 y6 C3 B/ ]4 E2021057 SIP_LAYOUT SHAPE Polybool assert error when adding dynamic shape prevents shape voiding.2 o" e H& w) Y
2012381 SIP_LAYOUT SKILL Ability to check if the Dynamic Unused Pads Suppression box is selected using SKILL, [/ C8 C5 s P7 q" o* f
1990299 SIP_LAYOUT UI_GENERAL Pressing 'Esc' cancels DRC checking when there is no focus on the Allegro PCB Editor canvas
# j) v: t) Q5 a+ k7 ?3 T1997317 SIP_LAYOUT WLP Advanced WLP, Metal Density Scan does not correctly calculate scan region count in Y direction( r. z% B( D$ [7 ~& g/ {' k
2029524 SPECCTRA ROUTE SPECCTRA stops responding when executing the quit command
' i5 }7 K6 ^ h0 Z1670888 SYSTEM_CAPTURE CANVAS_EDIT Rotation error when connected to a power symbol
* ^6 E5 }% F" u% @- z1880809 SYSTEM_CAPTURE CANVAS_EDIT Can modify only one RefDes from canvas for duplicate RefDes; can modify both from the Properties window9 H) Y6 @0 b: X7 t R, N: w
1979063 SYSTEM_CAPTURE CANVAS_EDIT System Capture : File > Close is grayed out0 H8 k A% U/ _6 f% \ G. O2 k. p
2034498 SYSTEM_CAPTURE CAPTURE_IMPOR Cannot find parts via Find & Replace after importing Capture design
7 h. ^; {3 ~3 o3 J1984561 SYSTEM_CAPTURE CROSSPROBE System Capture: Cross-probing from layout does not work when zoomed into a specific area on canvas& b5 y& ?4 }5 x) G6 R( U
1863460 SYSTEM_CAPTURE DARK_THEME thumbnail preview of pages is in light them but dragging the page the previes is dark
! k* [( B v; Y2025876 SYSTEM_CAPTURE EDIT_OPERATIO Route failures when dragging a circuit
6 m- `4 |1 i/ [! P+ g: |2005904 SYSTEM_CAPTURE FORMAT_OBJECT Pin name text is smaller in System Capture than in DE-HDL by about 25%* C) W" A% Z( {5 N
2036782 SYSTEM_CAPTURE IMPORT_BLOCK Unable to import the block from project.
5 k$ k0 ]) Y$ I" r) Z2025949 SYSTEM_CAPTURE IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not translate in System Capture9 G% y3 W B- D0 B# x% g
2025950 SYSTEM_CAPTURE IMPORT_DEHDL_ Broken connectivity on imported ground symbols* |4 O# s$ Q3 ^1 ?
2040923 SYSTEM_CAPTURE MISCELLANEOUS System Capture - Multiple Symbol Replace, disconnects and changes orientation2 d7 v2 k& C2 P+ N/ v
2017526 SYSTEM_CAPTURE NAVLINKS Page information missing in NAVLINKS; a$ D% W7 G/ P7 ?5 Q! z: Y
2015346 SYSTEM_CAPTURE PAGE_MANAGEME Rename page fails in some cases
% N$ ? U# r3 L9 m: d9 m$ o5 M) v9 @2038811 SYSTEM_CAPTURE PRINT Black & White PDF showing colors
* r9 T' S! a+ M ?- [& I1 |3 L8 l2048493 SYSTEM_CAPTURE SYMBOL_GEN Symbol Editor, Modify outline adds an 'X' in symbol incorrectly. n/ M* X+ T; D$ ~0 g5 _
2031995 SYSTEM_CAPTURE VARIANT_MANAG Variant Editor does not load the design and restarts the machine after sometime.- z$ t, l7 L% C$ |. ~' \" o
2032005 SYSTEM_CAPTURE VARIANT_MANAG Custom variables not saved for variants/ k9 D: S5 W4 ]2 q
1968431 SYSTEM_CAPTURE WORKSPACE Unable to reorder the pages (tabs) when opened in the workspace
+ n" @0 r: {0 v7 I' K4 A5 E9 G2040995 XTRACTIM GUI Running XIM from APD enables "skip DC R simulation" by mistake
/ j1 X- P' X, h$ C& g4 \+ J5 u' J* |* W9 C
6 W8 s" A8 G1 _. aFixed CCRs: SPB 17.2 HF051
}9 o4 S0 r$ Q ?: h01-30-2019
}! w4 o3 ?# w) r* `========================================================================================================================================================
4 F' E, v8 }, A5 @CCRID Product ProductLevel2 Title
0 p( f# o" p' |; J+ H2 p9 g6 f========================================================================================================================================================
7 w( S( h* a% e6 g* R& `2015843 ADW LIBDISTRIBUTI Error for library distribution (lib_dist_client) regarding string index out-of-range! P; r6 C7 k9 L0 X" O* ?: g0 k
1869914 ADW PART_BROWSER Adding components to System Capture schematic canvas takes long time in Linux clusters
; |) C+ Y4 T, [/ x2010458 ADW PART_BROWSER RefDes values not appearing on parts
1 k5 s$ O8 g9 d9 M2022630 ADW PART_MANAGER Unable to successfully import a DE-HDL Design into System Capture( y7 Z1 g9 q0 s% k
2005033 ALLEGRO_EDITOR 3D_CANVAS 3D Flex issues: Error message when opening design with bends in 3D viewer
f4 x* h; h( l! \2023496 ALLEGRO_EDITOR 3D_CANVAS Error for designs with bend in 3D Viewer
3 ]9 E6 c2 G9 K1 x- A+ l2033459 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation+ J- H; \8 Y* h- ~ F
1996431 ALLEGRO_EDITOR ARTWORK Via holes for connection have incorrect coordinates in Gerber1 z0 T3 b" n; C- p1 s
1995656 ALLEGRO_EDITOR DATABASE Attaching and Detaching a text file created with SKILL writeTable() function corrupts the text file
7 H& m9 b f5 _2027122 ALLEGRO_EDITOR DATABASE PCB Editor crashes when creating Place Replicate module
/ @6 @. T( ~) b. F2023916 ALLEGRO_EDITOR DFM DFF Annular Ring: Thru via pad to Mask violates on via in pad instances.
T( ?1 b) ]+ J T7 _9 Z2024523 ALLEGRO_EDITOR DFM PCB Editor crashes in Mask To Trace check of DFF.
+ U6 c" ]% r: _& P2021318 ALLEGRO_EDITOR IN_DESIGN_ANA Integrated Analysis and Checking: Unable to run simulation with Crosstalk flow
# }" @* N; U l1 @2014162 ALLEGRO_EDITOR NC Backdrill results using an OrCAD Professional license showing wrong values with hotfix 048
, t t, [: ~3 h9 k2010791 ALLEGRO_EDITOR PLACEMENT Setting dfa_pause_level to 3 and then moving and rotating part places the part with offset
; p* o, r3 g% q# F- N2017112 ALLEGRO_EDITOR PLACEMENT place_boundary shown at wrong location when moved with User pick and footprints rotated$ D7 z' H2 U/ s' n* b9 S5 Z! D
2028048 ALLEGRO_EDITOR PLACEMENT Rotate option using pick is rotating the outlines in different axis in view
- c/ k: k( ]% O9 f) W% P) p2028314 ALLEGRO_EDITOR PLACEMENT Crash on moving components in Allegro PCB Editor
/ r6 C- ~; a$ u- h' W$ {' S( {( P2029235 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when moving more than one component and hovering on IC
8 V3 `( ~" o/ h# F" _) R; e2022644 ALLEGRO_EDITOR SHAPE dv_fixfullcontact obsolete in release 17.2-2016
" F6 C5 ~' V0 p6 ]' \. j, _2023322 ALLEGRO_EDITOR SHAPE Gloss does not add teardrops on all clines.
0 T1 y# V- C1 W$ }! g2024235 ALLEGRO_EDITOR SHAPE Copper Pour disappears when area includes parts: Z( G1 `6 d& _& L
2024531 ALLEGRO_EDITOR SHAPE rki_autoclip is not working at a special XY location
; y- b! R# r7 G2024599 ALLEGRO_EDITOR SHAPE Cannot create round corner for shape
\. f% g3 @" T5 R' Q2024707 ALLEGRO_EDITOR SHAPE In-line void control does not work when there is no_shape_connect property attached* \/ y0 C4 h8 g% I
2026849 ALLEGRO_EDITOR SHAPE Cannot assign region name using the 'next' operation
( A, |* e$ ^9 @3 j3 P/ Q2030156 ALLEGRO_EDITOR SHAPE Shape Area report for cross-hatched shape includes hatching and boundary. m( K: E v0 K" { d
1852981 ALLEGRO_EDITOR SKILL Error message while creating Copper Mask layer without a name using SKILL not clear
- Z! J. q7 R' g& n+ i& O1968054 ALLEGRO_EDITOR SKILL Document of axlClearObjectCustomColor should indicate that it can clear color for DBID of Net
1 ~7 T) ~% A5 `: }2026429 ALLEGRO_EDITOR UI_FORMS PCB Footprint wizard: horizontal and vertical lead pitch level reversed in the image
( D7 q5 V" T, P1768032 ALLEGRO_EDITOR UI_GENERAL Numeric keypad does not work for file selection shortcut) i+ A( N, Z1 ]
1797376 ALLEGRO_EDITOR UI_GENERAL Release 17.2-2016: Padstack Designer saves padstack to the working directory when script is used5 q, i$ ^$ j m7 g! R/ {3 v$ J
1798524 ALLEGRO_EDITOR UI_GENERAL Unable to save a padstack using script
! x6 K% h5 A0 v% {2 J9 x5 Z, G% G8 c. K( }1823031 ALLEGRO_EDITOR UI_GENERAL Help not working for OrCAD Productivity Toolbox
2 ?% \- d L7 I- p* n1849921 ALLEGRO_EDITOR UI_GENERAL Analyze menu missing in OrCAD PCB SI
; w. e, V9 g, L% m5 z1951740 ALLEGRO_EDITOR UI_GENERAL Trigger for 'open' does not work when opening a .dra file: G1 L* s& |1 g, N/ h& [3 B5 L/ m
1952163 ALLEGRO_EDITOR UI_GENERAL Analyze menu missing in OrCAD PCB SI
g( ?9 q# F |1 |8 {1982966 ALLEGRO_EDITOR UI_GENERAL SKILL command to access the Option window fields while in Interactive commands.
% X6 f* u$ f! S9 q1983567 ALLEGRO_EDITOR UI_GENERAL Alias with Ctrl not working with 'command window history' variable enabled
3 x- D' e2 S" Z" _% G3 h+ ]1989507 ALLEGRO_EDITOR UI_GENERAL Third-party tool causes PCB Editor to stop responding to command. F/ K" V/ H6 @( Q
2003511 ALLEGRO_EDITOR UI_GENERAL Aliases using control (tilde) characters stopped working after upgrading to hotfix 048
6 e5 Z% z. M/ ~0 o3 i+ @6 X6 ^2010418 ALLEGRO_EDITOR UI_GENERAL New command window breaks funckeys
2 Y! |, e2 j! N) p- U( Q) L {5 v2018201 ALLEGRO_EDITOR UI_GENERAL SKILL axlDBControl ('activeLayer /') updates active class/subclass but ministatus form not updated2 t& K0 j: `) l) ^6 Y. `$ x
2023468 ALLEGRO_EDITOR UI_GENERAL axlZoomInOut does not zoom out, always zooms in regardless of zoom factor (positive or negative)
- ^! v( D& e8 X1 b2026428 ALLEGRO_EDITOR UI_GENERAL PCB Editor takes several minutes when saving a design
7 {4 _0 l( U" F! s Z2032697 ALLEGRO_EDITOR UI_GENERAL Funckeys with Ctrl not working with 'command window history' variable enabled( o/ S9 o6 f$ p+ I; V- z' k- T& {/ \
2032717 ALLEGRO_EDITOR UI_GENERAL Funckey combinations, such as Ctrl + M, not working
8 @) x: {) B( e! K& H9 D T) p- r2014211 ALLEGRO_VIEWER OTHER Arrow keys are not panning in Allegro Physical Viewer
. ^; C" a& f! P3 L1 }; {2039081 CAPTURE NETLISTS Netlist not created: netlist fails for numeric pin names with backslash '\'8 [+ y* }4 _7 q/ C
1993057 CONCEPT_HDL CONSTRAINT_MG Constraints disappear in hierarchical design (Electrical->Net->Routing->Relative Propagation Delay)
5 c- g5 H/ ^8 Q+ v2 h2004641 CONCEPT_HDL CONSTRAINT_MG 'Save Hierarchy' (hier_write) deletes bus object in Constraint Manager
0 @. [( f5 w* `2020901 CONCEPT_HDL CONSTRAINT_MG Incorrect match Groups created in CM (TDO design)
. }6 ]% Q3 v; A) D2014979 CONCEPT_HDL CORE The active schematic page randomly changes while editing text
- Z( p# n, m0 @2027905 CONSTRAINT_MGR DATABASE Pin Property changes in CM during uprev to release 17.2-20167 C' C; {, {% E \% i" o. J
1762263 ORBITIO INTERFACES Add set allegro_orbit_import variable to user preference
: A8 L& |! ~1 m2005860 PSPICE LIBRARIES Error when simulating design with TL494 part in release 17.2-2016
% h' |5 b: p- D+ E) V" M/ F1980072 PSPICE SIMULATOR Noise in the waveform when using DELAYT and DELAYT1 with capacitor5 E* g8 |9 i7 G
1977615 RELEASE INTEGRATION Cannot import third-party schematics into OrCAD Capture in release 16.6, ` X$ f. p3 }# l( W8 Q% L
2027009 RF_PCB SETUP 'RF-PCB' - 'Setup' changes not saved on Apply
8 I# }: j$ [6 r2002040 SIP_LAYOUT MANUFACTURING IPC 356 'ignore die layers' does not work: netlists to die9 p7 I- k+ A+ H! Z# a
2024703 SIP_LAYOUT WLP Cannot Add Pin Text: Error on 'Manufacturing' - 'Documentation' - 'Display Pin Text'$ i! p5 s9 Z, Q+ |) C5 q
2010045 SYSTEM_CAPTURE CANVAS_EDIT Cannot snap back vertical CAP until moved up and down horizontally
3 c- n: t3 b8 @3 r, Y' L* J1 F2010443 SYSTEM_CAPTURE CANVAS_EDIT Cannot select the CAP part, ~+ M. r: V0 O2 b8 Q
2012843 SYSTEM_CAPTURE PACKAGER Cannot short two grounds in the schematic4 h! e9 c H; V
2015574 SYSTEM_CAPTURE PACKAGER System Capture is treating quotes in PTF files differently from DE-HDL3 @# ^' N# Y5 i$ `7 p
2022653 SYSTEM_CAPTURE VARIANT_MANAG Variant Editor - Allow Alternates where ALT_SYMBOL is a valid match for JEDEC_TYPE9 H" \- N C$ Y! W3 a/ V; Q
2024742 TDA SHAREPOINT Accessing projects is taking time
. w/ Y6 d5 q ] Z2010531 XTRACTIM OTHER Allegro crash on repaint of command window0 k) I5 V/ t- A4 b0 ?8 k
2022351 XTRACTIM OTHER XtractIM is crashing the latest HF S0498 ]+ y* r) W) g7 Q+ _6 P
9 v, J6 o7 l" z. }
& P4 ?! [: ?" c1 nFixed CCRs: SPB 17.2 HF050( C- U% a8 j+ L
12-23-2018+ j, r1 \5 t/ O1 j9 f
========================================================================================================================================================* n. t3 x% d I" X9 A( _- B! ^2 X( c
CCRID Product ProductLevel2 Title" s0 ]" ^6 k- d
========================================================================================================================================================
2 ]2 ]0 }5 F$ ~2012119 ADW ADWSERVER Cannot connect Component Browser to server
: R; C8 C1 A8 R! t* @6 @0 D1998856 ADW ADW_UPREV adw_uprev fails and a typo in rule name( d/ ^9 m1 {; A8 u) \7 Y
1673333 ADW CONF Configuration Manager stops working and gives Java Timer-1 Error' e' k" y2 L2 P. {
1900342 ADW DBEDITOR 'Link To' on a schematic classification attribute does not work with linked attributes containing parenthesis; w7 |- f- l; U
1997516 ADW DBEDITOR DBEditor stops responding on changing attributes
2 S! [ W: a3 ]1986292 ADW LIBDISTRIBUTI Some parts are not updated in the part table in all_noauto and ini_noauto (restricted_sites).
0 _9 r7 z1 `' \2010460 ADW PART_BROWSER PKG-1002 error when opening a DE-HDL design4 `8 r. |) I: v% a; |- |1 I
2013430 ADW PART_BROWSER Add component is inactive if WB_SHARED_RESOURCES is not pointing to the installation directory
6 w! `7 |5 p7 y' l9 b2022806 ADW PART_BROWSER PKG-10005: Cannot package the following primitive instance in any section of the physical part. X! E* |* q, w* K3 p b8 V, H
2006528 ADW PART_MANAGER Part Manager does not update parts when Key PTF property value changes
" o/ K6 C& X$ ?# L& I1980397 ALLEGRO_EDITOR DATABASE Mechanical pins with route keepouts (RKO) not updated
' y1 V# J( n( h c+ G4 w5 ]" B* {1988171 ALLEGRO_EDITOR DATABASE Backdrill clearance Keepout is not applied consistently
( b4 F; y7 i; Z& k5 [1994280 ALLEGRO_EDITOR DFM PCB Editor crashes during Unplace component: ]8 K8 S! g! _1 k: ^- [# X4 ~
2012742 ALLEGRO_EDITOR DFM DFT for testpoint to outline not showing DRC
' |: a, W0 n8 ~- G4 A6 H2 i% V0 x& D2002680 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on choosing Add Connect for two selected nets
/ e& q% e0 Z/ E" i$ N5 {2004597 ALLEGRO_EDITOR EDIT_ETCH Illegal BMS Identifier error when copying multiple via structures" W7 {9 {) f: E" ]8 a
2004929 ALLEGRO_EDITOR EDIT_ETCH Net with physical pin pair constraints is using incorrect line width when routed
# ]" a0 o# G6 q' y/ _2008314 ALLEGRO_EDITOR EDIT_ETCH Adding nets in tabbed routing crashes PCB Editor
5 l$ g8 z c4 w7 O Z2018710 ALLEGRO_EDITOR GRAPHICS Using the mouse to zoom by scrolling stops working randomly" v1 v7 ^$ B2 H& E9 }
2018841 ALLEGRO_EDITOR GRAPHICS Canvas does not regain mouse focus after working in the Options pane in hotfix 049 n1 G) z+ i" H8 q" ?/ a
2019482 ALLEGRO_EDITOR GRAPHICS Canvas does not regain mouse focus after working with the Options pane in hotfix 049 on Windows 71 Z3 A/ Z/ Q S6 H
2019864 ALLEGRO_EDITOR GRAPHICS Using the mouse scroll button to scroll the canvas: focus is in the Options pane
2 k+ f0 g& b; f3 U2020750 ALLEGRO_EDITOR GRAPHICS Zoom in/Zoom out scroll does not work
3 @9 h' M( I5 {; p$ b( B2020847 ALLEGRO_EDITOR GRAPHICS Scroll up/down key focus remains in command screen even when canvas is selected6 G' F( D [7 g, N2 ]' T
1908812 ALLEGRO_EDITOR INTERACTIV Tools > Design Compare command does not work on Windows
0 L/ N6 _. [! }7 a% V1995846 ALLEGRO_EDITOR INTERACTIV When there is an embedded component, the result of Metal Usage report is incorrect.
+ U( G8 v# I$ y' {1 ^2011449 ALLEGRO_EDITOR INTERACTIV Command not found error (_impvision) for Impedance and Return Path DRC visions, K/ T. _6 w% L# c8 I- m/ t
1982867 ALLEGRO_EDITOR INTERFACES DBDoctor displays error for objects outside extent that cannot be fixed because the extents cannot be increased
Q' u6 ~" n- n; ^' ?1983177 ALLEGRO_EDITOR INTERFACES PCB Editor crashes when reading IDX file. m) L5 g: I; z4 M7 W; O
1985623 ALLEGRO_EDITOR INTERFACES STEP model not exported from PCB Editor
$ O( _0 C5 m% v; N1994855 ALLEGRO_EDITOR MANUFACT Drill legend with counter-bore: legend size not uniform when database set to inches* {5 ~+ G5 ~2 p% H" C: x" d
2001355 ALLEGRO_EDITOR NC PCB Editor crashes with NC route parameter
a `4 ~1 z0 R# n9 T% F1753414 ALLEGRO_EDITOR OTHER Ability to add Rigid Flex class in a format symbol+ J; v; u6 F B$ A, Q' X& Z, x# V
2004786 ALLEGRO_EDITOR OTHER Legacy menu option missing in OrCAD Professional
$ z$ L# R8 P, L2 h5 m: B g0 M1949695 ALLEGRO_EDITOR PADS_IN Third-party to PCB Editor translation does not make a clean conversion
1 h4 o0 e' M1 b6 Y& d) k! B1949658 ALLEGRO_EDITOR PLACEMENT SKILL module creation issue: subsequent runs rotate module incorrectly
/ S/ U+ \7 g @2001496 ALLEGRO_EDITOR PLACEMENT Constraint Region not replicated as part of the Place replicate apply command
* v+ ] K2 ?7 J2002989 ALLEGRO_EDITOR PLACEMENT Default rotation point is set to 'User Pick'
+ ~* |( G. r( T7 o4 r& ^2007301 ALLEGRO_EDITOR PLACEMENT DFA boundary is shifted when moving components with User Pick
# r- q5 y A+ u1 c3 `2007312 ALLEGRO_EDITOR PLACEMENT DFA boundary is shifted when moving components with User Pick
% @+ \5 V$ d/ H0 e1 o [/ n" v2008098 ALLEGRO_EDITOR PLACEMENT DFA boundary shows a shift if anchor point is set to 'User pick'+ i) J5 e- {$ Z! R' A6 b
2009085 ALLEGRO_EDITOR PLACEMENT DFA boundary is shifted when moving components with User Pick0 p( A) U2 [# Y0 p; _7 ^
2009090 ALLEGRO_EDITOR PLACEMENT DFA boundary is being offset when moving components with User Pick6 }. f/ @, A. N' `3 n
2009580 ALLEGRO_EDITOR PLACEMENT Component outline offsets during move process
0 S* t/ a1 F' }- F }2010726 ALLEGRO_EDITOR PLACEMENT Two images appear when moving component in release 17.2-2016, hotfix 048
7 g6 q3 S8 I$ b* Y6 A5 ]0 g: K4 s$ ^2 a$ G2010819 ALLEGRO_EDITOR PLACEMENT A separate outline appears when moving components using User Pick$ {% V0 l+ T) A7 @" L
2011454 ALLEGRO_EDITOR PLACEMENT DFA boundary is not centered correctly on moving components$ I& n- `! \+ |( v1 Z' _
2011497 ALLEGRO_EDITOR PLACEMENT DFA boundary shifted from the part when moved- t; e ]" g2 a
2014250 ALLEGRO_EDITOR PLACEMENT Moving a symbol using the 'User Pick' causing an offset image of the symbol outline getting attached to cursor g; [" X( Z9 I8 Q. l* [
2015676 ALLEGRO_EDITOR PLACEMENT Strange end-to-end DFA checking: offset of DFA from component when in user pick
9 x8 D! a) s$ Q0 F! b2016421 ALLEGRO_EDITOR PLACEMENT Fail to place symbols because definition is incompatible for attribute 'PW_GENERATED'+ ?) A5 w! u7 e* ` M
2016452 ALLEGRO_EDITOR PLACEMENT Some symbols cannot be placed due to property definition differences1 ^1 g/ ^8 ?4 X9 H/ Z
2016527 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes on moving all components on board- E t) j; L7 `- H
2017364 ALLEGRO_EDITOR PLACEMENT Strange behavior when moving component: DFA or place bound area is centered around the User Pick position0 F, O3 }! m, t4 |1 S: _4 @" `
2018859 ALLEGRO_EDITOR PLACEMENT Moving parts by 'User Pick' or 'Sym Pin #' shows two component placement boundary outlines5 @* `7 b; q, W0 |
2019364 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when moving components
: | \% {) O- E1 I, W0 B2019478 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when moving more than one component across the design
$ \. j. S' [: @9 ^( a" D+ X2 N7 ?2019624 ALLEGRO_EDITOR PLACEMENT DFA Boundary is offset from definition when moving symbols with user pick
; f( F2 r8 H+ m2021625 ALLEGRO_EDITOR PLACEMENT Graphical Issue with Edit - Move and User Pick: additional outline image shown
) ~' a- @7 b* u3 u% B& i2022203 ALLEGRO_EDITOR PLACEMENT Place bound outline is shown at the center of the pick when moving a part by User Pick
2 {8 B' D" @; F5 V8 j5 ~2024655 ALLEGRO_EDITOR PLACEMENT Moving multiple components causes PCB Editor to crash$ d6 g) t" T) a
2025895 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when multiple symbols are moved and on getting too close to another symbol
2 k- G5 x e8 e" B' d! h3 \ E2004497 ALLEGRO_EDITOR SHAPE Automatically deleting antenna shape is not deleting thermal reliefs associated with those shapes
0 j- m6 `& {( \( Q: N- m. V3 I& _2007832 ALLEGRO_EDITOR SHAPE Cannot void shape properly after rotating symbol5 b2 b1 c G u6 d6 A d! f2 [
2009601 ALLEGRO_EDITOR SHAPE Error for shape created using third-party SKILL utility
. L* T6 ?5 k$ y; X* S, s2010924 ALLEGRO_EDITOR SHAPE Dynamic shape does not void in route keepout areas: `* J& ^4 N5 U
2011176 ALLEGRO_EDITOR SHAPE Nothing happens on choosing 'Shape- - Change Shape Type' in Allegro Sigrity SI
! S6 _6 D& N2 D; ]2015446 ALLEGRO_EDITOR SHAPE Thermal relief connection created for static shape covering pin when inside a void in a dynamic shape.
( e) v2 N0 k" i% p9 ?2017273 ALLEGRO_EDITOR SHAPE Same net spacing does not void properly for shape to hole." a) `; ~- @% z: j! i
2012878 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as size differs for customState and customExteded in registry
6 o7 R: \" d/ w" y7 `; B: O2018177 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as size differs for customState and customExteded in registry
. z/ b4 B; q, F" Y; W2019437 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as size differs for customState and customExteded in registry
- n; J3 F) i" r# K- W- V2020491 ALLEGRO_EDITOR UI_FORMS Cannot load custom toolbars because the customState and customExtended Windows Registry entries are incorrect
6 _/ j2 o( A5 H v! l1897843 ALLEGRO_EDITOR UI_GENERAL Function Keys, such as F3, F6, and F7, are not working if tool is idle for some time8 W5 e5 k& R X* S* t7 D; S
2000445 ALLEGRO_EDITOR UI_GENERAL Funckeys not working in hotfix 048 with the new Command Pane as default
( w) U/ j8 E! w2001847 ALLEGRO_EDITOR UI_GENERAL Ctrl related funckeys not working in hotfix 048
C/ g( U- s3 \* \$ x2008112 ALLEGRO_EDITOR UI_GENERAL Funckeys using Ctrl and Shift do not work in hotfix 048 (QIR 7): K0 `+ f% N! z* U; Y$ [
2010370 ALLEGRO_EDITOR UI_GENERAL Shift + arrow key does not move component in release 17.2-2016, hotfix 048; A) P; D; g$ D$ ], K2 @
2015418 ALLEGRO_EDITOR UI_GENERAL Funckey not working
" B. K0 H8 S' a0 E, g: h/ x* l0 e2015443 ALLEGRO_EDITOR UI_GENERAL Text does not regain focus even on clicking after using a drop-down menu
! j* B$ y! J$ V2016899 ALLEGRO_EDITOR UI_GENERAL Dynamic zoom and funckeys are disabled after clicking a combo box in the Options pane
! a8 o$ `. \; G, q. X" @% Q2019753 ALLEGRO_EDITOR UI_GENERAL Infinite Cursor disappears regularly in hotfix 049 when infinite_cursor_bug_nt is set/ S7 h4 R5 R1 o2 W I, Q7 A
2019990 ALLEGRO_EDITOR UI_GENERAL Mouse over does not highlight pin, need to click H1 Z2 Z) `* Z' {* s' \/ b, ]
2020162 ALLEGRO_EDITOR UI_GENERAL Funckeys not working in hotfix 049: pressing F4 not running Show Element
* x* E- V7 W4 J3 Z$ ~9 `9 {* u$ s; e* K2020168 ALLEGRO_EDITOR UI_GENERAL Data tips not shown on mouse hover& a7 }7 u. M5 a6 }8 r
2020840 ALLEGRO_EDITOR UI_GENERAL Page-up/Page-down (remapped to zoom-in/zoom-out) stop working until mouse scroll button is pressed
% p6 v) B; C( O! t1 ~- h# y4 b2021416 ALLEGRO_EDITOR UI_GENERAL New user interface does not shift input focus and zoom in/out does no longer work in layout window$ |! S# z/ k0 J" w( \; a
2022185 ALLEGRO_EDITOR UI_GENERAL Ctrl related funckeys are not working
$ L+ O+ K( F7 H& o5 H3 A) {' U0 N2023402 ALLEGRO_EDITOR UI_GENERAL During Add text, focus does not move from the subclass dropdown to the canvas.' I8 a& H+ G" w
2025806 ALLEGRO_EDITOR UI_GENERAL Function keys and shortcuts not detected4 s; l& i$ x* F! g
2027581 ALLEGRO_EDITOR UI_GENERAL Funckey problem: focus lost from canvas on using another window
1 d# P. _3 t# K1 ^: @1 s2009382 ALLEGRO_EDITOR ZONES When deleting zone by Zones - Manage, the shape in zone is out-of-date8 a. L5 A. u1 Z+ k. B: [
1977211 APD DXF_IF APD: die pads shift after export DXF
! h# z( h( H% I/ @1 l3 Z7 v: a2018483 CAPTURE NETLISTS Error when extracting netlist from schematic (ORNET-1193)$ ?& p/ l N U% o
2022764 CAPTURE NETLISTS Schematic will not generate pstchip.dat file8 g$ E, D/ L) m: ?
1921557 CAPTURE NEW_SYM_EDITO Zoom to region option grayed out
; B# q4 ^/ U2 a3 l5 o- e1945203 CAPTURE NEW_SYM_EDITO Symbol Editor: No Zoom to Region and cannot edit Pin Type and User Pin Properties for multiple pins
2 _& p4 Z, y9 A& ~, n1950178 CAPTURE NEW_SYM_EDITO Ability to remove convert view of a component
3 T, B# H$ b; w1966792 CAPTURE NEW_SYM_EDITO JavaScript error on trying to edit pin name for GP0- ?7 L$ s' M4 ^: @
1969099 CAPTURE NEW_SYM_EDITO Cannot add convert view after creating a part8 b. l+ ~7 M& ?$ X1 E C
1969834 CAPTURE NEW_SYM_EDITO Shapes not mirrored around center if more than one shape selected in Symbol Editor0 K \, W$ q/ ]% A1 F" c# X3 D
1970984 CAPTURE NEW_SYM_EDITO New part is getting Numeric Numbering automatically3 s/ F9 S5 y3 v
1972607 CAPTURE NEW_SYM_EDITO New Symbol Editor: name cannot be edited unless value is entered for a new property
; q+ n) y4 y$ |; H. ?( Q/ f6 p1972635 CAPTURE NEW_SYM_EDITO New Symbol Editor: wrong listing of Symbol Properties in right pane
8 x5 i8 x4 f+ d1974296 CAPTURE NEW_SYM_EDITO Design Template font settings are not being honored for new library/part creation
( d8 l6 i7 n+ H9 E* b$ s1982783 CAPTURE NEW_SYM_EDITO Part Editor is blurry when zoomed out." C3 ]! y) G9 J: Z+ `" W3 @
1993361 CAPTURE NEW_SYM_EDITO Cannot change part numbering, set to Numeric by default0 ?9 I m- o6 ], ~; f. l
2003749 CAPTURE NEW_SYM_EDITO Cannot save edits to hierarchical blocks in new Symbol Editor in hotfix 0481 N }2 V, D. L
2004395 CAPTURE NEW_SYM_EDITO 'Pin ignore' modifications not saved in new Symbol Editor 'Edit Pins' after hotfix 0482 ]: Z% }) L L5 L
2007747 CAPTURE NEW_SYM_EDITO Cannot add Convert View after creating a part
{! b- G/ Q. z# K4 Z, @0 E2011321 CAPTURE NEW_SYM_EDITO 'Place - Picture' is not working for blocks in hotfix 048! [# [- ~* o# w/ P1 T
2013146 CAPTURE NEW_SYM_EDITO 'Part Edit' not updating changes in hierarchical block+ t% z9 r+ m$ z0 u4 l) q7 e
2002904 CAPTURE OTHER Unable to check out Capture license in release 17.2-2016, HotFix 048
: |# O% _# T5 ?. g1 ]9 R2 `2002922 CAPTURE OTHER Unable to check out Capture license in release 17.2-2016, HotFix 048* {$ d ]) w- |- S7 y
1988812 CAPTURE PART_EDITOR Parts created or edited with hotfix 038 Part editor do not use default font size
. s; e+ F# D9 w2008912 CAPTURE SCHEMATIC_EDI Design Compare shows 'NaN' in the graphical output9 v6 q$ D7 Q( a) |
1985701 CONCEPT_HDL CHECKPLUS Library symbols are missing from the examples folder" J2 w- x" {# F8 g6 [
1933789 CONCEPT_HDL CORE honor_sch_custom_texts; G0 z6 h. u9 D+ x0 G
1933892 CONCEPT_HDL CORE HONOR_SCH_CUSTOM_TEXTS
% ]" x, `) V0 { f1 w5 {: Z2001737 CONCEPT_HDL PDF DE-HDL crashes on choosing File - Publish PDF
8 o# D' g0 R F# E" V1 ]- _7 d" l2010508 CONSTRAINT_MGR CONCEPT_HDL Schematic data corrupted on reading the data from CM database using the CM SKILL APIs
& I$ I- \& U; P( E+ a$ {1997461 PSPICE AA_FLOW 'Edit PSpice Model' from 'Assign Tolerance' window does not work
Q# Y9 q* ?( _- D9 N; k2005948 SIP_LAYOUT DIE_EDITOR CTE expansion tool shifts pins off the die
5 z' ^ G2 {/ C2 J1893045 SIP_LAYOUT INTERACTIVE Refreshing bond finger labels causes all the labels to shift location
' y# m s: g3 m" l5 T0 M8 q2006926 SIP_LAYOUT ORBITIO_IF Bundle translation from OrbitIO is incorrect
: s0 z9 m& [' }2006659 SIP_LAYOUT SHAPE Cannot form fillets inside a shape in hotfix 0488 x, k2 I. N; b* n& E
1969192 SYSTEM_CAPTURE CANVAS_EDIT Pin Numbers of Discrete Symbols visible) N9 t w/ {4 ~
1982368 SYSTEM_CAPTURE CANVAS_EDIT System Capture switches to Auto Pan, even if the option is disabled, in the Notes mode4 |) _! I9 c, C8 l1 f4 \- m
1995012 SYSTEM_CAPTURE CANVAS_EDIT Connect lines do not move with components2 i( J0 I! p" E5 h; Q: G
1907992 SYSTEM_CAPTURE CONNECTIVITY_ Draw stubs is not respecting stub length setting.% T/ }: ~4 n: p
1960100 SYSTEM_CAPTURE CONNECTIVITY_ Moving components after routing failure: connect lines do not move resulting in disconnected route
6 w6 m3 s1 b U' J# O, r1988284 SYSTEM_CAPTURE CONSTRAINT_MA Log files and topology files are being stored at the top-level design (CPM) folder level- x' C1 f n+ x0 j1 N
1996039 SYSTEM_CAPTURE COPY_PASTE Cut and Paste change the pin numbers for connector after saving design.
2 W6 ~: K4 E4 ?1951700 SYSTEM_CAPTURE EXPORT_PCB System Capture: Export Physical - Change Directory UI entry block not displaying properly# C/ I/ Z# x* G h; z
1970761 SYSTEM_CAPTURE EXPORT_PCB Cannot import System Capture netlist if PCB Editor is launched with -proj argument
v" ~$ p* A- T+ a3 k9 j1997533 SYSTEM_CAPTURE IMPORT_PCB Pins do not swap in System Capture on backannotation8 T! f2 A ]% e$ H9 A5 t
1910962 SYSTEM_CAPTURE MISCELLANEOUS Dragging GND symbol placed on a pin sometimes disconnects the GND symbol
0 j/ Y, @ @# z' w# V# r) k0 `8 ^1962037 SYSTEM_CAPTURE TABLE_OF_CONT Table of content link number not same as page number in the title block
+ ^! V @* r2 Q2 w% S. B( L1986317 TDA SHAREPOINT Cannot enable Design Management and SSO session expires. F7 o) O: Y: r
2 U+ b* l2 h1 u. U8 L0 V8 Q; I: P' s1 i- x
Fixed CCRs: SPB 17.2 HF049# Q6 `' p! ^$ ?0 J8 N; h3 o% p5 U' Z
11-16-2018% }) R* S8 ~2 R0 R
========================================================================================================================================================; o/ W3 n+ u2 Y* T
CCRID Product ProductLevel2 Title* L* F3 y6 M+ h
========================================================================================================================================================
6 ?3 w& z' E( z: u7 ]2002642 ADW ADWSERVER Exception in adwserver.out with LDAP enabled7 A* g* e8 a* I5 p; ]
2007046 ADW ADWSERVER Component Browser is not connecting to server in hotfix 048) ^3 r" e* s, k ?7 c
1997678 ADW DBEDITOR Model not deleted due to missing cell model relation
8 W. J8 [' D4 |* E1 K1985059 ADW FLOW_MGR Flow Manager issues warning about project path that contains a period, removes from catalog file( W! a' \5 m3 h6 u* g( v& K' |
1991515 ADW FLOW_MGR Flow Specific Tools: Launch error after upgrading to Hotfix 044 and extending code! J. V4 _ W* M6 }
1972762 ADW PART_BROWSER The Schematic Models icon does not match the definition in EDM Component Browser. o! U' W2 M: \0 a5 z
1830062 ALLEGRO_EDITOR DATABASE Uprevving release 14.0 design with stand-alone DBDoctor in release 17.2-2016 crashes; works in release 16.6
9 R; s9 M1 B# f2 H* R' K1980161 ALLEGRO_EDITOR DATABASE NODRC_ETCH_OUTSIDE_KEEPIN assigned to text in library part is not passed to PCB Editor
3 ~( r: G) _) R2003757 ALLEGRO_EDITOR DATABASE Open circuit not detected by PCB Editor: reports unconnected pin as connected, C+ a7 S7 _, E8 a1 @4 z8 h; d
2009748 ALLEGRO_EDITOR DFM PCB Editor crashes on Update DRC
% [! L( B& R4 N: @1796895 ALLEGRO_EDITOR DRC_CONSTR Increase precision of Inter Layer Spacing check
) h& N( K l1 |0 G" T) ~1 T1997487 ALLEGRO_EDITOR DRC_CONSTR Cannot add teardrops to some pins
2 u8 n0 t6 \# a/ N" B7 t1857024 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using funckey 'y FORM mini padstack_list -+'
% [$ ^7 w2 b6 A, A1979750 ALLEGRO_EDITOR INTERFACES axlStepSet not working for component definitions e; v" R% n# T
1988168 ALLEGRO_EDITOR MANUFACT Graphical Compare in productivity toolbox terminates with errors. D9 g. Y0 M+ K6 `! A& ^
1982233 ALLEGRO_EDITOR SCHEM_FTB Netlist files cannot be imported into board as the process is not finishing, y/ h* U! o' p# c
2000367 ALLEGRO_EDITOR SCHEM_FTB Cross-probing between OrCAD Capture and PCB Editor does not work in HotFix 048+ m, O# ]4 i9 A7 `
2000397 ALLEGRO_EDITOR SCHEM_FTB Cross-probing not working with hotfix 048
8 C6 W( ?, T& {. z! \2000552 ALLEGRO_EDITOR SCHEM_FTB Cross-probing is not working if we are importing Netlist from PCB Editor/ G5 V- m3 }- f# r
2001165 ALLEGRO_EDITOR SCHEM_FTB Cross-probing between Capture - Allegro PCB Editor fails after hotfix 048" |2 J; s `( ?0 M/ z
2002635 ALLEGRO_EDITOR SCHEM_FTB Cross-probing issue because of Unique MPS Session in HotFix 048 (QIR7)
, L) M$ _1 o8 l6 E+ |# A2004252 ALLEGRO_EDITOR SCHEM_FTB Cannot do cross-probing between Capture and PCB Editor0 o P, x) W4 {; C
2004305 ALLEGRO_EDITOR SCHEM_FTB Inter-tool communication is not working properly in PCB Editor release 17.2-2016, hotfix 048
. [% o9 v1 T7 T1978660 ALLEGRO_EDITOR SHAPE Static shape on dynamic shape issue: thermals not removed when component is moved+ }5 T5 {( `- ?- ]7 P" A8 d* @5 w
1985035 ALLEGRO_EDITOR SHAPE Thermal reliefs not removed on moving parts
, E& D! |* u! l- d+ H0 m1960966 ALLEGRO_EDITOR SKILL Stackup import is not working in release 17.2-2016 via automation
% ]7 x5 b. C6 v6 L6 q; @# w2003651 ALLEGRO_EDITOR UI_FORMS Error on starting and loading footprints in hotfix 048: message about customExtended and customState, [- `& H4 ^' U8 `, ?. m+ o. `
2003810 ALLEGRO_EDITOR UI_FORMS OrCAD layout editor font size is too small for almost all UI# p5 Z9 w" r, I1 J+ h
2003832 ALLEGRO_EDITOR UI_FORMS Error on loading footprint in hotfix 048: custom toolbar cannot be loaded due to registry problem
9 A' u: m5 T( ]2004769 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as the size of customState and customExtended differs in registry
5 \/ H3 X1 n9 |9 x, a2007669 ALLEGRO_EDITOR UI_FORMS Broken scalability between OrCAD PCB Editor and Allegro PCB Editor1 v% S, r% M9 Q2 B! D
1987164 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding when multiple sessions are accessing third-party tool* x) o9 d0 w, @% ]: R3 S6 V
1983512 ALLEGRO_PROD_TOOLB CORE Allegro Productivity toolbox: Advanced Testpoint Check is not working
6 ]6 h& A6 z- s% O5 _1996008 APD 3D_CANVAS New 3D Canvas does not work in APD! N* S5 M! J0 J( W3 s+ c( B
1993698 APD SHAPE APD stops responding and database is corrupted on moving, deleting, or updating a symbol
4 ]. y6 `" m- h6 |1999446 CAPTURE OTHER Update symbol database in Trial! o) u5 T0 |2 b
1962222 CONCEPT_HDL CORE Nested hierarchy block RefDes transfer issue: suffix added to RefDes3 d8 B2 v2 Z+ N* e
1964260 CONCEPT_HDL CORE RefDes not updated in a hierarchy block on repackaging release 16.6 design: `. @4 Z1 K9 h. O' x
1972243 CONCEPT_HDL CORE Version filter does not work correctly5 M! D8 t% O" v/ F. i0 q
1993448 CONSTRAINT_MGR DATABASE CSet is duplicated with same name when modified in SigXplorer' z1 j4 V0 }: _% d. o) K
1976148 CONSTRAINT_MGR INTERACTIV DRC worksheet in Allegro PCB Editor: 'Go to Source' flickers worksheet and does not switch1 O0 u* s# l/ K; M9 P. o; z6 e
1948372 CONSTRAINT_MGR UI_FORMS cmDiffUtility fails to compare and gives the message 'Failed to read the configuration file'4 X- x$ k4 a7 S; `2 q9 c/ M
1961750 EAGLE_TRANSLATOR PCB_EDITOR Voids and some shapes of third-party board not translated correctly
+ E2 ~) i$ }3 h) ~1984569 FSP DECAP When a pin function is in an interface or custom connector is changed, decaps defined for the part is deleted
/ `( D, t1 Q, B& o' |" Q* A1984588 FSP DECAP FSP crashes when changing pin functions or bank settings for a connector2 b5 q0 a; n* g4 z; K$ `* z2 V
1984590 FSP DECAP FSP design fails to load if pins are defined with a pin function that is later changed in custom_connector.crf
# V! D6 D+ R9 l/ | a1985555 PCB_LIBRARIAN IMPORT_EXPORT JavaScript exceptions on opening libraries converted using con2cap+ B& b/ h* F5 }3 U
1961944 PCB_LIBRARIAN SYMBOL_EDITOR Hide symbol outline in new Symbol Editor/ c: u/ C0 y8 f2 q0 I
1967532 PCB_LIBRARIAN VERIFICATION libimport fails with ERROR(SPDWPAR-102): Metadata has the ErrorStatus value set.
* {3 D q5 M" W9 w1976965 PSPICE SIMULATOR PSpice 'Tools - Generate Report' not working in release 17.2-2016. P4 Z( e, r: K8 ?0 r0 I
1982260 RF_PCB FE_IFF_IMPORT Unable to successfully pull in .IFF file created in ADS. Y5 `# }$ B* i3 ~. F! q; b" a
1981585 RF_PCB LIBRARY Cannot load RF symbol via2 into PCB Editor
2 q( [# l, ?! L+ T, C% k5 l' v1 f8 p1976845 SIG_EXPLORER OTHER CPW trace models do not solve in SigXplorer after changing some trace parameters
- ^( O" R" y7 B5 H# @, ]+ A) Q' M1986466 SIG_INTEGRITY OTHER Delay in Relative Propagation Delay worksheet is displayed as a negative value3 Y" f% Z% M% v# i
1980264 SIP_LAYOUT INTERACTIVE SiP Layout crashes on running 'Manufacture - Documentation - Display Pin Text') c. ]! y+ I1 B" ]1 K/ N" n
1983381 SIP_LAYOUT REPORTS Incomplete Design Summary Report# `6 Y& p) }# E
2005709 SIP_LAYOUT SHAPE Dynamic shape voiding around same net cline segment: no property attached
- [! v) z1 h3 A+ n: a9 s1 z, @2008064 SIP_LAYOUT SHAPE Hotfix 048 (QIR 7): Shape creates void for same net cline, it should be shorted& V9 \/ D9 W- U/ A$ H8 q
1980967 SYSTEM_CAPTURE CANVAS_EDIT System Capture does not reflect part symbol changes2 A2 b2 y0 r( g& U/ m2 q
1988928 SYSTEM_CAPTURE CANVAS_EDIT Changing version 2 of the resistor part makes the PART_NUMBER property visible
6 k7 y& D0 ?- M" c1990215 SYSTEM_CAPTURE CANVAS_EDIT Draw Multiple Bits: Bits do not follow mouse smoothly
/ Q& O3 {, F" s1972658 SYSTEM_CAPTURE EXPORT_PCB Modified injected properties do not get updated in the pstchip.dat file after running Part Manager and Export Physical
8 x, a" ]! l V& B1989421 SYSTEM_CAPTURE EXPORT_PCB Part Manager does not update the PTF values
9 Q! U2 C2 o2 u9 ^+ c% J1992407 SYSTEM_CAPTURE PART_MANAGER Part Manager removes part properties and main window and details window updates are inconsistent, @% G$ c0 ^7 d. k
: c2 _- ]. q( j6 H! s4 a( M5 ]7 U9 j
) K1 h n5 Q! Z) bFixed CCRs: SPB 17.2 HF048
6 Y* Q& T& M" Z7 z0 }4 m9 E: ]; a$ u10-13-2018 j8 I# ?% J; o; {$ ]' h. W. X
========================================================================================================================================================
' |7 M$ g( e# U" b+ P4 RCCRID Product ProductLevel2 Title
* [4 U* s+ A0 C& ?5 X3 K========================================================================================================================================================$ c* }: X4 W" G! E: l
1913039 ADW ADWSERVER EDM Library Server exits with error message on starting library server service9 u) x4 g0 l" x! W4 R t
1709155 ADW COMPONENT_BRO Search query does not search for all the parts in the library
* ]- p3 q1 Z2 j: v1 }) ~! w1827231 ADW COMPONENT_BRO Clicking the 'a' key in Part Manager launched from DE-HDL crashes DE-HDL2 [0 w( N1 |( U. k# L5 A
1903818 ADW COMPONENT_BRO Parts that have comment_body do not display version5 G9 ?% g0 r' ]6 Q0 D# M
1917961 ADW COMPONENT_BRO Component Browser PPL column values are truncated when selecting the top '*' filter% e: V' }, u' c5 P( v* A
1938172 ADW COMPONENT_BRO Symbol version with COMMENT_BODY set to TRUE cannot be instantiated; C D$ R! l+ T
1914103 ADW CONF conf creates incorrect path in fetch_dump.ini when MLR is enabled.
% Y4 ^. P/ s, T1911422 ADW DBADMIN RuleP101 - PACK_TYPE check against schematic model not working. d; x0 H$ R5 X+ U. G& q
1926691 ADW DBEDITOR Adding a new classification and immediately trying to delete it results in errors
6 n7 {" m" A9 U1926694 ADW DBEDITOR Renaming a classification and then renaming it back to the original results in error; Y* L' i/ y& `" l, O# K
1934870 ADW DBEDITOR Adding a new classification and immediately trying to delete it results in errors
+ L/ ?- i! ^$ e2 M6 [& c1872387 ADW DSN_MIGRATION Design Migration does not cache all used parts into flatlib/part_table.ptf9 M) N( N" J" [; B" `: Q
1254292 ADW FLOW_MGR Flow Manager Open Last Project should open last project closed
) U( h7 u9 Z1 X% w7 T% _1281817 ADW FLOW_MGR '-proj' switch in 'pcbdw_fm' does not work; launches Flow Manager without loading any project
$ I+ T) E# I% E2 s( t- b1727286 ADW FLOW_MGR Product options for PCB SI and Power Integrity are incorrect in the flow and tool launchers
' R( L. |" `3 A1875498 ADW FLOW_MGR EDM fails to open or becomes unresponsive.
9 ?) o6 B$ Y, U4 U6 ~% B1879386 ADW FLOW_MGR Unable to access COS with the default Firefox version in the 17.2 installation( x) z2 w: A! f- ?
1922541 ADW FLOW_MGR Warning message for unavailability of Java version appears on opening a project on Linux
# Y* \3 G5 R3 U a0 [" W5 u1945451 ADW FLOW_MGR Checklist does not work with two-byte characters
+ ?! e3 P& X& Q% v/ f1956213 ADW FLOW_MGR Not able to invoke Flow Manager on the remote system
, l# L9 |$ \ T N4 ]1892285 ADW LIBDISTRIBUTI Symbol not consistently available in 16.6 ADW Library
3 h$ A" d. R% Z6 l& a3 I1961731 ADW LIBIMPORT libimport fails to create tar for two Capture models
1 R4 r2 a% u* d" d, J9 C1836620 ADW LRM Library Revision Manager crashes on clicking Help
w( ]( L" f2 y$ J* J) f1961845 ADW PART_BROWSER Error regarding environment variable
- L6 |: x$ ] }1890782 ADW TDA Launching TDO dashboard connected to PLM returns a license error+ u Q# k6 r8 i$ F+ w5 @! }" W: T) k
1980914 ADW TDA Cannot start Design Entry HDL and Component Browser in a TDO design: k% o7 T8 ~3 O' R) @
1833750 ALLEGRO_EDITOR 3D_CANVAS Soldermask Text is not shown in 3D Canvas
4 ]/ \3 g4 M7 [2 C! |& K1891230 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas Viewer not bending PCB with proper radius t( q i0 A- A* p: p0 L. y& w: d: o
1913338 ALLEGRO_EDITOR 3D_CANVAS STEP models missing from exported .stp file# k# k& K: o3 E
1927507 ALLEGRO_EDITOR 3D_CANVAS Get Error: All bend operations are disabled due to licensing and/or DLL installation issues on invoking 3D Canvas
c$ `/ w3 \% n1931508 ALLEGRO_EDITOR 3D_CANVAS Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas
( ~ L( o8 e5 ?& N! O* P" i" M7 X1943060 ALLEGRO_EDITOR 3D_CANVAS Placebound bottom is not showing correctly./ O/ v# o6 p; Q, t ~6 d% o. ?
1950099 ALLEGRO_EDITOR 3D_CANVAS Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas
# O! x) y2 I# y8 C$ |1988307 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
4 U! d! M* n# Y) c/ @# T" x$ h1923585 ALLEGRO_EDITOR ARTWORK Additional unwanted subclasses appear in film control when a new film definition is added5 g8 z, l0 W3 |: C
1944079 ALLEGRO_EDITOR COLOR Export of Board Parameters (Net Colors) does not contain entries for nets with spaces
" O' T$ U- A1 m1856320 ALLEGRO_EDITOR DATABASE Donut pad fails to connect with cross-hatched shape in full contact thermal mode, despite hatch overlap of donut., c5 X) Q- Y" s' `. [$ z1 @
1912313 ALLEGRO_EDITOR DATABASE Database corrupted during background process
1 R* M; f& J2 X7 J1913344 ALLEGRO_EDITOR DATABASE When changing accuracy of design, the thermal relief for donut pad's outer pad connects to inner pad9 [( o8 E5 V3 o+ L
1914470 ALLEGRO_EDITOR DATABASE Release 17.2-2016: export libraries command does not inherit posi/nega information7 N. W5 K. ? `! y4 x4 ?! K( `' d5 L
1932086 ALLEGRO_EDITOR DATABASE Unable to resolve DBDoctor error K. G9 Q# A/ W3 m4 T
1963932 ALLEGRO_EDITOR DATABASE DB Doctor is not recognizing placed parts and showing them as unplaced.
8 o; l" N8 G/ Q8 j' _/ S+ s1987735 ALLEGRO_EDITOR DATABASE Interior sub-lamination backdrill holes are displayed with Top Soldermask pads where backdrill does not exist1 f1 |0 q5 C0 U4 Z2 ]5 j6 a1 K
1977622 ALLEGRO_EDITOR DFM Not able to add value '5' or multiples of 5 in in DFF constraints for maximum stacked via count
: q. E0 e1 z/ t$ b' X4 V0 l1892809 ALLEGRO_EDITOR DRC_CONSTR NODRC_ETCH_OUTSIDE_KEEPIN property is not working on TEXT
0 v5 E( B' i( L# T' p1894765 ALLEGRO_EDITOR DRC_CONSTR DRC for no_drc_component_board_overlap is not created if the place bound is outside Place Keepin0 Z- m) m7 T+ C4 }% E) w8 s3 j
1896627 ALLEGRO_EDITOR DRC_CONSTR Moving components takes long time while doing placement! M1 [( |5 X! b5 V. }
1914591 ALLEGRO_EDITOR DRC_CONSTR Spacing constraints for Mechanical to Hole shows resolved constraints different from the actual air-gap/space' P/ Q. N( U7 R& e- @ T
1956468 ALLEGRO_EDITOR DRC_CONSTR DRC getting generated while moving the uvia and getting removed after updating DRC.
4 X- J6 C/ ^" @0 e8 J( m1884149 ALLEGRO_EDITOR EDIT_ETCH Arced Routing of differential pair creates unexpected arc radii+ y8 }* d' O: \& P. X' n% N" ~3 X
1891985 ALLEGRO_EDITOR EDIT_ETCH Etch edit does not follow the constraints' L# P2 U& _3 p) c; g
1860056 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes on right-click after choosing the Move command
8 }4 h: `% g! i- P# X" U1860723 ALLEGRO_EDITOR GRAPHICS APD crashes on right-click when using the Move command
; Q ]5 C8 T( P7 I1870058 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes when using Place Manual -H command9 H7 N; i4 Y$ F {1 r5 M
1930282 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes on executing axlVisibleDesign(nil) from allegro.ilinit) K) n& ?6 x2 L* D
1882813 ALLEGRO_EDITOR INTERACTIV Unable to set the end point with 'snap pick to' when adding an arc
* f7 h* V/ Q8 B$ S h) P1884725 ALLEGRO_EDITOR INTERACTIV Edit and Move vertex operation not working as desired4 W. f( e$ ^" R+ @
1902359 ALLEGRO_EDITOR INTERACTIV Connector boundary remains ON for a layer if visibility toggles in Shape Edit application mode" d0 N+ T- }5 S; |) U
1909004 ALLEGRO_EDITOR INTERACTIV Parameter description showing wrong for Padless Holes under Design Parameter Editor8 |0 M' g+ }1 S" ]! G2 i
1912055 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes on Delete By Query - AutoSilkscreen - Find By Query" k' o. u2 y+ q. x0 ?9 _, K2 N
1924503 ALLEGRO_EDITOR INTERACTIV Editing shape causes PCB Editor to crash
- g t1 q# R8 m( N- S& \1929614 ALLEGRO_EDITOR INTERACTIV Unable to Place Via Array when Staggered ring is selected in Global Ring Parameters." v7 t6 d# i+ @: Z' Z; B# Q
1938523 ALLEGRO_EDITOR INTERACTIV Change Shape Type message is same for dynamic and static shapes) M$ j4 W* T5 V0 S! H
1940827 ALLEGRO_EDITOR INTERACTIV Irrelevant/incorrect warning message when doing Edit- Change on Clines u! Z( c6 S' W) r) {$ q
1872653 ALLEGRO_EDITOR INTERFACES DXF export shows embedded layers in the layer configuration file
- o7 `3 d1 L6 J$ N1873971 ALLEGRO_EDITOR INTERFACES IDX proposal comments are not shown when importing the IDX file into Allegro
& t6 ?) f4 T3 z2 k4 {% C! ?1892172 ALLEGRO_EDITOR INTERFACES STEP Package Mapping form needs to be larger
5 a" o- \* f9 q1893311 ALLEGRO_EDITOR INTERFACES A line became two lines after import dxf
# ]$ Z: `6 ?. M# ]1937816 ALLEGRO_EDITOR INTERFACES Unit as % in Property Definition not supported by SubDrawing0 A4 }1 ~4 E0 V! H) J3 C
1973084 ALLEGRO_EDITOR INTERFACES Physical library not placed if design and IDF database not matched while running) E) c$ Q4 n4 t) J; u! M
1987526 ALLEGRO_EDITOR INTERFACES IDX import Fails to recognize SURFACE FINISHES Class
9 A. w9 f# F; v1 D1872856 ALLEGRO_EDITOR IN_DESIGN_ANA Message displayed when creating directed groups needs to be improved
2 ^1 x+ t9 }' @" m1900832 ALLEGRO_EDITOR IN_DESIGN_ANA RTP: Return Path DRC does not check circle void correctly/ O8 v8 X( ~6 z, ~
1935641 ALLEGRO_EDITOR IN_DESIGN_ANA Return path DRC crashes PCB Editor, W, w- N7 J) | l8 Y* `
1649465 ALLEGRO_EDITOR MANUFACT Manufacturing options are not visible in OrCAD PCB Designer legacy menu8 L1 j6 q# w' c7 b
1873417 ALLEGRO_EDITOR MANUFACT Autosilk fails to add line information. Only part of the line is getting copied to the autosilk layer.& k2 a/ }9 [- `
1911596 ALLEGRO_EDITOR MANUFACT Documentation Editor drill chart shows two different rows for the same slot.: `( v! }9 ?% E- W# a$ y
1937721 ALLEGRO_EDITOR MANUFACT Drill figure character scaled up in GERBER
3 T/ `+ }% L+ S+ ~6 S- g% N1 A6 t1957768 ALLEGRO_EDITOR MANUFACT Import IPC2581 on cross-section does not import line width and impedance
) X5 H( d( a+ c/ c; K# ?* X* T1969363 ALLEGRO_EDITOR MANUFACT Pressfit connector backdrill depth is considering MNC Layer, \7 Z3 u# p0 c: J& s" y, u2 ~. a
1891102 ALLEGRO_EDITOR MULTI_USER Rejected by server error messages when using Symphony Team Design
v* l% S8 k% v ^6 r9 r+ L1928082 ALLEGRO_EDITOR MULTI_USER Unknown SubClass BOUNDARY/MULTI_USER_LOCK automatically added when defining Artwork Output.
" K* U/ Z0 y. _& b1976705 ALLEGRO_EDITOR MULTI_USER Symphony client disconnects from server without any notification - despite ping mechanism( v9 Y8 W7 Q/ j! D; {
1972554 ALLEGRO_EDITOR NC Mill symbol moved from Nclegend-slots-1-2 to Nclegend-1-2 subclass if nc_param.txt not present: L4 K( B7 `) j* F* j; ?7 F% Y
1914412 ALLEGRO_EDITOR OTHER Autosilk lines do not clear padstacks that are not rectangular( B2 ~. \8 d$ X7 K% b7 s
1921933 ALLEGRO_EDITOR PAD_EDITOR column clearance cannot reset to 0 in padstack editor
0 \. e9 n# \2 Z H3 T1922234 ALLEGRO_EDITOR PAD_EDITOR DBDoctor reports 'illegal value for pad' and does not fix when zero corner radius for Rounded Rectangle is defined- J8 C4 s- |& y' o
1932183 ALLEGRO_EDITOR PAD_EDITOR Drill Symbol information not exported in Padstack XML if Drill Figure in none
" |$ N; [5 D$ o2 _1934880 ALLEGRO_EDITOR PAD_EDITOR Shapes with offsets not displaying properly in Padstack Editor views( Q$ P$ |$ q7 R4 B1 k
1813270 ALLEGRO_EDITOR PLACEMENT When a place replicate module is updated, the vias used in thermal pad are removed( C) J% m3 I! }9 u) z
1840275 ALLEGRO_EDITOR PLACEMENT Placing component with the Mirror option causing display problems
) B! `- U" w, z1 ^+ ~1854099 ALLEGRO_EDITOR PLACEMENT Align components to zero spacing causing mirrored components to overlap
7 P* y: Q* G g% F* }' o& Q1 z1854696 ALLEGRO_EDITOR PLACEMENT Pins shown incorrectly when the Alt Symbol and Mirror commands used consecutively3 U, S/ L* q" M! c
1862863 ALLEGRO_EDITOR PLACEMENT Too many messages in the command window when symbol does not support mirroring; p, O& S; l( @# f& |& ^! b/ ^% T( Z
1909857 ALLEGRO_EDITOR PLACEMENT Using Mirror with Alt Symbol placement displays incorrect graphics# q4 A" _1 u* y3 y
1917128 ALLEGRO_EDITOR PLACEMENT Place - Autoplace - Room when all the components of the room are placed on board causing crash
: ]; T k- ]! j/ R) o- {1925144 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding on using the Autoplace - Room command
+ o) M# ~: l2 l# `( }% Z+ M1961509 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes on choosing Place - Autoplace -Room
8 L: D& L( S1 [) k1930669 ALLEGRO_EDITOR REPORTS Net 'VSS' not included in the Etch Length By Pin Pair Report
4 r6 y5 o8 [& `2 C n1982934 ALLEGRO_EDITOR SCRIPTS PCB Editor stops responding if Generate button is used to create script from journal file
& K* q7 S$ k3 H3 q2 Q3 ~" ~3 }7 E1337346 ALLEGRO_EDITOR SHAPE Shape Check is generating problem point errors that seem unnecessary, m4 e* S8 Z0 U4 C; T
1396692 ALLEGRO_EDITOR SHAPE Zcopy with expansion not following board outline
) e( K- d: X0 h1902001 ALLEGRO_EDITOR SHAPE Shape behaving differently across hotfixes& ?' q I) M3 G8 a4 K! q+ y' L
1921287 ALLEGRO_EDITOR SHAPE 3D canvas is showing some stray objects
. z) u1 T6 ^" V/ B1 T `1936482 ALLEGRO_EDITOR SHAPE Option for Fillet to not obey NO_SHAPE_CONNECT Property
/ ?1 \0 m* |+ x+ D1943899 ALLEGRO_EDITOR SHAPE Only one Shape to Route Keep In DRC in release 17.2-2016 compared to two in release 16.64 t. J/ _; y" V7 e
1944041 ALLEGRO_EDITOR SHAPE shape_rki_autoclip makes shape voiding incorrect
2 e( F) B; [# B9 ~+ i1947675 ALLEGRO_EDITOR SHAPE Shape void error when dv_squarecorners is enabled
" _' N0 ^+ V6 L# m* J1949250 ALLEGRO_EDITOR SHAPE Shapes are filled even after raising and lowering priority
' I! @0 z. }3 O/ \+ R" E2 O1984526 ALLEGRO_EDITOR SHAPE Same net shape voided is inconsistent with respect to vias4 O: q+ c. H3 U) s, j* w4 T2 V
1984955 ALLEGRO_EDITOR SHAPE Dynamic shape creating same net spacing drcs.
7 u" ?" V v3 @0 O, Q/ e1839147 ALLEGRO_EDITOR SKILL axlDBGetLength() reports that the segments of a filled rectangle shape are invalid database ID arguments" w' W( G4 V' b. G+ A l a
1882776 ALLEGRO_EDITOR SKILL SKILL documentation for axlIsBetween() is wrong+ b+ h; X1 C! \
1882882 ALLEGRO_EDITOR SKILL Example for axlMathConstants needs correction in Allegro SKILL Reference
$ X3 t, S3 Q2 y5 j* P* ~1902712 ALLEGRO_EDITOR SKILL axlAltSymbolReplace moves symbol to the top of design while replacing, j9 m) C' K5 Z( v
1906329 ALLEGRO_EDITOR SYMBOL Mechanical Pin to Conductor property set on a pin in a symbol does not pass to the board
) I3 k; [3 Q' W/ H7 _1911343 ALLEGRO_EDITOR UI_FORMS Global Visibility not turning all layers off" L% T) O% @ c0 ?) E
1985584 ALLEGRO_EDITOR UI_FORMS Import logic changes the Current Working Directory" O, Z2 ~, Z$ ~0 w+ |2 C0 P, _
1987829 ALLEGRO_EDITOR UI_FORMS Import logic changes the current working directory. w3 Q4 p; J3 w& y2 R' m/ G& W
1992722 ALLEGRO_EDITOR UI_FORMS After netlist import process, the board file is changing its current path
+ S2 n( v3 h& k$ O- j1697506 ALLEGRO_EDITOR UI_GENERAL Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-2016
1 \* W. Y; m- ?/ X! f$ F" A1702631 ALLEGRO_EDITOR UI_GENERAL Etch Length by Net report does not list correct net name for nets in a bus8 S! c; H+ k. y V1 D
1703105 ALLEGRO_EDITOR UI_GENERAL Bus net names are incorrect in reports when using the allegro_html_qt variable# \% H2 ~7 }& x
1770786 ALLEGRO_EDITOR UI_GENERAL Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-2016
9 C8 v2 A9 b O, W5 Q1784938 ALLEGRO_EDITOR UI_GENERAL Etch Length by Net report does not show net names with angle brackets in release 17.2-2016
' G) ?6 u3 p& B2 p1822557 ALLEGRO_EDITOR UI_GENERAL axlUIWCloseAll is not closing text window in release 17.2-2016* O2 u+ B* t5 |- v6 M# p! E- }
1836400 ALLEGRO_EDITOR UI_GENERAL Net names are truncated in HTML reports2 _5 b* Z2 ^0 R, Q8 v
1869879 ALLEGRO_EDITOR UI_GENERAL Links not working in the Net loop report
1 t* b( J4 z( p. {1 H! G( R9 {5 }' ^1895878 ALLEGRO_EDITOR UI_GENERAL axlUIWClose()/axlUIWCloseAll() functions do not work when allegro_html_qt setting is enabled.
, V+ |, S' V4 n) }1912282 ALLEGRO_EDITOR UI_GENERAL PCB Editor exits with error message on editing objects
# k% G1 t: q9 {. H0 P$ d1913962 ALLEGRO_EDITOR UI_GENERAL PCB Editor toolbars change on choosing View - UI Settings - Save Settings and then restarting
4 R- q" H$ U& K8 h* M1933172 APD UI_GENERAL Cannot paste text into the command prompt without clicking when 'enable_command_window_history' is set. I; M; _5 T+ i0 k& i+ B
1843712 CAPTURE NETGROUPS Signals shown only for first segment of NetGroup k0 g6 _" R2 f
1917768 CAPTURE NEW_SYM_EDITO Missing package pin overview in Symbol editor5 j, f# f5 k) D' m/ J
1920088 CAPTURE NEW_SYM_EDITO Package view missing in the new Symbol Editor h! ?0 r( f* r& t0 ?4 m
1922196 CAPTURE NEW_SYM_EDITO Snap to grid issue in Symbol editor
+ s! g4 \/ G" u: N1927268 CAPTURE NEW_SYM_EDITO View Package is grayed out in release 17.2-2016, hotfix 038 and later versions
+ Q" V1 j1 I6 \8 i8 _1 Y1928012 CAPTURE NEW_SYM_EDITO In new Symbol Editor, View - Package is grayed out1 a6 L/ E9 L A y" Q
1930865 CAPTURE NEW_SYM_EDITO View Package missing in hotfix 0380 g+ g1 g2 d7 e* ~! G! d* ~9 Z
1938507 CAPTURE NEW_SYM_EDITO Issues with new Symbol Editor: Justification and spreadsheet usability+ F4 o) j% I" G4 y# e. v
1940869 CAPTURE NEW_SYM_EDITO Missing pins in 'Edit Pins of All Section' table view for 4k resolution but not in 2k resolution
7 u$ m3 Z2 A6 i! k1940888 CAPTURE NEW_SYM_EDITO Copying pins from a part and pasting on different parts not working properly.3 }! N6 Q) B5 A6 }( Q& j' Y- k
1942994 CAPTURE NEW_SYM_EDITO Cut / Paste of object in New Part / Symbol editor always pastes on grid" v4 p3 M; K: V) i- ~( t# w% \4 n
1944396 CAPTURE NEW_SYM_EDITO JavaScript error while copying from 'Edit Pins of All Sections'
5 x0 B9 v$ }7 E$ _8 Q5 e9 C1950224 CAPTURE NEW_SYM_EDITO Cyrillic alphabets are not displayed properly on Schematic.+ P9 V5 U/ X7 h' r( q3 N. B, C& m% E
1951369 CAPTURE NEW_SYM_EDITO Cancel closes Symbol Editor
4 V9 w3 d' K; e2 J1966785 CAPTURE NEW_SYM_EDITO Edit Part is grayed out
. B0 K4 O, D- X t8 ]6 r9 U+ [1973135 CAPTURE NEW_SYM_EDITO Issue with new Symbol Editor: cannot copy-paste pins
. u* V9 m/ B" K4 ? d& T- r1973344 CAPTURE NEW_SYM_EDITO JavaScript error on opening part from design
" N" |, i5 S$ O* P" M9 I1974122 CAPTURE NEW_SYM_EDITO Cannot copy-paste all pin list on the new Symbol Editor: z( `: }, I- W% e
1983593 CAPTURE NEW_SYM_EDITO Script error on copying and pasting to property sheet" {: f+ ^/ R- ~6 N' j& g3 q
1929692 CAPTURE OPTIONS PACK_SHORT issues with Pin Numbers that contain letters/alphabets
! L! [8 a2 y, k2 u0 ^# u1876939 CAPTURE OTHER Incorrect Capture renaming error (ORCAP-1310)
0 p, Y$ l7 n8 M" Q1 p- s1916090 CAPTURE OTHER Incorrect error message when 'save as' fails due to long directory path- i. e% @0 J! P9 B+ ~: G
1921927 CAPTURE OTHER Two functions are mapped to Shift + R in OrCAD Capture in hotfix 0384 j& R3 L! |9 q/ F, h# n/ x
1946453 CAPTURE OTHER Shift+R shortcut is assigned to two functions.8 ~1 r. F' f; L
1965456 CAPTURE OTHER Shortcut Shift + R is not opening the Independent Sources dialog box
" Q: Z# O0 u9 e0 C6 `- X, N) D3 O1968757 CAPTURE OTHER Close CIP is grayed when right-clicking on the tab in Capture.6 n, a- V, U1 s4 L2 S
1938437 CAPTURE PART_EDITOR OrCAD Capture new Symbol Editor Pin Type missing in table
7 i- u* ^4 [- D- Q, B1 U' G' A; m1906757 CAPTURE SCHEMATICS Intersheet reference is overlapping with the offpage connector name7 H+ r4 L _$ E5 l
1867016 CAPTURE SCHEMATIC_EDI Part placeholders not being positioned when moved$ ]' t# t8 @% }. K" I; g2 O
1932837 CAPTURE SCHEMATIC_EDI Parameters graphics are not correctly positioned
6 D- S9 q5 N# Z! l- X1949518 CAPTURE SCHEMATIC_EDI Getting error when comparing designs
4 j# g* p6 F3 l# E- q1967545 CAPTURE SCHEMATIC_EDI Only section A of heterogeneous part being placed and not sections B, C, or D- w! N. q; @. x0 [. b4 S# C
1933919 CIS DBC_CFG_WIZAR New CIS Configuration .dbc file created in release 17.2-2016 shows release 16.36 ?6 x* j% k# O* K h
1932550 CIS RELATIONAL_DB VIEW NAME in Relational Database configuration is not working as expected.
5 k, O; P, j0 S2 _1832524 CONCEPT_HDL CHECKPLUS Default checkplus rules show body height of 0 (sym_2 of the attached cell). This causes the cell to fail verification.
4 Y4 k/ N) K" x0 e' j. o% N1912023 CONCEPT_HDL CHECKPLUS signalWidth predicate does not recognize SIG[1..0] as bus.4 ?& Z7 S m! _5 ]4 l9 f6 q. r
1966120 CONCEPT_HDL COPY_PROJECT Copying release 17.2-2016 project results in message stating the project is of an older version+ H" m. B3 S. o& r; N1 G
1879425 CONCEPT_HDL CORE Adding signals with the right-click menu is not following the defined color scheme
S# M H+ V ~+ ?; Z1890542 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1911) when running export physical with backannotation* \$ w) S8 f" f6 E4 U: U2 ^4 a( q
1907684 CONCEPT_HDL CORE Moving symbol makes canvas unresponsive for a long time
0 @( u1 |: z0 y. U7 t1920711 CONCEPT_HDL CORE Pin names changes when mirroring the swapped section.
4 h) P/ p; ?: p2 I1931421 CONCEPT_HDL CORE On Linux, 'cpmaccess -read' returns incorrect value, h2 J0 K$ j* r1 l& J+ p5 y5 L' q
1931782 CONCEPT_HDL CORE Setting DONT_FORCE_ORIGIN_ONGRID to ON does not work for sig_name
% J" C) @) O) Z; i6 `- ~1932433 CONCEPT_HDL CORE _movetogrid causes signal disconnection8 {3 Z/ Z- e% s5 A2 o2 I
1946993 CONCEPT_HDL CORE DE-HDL Part Manager fails to update parts on schematic if new KEY properties exist in PTF but not in schematic' B6 C! Z/ U! h! A0 b( S( e/ Z
1947029 CONCEPT_HDL CORE Design Entry HDL Font Support not working for signal rename
9 @/ g" w/ E: { f2 U2 B, f! Z. I1962865 CONCEPT_HDL CORE Schematic symbol creation with '-' as pin name not packaging$ q) s& B+ f! a, A
1966805 CONCEPT_HDL CORE Issues with packaging design containing cells named with a leading underscore
- h& N K0 }3 a8 @$ R( p) p1 O5 k1967760 CONCEPT_HDL CORE DE-HDL crashes on moving Net Group/Port in release 17.2-2016, hotfix 044
, Z8 ^$ @2 P B9 Z+ T1 C1968282 CONCEPT_HDL CORE DE-HDL Part Manager fails to update parts on schematic when new KEY properties exist in PTF and not in schematic
3 Y/ E; j1 ]" r" b1972815 CONCEPT_HDL CORE Part Manager not updating missing key attributes from the ptf file by using 'Update instances' option: a& i* w3 p: w
1887790 CONCEPT_HDL CREFER CRefer links not working in selected cpm file+ }6 B o/ c! {, {8 J
1898535 CONCEPT_HDL INTERFACE_DES Global Navigation window does not reflect removal of a net on page2 that is part of a netgroup on page1
9 ~4 v3 w, A7 R8 R0 O4 D8 w/ h4 j1888048 CONCEPT_HDL PDF Japanese characters are not output correctly to PDF on Linux.! T9 @4 M- }6 T+ c, D( D
1937505 CONCEPT_HDL PDF Missing intersection dot in schematic PDF3 E& r9 T$ f# g! Y8 \+ M ^
1942486 CONSTRAINT_MGR CONCEPT_HDL CM crashes when you save after importing a TCF file6 f! t- q: z0 b+ {8 F$ K* T
1983743 CONSTRAINT_MGR CONCEPT_HDL Region Class-Class members are being duplicated in CM in the current session
q' g& A" j/ D! @2 @/ r) m1906573 CONSTRAINT_MGR ECS_APPLY Database corrupt and DBDoctor reports illegal database pointer error
% ?9 ]* p$ |: k# J8 w6 }1913805 CONSTRAINT_MGR OTHER Setting environmental variable CM_PARTIAL_DCF in release 17.2-2016 causing crash
; ?) J; M, |4 K4 g1 O; H1914813 CONSTRAINT_MGR OTHER C++ Runtime error and non-recoverable crash in class-class worksheet
3 L% k; C" _; G1920142 CONSTRAINT_MGR OTHER Xnet names are not consistent in the design
+ H$ |/ N: |* d4 {1898549 CONSTRAINT_MGR SCHEM_FTB Importing netlist causing crash in release 17.2-2016, hotfix 036
% d4 O, n& }% k, V$ }- u. u1814851 CONSTRAINT_MGR UI_FORMS Field solver /DRC check running forever3 d, t! N' Z+ w. e3 I: w* G
1889862 CONSTRAINT_MGR UI_FORMS PCB Editor hangs while assigning net voltages in CM# m6 E( k& C- I1 z- a6 r5 m
1965470 CONSTRAINT_MGR UI_FORMS Constraint Manager GUI Issue in release 17.2-2016, hotfix 039: Font size small and rows/columns in shrink mode
$ r/ A7 q Z9 N2 i% @8 f7 R1945406 ECW ADMINISTRATIO Tree view was not refreshed soon after changing the site permission." Q; W% V' E' |, [& e
1826848 ECW METRICS SPDWECW-551 and SPDWECW-553 should be warnings, not errors
- Z J& i( [$ Y$ Y9 G' }4 Q1933373 ECW PROJECT_MANAG ecwbatch does not accept password and does not ignore invalid users
- Q/ ~; l. W7 e: H# B: O, \3 S1921502 F2B PACKAGERXL Errors on running Export Physical:SPCOPK-1138 and SPCOPK-1149
& B& Y5 w7 ]2 G+ T4 J: j6 [$ y. n1929846 F2B PACKAGERXL PackagerXL is still creating the pstcmbc.dat file on a release 16.6 design uprevved to release 17.2-2016
7 p* i b9 w) Y j& h1953780 F2B PACKAGERXL Updated subdesign package information not updated on the top-level design in the reuse flow
& ^, C1 i2 X. V$ @1971738 F2B PACKAGERXL Deleting blank space from pstxnet.dat file crashing DE-HDL' c& g6 H1 z2 e- \2 u/ @
1891002 INSTALLATION DOWNLOAD_MGR Issue with Download Manager (Change Preferences Option does not Work)
. b: o$ G# f W4 M7 r, C1972890 ORBITIO OTHER OrbitIO-APR failed to run if PCB design included
4 ]( |5 Z e. q1954262 PCB_LIBRARIAN CORE Footprint model check in fails with verification checks failed error2 F7 U: \7 \ m( F& p
1943656 PCB_LIBRARIAN GRAPHICAL_EDI Symbol Editor is blank if .ascii file is newer than .css file" h: A8 @& g: s: ?' Y; r# T
1897887 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Inconsistent symbol results when adding vector pins in Part Developer
, y C( D# }* o3 X: F* ?6 q1898003 PCB_LIBRARIAN SYMBOL_EDITOR Issue with Page Border Symbol W1 `5 X0 ~; ~. G* E. L0 B
1842007 PSPICE LIBRARIES Change required in swit_reg.lib' o' V- F, }% ^, j
1906922 PSPICE LIBRARIES Mismatch in mapping of IC pins in model and PSpice template for analog device AD8138( m5 \& G) e" a
1947586 PSPICE LIBRARIES Update the model AD8138/AD in ANLG_DEV.OLB
. u9 D& X9 h* L$ G8 g7 u+ G/ S1748470 PSPICE MATLAB PSpice displays an error when sending current in co-simulation
2 T& }# D* l1 Y' q. E1802455 PSPICE MATLAB Incorrect current direction for pins in SLPS flow$ B2 x1 _ W/ ~$ J/ W7 c% U s
1852811 PSPICE MATLAB ORPSIM-2604 being reported in SLPS simulation0 S* E, B) s+ t, e; v/ R" D
1858716 PSPICE MATLAB Co-Simulation fails if 'RC' is used as reference of resistor
' |) P( s; M" [7 \1921641 PSPICE MODELEDITOR Model Editor in Client Server installation slow to invoke: n' Y8 x/ V" {" N: y
1922160 PSPICE MODELING_APPS New Capture Associate Symbol GUI not reading libraries
% \7 E- }8 @. G9 V* l) x* ?1843698 PSPICE PROBE PSpice icons appear very small on a specific computer
2 r6 J* n, K2 k6 V5 E1773841 PSPICE SIMULATOR orSimSetup64 crashes when running the simulation for attached design' F( ]* F* v$ r0 M& d" F+ w
1816316 PSPICE SIMULATOR Simulation stuck; however, the status bar is correctly updated during Pseudo Transient Analysis( m6 c' p1 l3 S
1887119 SCM IMPORTS Cannot selectively update changes in VDD& H1 Y6 A: h X
1889362 SCM IMPORTS Cannot selectively update changes in Visual Design Differences
8 |' N; t7 ^0 s! X2 t1958545 SCM SETUP Auto assign models does not work in SCM same way as in DE-HDL
3 ^- H% ~) p2 ?1988841 SIG_EXPLORER INTERACTIV SigXplorer stops responding or crashes in hotfix 047 when a design is saved
% n- R7 h8 L. L: r) h) k4 z1988943 SIG_EXPLORER INTERACTIV SigXplorer crashes on selecting Update Constraint Manager
1 m, c D! T5 t$ c1991375 SIG_EXPLORER INTERACTIV SigXplorer crashes when clicking Save
! h0 t# \) n5 e8 c2 @% f% x1 ?3 k$ k1993749 SIG_EXPLORER INTERACTIV SigXplorer crashes on saving topology: |. G/ V+ |$ i3 q8 s
1969975 SIG_INTEGRITY GUI Model Browser edits model above the one that is selected
0 W+ w/ P+ Z8 a5 }. S1953184 SIP_LAYOUT IMPORT_DATA Sub Drawing not saving dashed lines
H6 J6 ]4 ?; ?6 a7 E1913864 SIP_LAYOUT ORBITIO_IF SiP Layout design import results in wrong die rotation
0 `% [2 {; h* v& t' X5 ^1880237 SIP_LAYOUT PADSTACK_EDIT Background Window comes to the forefront when closing the Padstack editor6 n% J2 V7 Z1 ^- E. p9 _7 l' b% _- e
1972560 SIP_LAYOUT STREAM_IF GDS Export fidelity issue: inverted arcs
% L x- Q, I7 E# @5 I( c1 u1920317 SIP_LAYOUT THIEVING Thieving pattern does not allow for OOPS operation0 f* o& J2 _7 u7 n
1909075 SYSTEMSI DOC SystemSI PBA channel and circuit simulations do not respond if bit pattern is 1s or 0s+ m# m/ M; b/ q% S5 B
1916101 SYSTEMSI DOC Lack of stimulus in file causes Serial Link Analysis to become unresponsive
* R: A# i% B% F9 V1919562 SYSTEMSI ENG_PBA SystemSI generates wrong timing bathtub curves in channel simulations for write and read" n2 G8 p/ d% i1 u! d
1964064 SYSTEMSI GUI_PBA Able to sweep AMI parameters in SSI-PBA$ T5 X2 c0 C8 w7 Y+ {# N" }
1971266 SYSTEMSI GUI_PBA MCP header shows only 49 ckt nodes instead of 52 for s52p S-parameter file
. S V& Q2 R& W. Y/ T0 G) c! M1885625 SYSTEMSI GUI_SLA Manage AMI + DLL from Setup Analysis Window
/ X2 A3 O+ y- y! H4 Q1924382 SYSTEMSI GUI_SLA Data Rate field in SystemSI Stimulus property form is confusing for PAM4 operation
! R# P+ B, `5 a4 C- ?$ E) l1982341 SYSTEM_CAPTURE CANVAS_EDIT Signal rename does not maintain new signal name value
$ } L" \/ a; `" M5 v u9 C1976857 SYSTEM_CAPTURE CONSTRAINT_MA System Capture-CM Match Group Creation is not updating correctly0 _4 E+ x# f- ]0 A2 O
1929606 SYSTEM_CAPTURE DESIGN_CORRUP Opening design causes System Capture to crash; }9 n- d' l/ v% O
1914697 SYSTEM_CAPTURE DRC Overlapping component DRC does not work
; R$ P+ H$ R. F. L$ Q1973467 SYSTEM_CAPTURE IMPORT_PCB System Capture Import Physical shows many component and physical differences on a design that is synced up$ o L" {5 C+ q+ p: {! p* [
1962603 SYSTEM_CAPTURE NAVLINKS Ability to not underline hyperlinks for Navigation Link values
% B; s; q4 z. Y# E- {9 ?/ T" r1967639 SYSTEM_CAPTURE PART_MANAGER Part Manager does not open in System Capture for part property value changes even after setting the cpm directive.4 w9 L3 P4 P9 t6 j, Q
1964388 SYSTEM_CAPTURE SMART_PDF Some shapes are not visible in the smart PDF schematics! V- h! C5 ^( d; _. A. x E
1976832 SYSTEM_CAPTURE TDO Rolling Back local lower-block requires check-out of higher-level packaged & variant views0 d4 \5 N, w6 j7 i2 @; O' J
1976844 SYSTEM_CAPTURE TDO CM - TDO check-out dependencies are broken
7 q: W, P/ ]" g) Q0 s1976859 SYSTEM_CAPTURE TDO Variant Editor in System Capture -TDO allows to delete a variant without checking out variants view+ `( D% ]+ U" J
1839816 TDA CORE All the design objects are locked in the EDM dashboard after a DSFrame error
' b$ c) X: V) ]+ ^! |$ p2 T' j: F1889898 TDA CORE Cannot check in the top level of the project in TDO8 I |3 U8 c2 [7 v# V. j
1892411 TDA CORE Unable to undo the block checkout if something fails
3 f% R3 k" n& {/ B1877757 TDA DEHDL Refresh Hierarchy does not show latest TDO lock/unlock status in DE-HDL6 t' A/ V6 V' S* N- _; S
+ b* V- }% f+ `4 W
+ Q* t, V, O c" i5 `, _) HFixed CCRs: SPB 17.2 HF047
. k3 Q* X& A- w# n1 ]3 N09-9-2018; y5 T& [, W: x2 {" D
========================================================================================================================================================% p: e0 B" B; y; e5 x; b
CCRID Product ProductLevel2 Title
+ M) U! N, G9 Z# U4 S6 k: y* c; v========================================================================================================================================================
# q! c' j E- Y: r3 @1969527 ADW LIBIMPORT Getting java.lang.NullPointerException error on bulk import in hotfix 044
2 H/ z0 n6 ` s/ k$ b! s1976219 ALLEGRO_EDITOR DATABASE .SAV file not created although message states it is created
" U8 y( U* r9 X8 h0 e4 H! q' R1968270 ALLEGRO_EDITOR DFM PCB Editor crashes when running DRC
S" o1 G$ }& N. K1978421 ALLEGRO_EDITOR DRC_CONSTR False DRCs between via and its fillet shown after editing shape boundary9 B& j: H; a7 T; y) m, y w' Q4 |
1966772 ALLEGRO_EDITOR PAD_EDITOR PCB Editor and DBDoctor crash on editing DRA file: Found bad pointer, run dbdoctor
6 R, a# h V: ~, q1973866 ALLEGRO_EDITOR SHAPE PCB Editor crashes when deleting a group
3 q% n! F; g5 G) u1818779 ALLEGRO_EDITOR UI_FORMS Dialog box goes behind main window on clicking PCB Editor canvas
, j4 G) V; b0 y1 y1880175 ALLEGRO_EDITOR UI_GENERAL Multiple sessions of PCB Editor gets mixed up in Linux in release 17.2-2016) s$ s% Z$ g" t9 z3 ?1 N
1946027 ALLEGRO_EDITOR UI_GENERAL Arrow Keys in Canvas stop responding after changing the view.
1 C) @& @& O0 Z0 r2 L5 S1967701 ALLEGRO_EDITOR UI_GENERAL Arrow Key panning does not work when third-party SKILL call is active8 a# F$ ^* k; @* [8 H
1967706 ALLEGRO_EDITOR UI_GENERAL Observe Special Characters when command is run
: p- T1 ~4 t+ G& t1 N1971183 ALLEGRO_EDITOR UI_GENERAL Focus is lost from command line when Save icon is used
3 d* U, l6 F+ y( r4 j$ M$ N" l1971186 ALLEGRO_EDITOR UI_GENERAL Focus from Command line is lost when using CTRL + N
7 M6 K3 ^/ f* q h7 I" ?1971190 ALLEGRO_EDITOR UI_GENERAL Focus from Command line is lost when using CTRL + Alt
J1 N3 e: s! P$ l1971200 ALLEGRO_EDITOR UI_GENERAL Focus is lost in comand line when you save using command save
) o; u& @1 W6 g7 F+ F1961833 APD SHAPE Crash when changing dimension of existing via padstack in the design
4 M! w( `+ a# b4 y9 \! f! i6 L' d1968256 ASDA EXPORT_PCB SDA crashes directly after Export to PCB% [( J9 f5 m1 T, X; R( J% d
1970284 ASDA EXPORT_PCB Placing part crashes SDA4 F+ g8 a/ Y2 }4 ]! c+ E9 m
: e6 @# u" y4 O& G9 U; _2 ~" E. j
; |+ [- J9 ?9 _5 vFixed CCRs: SPB 17.2 HF046: A& [/ A N2 C
08-24-2018) \7 L2 s% b, e! `, P
========================================================================================================================================================7 y; Q% q0 `& K
CCRID Product ProductLevel2 Title$ t; V- A) h1 n- h
========================================================================================================================================================( o* ^* l5 ^% E: a
1880800 ADW PART_BROWSER Server connection failure on a running SDA session.8 L* ?8 o/ [) p: V& b* y
1880895 ADW PART_BROWSER NCB - components missing from the component browser* I% m) r# l6 J- n) \
1962336 ALLEGRO_EDITOR INTERFACES Smart PDF shows both top and bottom probe layers for a film layer with only a single probe layer (top or bottom)
0 Q1 O8 c, P$ U& v1955128 ALLEGRO_EDITOR MANUFACT Need to close PCB Editor to delete xsectionChart.log generated on placing a cross-section chart
2 b5 i7 ^1 |( q' a+ W ]2 [# e* e1969088 ALLEGRO_EDITOR SHAPE PCB Editor crashes on updating shapes to smooth
9 d+ c6 H( \+ r9 Y# h1963828 ASDA DESIGN_EXPLOR Unwired schematic block movement with text is not correct
9 a3 z h; Q% ~ T# l1 w& ^1954426 ASDA OPEN_CLOSE_PR Double-clicking to paste a note crashes SDA& }! F8 B) W, Z1 b: L' m
1965423 ASDA OPEN_CLOSE_PR Crash when working with notes in SDA
. F! n0 B- h( F) o0 A; O; e1960060 ASDA PART_MANAGER Original property differences not displayed in Part Manager on selecting a new part from CB and doing reset
! ^* m$ H4 s/ a" ?1 F# l1960112 ASDA PART_MANAGER Part Manager incorrectly updating part property values( ~- f6 l2 o+ [( |- N
1955723 ASDA ROUTING Draw Multiple Bits misses bit 0 when in reverse order., Y9 E! J4 p( ^2 i
1952963 CONCEPT_HDL CORE Variant Editor takes a long time to load; @' D! H! n# L
1962568 CONCEPT_HDL CORE Directive DEHDL_BROWSER_FILEPATH does not work+ P; I" T. C' v( r0 d3 n
1939192 PCB_LIBRARIAN SYMBOL_EDITOR pin_text size and location very different between DE-HDL and Symbol Editor resulting in text overlap* ~6 c+ c; q, e
1952967 SCM OTHER Error while copying a release 17.2-2016 design: message says design created in release 16.3 or an earlier version; {+ u; a% u1 X3 y2 l7 m$ p* [! Z9 _/ W
1948999 SPIF OTHER Some place_keepout shapes and antipads not exported. Z& _: O5 e8 a* R- i" P
; h8 o' Z# \! u& O; V" e) [, q; K. d2 D5 P0 E0 `. D
Fixed CCRs: SPB 17.2 HF0459 A9 v. r8 c7 {2 w# _% Z' T
08-10-2018
; w1 ^* N; g2 P B8 m3 l========================================================================================================================================================' a3 Z+ ^3 U8 D0 h
CCRID Product ProductLevel2 Title8 w. K: i* X9 W% T# w6 R7 v
========================================================================================================================================================
6 p& q2 ~! | r) I9 ^1934956 ADW DBEDITOR Footprint missing from part in release 17.2-2016
5 y7 f, c& R5 i7 x! a5 U G1945005 ADW DSN_MIGRATION Right side of Migration dialog box is cut off9 z& M% x1 [; B% D9 i
1933245 ADW FLOW_MGR 'Open last Project' button should open the last opened project- b. V x& F* f/ F& B1 y
1953210 ADW LIBDISTRIBUTI Library Distribution is not distributing all symbols. No errors for the missing schematic models.( i) k1 W( j, }9 N1 L: A
1953727 ADW LRM LRM missing two symbols when migrating from release 16.6 to 17.2-2016
" T( s, H4 [& `5 n/ ?1952923 ALLEGRO_EDITOR DATABASE PCB Editor crashes on trying to delete layer3 w5 ]: ^9 `+ e% V8 \7 N, x6 s
1957171 ALLEGRO_EDITOR DATABASE Pastemask offset not working when creating a symbol that requires two top-paste masks
. E: u4 z. S, c o8 O. H1960059 ALLEGRO_EDITOR DATABASE Stackup definition causes custom script to crash
! ]8 }. r& g! |4 k7 h" ]# d1932864 ALLEGRO_EDITOR DFM Exporting DFM Constraints losing the association to design level2 s7 E! C: Q) q' f$ z( V. u. h
1957467 ALLEGRO_EDITOR EDIT_SHAPE Compose Shape copies lines to wrong subclass
, O7 p) a7 K3 y' H5 b7 e w1938536 ALLEGRO_EDITOR GRAPHICS Multiple crashes on different boards after installing hotfix 0407 g8 g( [+ a7 [# I8 B' n
1954075 ALLEGRO_EDITOR SHAPE Dynamic Crosshatch shapes should be clipped inside RKI if RKI Autoclip is enabled
, q }- K! D- r# T1957803 ALLEGRO_EDITOR SHAPE Wrong dynamic shape status0 o! h9 M$ p& W$ \. B! j# Q
1949923 ALLEGRO_EDITOR UI_GENERAL Focus lost from command window when any command is active/ W6 h9 ], o9 B/ T- {
1963245 ALLEGRO_EDITOR UI_GENERAL Alias behaves as Funckey in release 17.2-2016, hotfix 044
7 X4 E% d. V) {1892126 ALLEGRO_PROD_TOOLB CORE Clines disappear and then reappear suddenly on using Route - Shield Generator' A0 c" M7 \. F+ \$ @3 f$ ]
1931127 ALLEGRO_PROD_TOOLB CORE ZDRC not working for Xhatch Shape3 m& O, K2 q9 A3 ^ c
1932563 ALLEGRO_PROD_TOOLB CORE allegro_legacy_board_outline environment variable not set in PCB Design Compare.- m6 y- V' _4 \ ? Z" f5 k! D
1929855 ALLEGRO_PROD_TOOLB OTHERS Outline not exported correctly for PCB design compare if Design_Outline and Cutout exist
4 ^& n9 N4 g% ~+ U% O4 S8 u1956494 APD DATABASE DBDoctor removes pads
; i+ i" q: {4 y, Y4 I& `- l1956291 APD INTERACTIVE axlSpreadsheetSetStyleProp should accept 0 and 1 as Boolean values for protection style' p0 k5 H+ \/ ~3 _$ K2 U
1960127 ASDA ARCHIVER Using the Tcl command 'archiveproject' crashes SDA( K( T, C$ k# [
1953718 ASDA CONSTRAINT_MA SDA Import Pin Delay fails with extra columns, does not explain why% [' D) Q, Z1 `& Y
1924498 CAPTURE SCHEMATIC_EDI Cannot place part 'B' for heterogeneous part if 'Preferences - Miscellaneous - Auto References' not set, ?1 E5 Z& S' D
1927129 CAPTURE SCHEMATIC_EDI unable to place heterogeneous part section directly from place part window
4 i: k# D' M# z Y* C7 ^4 i1928255 CAPTURE SCHEMATIC_EDI Unable to place a specific section from Place Part0 G+ \, |3 ?$ p+ l2 B$ f
1945207 CAPTURE SCHEMATIC_EDI Part selection pull-down reverts to part '1|A' when placing heterogeneous part' M9 O2 G( j) o
1945661 CAPTURE SCHEMATIC_EDI Section drop-down in Place Part window is not working6 M7 h$ _* c9 \& C; ?) Q& q3 J2 q
1958121 CAPTURE SCHEMATIC_EDI Preview and placement of sections of Heterogeneous parts is not correct in New Symbol Editor# b- _3 B' q3 {3 e0 W
1956535 CONCEPT_HDL CORE DE-HDL crashes on Import Pin Delay for a CSV file
/ r; |- L" g {" ^3 }1960922 CONCEPT_HDL CORE DE-HDL crashes on moving netgroup on Windows 10
$ B& ]# U# f1 ]9 }2 J2 ^) H1964016 CONCEPT_HDL CORE In DE-HDL moving around nets connected to Netgroups causes crash on Windows 10
+ f) p5 {1 E7 u8 X1907040 F2B PACKAGERXL Export Physical output board file name reverts to old when changing options
% Y" x7 o* M) t8 i8 E b1 T9 d( H1957862 ORBITIO ALLEGRO_SIP_I allegro2orbit failed to translate rounded rectangle padstack
# v( V4 A( I3 i9 k3 m) l' U0 w. R( T8 g- o$ d1 t: ~" Y
$ ~; a: _$ U+ W0 xFixed CCRs: SPB 17.2 HF044
C3 e# h2 `- ]4 A8 E7 }07-27-20187 z/ {5 F) h% Q* L# G' v7 d' L
========================================================================================================================================================
' A$ q5 ^: M2 H& C0 ~CCRID Product ProductLevel2 Title, }+ @: {, b9 f/ w# {
========================================================================================================================================================
% v8 M( G3 ]& C7 X; y1943727 ADW DBEDITOR EDM DBEditor: Cannot check in/out schematic model symbols with many linked parts+ ]) f) ~4 G9 U
1800630 ADW FLOW_MGR Support spaces in design directory path on Windows
1 e* K% m% O! C$ C+ E2 o1951052 ADW LRM LRM stops responding on project update and removes parts from design& T" k. ^: R ^3 l1 D" m8 J1 l
1891428 ADW PART_MANAGER Resistor turns into a capacitor when placed
8 O7 [; }# F1 X- z, V. P! o, E1945194 ALLEGRO_EDITOR 3D_CANVAS 3D Viewer crashes when opening from board file.% P4 u/ M( i$ A4 c8 U* w
1935558 ALLEGRO_EDITOR INTERFACES Exported STEP file missing components when viewed in free STEP viewer% y8 C6 o: t j3 A
1945640 ALLEGRO_EDITOR MULTI_USER Symphony client disconnects from server without any notification
) C* l( _* v8 N% U, r' P* L) W% K/ A1948454 ALLEGRO_EDITOR MULTI_USER Window DRC stops responding when run in Symphony
" o. L0 K- @8 l. y6 r1946619 ALLEGRO_EDITOR SHAPE Pin/via with suppressed pad on shape layer and thermal connection type of none should void to drill hole.4 k R# f! t1 }0 x5 r S
1946708 ALLEGRO_EDITOR SHAPE Same net hole to shape voiding is incorrect.
; w: ]- ^( S2 T/ b/ m1952213 ALLEGRO_EDITOR SHAPE Shape voiding from Thru Via when the via regular pad is not completely drilled out by Backdrill hole is not consistent
7 J! m( k+ y$ J2 ]7 X1889433 ALLEGRO_EDITOR UI_GENERAL Command window shows result at the end of a command rather than showing dynamic updates
1 K9 R5 `3 A( A% h1933503 ALLEGRO_EDITOR UI_GENERAL Extra click required to enable command window
3 N! |4 T! K# Q/ h1943692 ALLEGRO_EDITOR UI_GENERAL Funckey commands are not working
8 A* _7 ?$ b4 S1945914 ALLEGRO_EDITOR UI_GENERAL Mouse focus lost in the command console when doing an 'undo' from the toolbar icon$ M4 O# h! \2 x
1945920 ALLEGRO_EDITOR UI_GENERAL Focus lost from command window when the toolbar is used for any operation- m2 b9 `, P. A
1949922 ALLEGRO_EDITOR UI_GENERAL Focus lost from command window after save or even autosave. m& T3 G) W1 `; R8 k
1947551 ALLEGRO_EDITOR WIREBOND PCB Editor crashes in wirebond edit mode
8 j6 j' d4 s9 Y2 g2 T) \1935722 ALLEGRO_PROD_TOOLB OTHERS Panelization: Cannot place parts after migrating design from release 16.6 to 17.2-20167 X4 f4 r, Q7 X7 s$ p0 k9 R/ w# V- }
1951511 APD REPORTS The result of Metal Usage Report is incorrect.
, v- }. V F' y; A1952942 ASDA GRAPHICS Need metric (mm) support in grids in SDA+ c8 t4 @' W; A1 W
1948122 ASDA TDO If user ID has uppercase characters in teamassignmenttemplate.xml, TDO fails to join a project- o1 S+ O- p# _2 k6 t
1931199 CONCEPT_HDL COPY_PROJECT Stop hard coding Copy Project license inside EDM- f2 C0 A9 k4 W$ h) @' Q0 \
1938153 CONCEPT_HDL OTHER Component Browser stops responding on replacing and modifying components
2 C: }8 {) R4 H2 Q2 l. O1770601 CONCEPT_HDL PDF Wire Pattern set to two-dot chain line not shown in PDF/ K5 s( q$ K8 R3 ?2 q
1791175 PCB_LIBRARIAN CORE Allow baseline of cells with pins at symbol origin: change error to warning
" G: D# ?( |% ?1922238 PCB_LIBRARIAN CORE Unable to check in into EDM Server due to con2con error SPLBPD-323 - Origin on pin connection point! U" r) ~$ d# q$ b9 x; A9 m. Y
1936812 PCB_LIBRARIAN GRAPHICAL_EDI New Symbol Editor: Wrong text being updated when editing text after copy and paste& s M& X# M) \; i1 S3 l
1804159 PCB_LIBRARIAN SYMBOL_EDITOR Copy and paste of pins in new symbol editor: issues with pin name, rotation, and move* p. a/ N( E& |; g2 C8 g
1927422 PCB_LIBRARIAN SYMBOL_EDITOR Symbol outline not updated correctly in the new default graphic editor in Part Developer release 17.2-2016
5 t6 u) @7 G9 s1 O) I" d" k4 s1939272 PCB_LIBRARIAN SYMBOL_EDITOR Symbol Editor changes origin to bottom left, outline to invisible, shows rectangle with center rectangle at new origin
u: _+ X6 ]+ O" t% V$ v1928076 RF_PCB DISCRETE_LIBX dlibx2iff does not work with managed libraries and library-level PTF) d4 O% @$ L) A- A0 P: |
1929574 RF_PCB DISCRETE_LIBX Discrete Library to third-party Translator does not populate the Available Parts section correctly
3 r7 `. p5 J7 F: l- A, ^9 }7 Q1850360 TDA CORE TDO crashes while changing the root design; A R. u. f0 w8 O
1934388 TDA SDA SDA TDO crashes on attempting to check in a 'New Block in Shared Area'1 A/ E a# g1 }* p
: Q4 s$ p: q# y: R8 q4 f: Q1 D4 q( a
# }2 \+ B' W6 C6 o9 i0 B; xFixed CCRs: SPB 17.2 HF043
; v1 g2 w* N! ]0 ^/ X07-13-2018) c% _) A' ^* L! c4 p
========================================================================================================================================================7 h5 ~( h: t# n4 v2 ?
CCRID Product ProductLevel2 Title
7 ~4 E' R. g& ^========================================================================================================================================================- p0 G% j, [1 s9 z% q
1935813 ADW DBEDITOR Auto merging of DE-HDL and Capture Classifications is not working3 j1 s! @: u+ A. U$ O. X7 x
1935834 ADW DBEDITOR Some DE-HDL only classifications are removed during the CSV merge process of libimport4 W5 h' `* T3 Z& C: `& D! B5 p
1941570 ALLEGRO_EDITOR DATABASE PCB Editor crashes or stops responding on performing 'Info' or 'edit properties' on select pins, n- _ F! Q3 W3 X0 n5 R
1942536 ALLEGRO_EDITOR DATABASE Allegro PCB Editor fails to create backdrill plunges in Zone area+ O. K5 ^9 u0 A- b/ r1 L
1925899 ALLEGRO_EDITOR DFM PCB Editor crashes when placing components in Hotfix 039
6 M M: r# r0 T2 N! k1943113 ALLEGRO_EDITOR DFM Restore normal move/slide via performance when annular ring checking is enabled., [8 F- v( R* ]4 V
1940939 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashed on running the Gloss - Line and via cleanup tool; m3 G$ Q7 u# h7 O' A
1937754 ALLEGRO_EDITOR GRAPHICS Text string disappears when selected during 'Edit - Text' if using PCB_CURSOR
2 J$ b+ ?% w) V) l' v1937056 ALLEGRO_EDITOR INTERFACES Cannot import IDX acceptance of third-party change to PCB Editor" r" u2 [2 g$ [: E# P: z
1940197 ALLEGRO_EDITOR INTERFACES PCB Editor crashes when reading IDX file from third-party
0 R h) u3 g, i1940232 ALLEGRO_EDITOR IN_DESIGN_ANA PCB Editor crashes when running Return path DRC
4 ?( n& t# y& d0 H: R* p3 [2 F& |1916921 ALLEGRO_EDITOR PLACEMENT Property Pin_Global_Fiducial not inherited from symbol into board8 ~, Q! e' i, j
1862241 ALLEGRO_EDITOR REPORTS In 'Summary Drawing Report', the listed quantity for HDI vias is incorrect under Drilling Statistics% C1 D5 w" ] J3 G$ Y* `5 M
1935448 ALLEGRO_EDITOR REPORTS Etch Detailed Length Report lists only one coordinate pair per trace
4 G0 Z$ o3 N7 s) L# F1948322 ALLEGRO_EDITOR SHAPE Allegro hangs when axlPolyOperation api is called) Z; |$ A4 z/ U" o7 v4 C- g* u5 z+ w
1795564 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, focus is lost from command window after right-click1 r z) m; o2 j; @3 M. l" k$ B
1919247 ALLEGRO_EDITOR UI_GENERAL Infinite cursor graphics issues on move: Cursor disappears and symbol image remains at old location till refresh
# L% H0 x. A3 A6 ], L0 s! A: q' F1919256 ALLEGRO_EDITOR UI_GENERAL Infinite cursor graphics issue: Symbol disappears during rotate* Z8 v4 N! v( X' H; Y) b
1933526 ALLEGRO_EDITOR UI_GENERAL Panning is slow in PCB Editor in Hotfix 038
/ c- \% G0 B9 e$ L4 j1933530 ALLEGRO_EDITOR UI_GENERAL Strokes are slower to respond in release 17.2-2016
* ^; C4 r/ t/ ~- e$ p1933536 ALLEGRO_EDITOR UI_GENERAL Third-party dialog stops responding on running commands. {7 k+ N: y9 @( Y, F" ]
1782227 APD DIE_GENERATOR Ability to specify rectangular shapes in die text in
$ H! q) {* L6 }7 f1933011 ASDA PART_MANAGER Parts changed in library with new pin names are not reported or updated by Part Manager
4 Q7 Q9 y) a& x" J1924529 CAPTURE NEW_SYM_EDITO Global colors for pin name and number and part body not allowed in release 17.2-2016, Hotfix 038/039) j+ C9 [" j1 k9 h
1925846 CAPTURE NEW_SYM_EDITO Opening library or component with special characters in path throws JavaScript exception
1 {2 s% K4 G/ e/ M) v1928905 CAPTURE NEW_SYM_EDITO Pin name justification, length, and casing incorrect for generated parts in Hotfix 038; ^5 s: i* u: N# w/ i
1928965 CAPTURE NEW_SYM_EDITO Cannot move pins in Capture if Pin Name is missing& c8 Z4 m& P$ X; Z( x
1932149 CAPTURE NEW_SYM_EDITO JavaScript exception if path to part contains special characters in Hotfix 039
6 J. c# K( U# v4 E2 j' J5 J1936301 CAPTURE NEW_SYM_EDITO Cannot edit symbol in new symbol editor: Displays parsing error (SPSMI-1)( D- \+ M s* V. v0 t
1917172 CAPTURE PART_EDITOR Pin name rotating on schematic even when pin name rotate is off in symbol editor
7 `+ |; L R# x+ k3 b# w1924456 CAPTURE PART_EDITOR Color preferences for pin, pin name, and pin number do not apply in part editor but only in schematic
! P* `& E$ M! r1928872 CAPTURE PART_EDITOR Pin name locations are wrong and each needs to be placed manually% X4 a+ v- o `2 j7 l B
1929562 CAPTURE PART_EDITOR Changing pin name while adding a pin not intuitive in Symbol Editor# U* W! @1 Z2 ]( |. J8 E# ?
1932732 CAPTURE PART_EDITOR Part Editor issue: Pin name selection box too long and text not justified in Hotfix 040
" ]1 G" c8 j h: l' B+ o! ~2 E: y1933523 CAPTURE PART_EDITOR Connection box does not appear after changing pin of a placed part in Hotfix 0408 D `5 Q& a/ `) C
1936994 CAPTURE PART_EDITOR Error because of illegal characters in pin name and number and net name
( a% B* [/ }( ^# C# U- i1943074 CAPTURE PART_EDITOR Pin names rotated in Part Editor not rotated when placed on page. B& o& B. @, J
1943078 CAPTURE PART_EDITOR Pin name rotate not working.2 w; n! |" x% J0 ]6 S
1945055 CAPTURE PART_EDITOR Pin names not rotated in schematic5 p: i+ {: H4 w! U# S
1925700 CAPTURE VIEWER Pin numbers and text not shown during Variant View mode anymore.( w& B: y, z+ G) p2 n* l9 M
1914437 CONSTRAINT_MGR CONCEPT_HDL Constraint Difference Report appears even though there is no difference in constraint.
1 m. ~8 L& [' Y* X1935152 CONSTRAINT_MGR CONCEPT_HDL Match Groups are not formed with the correct pin pairs h2 h: A# {7 j! b& {3 l) G' m
1940575 SIP_LAYOUT ORBITIO_IF Need new routing flow2 t6 b0 k Z- B% K
1923722 SIP_LAYOUT STREAM_IF Use one symbol for all instances of a Via Structure
: L- l6 s, e- ^2 J c+ l. z2 H$ {- {) T
( L- e$ s; R4 T# c+ kFixed CCRs: SPB 17.2 HF042
) n9 }" I4 J4 H0 s' x; w06-22-2018$ V$ ^: o4 e9 I4 @3 W) \
========================================================================================================================================================
x! I0 ^- I& G9 vCCRID Product ProductLevel2 Title
& b( _) W @9 P5 f7 h) T5 L y7 y========================================================================================================================================================
. @1 l" g0 A! l5 l5 i1922654 ALLEGRO_EDITOR ARTWORK Difference in board and Gerber display8 q) n% G' r4 }
1932714 ALLEGRO_EDITOR COLOR Manufacturing subclass NCDRILL_FIGURE missing from Color Dialog when editing .dra file8 L0 n2 C S ?
1932316 ALLEGRO_EDITOR DFM DFM constraint reporting wrong DRC between backdrill via hole to shape clearance under copper spacing
, L. A! w3 C0 ^2 Y$ C: y1914334 ALLEGRO_EDITOR INTERFACES Design Compare does not import some netlists created using Export - Netlist with properties from PCB Editor6 t, |. e+ L& u& R# j5 Y1 @" m9 }3 l
1910213 ALLEGRO_EDITOR MANUFACT OrCAD PCB Designer shows Backdrill Status in Check - Design Status
8 p) O, z2 S: h4 n2 R) H0 C1933049 ALLEGRO_EDITOR MANUFACT NC Route seems to put all routed drills in the same .rou file regardless of what layer they are on.
# X3 Q8 y2 B1 M/ v1880576 ALLEGRO_EDITOR PLOTTING Extra lines appearing in plots that are mirrored( [8 h6 i+ g6 f) m; ?
1881031 ALLEGRO_EDITOR PLOTTING Plot Preview with the Mirror option in the Plot setup creates fancy lines on shapes
- H* n( d! X+ `/ U9 i1908005 ALLEGRO_EDITOR PLOTTING Plotting with mirror options set results in strange lines on the plot2 R; ?, r v9 K. F- [; [! p
1909530 ALLEGRO_EDITOR PLOTTING Use mirror function when plotting lines to design
" |& {" {2 _- V7 S3 @+ b; d; v$ n# V1919405 ALLEGRO_EDITOR PLOTTING Printing with the mirror option results in arcs in Print Preview
1 d& j a: ?# Y0 m3 C2 s1830419 ALLEGRO_EDITOR SCHEM_FTB Import Logic with 'Overwrite current constraints' deletes attributes from drawing0 g/ `) _" v7 N* Q {
1935253 ALLEGRO_EDITOR SHAPE Compose shape command causes tool to stop responding+ `$ `7 _* a* Y5 V
1571600 ALLEGRO_EDITOR UI_GENERAL File - Capture Canvas Image missing in release 17.2-2016% y, Q6 Y5 i: b8 G: R
1650403 ALLEGRO_EDITOR UI_GENERAL Include Capture Canvas Image command in Allegro PCB Editor release 17.2-20164 ~5 d% \% g/ I# P' d
1710310 ALLEGRO_EDITOR UI_GENERAL 'Capture Canvas Image' command is absent from the file menu in PCB Editor in release 17.2-2016- W& p6 n- t6 x) J9 V& K% A- l
1718407 ALLEGRO_EDITOR UI_GENERAL Reintroduce the Capture Canvas Image command5 c3 t- z6 u$ K' L" b! K
1729699 ALLEGRO_EDITOR UI_GENERAL Capture Canvas Image is not present in release 17.2-2016
0 y- K7 F$ j, n; P" E: L: K9 h1753234 ALLEGRO_EDITOR UI_GENERAL Capture Canvas Image missing from the File menu
7 L% u5 l" s3 K$ ]7 M& E( Z1754222 ALLEGRO_EDITOR UI_GENERAL Need command to capture view window as image in release 17.2-2016/ N! t& d# y5 w0 n3 m5 y
1794348 ALLEGRO_EDITOR UI_GENERAL Reintroduce Capture Canvas Image in PCB Editor in release 17.2-20160 k% n7 Z0 O7 v; v O$ k- X% A, o
1818610 ALLEGRO_EDITOR UI_GENERAL Restore the option to capture canvas image in PCB Editor in release 17.2-2016
! J8 ]2 G1 t, w7 m9 O1844591 ALLEGRO_EDITOR UI_GENERAL Reintroduce 'Capture Canvas Image' in release 17.2-2016* I! n' N; D; B
1869380 ALLEGRO_EDITOR UI_GENERAL File - Capture Canvas Image missing in release 17.2-20165 d0 [/ v8 b1 l: ]" T% |
1889412 ALLEGRO_EDITOR UI_GENERAL Cross-probing between two boards in release 17.2-2016" {$ x: @/ S- w- |& |9 h
1922329 ALLEGRO_EDITOR UI_GENERAL Add the 'Capture Canvas Image' command in release 17.2-2016* |$ w% ^% f7 L7 R
1932070 ALLEGRO_EDITOR UI_GENERAL File - Capture Canvas Image is missing in release 17.2-2016
0 [' D, W& N! H, M. t$ j1885594 ASDA PACKAGER Export to PCB Layout exits without reporting error when Netrev fails$ @2 p2 \$ X0 A. G
1931657 ASDA PACKAGER Export to PCB Editor does not work for a project1 a* T4 [7 z Z a& t7 j
1937757 ECW METRICS SDA metrics not getting collected" c, A' V/ a# B. k2 B; ?+ H& Z
1934482 EMI SETUP EMControl function flow is not working correctly in release 17.2-20163 d" [; k! [# i# C
1931623 SIP_LAYOUT EDIT_ETCH Shapes are not updated and force update does not work1 t8 ^( e9 f' o" D9 [
/ j. D( I0 }9 d& _& ?, J4 a+ \0 b
' M+ L( r3 }0 ?7 T% D9 d
Fixed CCRs: SPB 17.2 HF041+ N5 _) ]( x( Z3 k: t( a
06-9-2018
8 S/ Y0 Z5 w2 L% O========================================================================================================================================================
% A7 L* k6 Q( T( b" y- Y, fCCRID Product ProductLevel2 Title
$ x7 V) P1 I7 P# W6 g9 l========================================================================================================================================================
1 R9 b) k. k% j F n: q; {1880083 ADW ADWSERVER ALM fails to connect and authenticate LDAP server0 ]1 Z, C0 f \
1922218 ALLEGRO_EDITOR 3D_CANVAS PCB Editor stops responding when 3D Canvas is opened for a symbol
* z/ ]! t I/ X" k1915838 ALLEGRO_EDITOR DFM Outline to non-signal geometry is not working for non-etch layers in design# I, `9 y0 t6 K$ f' ?
1925263 ALLEGRO_EDITOR DFM False minimum spoke count DRC1 x4 m" m1 g( ?! E3 o+ @
1895486 ALLEGRO_EDITOR INTERFACES Importing IPF displays error regarding line being outside drawing extents (SPMHMF-409)
# p' t1 |( n+ ?$ V5 n/ T1927266 ALLEGRO_EDITOR INTERFACES Miniaturization license required when using enterprise licenses
4 w, d" r; P, | r* G8 p1912186 ALLEGRO_EDITOR IN_DESIGN_ANA Coupling analysis on one net takes a long time6 N$ E! `" l4 g3 L
1916015 ALLEGRO_EDITOR NC Improve the message for reporting unsupported characters in the directory path while generating NC Drill data
3 @. G' U( U( \( n3 y1 `1926072 ALLEGRO_EDITOR SHAPE Dynamic shape to route keepout not voiding correctly
( K4 [% p" | O J, r- H1903202 ALLEGRO_EDITOR UI_GENERAL HTML report dialog does not handle relative links to files correctly
n: B$ m2 T/ A' j9 `0 P. {$ }1880684 ALTM_TRANSLATOR CAPTURE Importing third-party schematic is not working in Capture
+ m$ V' G/ N6 \1870218 ALTM_TRANSLATOR DE_HDL Unable to translate a third-party design to DE-HDL. Q6 R: u% Q5 D' x/ V
1881208 ALTM_TRANSLATOR DE_HDL Third-party to DE-HDL translation: schematic symbols missing all pins
9 E, b, X9 R) C# W1889909 ALTM_TRANSLATOR DE_HDL Third-party to DE-HDL and OrCAD Capture translator fails with error message or crash, M/ z& w$ {) a" u4 K# Z) l$ g) A3 a
1924375 ASDA NEW_PROJECT SDA new project path truncated at ellipses
1 U; q% j8 r, Y3 |( M7 b1900957 ASI_SI OTHER axlLicDefaultVersion() in SKILL console crashes PCB Editor in release 17.2-2016 and works in release 16.6
8 M% p% ~. R7 a8 I" m3 j3 `1918499 CAPTURE NEW_SYM_EDITO Text in new Part Editor is always left-justified and justification cannot be changed
& |3 E- l! {6 \6 ~, y1921505 CAPTURE NEW_SYM_EDITO Error if property name starts with the less than character '<'
$ ~2 H# ^6 N0 c6 O0 M- I2 r1924273 CAPTURE NEW_SYM_EDITO Error if property name starts with the less than character '<'
1 V# Z8 o3 }" ~" R1 |1924332 CAPTURE NEW_SYM_EDITO Capture reports an error when editing pin numbers where names contain the less than character '<'2 p% x" I$ e4 K6 o
1934655 CAPTURE NEW_SYM_EDITO Properties populated in older release show up blank in new Symbol Editor
5 g4 Z: t* R7 H6 W, X0 I1855851 CAPTURE OTHER Crystal Reports not working in release 17.2-2016* M/ I8 T& C7 x. b1 z! ]7 y' C+ e. a
1918048 CAPTURE PART_EDITOR Unable to modify pin type and shapes for multiple pins simultaneously in new Part Editor0 R, i* n1 q0 a* v- p7 d- |; C
1919459 CAPTURE PART_EDITOR Part Editor background display color is not consistent when zoomed out/in3 k5 H: V. _1 F7 U @: t+ r7 Y
1920078 CAPTURE PART_EDITOR Option needed for updating pin type of multiple pins in the 'Edit all pins' menu5 @# F5 M" R# K
1922785 CAPTURE PART_EDITOR Cannot place pin array with zero in the suffix in Symbol Editor I$ [: s! s u) Z9 ?3 \! G
1922831 CAPTURE PART_EDITOR Symbol Editor redraws when scrolling with non-default background and when zoomed out/ r$ F% M. B( }7 |; d$ u
1923772 CAPTURE PART_EDITOR Placing pin arrays results in error
6 `6 g3 c7 V6 L# a1888897 CAPTURE SCHEMATICS Capture slowly redraws schematic page6 H- g, ^, O$ F& o% d
1910087 CONCEPT_HDL CORE DE-HDL crashes when adding Current Probe to a design
$ B' |$ N5 K+ M2 h" E' O3 h1930364 CONCEPT_HDL CORE SIGNAL_MODEL properties not deleted on importing release 16.6 DML design into release 17.2-2016 non-DML design
) e9 Z) w! e/ {1920716 CONSTRAINT_MGR CONCEPT_HDL Issue with the passing of physical and spacing CSets between Design Entry HDL and PCB Editor
* m4 Q+ q; o; x Q1902591 ECW OTHER Flow Manager reports a digital certificate error when launched with Pulse1 n6 Y# ~5 @- p7 S' C$ a( {
1926029 PCB_LIBRARIAN GRAPHICAL_EDI PDV Symbol Editor opens to a blank page in release 17.2-20161 L" I3 q8 _. ^3 [' q1 o7 H9 T& Y/ c
1884694 PSPICE ENCRYPTION User-defined library encryption is not working as expected
6 N8 A& O# _: N. s) O. A1927537 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes when running manufacturing checks on specific designs9 e l1 G2 J: v& p$ T) a5 N
1878733 SIP_LAYOUT CROSS_SECTION Layer Function and Manufacture fields in Cross-section Editor are grayed out for soldermask layers in SiP Layout
$ `9 d' T- g( H: H+ m1900628 SIP_LAYOUT CROSS_SECTION Board thickness in Cross-section Editor does not change even after soldermask layers are added2 n2 K- }% W0 g
1 Y; p, X0 t1 \3 o1 k$ [! A) _/ q7 Z
5 e- R: r/ ^0 i1 o" i* EFixed CCRs: SPB 17.2 HF040
& i1 W7 q2 s1 f) a/ q5 x05-27-2018& b+ D$ q. s0 Y, @" ^$ O
========================================================================================================================================================
2 o4 c% Q1 g. v& Q1 V% X f& g0 aCCRID Product ProductLevel2 Title! C& h$ v: M. Z! M Z% U
========================================================================================================================================================, w1 g: R7 [) D
1924541 ADW CONF Designer Server configuration cannot be completed+ M" ^& E2 u7 }* M
1906973 ADW DBEDITOR Rename attribute fails to preserve values in affected parts3 ^( W- {# }' d. g9 [
1718524 ADW FLOW_MGR FM: Find Projects does not find any projects when Project Path contains a period6 F9 {. j6 {8 i3 r7 l! h
1803310 ADW FLOW_MGR EDM Find Project no longer supports dot in the project path2 [( \; L) e$ a, D% U4 E; T
1916898 ADW FLOW_MGR Flow Manager does not recognize projects with a dot in the path7 A; Z3 t' N4 f( A, v; f
1887669 ADW LIBDISTRIBUTI ptfgen displaying Java errors
5 y+ H! R: L0 Y4 h1897991 ADW LIBDISTRIBUTI ptfgen fails with error LIBDIST-1062 in library distribution.6 E: ]( {! b. r% \9 X9 Q
1915319 ADW LIBDISTRIBUTI ptfgen should rerun with the -rewrite2db option automatically
( p) {8 G% Y; S: e* s1 w3 A+ V1920309 ADW LIBDISTRIBUTI Java exceptions in the ptfgen log file% J' F, c9 S5 f. A ?9 d
1914706 ALLEGRO_EDITOR DFM False Mask to trace DRCs
6 \* {; V$ s8 {1912290 ALLEGRO_EDITOR GRAPHICS Infinite PCB cursor: symbol move results in symbol trail and disappearance of cursor and symbol
* X8 n8 b; s$ l8 j+ k( h, c; F6 q1927425 ALLEGRO_EDITOR GRAPHICS Infinite PCB Cursor disappear while moving objects on layout
9 T" g* F$ e; R4 b. M1 k1908867 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes in release 17.2-2016, Hotfix 036 and 0378 M7 ~ k4 Z9 [. j* X/ h; b# A0 T
1906116 ALLEGRO_EDITOR IN_DESIGN_ANA Allegro Integrated Analysis and Checking: Coupling vision shows the influence of voltage net1 d7 c }; B, P9 ]- V0 n. }
1918161 ALLEGRO_EDITOR MULTI_USER Symphony crashing and clients disconnecting from server cannot leave session, error applying DBupdate: k# e$ `" M: p0 U* i
1919467 ALLEGRO_EDITOR MULTI_USER Random crashes while routing design in Symphony7 W9 ^) z. t+ Z" B7 N
1918702 ALLEGRO_EDITOR SHAPE Differential Pair vias not voided in a split plane
& Z; V7 z- n8 [( q, v* N8 H1905109 ALLEGRO_EDITOR UI_GENERAL PCB Editor randomly stops responding in release 17.2-2016 in Linux) @- r1 S. H6 x# R( u
1882365 ASDA CANVAS_EDIT SDA - body changes but not properties when changing version of a symbol( m2 _: P5 B9 S8 r
1900370 ASDA CANVAS_EDIT Version command in SDA should use placeholders from selected version
6 u0 t2 l" x6 Y& r+ o6 _1901120 ASDA CANVAS_EDIT Choosing a different version of a placed component does not use the property placeholders as per the new symbol3 a# {7 T( Y! x2 s, M
1907497 ASDA GRAPHICS DNI Cross Mark much larger than Components
; ~5 U) v7 S4 b; o! Z/ F$ H1895135 ASDA MISCELLANEOUS Design created in SDA has the cds.lib containing a pointer to worklib
3 V8 { |% L( v. _1 I. S& Y1895139 ASDA MISCELLANEOUS Irrelevant warning related to worklib when running checkplus on SDA design5 K$ W3 r+ |. ^- l7 Y$ J
1920753 CAPTURE LIBRARY JavaScript exception reported on opening part with name containing '\' in hotfix 0382 x5 Z5 R0 h. c- N/ H% i9 U$ \
1925848 CAPTURE LIBRARY New (QIR6) Symbol Editor has Script error / SR 600037969
. h" q" w9 I2 h" r f1916991 CAPTURE NEW_SYM_EDITO New part/symbol editor ignores grid color set in Preferences
9 F8 \* A. F: p. y# X0 D8 O" _1917090 CAPTURE NEW_SYM_EDITO New symbol editor goes into permanent pan mode on clicking the middle mouse button9 F2 C/ I) d# j# i- J4 w
1918041 CAPTURE NEW_SYM_EDITO Saves As for symbol in library from new symbol editor saving 0 byte files7 f& |" x3 u% j3 j4 }- }( |
1918497 CAPTURE NEW_SYM_EDITO Moving multiple items using the arrow keys results in error in new part editor
: r+ M' N1 V/ N1918711 CAPTURE NEW_SYM_EDITO Unable to do a Save As from a Library part to change the name
3 P5 j0 h9 O% _: k; k1920889 CAPTURE NEW_SYM_EDITO Unable to edit symbol with name containing '/'
! u7 f2 z$ C9 h% ~% i- A: \+ V: {/ Z# q1922123 CAPTURE NEW_SYM_EDITO Save As for symbol in library from new symbol editor saving 0 byte files( C0 t! R- V$ I' Q! F2 o% k, I
1922276 CAPTURE NEW_SYM_EDITO Space between pin name and pin for names having bar/ n! P6 ^0 K2 F$ Y- C
1922282 CAPTURE NEW_SYM_EDITO JavaScript exception on closing new part editor window using keyboard shortcuts% N' u3 U) f( ^% C+ P0 r
1923526 CAPTURE NEW_SYM_EDITO Unable to "Save As" in new symbol editor., Y/ p, o! v; P; A! G, C
1927262 CAPTURE NEW_SYM_EDITO The File > Save As command in version 17.2-s038 differs from earlier versions3 X; y: i: l# i. d. \
1919322 CAPTURE PART_EDITOR JavaScript exception on opening parts and creating new part using right-click* v$ Z! ]. z' t2 B) I
1914183 CONSTRAINT_MGR XNET_DIFFPAIR ECSet fails to map in PCB Editor but maps fine in DE-HDL; h/ R4 }/ b0 l! v! H; p5 _
1908102 ECW DASHBOARD Some lines in Design Dashboard in Pulse are grayed out
% X# b/ O' s; D U3 x. D4 G. o1914812 F2B PACKAGERXL Hierarchical variable not evaluated
. b$ A( b1 C3 o$ O3 M% k1639231 PSPICE ENVIRONMENT Remember last location in simulation settings
m/ w: F' R2 Q- M5 I1804391 PSPICE ENVIRONMENT Libraries with uppercase extension (.LIB) not retained if added using 'Add to Profile'
6 J \# T/ p! K" E9 J1 M. g+ h1879915 PSPICE ENVIRONMENT Check points cannot be loaded from a directory with space in its name
- i. Z7 q9 ?' c; n1695306 SIP_LAYOUT STREAM_IF SiP Layout - Stream out issue: Embedded or stacked components using pad reference in more than one layer
1 j: J( a' o, |; u6 i. p/ O5 G$ v$ @; v8 P
! z) m1 R- W2 j) x8 j% `Fixed CCRs: SPB 17.2 HF039, ^. m, t8 b$ _& O
05-11-2018
. q* O. m6 F) P& ~% W# c, w========================================================================================================================================================3 n- y& w& q# O% i u/ r
CCRID Product ProductLevel2 Title l0 Z e+ f% `8 ]0 D
========================================================================================================================================================( {7 T9 e' \/ N% g
1915149 ADV_PKG_ROUTER OTHER Auto-connect fails to initialize when rats are selected, but works with bundle. T6 Z) h' M* Q/ m# o! g9 j
1870109 ADW ADW_UPREV Most mandatory properties turned into optional properties following database uprev
4 |1 Z# P& T% M1 n1758396 ADW CONF Server Memory setting in setting.ini is lost if server is re-configured using Conf
q1 X: R7 \, z" S2 o1911591 ADW FLOW_MGR Flow Manager does not start on high latency (> 25ms) networks: displays Java Content Disabled dialog+ \, s' j! O% b( o8 Y
1887861 ADW LIBIMPORT Library Consolidation reports front2back issues but does not provide information about the issues.- E" H% S1 J& [$ J) O, i" x
1778977 ADW REPORT_GENERA reportgen memory setting too high in release 17.2-2016 resulting in launch failure
! A2 [8 z2 o. ?7 Z, L& m2 Z/ g2 P1900422 ADW REPORT_GENERA Save in reportgen does not save Preferred Part List entry into .rep file
5 s: l! J B& i0 I+ T2 L3 Y+ g4 ]* B1903888 ADW REPORT_GENERA Report generator not outputting values as expected for PPL field
2 c1 ^& ?" C% z* n. g9 P1916903 ADW REPORT_GENERA Reportgen -gui is not producing the expected result1 v! w# {9 j1 _
1902184 ALLEGRO_EDITOR DATABASE Add connect in package symbol crashes PCB Editor when using the 'clearance_view' variable
J) r$ e9 Q8 V+ b) ?% E1914793 ALLEGRO_EDITOR DATABASE Updating shape crashes Allegro PCB Editor( k% o9 L5 w7 W2 M0 V
1905138 ALLEGRO_EDITOR DRC_CONSTR Max Via count DRC disappears on running DRC update
- Q- L5 H( F# l( L1848015 ALLEGRO_EDITOR MANUFACT Export Creo View cannot find the webpage on the PTC site- n, L3 d( V" s' r1 E* v) J9 @" B
1850553 ALLEGRO_EDITOR MANUFACT 'File - Export - Creo View' is not working: d5 U. y, K% d! N" p. `: e
1853960 ALLEGRO_EDITOR MANUFACT PTC Creo Interface link is broken% n1 v u- }$ t B. K9 K
1862305 ALLEGRO_EDITOR MANUFACT PTC Creo interface link is not working0 C' H1 H7 k) a5 @) v% u4 ?
1878682 ALLEGRO_EDITOR MULTI_USER Delay in Symphony server session when server is started from Allegro PCB Editor
2 V+ K: L6 P' a [) t1890108 ALLEGRO_EDITOR MULTI_USER Database rejections in Symphony4 s0 t3 [' } {+ Z+ p0 ?
1887331 ALLEGRO_EDITOR NC Milling (NC route) in Gerber tools is not the same as what it is in the board.
4 k/ z* w. \: ^* A7 ?1898179 ALLEGRO_EDITOR RAVEL_CHECKS PCB High-Speed option required for high-speed rules when Venture license is selected" W/ ^; U: H* p3 d/ ?2 T5 e3 S
1461142 ALLEGRO_EDITOR SHAPE Pin with nearly-tangent via fails to generate void in dynamic shape, results in short.- s* U( X/ w7 V3 l. h
1863467 ASDA CROSSPROBE Highlighting all parts in PCB Editor does not highlight all parts in SDA4 z) e9 |1 L4 E1 {" J: E1 S
1910974 ASDA CROSSPROBE Cross-probing between SDA and PCB Editor does not work
8 C# e% _" _" c; Y+ ], v1904440 CONCEPT_HDL CORE SPCOCD-577 error on migrating from release 16.6 to release 17.2-2016/ E" v( x& L: o0 S: U
1909611 CONCEPT_HDL CORE DE-HDL stops responding on running '_movetogrid' and clicking 'No'
/ h- c6 @% D" h& j: n1808743 CONCEPT_HDL PDF Inconsistent display of Publish PDF hyperlinks0 _8 V. s3 P9 x7 y3 P# i2 w
1894868 CONCEPT_HDL PDF XREFs getting clipped in the Published PDF/ s9 K5 y7 z. @3 \* j7 M8 N: u( J, f
1911676 CONSTRAINT_MGR CONCEPT_HDL DE-HDL Constraint Manager crashes on selecting ECSet and then creating pin-pair option& b1 w, }$ T, x$ i/ ^
1913968 CONSTRAINT_MGR CONCEPT_HDL Match Group pin-pairs are not created on applying ECSet to differential pair$ @" E. O4 W# U
1899638 CONSTRAINT_MGR XNET_DIFFPAIR Differential pair buffer models are extracted differently in release 17.2-2016 and release 16.63 j& u4 H0 W+ @+ U5 x# c; A
1914116 ORBITIO ALLEGRO_SIP_I Unable to import OrbitIO file to SiP Layout
6 e4 r: q8 U4 z s0 j0 W" T1896487 PCB_LIBRARIAN GRAPHICAL_EDI Use lower-case characters for notes and pin text in New Symbol Editor
6 p8 W- s- c3 }" I4 \! P6 V( W8 I1898008 PCB_LIBRARIAN SYMBOL_EDITOR Styling is not available for custom shape and pins. {3 x9 `9 J k
1644787 PSPICE FRONTENDPLUGI PSpice Model Search window does not show complete library path# y1 E0 C* C! b, t5 ^
1785939 PSPICE FRONTENDPLUGI PSpice Part Search library browser should display path of the library directories& U# M: G& A% I; t y; {
1855867 PSPICE FRONTENDPLUGI PSpice Model Search window does not show complete library path
; ~9 B0 H$ T: Z0 f. b1 f1887016 PSPICE SIMULATOR Pseudotran should always be invoked first time in case autoconvergence is ON2 D5 n# k* S" f
1895752 SIG_INTEGRITY OTHER Layout Cross Section: Wrong Differential Impedance calculation (0 ohms) in RHEL Linux 7.1 or later versions1 v" a- A; b* p. P- G4 n: h
1895759 SIG_INTEGRITY OTHER Cross Section does not calculate correct differential pair impedance in Linux CENTOS 7 and gives 0 value( ^& ~; n: u" W
1909257 SIP_LAYOUT INTERACTIVE Error 'E- (SPMHGE-639): Copying component with bond wire is not allowed' when copying SMD symbols
1 b( b6 y- z" z% Y) T1900970 SIP_LAYOUT SHAPE Shape does not void around SMD Pins and Vias inside pad: |* i; w; _; e7 e) F
1885496 SIP_LAYOUT SYMB_EDIT_APP Pin Numbering: different results for release 16.6 and 17.2-2016 for the same case.0 t$ B8 N3 i, X. x# l( V
1907796 SIP_LAYOUT SYMB_EDIT_APP SKILL commands fail to change pin number in SiP Layout- U; g- k2 o) b Q/ @8 V
1887703 SIP_LAYOUT WIREBOND On trying to add wire bond to a die, SiP Layout crashes displaying a restart message! h+ R8 N) y+ o
1903081 SPECCTRA LICENSING PCB Router is failing in Linux 7.1 in release 17.2-2016
1 ?! ?6 e; c! g6 M. H$ |6 E4 U! _: e1721606 SPECCTRA ROUTE PCB Router stops responding on exit if opened in the stand-alone mode
1 O0 u$ y$ {, I! i1844366 SPECCTRA ROUTE Allegro PCB Router will not exit3 X2 |) l/ _' i1 s1 A2 w* y4 y
1873716 SPECCTRA ROUTE PCB Router does not close if opened from Allegro PCB Editor or in the stand-alone mode
& X! I8 Q# }; ]0 W( v/ B* M7 S% x6 j1907703 SPIF OTHER PCB Editor crashes on choosing 'File - Export - Router' in release 17.2-20164 B1 C( S! C# c& j, p5 j* t0 l7 I$ [
1889059 VSDP DIEEXPORT Incorrect pin location if bump cell origin is not at lower left for rotation other than R0
: {" [8 z$ h% L& Q$ i7 n
8 ?& U( E( t5 U. m3 S7 u. i9 D" d
Fixed CCRs: SPB 17.2 HF038% B P# n4 N: z
04-27-20180 M5 T! b& }" \
========================================================================================================================================================8 y5 D6 U- _& G( |
CCRID Product ProductLevel2 Title" w8 l1 H( L/ ?* I' S% Q
========================================================================================================================================================
T4 w$ N7 _6 G Z6 I4 l T1861616 ADW TDO-SHAREPOIN Team Design Option requires Allegro_ECAD_Collab_Workbench license feature
3 X9 ~. ]3 l+ ^: ?, O1784170 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Canvas does not show the flex zone thickness correctly
' z( Y0 ~7 V6 t4 N. W6 m/ j1801053 ALLEGRO_EDITOR 3D_CANVAS Moving component in 3D Canvas does not move the pads* D F* Y9 X) T) ~
1805038 ALLEGRO_EDITOR 3D_CANVAS Soldermask and drill not refreshed when component is moved in 3D Canvas, or on the board with Canvas open' v0 n u4 w3 b7 @
1808579 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas displays annular ring incorrectly5 x4 {6 s6 P& o# C f
1816732 ALLEGRO_EDITOR 3D_CANVAS Mismatch in shape width between board and 3D Canvas
; i2 F% r% D& _7 e, _+ U. i# X1822778 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas does not display nets when selection is done through click drag, k# x8 S4 U5 I: |
1838129 ALLEGRO_EDITOR 3D_CANVAS User is not able to create a pastemask layer that is visible in 3D Canvas6 v% k1 R! e4 `) `
1842911 ALLEGRO_EDITOR 3D_CANVAS Etch shapes not visible in the 3D Canvas when invoked from a symbol drawing
6 w+ ]. B/ r9 M+ D! R7 ?1849380 ALLEGRO_EDITOR 3D_CANVAS Mirrored components placed in flex zones are not displayed in the 3D Canvas
$ [" f: j+ E) b* h* Y9 _4 M1851898 ALLEGRO_EDITOR 3D_CANVAS STL export from 3D Viewer scales it up by 100
2 q* s3 K" [" d7 [/ {1853378 ALLEGRO_EDITOR 3D_CANVAS The new interactive 3D Canvas has a display issue with the off-centered drills.
6 \) [, F$ [; @/ ^2 D* G( r5 q1859713 ALLEGRO_EDITOR 3D_CANVAS PLACE_BOUND shape with package_height_max and package_height_min set displayed incorrectly in 3D Canvas6 _. z4 z2 a( A3 w. I+ m
1880073 ALLEGRO_EDITOR 3D_CANVAS Design Outline is not displayed correctly in 3D Canvas
- [9 ?% T: H( r/ ~, m& g1880338 ALLEGRO_EDITOR 3D_CANVAS Step Model missing in interactive 3D canvas., O z' e/ r3 Y! O" r: F9 o
1881889 ALLEGRO_EDITOR 3D_CANVAS Changing the color of STEP model in STEP Mapping Window does not display this color in 3D Canvas.
: K/ e$ X, p# e! N }' `1889861 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas swaps padstack from Bottom to Top) F3 L1 g! w; X+ i9 W) h
1830749 ALLEGRO_EDITOR ARTWORK Gerber 4x and 6x output do not fill the shape
: M* o8 u5 ~# c# A1848514 ALLEGRO_EDITOR COLOR axlVisibleDesign does not interact with wirebonds
& F4 p0 D1 g/ s8 F/ S% [" z/ ~# \1837388 ALLEGRO_EDITOR CROSS_SECTION Cannot add solder mask to the site layer mask file
# B- z6 R1 J% |1859797 ALLEGRO_EDITOR CROSS_SECTION The Report only option does not work when choosing Setup - Cross-section - Import - IPC2581( i8 H' @; G) v& @5 K
1877858 ALLEGRO_EDITOR CROSS_SECTION Dynamic Pads Suppression option is not working correctly
; {* T/ V. t$ L9 V+ s0 s1880093 ALLEGRO_EDITOR CROSS_SECTION Unused Pad Suppression options are not working correctly and are reset on opening cross-section* k& d* L4 {3 _( m* t. J
1886283 ALLEGRO_EDITOR CROSS_SECTION Unable to turn on 'Dynamic Unused Pads Suppression'
" x! p' H( I# a& j2 i% y# U6 J1890959 ALLEGRO_EDITOR CROSS_SECTION Dynamic Pads Suppression option is not working correctly! S$ e9 @8 [3 t- e" M6 \
1900397 ALLEGRO_EDITOR CROSS_SECTION Dynamic Unused Pad Suppression option in Cross-section not working at one go.
0 I4 r% K- P1 \ B5 s4 K! n1905315 ALLEGRO_EDITOR CROSS_SECTION 'Dynamic Unused Pad Suppression' cannot be turned on.) |+ i$ p7 ^2 D/ N
1861406 ALLEGRO_EDITOR DATABASE Refresh symbol for flex zone not mapping padstack layers correctly' u2 m- L: r! n( H( d
1877132 ALLEGRO_EDITOR DATABASE Fail to open #Taaaaed17598.tmp file and save database
. q0 A7 J# V; ^1883747 ALLEGRO_EDITOR DATABASE PCB Editor crashes on stackup modification- q) O8 v6 { J. n# X+ G7 k g
1860238 ALLEGRO_EDITOR DFM Applying a DFF constraint set closes PCB Editor instantly
1 b" l2 T" [) H0 J1872780 ALLEGRO_EDITOR DFM DFF false pin to via DRCs: Copper Spacing, SMD pin Pad to Thru Via pad1 S/ t1 A9 _# f1 A4 m& c
1823912 ALLEGRO_EDITOR DRC_CONSTR Thru pin to Thru pin DRC between Symbol Pin to Mechanical Hole (with NO regular pad)
# ?. s0 S& _ z1828168 ALLEGRO_EDITOR DRC_CONSTR Upgrading from release 16.3 to 17.2-2016: Differences in spacing constraints: _; d$ ~- M! X" D- r
1844780 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to Shape Air Gap value is reduced when updating shape; M+ r: Y# M- L- H. g6 Z
1845011 ALLEGRO_EDITOR DRC_CONSTR When upgrading from 16.6 to 17.2, Spacing constraints for shape to mechanical pin not being resolved properly
6 C! e+ v+ ] D! ~1861548 ALLEGRO_EDITOR DRC_CONSTR Inconsistent Micro via to Micro via drill to drill overlap DRCs: Z- `0 N; G: I4 u( W" ~- P
1862281 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin/hole to Shape spacing too small/ f( I7 s: k$ R* S* y
1887145 ALLEGRO_EDITOR DRC_CONSTR Mechanical pin to conductor spacing setting is overriding constraint region in release 17.2-2016
1 E1 y7 _& `6 m! B/ G( t- O) S1893012 ALLEGRO_EDITOR DRC_CONSTR Shape voiding not taking the shape to hole spacing rules for NPTH
- l5 i0 y6 q: ?0 b+ N+ J; W+ G5 W1906840 ALLEGRO_EDITOR GRAPHICS Context menu stays when PCB Editor is minimized.3 S& Y0 k+ N6 z: R8 ?
1738624 ALLEGRO_EDITOR INTERACTIV 'Invalid Sector' error when saving psm file for symbol that has die pads, which are copied
& [5 p) { I, L {1800741 ALLEGRO_EDITOR INTERACTIV Search in User Preferences Editor is giving incorrect results
- S3 ?" G0 _' G6 M p1812530 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes when opening a file that is in an unsupported format
0 y4 i* V5 Q" u1812570 ALLEGRO_EDITOR INTERACTIV PCB Editor hangs when an invalid pin number value is specified as the rotation point in the symbol preselect mode) v5 @. D& F# z$ t
1826819 ALLEGRO_EDITOR INTERACTIV 'Route - Resize/Respace - Align Vias' menu is not available" k1 n1 I6 [8 C$ b/ i: \! }& e' ?
1842645 ALLEGRO_EDITOR INTERACTIV Via align command is missing from the menu path
8 @4 F! y5 B+ F2 H! U9 S. A1845748 ALLEGRO_EDITOR INTERACTIV With 'Shape - Change Shape Type' enabled, changing visibility reverts the Shape Fill selection to dynamic copper./ d2 \3 w+ _" ]
1849700 ALLEGRO_EDITOR INTERACTIV Add the reason for generating DBFIX_PAD, to the dbdoctor.log.( T/ r3 w K2 u" ]0 l/ p5 I' z" K3 i
1860934 ALLEGRO_EDITOR INTERACTIV Auto-Paste environment variable is not working as it should
! V0 ?1 y7 h3 R/ s( \ ?& O1861928 ALLEGRO_EDITOR INTERACTIV Provide a Persistent snap pick option for Display - Measure1 }4 ^. U3 M& T) x$ `. d: i( q
1864238 ALLEGRO_EDITOR INTERACTIV Shape place rectangle issue: Dimension of placed rectangle changes on cancelling action
7 t; n) l. Z7 a1877026 ALLEGRO_EDITOR INTERACTIV Filled rectangles on ETCH/TOP and ETCH/BOTTOM are not getting copied
3 N/ e8 Z. ?- W: g2 O g- Y% o1881637 ALLEGRO_EDITOR INTERACTIV Radius of Shape changes when trying to place circle using Place Circle mode.) a' @- }/ O' M/ W
1883032 ALLEGRO_EDITOR INTERACTIV Find by Query does not find all padstacks in a symbol drawing
8 o% s: a" m3 V1855248 ALLEGRO_EDITOR INTERFACES The Technology Dependent Footprint command returns an error: p. q/ _; D: R/ Y
1885716 ALLEGRO_EDITOR INTERFACES Increase supported STEP model size to enable the use of models larger then 500MB+ R; m$ I* ^" s1 E
1860835 ALLEGRO_EDITOR MANUFACT Display a message when backdrill_max_pth_stub is defined for vias or pins only) c+ @& o# \' C3 A$ k, _1 L! g
1869528 ALLEGRO_EDITOR MANUFACT Backdrill out of date when deleting Teardrop and Sliding cline with Teardrop8 y9 u0 J% q* d/ L( h
1885672 ALLEGRO_EDITOR NC NC drill is creating false backdrills when repeat code is turned on in release 17.2-2016
# x4 {* P; a3 R4 ], v, T1895084 ALLEGRO_EDITOR NC Padstacks with backdrill data trigger backdrill out-of-date even if the board is not set up for backdrilling# t Y) H3 S1 y
1837514 ALLEGRO_EDITOR PAD_EDITOR Offset is not consistent for keepout and mask layers in padstack editor.+ |! {) t1 o/ L6 [
1842902 ALLEGRO_EDITOR PAD_EDITOR Scrolling through the .pad files in the Library Padstack Browser displays Error(SPMHA1-161)5 A; v/ t5 O. p+ ~% W4 h" G
1846504 ALLEGRO_EDITOR PAD_EDITOR COVERLAY_TOP definition lost while opening and saving a 16.6 pad in 17.2 padstack editor
0 j) W+ e7 G% {! ]5 h- w, Q1879453 ALLEGRO_EDITOR PAD_EDITOR The 'Y' tolerance in the Padstack Editor does not update when changing the units of the padstack.- k1 C- M4 M M& V. q4 `
1805202 ALLEGRO_EDITOR PLACEMENT Place via array adds via on differential pairs incorrectly
1 K- _. r' U* @$ d* Z& s- F6 y1806675 ALLEGRO_EDITOR PLACEMENT Place - Manually - Quickview displays the Assembly Top details only
5 ^- P8 ?$ ]6 g. w) d1835177 ALLEGRO_EDITOR PLACEMENT Can place symbol even after cancelling copy by choosing 'Oops' from pop-up
/ k9 ]( k2 B: w3 Z+ z# M7 I1846892 ALLEGRO_EDITOR PLOTTING PCB Editor Export PDF does not show lines correct for certain component
2 L+ g2 r' G+ _0 B# O1006328 ALLEGRO_EDITOR SHAPE Static shapes should void around corners as dynamic shapes do
. i3 d% q: Q' }) p1033326 ALLEGRO_EDITOR SHAPE Cannot compose lines to shape
# ?: A# A3 J: s7 D, y6 S7 |1045089 ALLEGRO_EDITOR SHAPE Dynamic shape voiding is inconsistent for solid and xhatch shape fill type
* `. ]. r9 O* h8 u1069959 ALLEGRO_EDITOR SHAPE Compose shape crashes PCB Editor5 O, O' c) s" E) U- ~0 a& M
1085907 ALLEGRO_EDITOR SHAPE Pad does not get thermal connections to shape if outside of the shape outline by more than DRC spacing.
( x R0 V' x3 }6 B) C- D$ f) W. n" j' s1143563 ALLEGRO_EDITOR SHAPE The pin void inline clearance does not seem to dynamically update the shape and requires a 'force update'.' g, |- r! v1 L. b4 \" }3 q) z
1243688 ALLEGRO_EDITOR SHAPE shape_rki_autoclip fails to clip shape to route keepin
5 _ b2 S. x2 ~! Q1269069 ALLEGRO_EDITOR SHAPE Shape void not working properly in release 16.5 hotfix 054, V2 |1 I3 B. F8 l& P1 S) f
1327755 ALLEGRO_EDITOR SHAPE Need the ability to nest dynamic shapes on different nets partially or entirely
+ Z" m- d9 j+ ^0 A5 S( S7 @ ]2 [9 ~$ ]1417394 ALLEGRO_EDITOR SHAPE Shape not updating correctly
. G& n& J- A; i8 k9 w1430742 ALLEGRO_EDITOR SHAPE When adding fillet to an irregular pad, the fillet might not be added or be strangely shaped. o" \6 E' D5 f
1750760 ALLEGRO_EDITOR SHAPE Shape to Route Keepout DRC for a void that meets route keepout) o$ N+ l- ~1 U
1793898 ALLEGRO_EDITOR SHAPE Add teardrops fails to add anything with different settings
" U- J1 A; H- m0 x. { \$ B1811662 ALLEGRO_EDITOR SHAPE 'show measure' gives incorrect air gap value between two pins
% R; w+ |( ^$ }! |* c' C9 m1820901 ALLEGRO_EDITOR SHAPE The pins on adjacent layers are voided as Rounded Rectangle instead of Rectangular as defined in padstacks; N/ e, }; I$ ~# A9 {
1829570 ALLEGRO_EDITOR SHAPE Display measure airgap value is very large' u& }9 W2 |3 I# c+ _: Q! f
1858696 ALLEGRO_EDITOR SHAPE The via to the edge of the board is not connecting to shape even with the PAD_SHAPE_TOUCH_CONNECTION property added. q$ _! u" L# S$ t+ h
1873384 ALLEGRO_EDITOR SHAPE Boolean AND operation returning nil
. s, u' _1 ?) v; ^9 k1873860 ALLEGRO_EDITOR SHAPE Copper shape does not respect route keepout- ^& o" v8 N4 f/ h7 K4 s
1889312 ALLEGRO_EDITOR SHAPE Shape voided for net vias on adding 'PAD_SHAPE_TOUCH_CONNECTIONS' when enabling via suppression- f( U/ T: c9 @* B7 u
1890702 ALLEGRO_EDITOR SHAPE Not able to add teardrop in release 17.2-20161 p s$ H6 c* Y/ ^ C; K% ?
1892692 ALLEGRO_EDITOR SHAPE Thermal relief connections being added to static shapes present in the void inside Dynamic Shapes' i5 y; D9 D( ?: J9 W' n. _
1893492 ALLEGRO_EDITOR SHAPE 'merge shapes' results in moved void& D1 v3 P: l1 i2 i6 t2 \
1896543 ALLEGRO_EDITOR SHAPE Same net pin will not add thermal connection to shape if it is a rotated slot in the symdef8 \, K$ o, \1 P6 A9 c
1897645 ALLEGRO_EDITOR SKILL axlCNSGetSpacing() returns nil if active class is non-etch.
0 v- n# T+ P5 x7 h s$ T1822364 ALLEGRO_EDITOR UI_FORMS Design Parameters dialog disappears if prmed is called while show measure is active* f% y, p7 F0 X
1834395 ALLEGRO_EDITOR UI_FORMS Setup menu of OrCAD PCB Editor is missing the Anchor 3D View command
; z& P! h* @" n& {( ]* u9 [1838941 ALLEGRO_EDITOR UI_FORMS Anchor 3D View command is not available in OrCAD PCB Editor Setup menu
3 Q2 N E0 g& K1 h& u1 g1716433 ALLEGRO_EDITOR UI_GENERAL Alias keys do not work until mouse scroll key is activated
, f6 z& Y* N7 C# l. A1721761 ALLEGRO_EDITOR UI_GENERAL During manual placement of symbols, hovering over symbols does not highlight them2 Q1 n- f3 ?2 g2 f% p6 \0 x0 U, Y
1732915 ALLEGRO_EDITOR UI_GENERAL Alias does not work in release 17.2-2016 when switching windows
2 b# [) b# w( ~5 `5 k/ d1 }1770723 ALLEGRO_EDITOR UI_GENERAL Funckey does not work if focus is not on canvas in release 17.2-2016
$ _6 S6 q: e6 I2 s: `5 {5 V5 j1793839 ALLEGRO_EDITOR UI_GENERAL Function Key does not work if a form is opened by a previous command% v0 A" j% ]$ H5 Z- [0 W
1813961 ALLEGRO_EDITOR UI_GENERAL Inconsistent file formats available when saving reports6 K: A# K6 v9 q
1816716 ALLEGRO_EDITOR UI_GENERAL Shortcut not working when using working layer with 'add connect'7 d3 r4 Q- {) T
1864321 ALLEGRO_EDITOR UI_GENERAL Funckeys not being registered after focus has moved to other window and back again in PCB Editor u' T- @7 P% y5 N3 r- B+ {6 S
1865010 ALLEGRO_EDITOR UI_GENERAL PCB Editor does not get focus when clicking shortcut after switching from any other program or application. X! r' u8 H* _1 q$ p/ Z. e- `3 t0 g
1868708 ALLEGRO_EDITOR UI_GENERAL Allegro PCB Editor, funckeys stop working intermittently in release 17.2-2016, hotfix 032
l% K* d$ [+ ^$ u r* Q$ J1869745 ALLEGRO_EDITOR UI_GENERAL Allegro 3D Canvas window becomes active on pointing at minimized icon on taskbar/ @% m% Q- B7 o+ P K$ A
1869860 ALLEGRO_EDITOR UI_GENERAL Hotkeys no longer functional on switching from PCB Editor to another application and then back again
, H( N7 t0 q" i1870744 ALLEGRO_EDITOR UI_GENERAL Need html extension added to Save pull down menu.! b& l u. x! u
1870996 ALLEGRO_EDITOR UI_GENERAL If you switch from one active window to other, hotkeys stop working
. ~0 a* j- f0 f3 M! N1883507 ALLEGRO_EDITOR UI_GENERAL Hotkeys stop working after Allegro PCB Editor UI window is opened$ j: C8 X, z% g8 B
1886981 ALLEGRO_EDITOR UI_GENERAL Focus lost from layout when switching between PCB Editor and Capture% l& I0 g9 g$ F2 P5 C
1887519 ALLEGRO_EDITOR UI_GENERAL Release 17.2-2016, hotfix 034: Shortcuts defined using funckeys not working correctly: a; s2 A; M8 D9 @1 |
1887660 ALLEGRO_EDITOR UI_GENERAL Alias does not work in release 17.2-2016 when switching windows.
. ^# s% f7 W8 x1891204 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes if SKILL form is closed using the Close icon ('X')) N" j! k; Q1 L# m1 y7 X
1898059 ALLEGRO_EDITOR UI_GENERAL Funckey commands are not working consistently in release 17.2-2016
* v3 g5 N- T1 R5 P# [, F0 {1902322 ALLEGRO_EDITOR UI_GENERAL Cannot use funckey commands when cross-probing
0 f, L8 V+ s( B1905906 ALLEGRO_EDITOR UI_GENERAL Issue with keys and focus when navigating between windows
% |* E, B( [8 G, E- R& o1913768 ALLEGRO_EDITOR UI_GENERAL Uppercase funckey shortcuts do not work$ b+ O2 i: c4 \* j) \: @
1751586 APD OTHER axlGetMetalUsageForLayer() for etch returns value including pins and vias
" P% A1 n) }/ ?4 H; O/ D4 E- s) A( |% S1863241 APD SHAPE Fillet is left on the T-Point without Cline(center) connection.
8 p ]$ \' ~" P* w# \+ G2 @/ o1894438 APD STREAM_IF APD/SiP Layout: Export rounded features as circumscribed and not inscribed polygon in GDS. h3 R/ W6 a2 w: [8 h
1812699 ASDA AUTOMATION Enhance the performance when extracting data from SDA, using TCL functions9 {2 ?$ z% M" K. |8 V7 ~
1863436 ASDA CANVAS_EDIT alignment guides are not displayed when placing or copy a part, only when moving. They are most needed during placement' G7 e- n# o$ w# _# k
1863445 ASDA CANVAS_EDIT Dark theme blue text in docked CM needs to be of a different color: difficult to read
1 o& ]# E' D& C) q9 i1802111 ASDA DARK_THEME Dark theme in SDA should also change the border line color and text color of grid references: they are still black
' M4 G0 g9 Z+ n' A0 @1869951 ASDA EXPORT_PCB File browser button in Export to PCB Layout flashes graphics of the window behind the form
9 f* _2 H' j8 Z: v' @. T2 o- w1845831 ASDA FORMAT_OBJECT Width of the twisted pair of wire should automatically be set to 6, otherwise it is not drawn correctly
/ Y9 q3 M4 a2 I! X+ A9 ^1879914 ASDA INTERNATIONAL Using French Keyboard cannot use the . (point) delimiter to set VOLTAGE property value
7 d' V# }( P: Y/ U! {# t1865753 ASDA MISCELLANEOUS Inconsistent and non-ideal behavior in SDA product choice dialog, small box, hard to check unlike the bottom box9 P5 ?) n3 j6 i5 m7 l" y
1863457 ASDA PACKAGER Unset all user-assigned references globally+ D( {+ r+ J9 B% T* r
1889301 ASDA TDO SDA TDO Crashes when switching to/from Offline mode, @ y- Y1 ]* F7 G. v, r) Z# J
1823203 ASDA VARIANT_MANAG Variant setting part to not present does not do anything3 w9 R) Z" G4 G# N
1823992 ASDA VARIANT_MANAG Variant Editor fails to read netlist if a net is named NC2 K+ a$ z2 V2 v* m/ x% Z
1863451 ASDA VARIANT_MANAG variant mode can select multiple parts to add to variant but can't select multiple parts to hit reset& K0 x3 p6 p3 ]- d
1863455 ASDA VARIANT_MANAG Cannot resize any panels in the Variant mode
! c* q; F4 ^* z3 u1874952 ASDA VARIANT_MANAG Letter I in the alternate part icons in variant spreadsheet should be white for readability
S* W+ P! l% b5 a1878401 ASDA VARIANT_MANAG SDA Variant Display - DNI marker color switches between black and red
- ~$ h- `6 L) \. d1877239 ASDA WORKSPACE SDA DRC window is hidden if undocked and minimized; m4 S$ j; i6 K9 [
1809605 CAPTURE LIBRARY Part has pins in the incorrect order in the Connectors library: K' S X% D' A, O
1638693 CAPTURE OTHER Capture Footprint Viewer not showing footprint.
: Q X. p2 l# V% J6 k1873612 CONCEPT_HDL COPY_PROJECT Copy project causes nets to be added to net groups and ports - fails to package due to mismatch
7 w% S4 J" ^7 N' b J7 u# r. R1779289 CONCEPT_HDL CORE Adding a component and wire and saving the design results in a 'Connectivity save failed' error
# A. x2 K* i* \( x7 ^ H1878719 CONCEPT_HDL CORE Cannot enable or apply block variants at the top-level in a hierarchical design.. w2 B3 u2 g6 W
1865480 CONCEPT_HDL OTHER 'partmgr -ptfMode shoppingCart' cannot output cell name with project ptf file into shoppingCart.xml
; A+ G9 b6 h% v! B( o3 ^4 e( s: S1829966 CONSTRAINT_MGR CONCEPT_HDL DML independent flow: Export Physical audits missing signal models in release 17.20 M) `, P9 ~3 P$ m1 A! R
1904458 CONSTRAINT_MGR ECS_APPLY 'Audit - ECSets' crashes DE-HDL in release 17.2-2016, Hotfix 0371 o! o/ B8 \0 S2 S* E: }1 ~. z
1798269 CONSTRAINT_MGR OTHER Script changes '-' in layer name to '_'7 l" t( p. |$ z" ]# r! E% z
1835520 CONSTRAINT_MGR OTHER Cannot add members to netclass name with parenthesis
3 Q( E8 S& Q3 T$ \6 ~1896638 CONSTRAINT_MGR OTHER Constraint Manager worksheets jump abruptly
* | M' l7 Z& I3 j% D# Q1801938 CONSTRAINT_MGR UI_FORMS Add To Netclass window: Focus not on ClassSelection
2 Y9 I5 @ q5 @0 O/ B+ a. |* k1854060 CONSTRAINT_MGR UI_FORMS Using the tab key in the Manufacturing workbook jumps a cell
; |# e4 R$ ~6 D7 s/ T1881832 ECW ROLES_PERMISS Adding Users in SSO environment using PS is error prone
2 f+ W# |% Y0 Q# c7 D1864870 F2B BOM Incomplete BOM report generated, f( R. C- ?$ D! w+ o# ~$ |% ~
1846578 PCB_LIBRARIAN GRAPHICAL_EDI radio buttons and clickable buttons are hidden in the UI for verify rules
0 P+ W4 C* e- k5 u1854080 PCB_LIBRARIAN METADATA con2con needs to support special characters in Primitive Name
" n1 ?2 T+ T; o- {1796377 PCB_LIBRARIAN SYMBOL_EDITOR Unable to move pins using arrows when symbol is opened in Symbol Editor
0 q5 p/ r" U; @. x1839692 PCB_LIBRARIAN SYMBOL_EDITOR Properties tab grayed out in Symbol preview window; h% ^7 p' h: e- X0 {6 Q
1865657 PCB_LIBRARIAN SYMBOL_EDITOR Cannot change symbol properties using the General tab$ v3 x) F4 B7 r& a; }
1906888 PCB_LIBRARIAN SYMBOL_EDITOR Properties button in Symbol Pins tab of the Symbols section is inactive.
$ Z5 O. h: S" C1891248 PCB_LIBRARIAN SYMBOL_EDITOR Copy and mirror arc drawing object in the new Symbol Editor results in wrong arc on opening symbol in DE-HDL
, x# c2 O0 I* j0 S' ]1908381 PDN_ANALYSIS PCB_STATICIRD Allegro PCB PDN Analysis crashes after performing analysis and saving result in release 17.2-2016; O& S: b% j: I! r. ]" B* K8 L5 s
1825087 PSPICE AA_OPT Graph view menu does not appear when we use 'Curve Fit' in Optimizer.
- ~9 J/ c) `1 X9 k& e3 A* f, I! ^1808091 PSPICE ENVIRONMENT 'orSimSetup' crashes when 'Restart Simulation' is selected
: T3 n. I$ N1 G6 u- o' K1811782 PSPICE ENVIRONMENT Setup Simulation Profile no longer enables Advanced Markers when appropriate' i- B; l7 ? Y, b6 [
1834147 PSPICE ENVIRONMENT PSpice Part Search library icons not displayed if product is installed in the Program Files folder in release 17.2-2016
" c4 x7 H# Z" \+ m* r5 @( ]) S1841992 PSPICE FRONTENDPLUGI Getting a blank Error dialog while adding a marker
6 l0 s- s; K) h1 h1858574 PSPICE NETLISTER PSpice simulation: Some models cannot be used after upgrading to release 17.2-2016
) g$ G9 S' a, s' }0 ^1865022 PSPICE NETLISTER The division operator is not recognized by PSpice in DEV expressions in release 17.2-2016- ]6 k3 Z4 q# t$ W
1677119 PSPICE PROBE PSpice crashes when plotting simulation message summary4 O4 r, v7 C' V( w. e7 T) |( S" e% a
1837046 PSPICE PROBE On Windows 10, PSpice crashes on clicking Yes to see message
% r/ u& I6 V3 A3 p. O1 K0 d5 ?) H" A1879387 PSPICE PROBE PSpice crashes when we choose to plot simulation message summary2 ?" _1 k6 R0 \' X8 V8 r( ]
1842231 PSPICE SIMULATOR Wrong results in PSpice Advanced Analysis for DC Sweep Analysis, l: K$ m3 m' `/ U9 ~2 N
1843446 PSPICE SIMULATOR Distribution type is not showing under Assign Tolerance window for transistor+ s) |, ]- ]9 I
1872630 RF_PCB ROUTING Transition taper length does not work in route- Add RF trace
' |* J: l: [3 G. ]- i1872636 RF_PCB ROUTING Inherit Width parameter in Route -RF trace only uses width of one side* ~' \6 |. ]& l& y+ d4 P
1872644 RF_PCB ROUTING Regression RF trace: change in trace width not retained while routing; n- j9 T3 [- K/ f7 B
1901201 SIP_LAYOUT EXTRACT extracta is not retaining custom layer names* ^" H" i# E) D( ]
1813380 SIP_LAYOUT OTHER Layer Compare is not adding the required shapes
7 `* [7 u7 X1 W3 w/ A: d# _ P+ [1852762 SIP_LAYOUT OTHER Error generated in Package Design Integrity Check when adding soldermask to my design! k' J) w: a* d9 L$ T) [
1886847 SIP_LAYOUT REPORTS Incorrect metal area in metal usage report
0 s* ]. t( P" l& M1 [* U% Q# V7 [6 D1491315 SIP_LAYOUT SHAPE Dynamic shape filling exceeds the shape boundary on running 'create bounding shape' command8 H$ x- Y" n& C2 D
1853989 SIP_LAYOUT SHAPE 'Shape - Select' and then' Move' from pop-up with ix 500 iy 0 moves shape diagonally
) W2 H( }) T& O! z2 t1868509 SPECCTRA PARSER Autorouter takes long time to invoke3 {) T# m$ ]5 V6 }& G* p9 M. @2 @
1869317 SYSTEMSI ENG_PBA SystemSI PBA does not align correlation waveforms correctly on Linux platform; _, O- Y6 q4 Q" C$ e
" _2 }5 L f7 }1 N& y, ^
0 e8 d' v4 M4 mFixed CCRs: SPB 17.2 HF037
0 O, O- D1 o5 K+ l03-30-2018
- `, i* R8 W- H X: i! u========================================================================================================================================================5 {, z4 f) ~6 ?. l( W/ \% ^3 t# x. P
CCRID Product ProductLevel2 Title0 i+ y) d& u1 O9 _) _
========================================================================================================================================================' l/ M4 d5 q5 D" t6 v/ {
1886573 ALLEGRO_EDITOR IN_DESIGN_ANA Fail to launch Sigrity executable from release 17.2-2016) R7 {$ e& U6 t1 l- I
1891113 ALLEGRO_EDITOR NC Clubbing total backdrill layerwise data
% ]9 b+ w7 p5 G7 C7 ?" h0 @2 Q1886085 ALLEGRO_EDITOR SHAPE Line to Thru Via DRC is not displayed automatically
2 A* Q( G* U# d. y6 Q: [% g3 y1 m1850888 ALLEGRO_PROD_TOOLB CORE Design Compare crashes immediately after execution5 t$ [( N* k7 X3 F
1639079 ALTM_TRANSLATOR CAPTURE Title block issues with third-party design
: `' K, ~% O8 R1722577 ALTM_TRANSLATOR CAPTURE Third-party translator does not work in Capture in release 17.2-2016 if CDSROOT is not defined9 g" f" C9 r5 i K, X- w1 E
1744697 ALTM_TRANSLATOR CAPTURE Third-party translator crashes
2 w$ V! P, D4 D$ p: L0 Z1820160 ALTM_TRANSLATOR CAPTURE Title block does not show ghost image when selecting it for placement
& p8 m& E/ Y3 S) ~6 s1628560 ALTM_TRANSLATOR PCB_EDITOR Third-party translation to PCB Editor not working properly
& ^) o: W' m) W2 z! [1 R1836750 ALTM_TRANSLATOR PCB_EDITOR Third-party translator fails to translate a complete design
+ T1 P+ z5 G3 [- d# W1844423 ALTM_TRANSLATOR PCB_EDITOR Third-party translation takes a long time in release 17.2-2016
* \# g* ]# A. X$ i1849338 ALTM_TRANSLATOR PCB_EDITOR Third-party translated board not correct& h& f: {6 N* B
1894607 CONCEPT_HDL CORE Closing CM during 'Save Hierarchy' crashes DE-HDL, N" b: Z# \" \; x
1703351 CONSTRAINT_MGR CONCEPT_HDL SigXplorer shows invalid models instead of default models in extracted topology
. T0 y: t' v, K3 c, ]& O1868687 CONSTRAINT_MGR CONCEPT_HDL DML-independent flow: some pin-pairs missing for Differential Pair XNets when migrating 16.6 design to 17.26 t: m. q* n! z5 q
1868747 CONSTRAINT_MGR CONCEPT_HDL Additional pin-pairs created on migrating design to release 17.2-2016 DML-Independent flow
# `; H2 B; I, S) z _$ U1887794 CONSTRAINT_MGR OTHER Ability to disable cross-section changes in F2B flow
: r& a$ m M" y" w; f; j1859193 MODEL_EDITOR TRANSLATION DML provided by Model Integrity has a parsing error: curve must start at time zero
( b) s J) s* g1 ^2 E: H$ q e: l- }) P: U1 F4 F# A$ C
6 ~* v W& u! b/ Z* w! n/ zFixed CCRs: SPB 17.2 HF036
9 `. B! {/ ]: P+ a8 J# `( @03-16-2018; c8 f6 p5 l0 V) {7 |' N; B3 w
========================================================================================================================================================8 r1 ^1 F; f; _ d
CCRID Product ProductLevel2 Title, z4 X: ~7 p9 y* T
========================================================================================================================================================
; w8 b) x) l2 }# |! [/ S4 d1880209 ADW DBEDITOR DBEditor quick search is resetting the check boxes in the Attributes tab" \' \ v% K U; P. p. w0 f' C9 _
1880376 ADW DBEDITOR Allegro EDM Database Editor wildcard search functionality broken after installing hotfix 034.
5 N% Z( f3 ~2 c1 L8 j1855444 ALLEGRO_EDITOR DATABASE PCB Editor crashes on creating MDD files after deleting subclasses" _" ^3 k, L) N; c- M5 i' H$ b
1863478 ALLEGRO_EDITOR DATABASE PCB Editor crashes on a specific machine when loading any .mdd file
# H% c0 x$ S; K+ @2 ~8 d1875544 ALLEGRO_EDITOR SCHEM_FTB Constraints are getting removed3 W, U: p7 n3 z( U* x; {+ @: c8 ]- b$ ?
1719683 ALLEGRO_EDITOR UI_GENERAL Incorrect display when using infinite cursor.1 o" T8 g1 v; _& _1 e( r# y
1765989 ALLEGRO_EDITOR UI_GENERAL Selection window does not work correctly with infinite cursor option checked. s" n! c. C0 V
1885667 ALLEGRO_EDITOR UI_GENERAL Infinite cursor is not working correctly; w0 B. ~) e; E2 K/ h5 p
1873954 ASDA IMPORT_DEHDL_ SDA: Inconsistent pin number positions on part in an imported DE-HDL project# u; O' k2 y$ q: [; p
1873883 ASDA NEW_PROJECT SDA: New project from DE-HDL creates blank Page 1
7 f' E' K6 S7 l9 i g, h9 U1852036 ASDA VARIANT_MANAG Design with variant cannot generate a variant BOM% e- h' v+ `' c1 a
1875549 CONCEPT_HDL CORE Incorrect PART_NUMBER/VALUE properties on schematic1 `& V/ p4 j2 w. u+ r6 B
1881848 CONCEPT_HDL OTHER License issue: Cannot open Allegro Design Authoring and unable to choose options and features5 g6 p" E. _% d3 ?- v. v
1872189 CONSTRAINT_MGR CONCEPT_HDL Pin-pairs are created for incorrect members of differential pair after ECSet is applied
; G' A: T# L1 G/ D7 Q1880235 CONSTRAINT_MGR UI_FORMS Ability to lock auto-generated Constraint Set in UI2 H! X+ m9 \! `9 M
1868711 CONSTRAINT_MGR XNET_DIFFPAIR Nets are dropped from XNets on the BRD file in the front-to-back flow
$ h) p, i; K, U* T" {" i1879296 ECW PROJECT_MANAG Mode to remove Uprev Lock from locked webs in admin keys
$ a5 ]% m/ B) R; x8 L5 z5 i8 L1881632 PSPICE SLPS PSpice creates 'psp_input.log' during co-simulation flow+ \ g l2 x6 ^$ [
1879302 SCM OTHER SCM crashes when global nets are changed in the Block Packaging Options dialog box
! u" O+ X0 z1 z* i& {. o1879580 TDA SHAREPOINT GetData error when opening a project in Design Data Management0 k" n, n* [1 Z' V$ E0 k3 c
$ D$ m2 F! B& r+ O1 {4 z2 S/ c a7 {" X: z% D( S
Fixed CCRs: SPB 17.2 HF035
1 j5 S; `: ?2 C4 @03-02-2018
+ J. R; w" Q" C P' X4 t1 T5 V; h========================================================================================================================================================
- F2 M0 e2 e( r$ lCCRID Product ProductLevel2 Title x% S- L* l4 {- ]; D
========================================================================================================================================================
# @; j4 p; l7 |- G1873547 ADW ADW_UPREV adw_uprev resulted in incomplete footprint XML
) q7 g; f9 B+ n* v! k/ {8 f2 n: v1643895 ADW DBEDITOR Create Footprint model name is not working properly if footprint exists in local flatlib
' i9 R0 Q2 g! F# h+ [) ]1846400 ADW DBEDITOR 'Copy As' and 'Rename' STEP model options do not work8 l0 c$ z! H+ d- Z
1868299 ADW FLOW_MGR Copy Project fails and makes Flow Manager unresponsive: W. Y& l* P( ^- v$ n
1872796 ADW PART_BROWSER Part/Model Details Attributes are all empty when connected to the EDM DB, o! u* s& h6 R2 p
1877199 ALLEGRO_EDITOR DATABASE Purging backdrill adds bottom filmmask to vias when it is not defined in the padstack" G- K$ G% Q: @- ?* }
1877219 ALLEGRO_EDITOR DRC_CONSTR PCB Editor crashes on updating DRC
* @( a0 e& O+ K. A3 |5 s/ K+ L1875528 ALLEGRO_EDITOR GRAPHICS Subclasses disappear in partition" M S0 C# L: ]5 P- \' K. r
1868364 ALLEGRO_EDITOR OTHER Translator for Layout to PCB Editor fails in release 17.2-2016 but works in 16.6
# H# w3 p3 U- n7 ]( n, c$ H1822989 ALLEGRO_EDITOR UI_GENERAL PCB Editor very slow when using infinite cursor0 P$ i8 q6 W) k$ X6 H
1855275 ALLEGRO_EDITOR UI_GENERAL PCB Editor becomes slow if OpenGL is disabled
6 X' ]$ t/ r; A1868803 ALLEGRO_EDITOR UI_GENERAL Infinite cursor not working as expected
0 _7 ^7 `4 L& g- W1 ]1869523 ALLEGRO_EDITOR UI_GENERAL PCB Editor hangs inconsistently on axlOpenDesign; C& Q" H- y7 @. d2 y
1871409 ALLEGRO_EDITOR UI_GENERAL ESC key does not function with Enable_command_window_history set
' i; f# [9 Y5 J* ~' @) C8 @1812306 ALLEGRO_PROD_TOOLB CORE Incorrect DIFF result of PCB Design Compare
8 u5 K# ?6 o" z9 q g1872772 ASDA MISCELLANEOUS SDA pulls a license for 'Allegro_performance'
( V% B( s/ [6 T! q" X) }5 c1877070 CAPTURE OTHER Capture redraws icons
1 h6 B( e0 C+ T1 C) C2 u3 `1863624 CONCEPT_HDL CONSTRAINT_MG XNet names are changed in the designs migrated to release 17.2-2016, G* X$ [# V- o( E4 R; I& C9 u
1866290 CONCEPT_HDL CORE variant editor/DE-DHL crashed when changing a component property" r/ G' o1 A, D& v- ]
1858139 CONCEPT_HDL OTHER Slow graphic response in Windows10: Icons redraw) m1 e/ K7 y. b1 o0 d z' |1 P! ?2 |
1872703 CONCEPT_HDL OTHER Icon and toolbar in DE-HDL keeps on refreshing for every command
1 n; H% L$ x- W: {# q1873949 CONCEPT_HDL OTHER DE-HDL user interface refreshes frequently' o- w- c1 i6 w# \. H" m* t
1871542 CONSTRAINT_MGR INTERACTIV Extracting object with 'Referenced ECSet' does not inherit T-points from the applied ECSet
! D0 X* S) g X9 W" }2 V8 m1868812 CONSTRAINT_MGR UI_FORMS Cannot Save Log File from CM ECSet Audit.
5 w0 m2 B' L8 Z1878574 ECW PROJECT_MANAG Duplicate entries are created in SharePoint users list while creating project on SSO setup, m. R$ Z5 Q, {
1878619 ECW PROJECT_MANAG Too many mails generated on doing create project. N7 d. Q+ Y2 M9 o7 X
1862772 ECW TDO-SHAREPOIN Logical BOM file name not displayed in Changed Files of Pulse Activity Log.) e8 }& a' _ h
1860641 INSTALLATION DOWNLOAD_MGR Download Manager remembers credential settings- A2 g8 A4 z( ?2 Y
1867195 INSTALLATION DOWNLOAD_MGR Download manager crash
! B% ?1 ~: Z, g1872187 SIP_LAYOUT DRC_CONSTRAIN Sliding a cline removes DRC markers but updating DRC shows more DRC markers
: H8 }* z5 @" T; K/ K! Y8 O% |6 ^, u% L2 A
5 s9 w: L' M- j- q- d
Fixed CCRs: SPB 17.2 HF034
; }1 K3 e' T! M3 D02-11-2018
& z' Y! B. z$ o' l========================================================================================================================================================3 S, K9 \9 G# l: _3 J2 h
CCRID Product ProductLevel2 Title
2 S$ D; g$ l% p" A: n" B========================================================================================================================================================
3 A8 |2 u. V& S1863981 ADW ADW_UPREV adw_uprev is taking a long time after installing hotfix 031
# L" ~ [* [( _; F% }1 J8 o Z1868186 ADW DBEDITOR Configured LDAP authentication giving error on launching DBeditor after ISR31 installation, J4 K0 J8 u* m
1861524 ADW LIBDISTRIBUTI Library distribution is checking for obsolete classifications every time it is run hence taking more time
# H- H1 y/ C4 _% k1842998 ADW LIB_FLOW Footprint model check-in fails with verification checks failed error
; V& U {# y' N- M0 @# G0 ~# H2 {1863047 ALLEGRO_EDITOR DATABASE The layer added above the TOP layer in SiP Layout cannot be deleted from database.+ v* x% s+ T: P( f
1852799 ALLEGRO_EDITOR DFM Refresh symbols crashing inside constraint re-enablement code
1 q# Z" |: ^+ g8 k1865732 ALLEGRO_EDITOR DFM The Thru via hole to Pad check in Annular Ring should check only the Finished hole size instead of backdrill diameter
& d4 v5 u' k h, g0 m- s8 Q: G1862977 ALLEGRO_EDITOR DRC_CONSTR Differential pair phase tolerance DRCs introduced in release 17.2-2016 DML-independent flow
5 T5 z% ~! F5 {- N) ?- n1864460 ALLEGRO_EDITOR EXTRACT Running Extracta from outside using command window writes layer name for top/bottom layers incorrectly for SiP designs
# w4 n: p0 A7 k1859208 ALLEGRO_EDITOR GRAPHICS Pop-up menu remains on desktop when PCB Editor is minimized5 C$ z0 A+ j; i) z3 I* A8 N, b
1866422 ALLEGRO_EDITOR MANUFACT Backdrill update taking a long time
; H/ |- a4 i) a1867148 ALLEGRO_EDITOR MANUFACT Backdrill update taking longer time to process.
- o0 e' ]5 _. D* m- H1872127 ALLEGRO_EDITOR MANUFACT Backdrill performance issues - Additional fixes required for S0342 `+ b: I5 x2 W. ^4 V
1866577 ALLEGRO_EDITOR SHAPE Board becomes unresponsive on Shape Update or Slide Trace# E, _( d1 X. G& [6 O6 }7 c% ]
1867590 ALLEGRO_EDITOR SHAPE The Shape to Pad clearance on multi drill oblong padstacks is not working correctly
0 D# l; t+ B) u- s2 W1 h# p* a/ `1871902 ALLEGRO_EDITOR SHAPE Void issue during rotation of symbol with multi-drill padstack from hotfix S032
7 O% Y5 j' G( j4 }1866778 ALLEGRO_EDITOR UI_GENERAL Unsupported prototype 'Enable_command_window_history' is not allowing text edits using arrow keys! q) P4 [' I8 N3 I% n1 @+ C7 ?6 w! }
1865757 ASDA DESIGN_CORRUP SDA hangs when trying to save design or copy page or circuitry
: ]5 I) D V* y6 |- u p" p1865872 ASDA DESIGN_CORRUP Corrupt design crashes on editing.
' m1 U( Z5 c% O( @5 T( Q1867039 ASDA DESIGN_CORRUP Design corruption issues: L$ ~2 S f2 s, J9 v) A
1831263 CAPTURE OTHER Toolbar refresh is very slow on windows 10 after installing latest windows patch
E7 w( k l3 x7 Z$ g3 O1843595 CAPTURE OTHER Icon refresh is very slow on Windows 10 Professional after installing Hotfix 0291 L7 Y6 \* ]1 X3 U+ G3 I
1845003 CAPTURE OTHER Application slow to respond after running for a long time/ h5 y3 q2 T0 k3 [4 D
1847062 CAPTURE OTHER Starting OrCAD Capture redraws the toolbar icons many times.+ V, s% |' Z0 D1 C
1850816 CAPTURE OTHER Capture redraws toolbar very slowly and repeatedly) E0 U" x$ N. i2 I! `0 U
1851346 CAPTURE OTHER Capture CIS redraws toolbars repeatedly6 Q/ G0 v O* B* j. \1 _4 t' b1 O/ n
1851354 CAPTURE OTHER Capture slows down in Hotfix 30 as tools icons are repeatedly redrawn very slowly' k* m: w; t0 B: w
1851883 CAPTURE OTHER Toolbar content refresh is very slow
2 c+ ?' |; H; L, {7 @6 e" {1852819 CAPTURE OTHER Capture refreshes toolbar again and again, _: K# u8 r# ]: t6 r
1853395 CAPTURE OTHER Release 17.2-2016: Capture is refreshing toolbar icons many times at startup with latest hotfix9 S/ V9 V/ C4 p- ?* d! z1 u
1853972 CAPTURE OTHER Capture starts and redraws toolbar very slowly+ Z9 d/ _- e" i0 I0 U
1854735 CAPTURE OTHER Capture toolbar reloads multiple times
7 ^0 m" H: \ w; g7 r) p- S1855850 CAPTURE OTHER Toolbar content refresh is very slow
% ]* r4 q$ n1 E1857523 CAPTURE OTHER Toolbar icons refresh multiple times and very slowly in release 17.2-2016/ {3 X0 x- Q( B( L. m" i: r
1859219 CAPTURE OTHER Toolbar is refreshed multiple times while starting Capture CIS
. A/ C% u0 {- ?5 y; L2 [) ~, c1859626 CAPTURE OTHER OrCAD Capture does not work with the latest Windows 10 update' t- G: o7 s+ w9 e B
1863341 CAPTURE OTHER Toolbar icon refresh is very slow% X9 V6 H( g9 r
1865661 CAPTURE OTHER Release 17.2-2016, hotfix 032: Capture extremely slow on Windows 10) r3 p8 @# ^! _
1867009 CAPTURE OTHER Slow graphics with Design Entry CIS on Windows 10.
9 C# A2 p2 R1 N- m; ]% Y+ Y1869160 CAPTURE OTHER OrCAD Capture poor performance (toolbar related)4 t: v# I2 A9 m; k$ s8 X
1869692 CAPTURE OTHER Redrawing of toolbars on Windows 105 Y* B2 e: \4 T' f+ p. g$ |1 E9 {) M
1870310 CAPTURE OTHER Allegro Design Entry CIS redraw issue
( W7 g4 x/ j) L1870367 CAPTURE OTHER OrCAD Capture Slow Redraw
6 o* ] }# Z" N# g' C8 W% d1871382 CAPTURE OTHER Schematic will not open and toolbars refreshed repeatedly
9 c2 y, g0 @0 e+ @1872427 CAPTURE OTHER OrCAD Capture freeze on Windows 10- N( X* V/ R7 l& _; P% x( @! W
1862679 CONCEPT_HDL COMP_BROWSER Unable to input property value to search in Part Information Manager
+ @ ]! y0 @1 s! a7 u1865039 CONCEPT_HDL CORE 'Save Hierarchy' of a release 16.6 design opened in release 17.2-2016 results in unexpected part changes
7 ]+ p+ E. u T, ~+ `( {: B1866544 CONCEPT_HDL CORE XNET_PINS added to migrate Design as DML Independentflow does not get saved in the CSA files4 ~2 N) L* o7 H$ j; [
1849363 SIG_INTEGRITY SIMULATION Differential impedance calculation shows ZERO when changing dielectric constant% v9 @: k0 a* G) k9 d7 g
1854195 SIP_LAYOUT UI_GENERAL After setting 'enable_command_window_history' in QIR5/Hotfix 031, Edit - Text no longer functions9 f; f# v/ k3 c% T
# l( S, ] x0 m5 |0 E8 F7 ]+ ~
( r7 d! @6 }4 e5 y, }* s8 n+ YFixed CCRs: SPB 17.2 HF033
/ M. W* B3 F: g3 j* \01-25-2018
. T6 {8 L% X# j% s( D& y; B1 _3 R========================================================================================================================================================( z* Q# w6 Y" ]4 G9 r
CCRID Product ProductLevel2 Title5 Y' w. r) ?' a5 O" \
========================================================================================================================================================
/ e. J% m; J7 `/ k/ t( j3 X1828672 ADW ADWSERVER LDAP connection error while trying to log in to DBeditor
1 H/ r) Z3 g) p& {7 k( @4 ~, P1840699 ADW DBEDITOR Unable to release footprint model due to older version being linked to a DE-HDL Block Model
. g; h- n: o" r B1852402 ALLEGRO_EDITOR DATABASE Cutouts are not converted correctly when opening release 16.6 board in release 17.2-2016- D2 a2 w- t( a! t# a$ X, }
1855223 ALLEGRO_EDITOR DATABASE Release 16.6. BoardOutline not fully converted to release 17.2-2016 Cutout Layer
$ ^7 z5 i C0 Q, k1855252 ALLEGRO_EDITOR DATABASE Unable to open a previously saved release 17.2-2016 database
# W+ L1 V" h" f2 p1863025 ALLEGRO_EDITOR DRC_CONSTR Shape voiding to Via pad with backdrill keepout is oversizing the Dynamic shape void by the backdrill keepout; [. y; V$ g+ Q( q- j4 W" n4 M; R; D
1854087 ALLEGRO_EDITOR EDIT_ETCH Sliding arc crashes PCB Editor, w: F3 s9 h. M) q7 c1 J
1840667 ALLEGRO_EDITOR INTERACTIV Choosing 'Change Text block to' from pop-up displays message 'E- (SPMHGE-150): Text font is not defined', [0 S* f D1 y F! z4 E- Y
1849133 ALLEGRO_EDITOR INTERACTIV On choosing 'Change Text block to' on text , 'Text font is not defined' message appears# X, v9 N0 q- a. ^" a4 Y9 A
1854695 ALLEGRO_EDITOR MANUFACT PCB Editor crashes while performing nc_route' v' N8 |; ?0 P" N* a/ H! A" e) y( c
1854634 ALLEGRO_EDITOR NC NC Drill file is generated with half the number of Drill Holes on enabling 'Optimize drill head travel'
2 M1 V+ ^' c* M4 r) A8 I1856773 ALLEGRO_EDITOR NC Issue with Optimize Drill head travel in hotfix 031: Missing drill holes0 |' {/ u6 Q' G& y0 J5 Q4 x1 z' x3 I
1860876 ALLEGRO_EDITOR NC NC route critical difference between hotfix 031 and 022: No slots found warning& |9 h% d1 h4 f) ^* i+ Y; u4 t
1758671 ALLEGRO_EDITOR OTHER Export parameters takes long time to export and some times the process hangs9 E0 ~- F( }* z; p# g1 Y. k" r$ ^4 a S
1040989 ALLEGRO_EDITOR SHAPE PCB Editor crashes while editing board outline
4 j- B; `% i: U% p- q1328385 ALLEGRO_EDITOR SHAPE Check for missing thermal reliefs when shapes overlap
/ u" p( x% u# b% \) U, @/ I5 d1366376 ALLEGRO_EDITOR SHAPE Thermal created for Xhatch shape overlapping another shape, but not created when solid shapes overlap" h: z: ~6 C; H+ C- d; V' M2 m
1716436 ALLEGRO_EDITOR SHAPE Acute angle trim should not violate DRC.
! u u" v; J2 d+ @. l1822377 ALLEGRO_EDITOR SHAPE Setting shape parameter Acute angle trim control to Full round produces unwanted shape to keepout DRCs
6 o6 W8 P& K9 J& B4 M( V. v1826436 ALLEGRO_EDITOR SHAPE Same net shape to hole spacing not voiding shape for cline of different net moved close to vias of same net shapes
" j% C2 S8 i3 X: _1834510 ALLEGRO_EDITOR SHAPE Same Net Shape to Via Spacing does not always clear correctly# u p2 `6 K$ j: v7 P) ^' Z/ r
1850716 ALLEGRO_EDITOR SHAPE 'DiffPair combined void for vias added with Return Path option' does not work with fillet and pad suppression
5 d. N- U0 \0 |3 Z4 V! K$ L1852814 ALLEGRO_EDITOR SHAPE Thermal reliefs are not created after placing modules.
0 j/ ]1 R0 v, Y% r1853453 ALLEGRO_EDITOR SHAPE Route keepout clipping of cross-hatched shapes needs to be corrected8 b% ]! V# K& ~, Z# i- Q
1859391 ALLEGRO_EDITOR SHAPE Shapes are not using 'minimum aperture for gap width' for voiding after back drill update.9 ~' c2 t# v( }3 x: k r; ~ u
1859410 ALLEGRO_EDITOR SHAPE Shape to Teardrop is not using same net spacing rules
+ u+ O( P/ C. M! U7 J1825397 ALLEGRO_EDITOR UI_FORMS Option panel disappears in release 17.2-2016
b/ ~5 z& U3 w6 K- `! Q8 }/ [7 r4 n1854070 ALLEGRO_EDITOR UI_GENERAL enable_command_window_history prevents many aliases and commands from working correctly
0 A$ a) [5 M+ m! ]1855180 ALLEGRO_EDITOR UI_GENERAL Comma and dot do not work in funckey if 'enable_command_window_history' is set( N; L Z. A5 A4 a
1860003 ALLEGRO_EDITOR UI_GENERAL Icons and features missing or behaving differently in release 17.2-2016, Hotfix 0318 N$ S) V8 }+ b) Q
1861278 ALLEGRO_EDITOR UI_GENERAL Icons and menus missing in PCB Editor in release 17.2-2016, Hotfix 031
5 V6 ?4 f4 o% c2 \1 C1862292 ALLEGRO_EDITOR UI_GENERAL Layout Pins icon missing in toolbar in Symbol Editor since Hotfix 031
6 U% J1 a E4 m; s1793284 ALLEGRO_PROD_TOOLB CORE Limit View (V1R, V2R, COM) for OUTLINE layer.
$ s5 I3 g+ Y. T) K0 W$ @1712701 ALTM_TRANSLATOR CAPTURE Third-party translator shows error for missing operand
# W. {! [- e& o6 u5 E/ S0 E; v) H; R1802182 ALTM_TRANSLATOR CAPTURE Imported schematic has connectivity loss
2 A9 j; V3 L! s" \1802462 ALTM_TRANSLATOR CAPTURE Hierarchical ports placed incorrectly for imported third-party design
/ Z, V' m8 }! S8 ~1823935 ALTM_TRANSLATOR CAPTURE Translating third-party schematics with hierarchical pages from Design Entry CIS o& q0 j# P/ S! M* {$ y
1830570 ALTM_TRANSLATOR CAPTURE Third-party to Capture translation is translating only one page out of 327 F! @8 Z. S/ X
1839627 ALTM_TRANSLATOR CAPTURE Third-party translator is not importing complete schematic
% E7 f, L3 S. o0 L% {1846965 ALTM_TRANSLATOR CAPTURE Cannot translate third-party schematic; P2 l7 l9 o ^$ X
1816767 ALTM_TRANSLATOR DE_HDL Error when translating third-party schematic to DE-HDL. t: D% K. T D* Z! R
1845601 ALTM_TRANSLATOR PCB_EDITOR Cannot operate third-party PCB translation in release 17.2-2016 Allegro Venture PCB Designer license
8 L2 M/ Z) S4 G8 @6 Y8 O6 a1841060 APD DIE_GENERATOR Cannot 'die text out' from SiP Layout or Allegro Package Designer6 b, \7 e: ]1 ]
1793232 APD SHAPE When fillet/taper not connected to a pin, voiding process incorrectly applies shape clearance values
: x! e- ^, K+ V# n) e1846541 APD SHAPE shape degassing does not obey void to shape boundary
, [8 H' E6 Z" E; O" x1863446 ASDA CONSTRAINT_MA A space in the name of a spacing or physical constraint results in the incorrect constraint set name
4 C. p5 p" v" U. v# B. {# Z* i1859678 ASDA VARIANT_MANAG SDA - When hovering over all three buttons, under Preferred Parts in the Variant info it says (Do not install)
J" V( l3 n3 t/ e3 N2 ~, D1815839 CONCEPT_HDL CORE Allegro Design Entry HDL crashes when entering Location data manually
8 k) B6 o# f# o! |6 u: O1841857 CONCEPT_HDL CORE Unable to modify Components in non-windows mode
: k0 ~4 [/ E1 i5 @: S' Y/ b1852096 CONCEPT_HDL CORE Creating a block using top-down approach does not generate the CSB file
7 f" s S8 h8 a5 |1857390 CONCEPT_HDL CORE DE-HDL crashes on moving symbol% e' T! x. l9 S0 i* f6 x
1789070 CONCEPT_HDL OTHER Having folder 'allegro' in cpm root directory gives error while launching layout editor from Project Manager
5 I/ ]; k2 d0 g7 ?4 o1862484 CONSTRAINT_MGR CONCEPT_HDL Extracting an ECSet in SigXP is missing a t-point
) {) s+ e. g1 F* l2 W ~0 J: J1863045 CONSTRAINT_MGR CONCEPT_HDL Pin pairs deleted for a few differential pairs after upreving the design to release 17.2-20165 J) E" W0 a' R2 ^& K
1863054 CONSTRAINT_MGR CONCEPT_HDL Differential Pairs are treated as invalid objects on upreved design
1 F7 f8 h7 D9 {6 a9 R: B. {& D1863094 CONSTRAINT_MGR CONCEPT_HDL Pin-Pairs are shown duplicated in the topology for the extracted object (Diff Pair)( Z) l' Z6 A7 L6 W
1831998 CONSTRAINT_MGR OTHER 'Tools - Options' settings not saved on closing Constraint Manager8 s$ w/ l, M7 F# j4 S9 s$ r0 Y
1855324 CONSTRAINT_MGR OTHER Enable the option 'Expand Hierarchy' in 'Find and Replace' dialog, by default! a0 t4 J8 [2 j2 f
1860847 CONSTRAINT_MGR OTHER 'Include Routed interconnect' option once enabled, should remain enabled for that board file! I( E# l" }. s) s5 Q# P' b
1843359 EAGLE_TRANSLATOR PCB_EDITOR While importing third-party PCB, many footprints do not convert, even though the log file says footprint created
4 E6 D9 S( l1 h1839978 SCM REPORTS dsreportgen unable to output reference designator from a lower-level hierarchical block if it has a single component
9 x3 n5 u' f. `0 @9 y( `. r1850013 SIP_LAYOUT OTHER Environment variable 'icp_disable_cte_auto_update' needs grammatical change
9 _( l* Y- c1 a; i0 w# e; Z1833742 SIP_LAYOUT PADSTACK_EDIT When creating Die to Die Via using Generate Padstacks, resultant pad stack has wrong Layers
! n0 E2 {: a& n9 ^, x1619098 SIP_LAYOUT SHAPE Acute angle of shape in design
2 W2 r7 P2 P/ u2 s% n5 n6 F1728628 SIP_LAYOUT SHAPE Auto-void in dynamic shape does not disappear if object is removed
% T; Z1 S3 c$ c' R1854592 SIP_LAYOUT VIA_STRUCTURE Create via structure returns an error% F5 i1 F! P' G6 a; T! U: x8 v
5 E/ Q3 Y5 ^% F4 T, r8 P' I
+ ?' H; \- a) V9 e# F% p
Fixed CCRs: SPB 17.2 HF032
. z4 j" I. I& Z) f01-13-2018) j5 g6 y0 W* ^+ {1 r7 ?4 P# o8 ]
========================================================================================================================================================0 D" {9 n2 J5 F6 R5 D; F) x" i; j
CCRID Product ProductLevel2 Title$ M) g3 P* a( \9 v$ x
========================================================================================================================================================
. ]" ]5 l6 F# `# M; m1 f1846603 ADW FLOW_MGR Copy project GUI not displaying correct design name after changing the project folder name) M; b! _0 @3 L5 L: |
1831152 ALLEGRO_EDITOR 3D_CANVAS New 3D viewer canvas is blank! R0 x' }, E7 |
1805870 ALLEGRO_EDITOR COLOR Color file with dot (.) in the filename is not recognized for setting color from the Visibility tab
+ ^# `# M3 u. F7 ~- ]1843126 ALLEGRO_EDITOR DATABASE DBDoctor UI is taking very long; }3 q) a9 F- Q' n
1857588 ALLEGRO_EDITOR DFM Design for Fabrication - Aspect Ratio is not taking correct drill hole size y* W. d- @; B: w: m3 k
1844313 ALLEGRO_EDITOR INTERFACES STEP output viewed in third-party tool has parts sunken into the secondary side
/ A' g0 D4 A0 `* a1801301 ALLEGRO_EDITOR MANUFACT Export IPC 2581 fails if VOLTAGE property is attached to the nets on each side of a RF component0 v) T3 f5 X# m r# }3 m4 Y
1850078 ALLEGRO_EDITOR MANUFACT Choosing 'Manufacture - Artwork' crashes tool
+ x% Q: \: C- g- V9 ^$ m1844049 ALLEGRO_EDITOR MODULES Module deletion not removing related component information.: N9 t5 I% X- f% X% {4 l* c t
1849665 ALLEGRO_EDITOR MULTI_USER Shape rejected by muserver, O7 }% w, \+ c$ C. Y
1782831 ALLEGRO_EDITOR RAVEL_CHECKS RAVEL file does not load when it is located on a network with a UNC path specified/ K# j/ k/ n" X9 T
1830442 ALLEGRO_EDITOR SCHEM_FTB Fail to import technology file with message for failure to read the configuration file
9 k( O" X& Y) v2 ~ R1837391 ALLEGRO_EDITOR SCHEM_FTB Capture Property cannot rewrite or update constraints in PCB Editor& E2 J/ @+ K! }9 a
1840643 ALLEGRO_EDITOR SCHEM_FTB Export physical does not work after modifying PCB cross section( N" X, L3 A; k; P4 h8 T$ S
1718165 ALLEGRO_EDITOR SHAPE Drill hole cannot be voided by shape
1 E% Z0 B- l- j3 u9 M& |1753245 ALLEGRO_EDITOR SHAPE Update Shape retracts more than the shape to shape spacing! c# @2 Z3 k" ?# V/ ]8 B$ Z$ S; E) a
1827366 ALLEGRO_EDITOR SHAPE out of date shape is not flagged as out of date
1 ]- i% Q5 H: R3 X, A! j% y2 w0 {1828208 ALLEGRO_EDITOR SHAPE Shape remains out of date, but status shows otherwise
: u; R. p4 @, f5 i6 e# J9 T0 r1832098 ALLEGRO_EDITOR SHAPE Skip via shorts to plane at few places even after the necessary keep-outs are assigned to the via pad-stack.+ I7 |( d& n8 j9 n/ E9 E/ N
1834281 ALLEGRO_EDITOR SHAPE DBDoctor creates a large number of DRCs$ N- u; M/ N1 b d; z
1842121 ALLEGRO_EDITOR SHAPE Unable to clear the Drill Hole to Shape Spacing DRC as Pin is not able void to the shape correctly.
# b8 a j9 G, C" u) y7 T1846010 ALLEGRO_EDITOR SHAPE Changing MCAD hole to copper spacing in Analysis Modes - Design does not make shapes out-of-date: a% N. T1 p |0 y( R4 V% p
1839119 ALLEGRO_EDITOR UI_GENERAL On some machines, PCB Editor hangs when launched with a script that uses SKILL to open a design' p' w% k; y+ [, S, R
1828794 APD SHAPE Setting Shape Fill Xhatch Cells option to HIGH, crashes the application8 j4 x8 Q+ Q; B/ {
1840748 CAPTURE PROJECT_MANAG Capture crashes on opening or creating designs4 H7 O4 F% t) W k! U
1785298 CONCEPT_HDL CORE Incorrect object access during variant load+ N3 }2 b: l0 J5 l( X3 I) p
1832119 CONCEPT_HDL CORE Save Hierarchy shows ERROR(SPCOCN-2010) messages but design packages without error* o6 u5 O* o+ }4 a B2 |" [) C
1833036 CONCEPT_HDL CORE nconcepthdl crashes with a core dump when running an external script
6 O% G6 `! d8 m/ B2 x$ E1841545 CONCEPT_HDL CORE NO_XNET_CONNECTION properties added to two-pin filters after upreving to release 17.2-2016( r3 z( i1 {" ], B! @5 x
1842289 CONCEPT_HDL CORE Opening a schematic in release 17.2-2016 causes the .dcf file to be overwritten
4 b5 G; s( S# a- S1841543 CONCEPT_HDL OTHER DE-HDL crashes when changing a net name/page name/bit bus after installing release 17.2-2016, Hotfix 029
- D0 ]& w8 X; l) C& q1 A7 j& {1843791 CONCEPT_HDL OTHER Table of contents listing does not update for some hierarchy blocks at the top level. a$ C! I4 m! j8 `& l
1850709 CONCEPT_HDL OTHER DE-HDL crashes on editing text on canvas in release 17.2-2016, Hotfix 0304 ?0 n" w; G# O3 I; M3 G
1853377 CONCEPT_HDL OTHER DE-HDL crashes on trying to edit bus tap value on Windows 10.: [0 M/ x3 j3 B- j
1857213 CONCEPT_HDL OTHER DE-HDL crashes when changing Power Property
! ^) A4 l2 ~4 C! I1857214 CONCEPT_HDL OTHER In release 17.2-2016, DE-HDL crashes on using 'Change' for a $LOCATION text value on Windows 10! J1 ?1 U6 ?: p( a% H: Z( S
1821982 CONCEPT_HDL PDF Pin number shown in PDF published from DE-HDL$ g* D; H- d: v6 @/ U8 w8 X' J
1848615 CONCEPT_HDL PDF PDF Publisher shows incorrect pin text values for parts
% z V' X! M4 ^% z1845996 CONSTRAINT_MGR CONCEPT_HDL Confusing error message regarding 'Auto XNets Off Mode' vs 'DML Enabled'2 [ n9 k1 f( M9 [
1854190 CONSTRAINT_MGR CONCEPT_HDL 'Audit - Electrical CSets' hangs Constraint Manager after the design is upreved to release 17.2-2016" Z/ |. S1 d% h: k
1854868 CONSTRAINT_MGR CONCEPT_HDL Match Group getting deleted after upreving the design to 17.2 and removing the signal_models: ]# g1 u5 l( e' ^) k, l+ u% f
1854872 CONSTRAINT_MGR CONCEPT_HDL Additional Pin-Pairs getting created on the DiffPair after upreving to 17.2
2 w6 g. }; W) u# N1822624 CONSTRAINT_MGR ECS_APPLY Cannot copy PCB net schedule from a net to other nets
+ g* Z1 N3 U$ d2 F1854883 CONSTRAINT_MGR ECS_APPLY Match group showing 0 length for pin pairs in design upreved from release 16.6 to 17.2-2016
. x6 C3 t# c% z( N3 r- Z! D# _5 ]" z2 e1855893 CONSTRAINT_MGR OTHER SigXplorer extraction crashes PCB Editor
. W% N; {7 V3 I* @; G. Y1855917 CONSTRAINT_MGR OTHER SigXplorer extraction does not extract constraints unless the worksheet is opened once in CM; g; c, [9 |9 K: }& C2 h
1855350 CONSTRAINT_MGR UI_FORMS Constraint Manager significantly slower in release 17.2-2016, Hotfix 0315 H' G# K) }# R2 Q# p6 u
1855860 EAGLE_TRANSLATOR PCB_EDITOR Cannot invoke a CAD translator in PCB Editor4 L; N& k* y9 x5 i
1857745 EAGLE_TRANSLATOR PCB_EDITOR A CAD translator does not invoke in PCB Editor; v/ [2 K3 N7 G/ O. \' ^8 W
1859005 EAGLE_TRANSLATOR PCB_EDITOR Eagle translator is not invoking at all
+ D4 b6 `( {3 ]1 ~1843091 F2B DESIGNVARI Variant Editor allows mismatched JEDEC_TYPEs in release 17.2-2016
; j' ^7 H. p% C/ E+ e7 \1719059 FSP DE-HDL_SCHEMA Termination resistors on buses not being drawn efficiently
. W4 e9 B: v! p; M1823419 FSP GUI Net Name Template not visible in Change Net Name in Windows 10 O. Q9 Y9 u5 [$ y# u4 E
1480035 ORBITIO ALLEGRO_SIP_I Die symbols are mirrored when imported back to SiP Layout! Z7 {' o( U8 T* e( | E6 M0 D
1853331 PCB_LIBRARIAN SETUP CPM file not updated from PCB Librarian setup/ _" N& u" a8 E. x* a3 W! s; s- T" X
1841308 PCB_LIBRARIAN SYMBOL_EDITOR Symbol not updated in Library View& D2 D2 A: l# X( J; p: B Y
1831269 SCM OTHER Blank properties of associated components are being filled with NULL7 V1 \! |* g; R
1719057 SCM SCHGEN Pins off grid for voltage nets
& X& y, I6 W! D; ?2 E& f1719060 SCM SCHGEN Pull-ups and pull-downs showing upside down in view+ Q5 P7 x, b+ ?3 k' k( e4 N$ w% p
1732687 SCM SCHGEN Schematic generation deletes IO ports; says it's placing them on last page, but never places them# A( H8 [8 x; q( i
1855932 SIG_EXPLORER OTHER For non-DML designs, SigXplorer defaulting to mils when PCB Editor design units and CM constraints are in mm
) k, [& z8 J* k1 X F1824035 SIP_LAYOUT WLP SiP Layout DRC GUI not reading Tcl blocks in PVS DRC rule deck8 y2 ^1 L: r4 F$ ~3 k1 l1 b; G
$ U1 V! q1 Q- m' |5 [9 [9 A( j. v& N3 I, r7 @
Fixed CCRs: SPB 17.2 HF031* B1 T. e: z% [8 S/ U/ ^( `8 r
12-8-2017. ^0 X; j) M, {* B
========================================================================================================================================================
3 [7 R, d( N/ B: b: ~CCRID Product ProductLevel2 Title* x! \# @. y" v' A3 |7 D7 _
========================================================================================================================================================6 c( F8 a5 G. ~0 m: D
1746108 ADW DBADMIN Adding and then saving a custom rule set in rule manager results in corrupt rules.xml
' L7 L# r" c% F5 G' D1609983 ADW DBEDITOR dbeditor should automatically change mechanical kit names to uppercase$ {" g7 S6 K3 H8 T
1807139 ADW DBEDITOR Cannot add new properties, though the new properties were shown in dbeditor
9 H1 @3 ~. p! \6 N' @. G: G& L1807410 ADW LIB_FLOW Checked-in parts not available in database
3 k( r. A% r" d- `+ h) u1797408 ADW TDA TDO crashes without displaying exception during check-in* V4 n' H3 P! ~) @
1804500 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas fails to show all placebounds of a .dra
- Q$ e# H* y& Z5 X- S5 p1810758 ALLEGRO_EDITOR 3D_CANVAS 3D Viewer represents symbol incorrectly in hotfix 025 but as expected in hotfix 024
& {) f7 [2 Y1 N0 j ]4 y1795567 ALLEGRO_EDITOR EDIT_ETCH Route menu has same hot key for 'Connect' and 'Convert Fanout'
5 ]5 ^; d/ q- a3 i1796525 ALLEGRO_EDITOR EDIT_ETCH AiPT is not pushing dynamic shape to add bumps to resolve dynamic phase DRC) {4 a0 `8 W3 @
1818170 ALLEGRO_EDITOR EDIT_ETCH Fanout with Outward Via direction is shorting few pins2 Q# h1 P! @! t/ F4 g3 E. H
1712658 ALLEGRO_EDITOR INTERACTIV Add connect: Pin remains highlighted even after choosing 'Done'! U$ I I+ C" Y6 l( k! X; a2 f
1727193 ALLEGRO_EDITOR INTERACTIV Logic - Part List truncates device names to 64 characters though database allows longer names
|& n- z5 L$ g9 Q1775484 ALLEGRO_EDITOR INTERACTIV Choosing Next with persistent snap in Show Measure disables persistent snap" m5 @- s: T8 h: Z) i1 `* r: _
1711860 ALLEGRO_EDITOR MULTI_USER Multi-user lock cannot be cancelled$ n& d" k" M3 L3 T( y8 n- K* f
1812448 ALLEGRO_EDITOR NC Crash when canceling NC Parameters dialog$ P4 Q9 P" q ]% c( w) b
1792987 ALLEGRO_EDITOR PAD_EDITOR Pad Designer does not recognize flash names longer than 31 characters$ _ k) Q% q4 \4 D' Y
1810958 ALLEGRO_EDITOR PAD_EDITOR Padstacks with offset holes
5 n" e# T+ I* `! \& m6 W, b+ I- M787024 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in regions
! @% v% p3 \! m( {2 u3 w793232 ALLEGRO_EDITOR SHAPE Line to Shape spacing rule outside region affects shape void in region+ t7 ]: i @" V A/ [
797245 ALLEGRO_EDITOR SHAPE Line to Shape Spacing with Region not followed0 x6 `# p8 F) Q% N
865822 ALLEGRO_EDITOR SHAPE The autovoid functionality should use the true line-to-shape spacing value2 A6 w8 x- O+ {# Y8 C2 \' k/ C1 r
912051 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in regions
+ S% P) C8 B, [4 t* b- Q965714 ALLEGRO_EDITOR SHAPE Region constraints are not working correctly on dynamic shapes8 _8 N; h" e2 |3 o- j" j
968342 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region is taking conservative value and not the actual spacing value' [. S$ m+ v5 ? S' N5 p
974734 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
9 K ? C. P; a7 g: J7 k1073908 ALLEGRO_EDITOR SHAPE Allow line to shape spacing in Region, j4 h8 u: t7 H& E' c; v% H
1154787 ALLEGRO_EDITOR SHAPE Region constraints not applied correctly to dynamic shapes
/ i% r2 W$ N+ E1171283 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
# U# I% g+ w7 z2 s \. ^1181767 ALLEGRO_EDITOR SHAPE Allow override on line to shape spacing in Constraint Region
! i& ~+ I$ Y; v4 @& w1183792 ALLEGRO_EDITOR SHAPE Allow override on line to shape spacing in Constraint Region8 Y0 S# w- [( v+ ]$ P; i. b v
1186210 ALLEGRO_EDITOR SHAPE Line to shape spacing constraint does not follow the Constraint Region value+ H' c4 b q8 I) Z$ a- `
1192312 ALLEGRO_EDITOR SHAPE Region constraints are not working correctly.
# {4 Z" D% K$ ]8 q. _) B1387021 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in Regions
8 |( l1 n- u9 u$ ^' m- W1 S3 _1447891 ALLEGRO_EDITOR SHAPE Resolved constraint and actual air gap differ
! e; s1 C2 Q- Z, k. }/ I1465383 ALLEGRO_EDITOR SHAPE Line to shape spacing constraint does not follow the Constraint Region) A: V! U2 W. g4 O$ m8 M6 t
1583144 ALLEGRO_EDITOR SHAPE Line to shape spacing inside the constraint region does not follow region rules# {- q" X5 b- ^7 a% w
1591320 ALLEGRO_EDITOR SHAPE Resolve shape to pin constraint in constraint region
0 b& t' [/ s d# q* W+ V2 W& j1627305 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value
3 X$ J- S, W4 G6 U- ~: N5 C9 e1694552 ALLEGRO_EDITOR SHAPE Constraint region not working correctly
2 r2 y/ Q( m) f3 J7 B# J0 b" T1764474 ALLEGRO_EDITOR SHAPE Line to Shape Spacing for Region should be used inside region instead of conservative value
9 D9 h) q/ K8 n4 h# }6 J% @1775119 ALLEGRO_EDITOR SHAPE Shape voiding is not following constraint rules for dynamic shapes in a constraint region) @: P+ M' W. } J2 Z; E
1784916 ALLEGRO_EDITOR SHAPE Shapes are not voiding to other shapes against DRC settings, creating random DRCs.
- X) g* {: L% g/ a1793179 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape; d$ c; k8 p) w1 I b2 }
1803365 ALLEGRO_EDITOR SHAPE Region shape to shape constraints take precedence when shapes have multiple constraints$ U, D' X* d9 F' j6 o; k
1800530 ALLEGRO_EDITOR UI_FORMS 3D Anchor menu missing when using new style OrCAD PCB Editor menu% B( e# a1 O8 c+ R
1813604 ALLEGRO_EDITOR UI_FORMS 3D Anchor View is not available on OrCAD PCB Editor menu.
6 {! h: u) s; Q5 e4 _; N1784710 ALLEGRO_EDITOR UI_GENERAL During Place Replicate and saving file with same name, the warning pop-up window does not show on top
3 S! z0 N- S5 Y+ J+ G4 ?! v1784728 ALLEGRO_EDITOR UI_GENERAL During Place Replicate and saving file with same name, the warning pop-up window does not show on top% I; _% A7 j2 x
1721853 ASDA CANVAS_EDIT Movement of components results in shorts and inconsistent routing
* x6 p- Y# Y8 U$ Q% y. P7 K1802120 ASDA CONTEXT_MENUS Ports are selected though filter is set to Components7 W |8 C3 {* Q, S
1803832 ASDA MISCELLANEOUS Browse and select new libraries without editing cds.lib
) m+ X. `( `9 c- m4 J8 Y: [& x1804643 ASDA TABLE Exception when pasting table data from third-party tool in SDA1 I* {! T- y4 s
1794004 CAPTURE LIBRARY Diode pin numbers different in Capture in release 16.6 and 17.2-2016
& I* P% V# O" B6 `( h) A' v2 ^5 s1735506 CAPTURE OTHER File menu is missing in Capture! `, }% e. R2 b E8 y! R1 m# p) G
1766663 CAPTURE SCHEMATICS Capture crashes during part placement+ `) N- k* J% g! M% d$ n
1762181 CAPTURE SCHEMATIC_EDI Crash on 'Push Occ. Prop into Instance'
; D, C V- ^! P# z& l+ L7 L$ ?3 e1 ]1786762 CAPTURE SCHEMATIC_EDI 'Remove Occurrence Properties' and 'Push Occ. Prop into Instance' corrupt database* z& C9 \5 ]+ Q( o6 @3 a, Q m
1759424 CIS PART_MANAGER Unable to save the link database part from part manager+ z. p& m! a+ R) G1 g
1802670 CONCEPT_HDL CORE Variant commands take 6 to 10 hours to run on a block
+ d2 W R% S1 R$ I0 e$ b1 j7 F1816798 CONSTRAINT_MGR CONCEPT_HDL CM API ACNS_DESIGN returns the design name in mixed case9 }' D$ V+ X" Z5 X# O
1812656 CONSTRAINT_MGR DATABASE Constraint Value specified at the DEFAULT PCSet/SCSet is not shown in bold blue
, _% o5 u0 \: F1635766 CONSTRAINT_MGR UI_FORMS Worksheet views are not changed as per input% F! s# \$ R5 T
1700505 ECW PART_LIST_MAN Shopping Cart Quantity is not read or not displayed in Pulse# u0 |" f1 Y0 T2 R. s
1797371 ECW PROJECT_MANAG Clicking on another project sometimes takes you to the default project instead of the project you click on% F2 P, y5 v5 z
1843526 INSTALLATION TRIAL Trial installer should not check disk space in update licensing mode
) o' T, D7 q( c3 \" k1762148 PCB_LIBRARIAN SETUP Part Developer: Text not readable in Setup form
' {' N# f) c# |1 ?1770760 PCB_LIBRARIAN SYMBOL_EDITOR Symbol Editor does not remember the last size of the window9 m2 x' {8 d& n* s6 e, v
1773604 PCB_LIBRARIAN SYMBOL_EDITOR Option to switch between the new and legacy Symbol Editors% m8 l; M( K- F) l
1800354 PCB_LIBRARIAN SYMBOL_EDITOR Resistor has too many lines and looks wrong in new symbol editor
$ t. w, f" }% S( b( r" A1813346 PCB_LIBRARIAN SYMBOL_EDITOR Resistor looks different with multiple diagonal lines in new Symbol Editor but looks normal in DE-HDL
& h1 u; `2 }, k2 k5 S& M1815279 PCB_LIBRARIAN SYMBOL_EDITOR Unable to change Grid Settings from Lines to Dots
. \4 m6 @/ X: S& m# n1738603 PSPICE DIG_SIMULATOR Release 17.2-2016 PSpice digital model: Delay defined by PINDLY is not taken into account
" j% Q! z F" k( Z1 M4 P: e1802905 PSPICE ENCRYPTION Incorrect option shown in PSpiceENC syntax in usage detail
2 c5 N% t+ c) c [- x0 ~- I/ [' X1765345 PSPICE ENVIRONMENT Custom distributions are not added to the dropdown) i9 d1 U" G4 O" Q R' g
1784856 PSPICE ENVIRONMENT PSpice ignoring directory changes for Save check point in simulation setup session8 L( V7 x: F8 y, B. g$ d
1817805 PSPICE ENVIRONMENT Incorrect result for PSpice 'Start saving data after'
; d) ]8 V. k3 E9 {1784507 PSPICE FRONTENDPLUGI Spelling of 'Definition' in PSpice Part Search is not correct4 r6 f1 |8 V! Z' M
1801790 PSPICE LIBRARIES SAC model giving errors
$ Z" F I) D' p& R+ Q1738776 PSPICE SIMULATOR PSpice simulation stops before TSTOP
! o4 m. S6 ]4 x% W0 x6 t1795950 PSPICE SIMULATOR Simulation cannot be completed in release 17.2-2016 but is completed in release 16.65 }3 I- d9 Z' f" V1 `4 D w5 Y' b
1803407 PSPICE SIMULATOR Getting convergence error on a model
% W% n1 B' z, h5 s1814759 PSPICE SLPS .INC file is not working with SLPS; C; Y. w U3 m% q. u; a
1715859 SIP_LAYOUT ETCH_BACK Etchback mask not overlapping each other; creating floating metal
" P. x2 a- f/ A7 l5 g" j1729523 SIP_LAYOUT INTERACTIVE When creating a bond finger solder mask the results do not match the required settings1 O1 X% ^( V) h3 r
1800069 SIP_LAYOUT INTERACTIVE Corrupt dra/psm symbol, but the reason is unclear
b X% K( K1 t4 S1 w! m1756620 SIP_LAYOUT SHAPE Performance issue when moving vias.; v6 b8 O& f# V1 Z# ~ y
1782928 SIP_LAYOUT SHAPE Shape merging (logical operation) shows error though measuring shows elements are correctly spaced( p+ A& @1 |* K3 ?7 `2 @( Y* K# `
1816454 SIP_LAYOUT THIEVING Thieving: need thieving as a specific data type in CM to better control the filling pattern
+ s9 ?! ~1 d5 b. [3 ]1728026 TDA CORE Check-in should not require all child objects to be checked in specially if they are not checked-out4 L( }5 f# w* w, n( V& l
1823976 TDA SHAREPOINT Connection to server terminates when joining a project/ ] J% u* A6 ?+ T+ R
1 U8 Z: N8 _. G" r
2 I9 ^) P2 C- Q" ~
Fixed CCRs: SPB 17.2 HF030. h# W! e' K% [% K0 n
11-17-2017
; }' L- v2 t/ d Q========================================================================================================================================================1 {) p# A9 V) k' E3 e
CCRID Product ProductLevel2 Title1 }& O' Z2 D) r: B, x& @" q
========================================================================================================================================================
" z7 x- @6 z+ f/ A- @/ G4 I9 t; g- T1821774 ADW DBEDITOR MPN is tagged Pending Purge after deletion and lib_dist
) Z2 V0 @% m$ [. A! Z3 o, i& a1829549 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase DRC marker displayed at the design origin& k- Y) X3 a, i8 R S- K7 i
1690998 ALLEGRO_EDITOR INTERFACES Runtime error when running PDF Publisher: S9 _& X# z! w
1805203 ALLEGRO_EDITOR INTERFACES Runtime error when exporting smart PDF on a large board with all film layers selected
- K' A' B; X8 M1811698 ALLEGRO_EDITOR INTERFACES Runtime error while exporting PDF
- E" I4 R0 A0 `" v. G1823818 ALLEGRO_EDITOR INTERFACES Cannot map some step models
) d2 j) E% Q9 |5 h% p& Q: M' s4 Q1750654 ALLEGRO_EDITOR MANUFACT Cut marks cannot be generated on cut outline.; @7 t6 o' D; w( V9 w/ \
1828293 ALLEGRO_EDITOR NC Incorrect status returned for backdrill! ^, n5 r: {8 U+ i: a0 L
1825401 ALLEGRO_EDITOR PADS_IN In PADS library translation, pads_lib_in fails to create Placebound_Top as a shape! \! B1 K: [2 [# K
1825427 ALLEGRO_EDITOR PADS_IN Symbol drawing files (.dra) created after PADS Library translation are not getting renamed to their decals
! f9 B5 E8 \$ T2 g1825460 ALLEGRO_EDITOR PADS_IN Pins are moved from their correct locations during PADS Library Translation' Q! K! t$ {# g' G) _9 \0 O
1831200 ALLEGRO_EDITOR PLOTTING Incorrect PDF output for traces
3 [* H: r9 y. q$ L2 j1321314 ALLEGRO_EDITOR SHAPE Force update of dynamic shape generates thermal tie that causes net to short3 N% @6 A. d8 z: z# }$ q
1647585 ALLEGRO_EDITOR SHAPE Void around holes is not circular but of the shape of the bounding box1 Z* q: B& s$ E/ h: G
1830676 ALLEGRO_EDITOR SHAPE XHatch Shape not voiding properly3 p* [6 G5 f1 g
1821286 ALLEGRO_EDITOR SKILL Using axlSetParam to set static shape clearance parameter crashes PCB Editor
1 M3 Q( h' \0 C* g0 g' P1804662 ASDA DARK_THEME Dark Theme: Change color of selected cells in Rename signals dialog so user can see they are selected8 ], c/ I1 `3 Y2 D$ {0 q
1817486 ASDA NEW_PROJECT Need to save a project with a new name, 'copyprojectas' does not seem to work
6 V7 ]) Y/ R6 Y( h$ k' F1826023 ASDA NEW_PROJECT SDA requires user to go into project settings window twice to add a library( x. Z Q; y( [2 E/ n' O6 G
1830632 ASDA SCRIPTING SDA crashes when you type 'find -types' in the Tcl command window' J/ ~7 D& s& J7 w. E- G: Q
1798864 ASDA VARIANT_MANAG Retain default part visibility when substituting preferred part for variant
3 J0 r5 l7 ~! z$ G8 L: m1798865 ASDA VARIANT_MANAG Value attribute of variant is off while printing though on for default and view
: {5 [& f/ C) a! O' v0 x1798866 ASDA VARIANT_MANAG Variant Printing: Pin numbers printed though set to off on default part3 G' G# V# K: V; W7 R' |. U
1831836 ASDA VARIANT_MANAG Cannot delete existing variants in design
, z7 {2 }/ l/ N* }5 Y1821120 CONCEPT_HDL CORE SIGNAL_MODEL attached to a component is not displayed on the canvas in the Attributes form' K% f1 a b( R8 Y( h" R7 G
1824714 CONCEPT_HDL CORE Display issue: Page border disappears when running the command _movetogrid; u1 J4 [7 h& L/ c7 F8 o7 Y
1822587 CONCEPT_HDL CREFER CRefer crashes on a hierarchical design using split blocks
; h: q. V+ j3 O2 t1 }9 s3 e' h Q1825461 CONSTRAINT_MGR CONCEPT_HDL Uprevving to release 17.2-2016 adds NO_XNET_CONNECTIONS on components having custom models+ P' i5 B& ?/ t0 [
1825968 CONSTRAINT_MGR DATABASE cmxlGetObjects returns all the aliased nets and the physical net that goes to the netlist; ~+ R4 a y* A2 Q7 v9 x
1819622 CONSTRAINT_MGR XNET_DIFFPAIR Discrete with NO_XNET_CONNECTION removed from topology when extracted with Routed Interconnect
+ a( i0 Q" ^$ K! j# [6 g9 `5 u1829762 ECW PROJECT_MANAG Pulse log in: Multiple processes triggered, generating many zip file packets and corrupting many of the packets2 r$ O" D4 o/ r7 G+ Q2 x0 r% Y
1810296 F2B BOM BOM includes status column, nothing should ever be forced on a users BOM output
A" Y. l$ D3 [' Q. |+ v1824593 F2B PACKAGERXL PXL crashes and removes the pxl.log file from the Packaged directory
6 ?! I+ P* K1 t% ^1832005 F2B PACKAGERXL Message stating 'PXL has stopped working' when packaging design
1 N( _& t ^% h& e# k* r0 M; U" U1822912 RF_PCB AUTO_PLACE rf_autoplace fails for RF component containing variable
2 J b4 u7 b! ?: u8 D; A* Z1803731 SIP_LAYOUT DXF_IF DXF export from 'Component Geometry/Pin_Number' subclass not working in release 17.2-2016
. |+ R: r* x# N6 p5 |. s1825478 SIP_LAYOUT SHAPE When running the Shape Islands report it is listing all the Fillets as Islands& K3 j" A0 X) Q
G3 T' y: U: O- w- m
, ^* h8 a9 ]& H# b3 LFixed CCRs: SPB 17.2 HF029
9 q. p2 B: Q& Z- w8 P2 y11-3-20177 C( E+ x9 T8 m' _3 ?
========================================================================================================================================================
( B* V% U% `) {; OCCRID Product ProductLevel2 Title3 h, D1 P! x1 P' g" `+ Q
========================================================================================================================================================
6 v* l/ q9 l# ?, ~3 p1814597 ADW DBEDITOR Associate part classification is very slow in release 17.2-2016 of Allegro EDM
& M# s# d& p* M, [1733482 ADW FLOW_MGR After installing QIR3, Flow Manager prompts with Java Help question0 v5 ~ J) l, d5 K
1814789 ADW PART_BROWSER PTF shows data in old component browser but not new component browser
2 i5 b U, x" h' N7 I" B D1808620 ALLEGRO_EDITOR DFM Missing graphics in new drc browser.+ K8 W, h; \0 H3 X" m$ m. b' M0 P
1814558 ALLEGRO_EDITOR DFM Silkscreen checks do not work if silkscreen is defined as mask in cross section# ?, Y+ L( i9 N: i6 e7 H
1807996 ALLEGRO_EDITOR EDIT_ETCH Route Clearance View is not using the correct spacing constraint when nets are partially routed in a region. w0 a% g" `( H" ~8 A
1747929 ALLEGRO_EDITOR INTERFACES Cannot import logo/bmp on a .dra file
* b% |! ?0 }: N m1820142 ALLEGRO_EDITOR INTERFACES pdf_out command not supporting UNC paths for the output pdf file
! P' p T7 C6 M' }1671865 ALLEGRO_EDITOR MANUFACT Exceeding 20 characters in Artwork Control Form - General Parameters - Prefix displays 'Illegal Character(s)' error
@5 B0 F( q) Q6 {+ L1710032 ALLEGRO_EDITOR MANUFACT Adding Artwork prefix gives error for illegal characters
/ G' J/ `7 y8 r9 h( N2 |& Y1714911 ALLEGRO_EDITOR MANUFACT ERROR: 'illegal character(s) present in name or value' while adding prefix in Artwork Control Form
1 P T) c" ?# x7 u0 B* a! Y5 P1813950 ALLEGRO_EDITOR MANUFACT In the drill chart, the titles 'tolerance_drill' and 'tolerance_travel' seem to be reversed
* \+ N. T/ l& y1820970 ALLEGRO_EDITOR MANUFACT IDX_EXCLUDE and BOM_IGNORE excluding objects from IDX export
2 `' b Q+ k& b/ q9 l5 O* y1822045 ALLEGRO_EDITOR PARTITION Shape fillet becomes static shape and loses fillet attribute after importing partition+ s. l* l9 S0 p! G1 F
1776181 ALLEGRO_EDITOR SHAPE Placing via arrays around a differential pair places vias only for one net, s! Z5 J* n$ ^' F o4 f, e
1817283 ALLEGRO_EDITOR SHAPE Allegro PCB Editor Show Measure Air Gap shows a very large number# c4 N0 v# }1 ]0 R* N! i' B
1815595 APD DRC_CONSTRAIN Differential pair spacing constraint not propagating to physical cset nets* M7 X% f8 i" e7 M, \1 \
1785116 APD SHAPE Big size die performance issue
: S P2 o9 c% |, V8 i0 }1811134 APD STREAM_IF GDS stream out with 2000 precision has sharp edges along shapes./ H( b$ c1 i1 v2 r/ L- p, l
1811882 APD VIA_STRUCTURE High-speed via structure refresh fails. B9 n, I. o% @7 W3 i
1814878 ASDA DARK_THEME Part Manager: Difficult to read black text on black background
: F- R) }4 H( N, f$ J# e1 \1814889 ASDA DARK_THEME Change 'updating route in progress' message color: a bright orange bar in dark theme is difficult to read
: V, ^' h# @, @& `1817355 ASDA PAGE_MANAGEME Double-clicking a library in project preferences library does not move the library but changes appearance
7 _3 ]) N; o6 i0 S- B& n1817964 ASDA SHORTCUTS User Preferences shortcut misspelled
7 C" z: z4 h# a; D. }, U3 J1820247 CONCEPT_HDL CORE DE-HDL crashes while saving a design4 [( }8 F/ a L0 h. {1 x) X
1823187 CONCEPT_HDL CORE DEHDL allows editing of the locked component's refdes using change text editor
$ c/ H8 g- H" O) F- J1824052 CONCEPT_HDL CORE Trying to edit on a group containing a LOCK component, deletes the packaging data on the schematic/ g% a1 [7 b+ ^! i
1813987 CONSTRAINT_MGR OTHER PCB Editor crashes when Constraint Manager is closed; e' h- c" f& V7 c$ D
1821129 CONSTRAINT_MGR XNET_DIFFPAIR Uprev to release 17.2-2016 adds unwanted NO_XNET_CONNECTION property to discrete symbols6 y0 o b7 ~ s' J5 e% G
1814725 PSPICE PROBE PSpice Measurements crashes PSpice for a digital simulation
) _( Q& r! b v6 b. J3 t1808672 SIP_LAYOUT INTERACTIVE create bounding shape command options: 'Min Area' and 'Sync with shape layer'
# t1 ?6 J4 ^5 @! ^, G2 M8 I1817458 SIP_LAYOUT MANUFACTURING Error in DXF conversion after updating SiP Layout from Hotfix 066 to 082 in release 16.6
8 A9 F2 i. _% R* E& d) F0 I T1 i1 W- I9 {( O
3 z% K: v+ o0 a8 p8 ~
Fixed CCRs: SPB 17.2 HF028( H0 Q0 |! o" A0 k( ^) o$ c
10-14-2017 y) E/ G9 G( Z: n1 i
========================================================================================================================================================
~: H4 k: _' [4 i+ y! iCCRID Product ProductLevel2 Title! B2 D1 I0 D1 r- Q' {- V: |
========================================================================================================================================================
* S) W9 E b. g3 }& u5 |1773530 ADW FLOW_MGR DE-HDL hangs on importing components from another design or copying and pasting components within a design
9 \4 }/ v5 b0 R1790584 ADW FLOW_MGR SKILL code for comparing two PCB Editor .brd files does not work in EDM in release 17.2-2016# D& c" W, b3 G; T- \$ H6 A! L5 p
1794116 ADW FLOW_MGR LRM fails to run on project ^" z9 S4 @" T) l
1811532 ADW FLOW_MGR The message for missing tools.jar should not appear in adwcopyproject.log
) ~( q' \" h: n" D1 l2 l$ u1812109 ADW LRM Library revision manager displays errors while re-importing updated sub-blocks# C! V) A3 o. h
1771851 ADW PCBCACHE Problem in packaging upreved imported block
) z# l& q% z! ]7 u# [3 e1814785 ALLEGRO_EDITOR 3D_CANVAS PCB Editor crashes when a bend is created and then viewed in 3D Viewer+ h3 C; x& L9 `
1800131 ALLEGRO_EDITOR DATABASE allegro_downrev_library utility fails on Windows 10
8 w0 m7 u$ o5 M1 V6 }9 S) `9 E1814607 ALLEGRO_EDITOR DFM DFM check for soldermask does not include Package Geometry/ Soldermask if the soldermask is part of stackup# C& i' n* c% F* Q
1813996 ALLEGRO_EDITOR EDIT_ETCH Add Connect crashes PCB Editor if clearance view is set to channel
5 `$ Q* n- V+ j% D/ x1810832 ALLEGRO_EDITOR SCHEM_FTB Error while doing Export Physical from DE-HDL to PCB Editor
8 {2 w' Y6 |3 u- K2 w+ }2 A1811785 ALLEGRO_EDITOR SCHEM_FTB Import > Logic > Import Directory does not resolve the relative path to the packaged folder
" U* a" k+ k% c, j+ Z- q1814166 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version of database9 n' Z# C/ W3 e- [ G- v( V) t0 R/ |
1817891 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version0 C2 K' q7 }0 Q! j* P
1818954 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version of database
0 K% o/ b0 j+ D1812808 ALLEGRO_EDITOR SHAPE Artwork is different from PCB board$ t, T0 w. f6 O4 l( g# [; \3 o
1814836 ALLEGRO_EDITOR SKILL Doing zcopy Xhatch pattern crashes PCB Editor in release 17.2-2016( _4 } u( |$ m6 \
1772218 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding on Show Element
- Z- Y1 A& |; P# N( q: V1778353 ALLEGRO_EDITOR UI_GENERAL Intermittent PCB Editor crashes on loading IDX in release 17.2-2016 Hotfix 020
% W: p6 Q [4 T, ~ d" n; D1818077 ALLEGRO_EDITOR UI_GENERAL axlViewFileCreate disappears behind window or is blank; c- p+ H0 M) u& `* ^& N6 l
1807423 ASDA NEW_PROJECT SDA CPM file has erroneous date
! n* g- @; n" m# h# [ S1809597 CONCEPT_HDL CORE Problem auditing SI model in Allegro Design Entry HDL from Hotfix 025 onward, no problem in Hotfix 024
/ E) k: C8 z6 ~3 s9 W6 j4 f# j1810322 CONCEPT_HDL CORE Unable to package design if OK_NET_ONE_PIN property is set' @4 U; I; k5 ~# Q" E/ q
1813436 CONCEPT_HDL CORE Read-only block import issue in same session: displays error message SPCOCD-5533 P$ z3 N9 N& p/ ~
1813912 CONCEPT_HDL CORE The response in DE-HDL is sometimes extremely slow5 w: n" A7 w1 ], n. W% R
1812506 CONCEPT_HDL INTERFACE_DES Error messages during packaging followed by a success message though there are errors in design/ k% P% a/ c6 T% B- J* Y0 J4 }; ]
1808677 CONSTRAINT_MGR CONCEPT_HDL Auto-generation of differential pair finds several instances of the same net6 p4 E9 _0 t( H1 h8 S6 r
1808898 CONSTRAINT_MGR CONCEPT_HDL Unable to resolve the ECSet mapping errors if the topology has pin of PINUSE POWER & GROUND
- o+ q. [% }; ~* I6 t1810320 CONSTRAINT_MGR CONCEPT_HDL DE-HDL - Constraint Manager: Cannot add group to net class if a net in group is a member of the net class, c% h* z+ P6 L$ Z& p2 u
1812459 CONSTRAINT_MGR CONCEPT_HDL Auto-generation of differential pairs has issues
o! z) S& i) t/ n1796234 CONSTRAINT_MGR OTHER PCB Editor crashes on query (ALLOW_ON_ETCH_SUBCLASS) without data type defined
/ X2 T& G3 {; O1 e* J5 d1811692 CONSTRAINT_MGR OTHER Constraint Manager: Set Topology Constraints - Rel Prop Delay - Pins is empty in release 17.2-2016 Hotfix 026
. e" C2 K3 W$ x; y1816311 CONSTRAINT_MGR XNET_DIFFPAIR Extracting a differential pair into SigXplorer crashes DE-HDL" l9 T# `) n8 [) h. [* m! O
1807593 ORBITIO ALLEGRO_SIP_I Die symbol shifts when importing die from OrbitIO to SiP Layout; O8 C2 ^8 j7 _5 a/ H( g1 Z& K/ T
1800763 PSPICE SLPS Error while running co-simulation in MATLAB for PSpice-SLPS demo designs
9 I$ m# d3 G0 [1 W' `7 {
- R0 @0 h/ M' }1 y" f* w. H8 K
: t& _* p0 s$ \Fixed CCRs: SPB 17.2 HF027
/ t% E; B; X- U; r! P) c09-29-2017" k' U4 y7 r* X6 U
========================================================================================================================================================1 j+ D" O- X2 Z& k
CCRID Product ProductLevel2 Title
" ?. W J) q, X6 j( Z0 Y2 l' ]+ w========================================================================================================================================================5 D/ C5 \+ w4 n9 |6 ~
1795353 ADW FLOW_MGR Tool unable to find project in windows_project.txt* _# m, Z5 N- w6 w) a
1810386 ADW FLOW_MGR Error regarding not finding project in 'windows_project.txt'
9 w1 q t) K* [8 H3 _5 ~) e E B1743732 ADW LIBDISTRIBUTI adwserver -install does not give error if it cannot connect to server.1 `7 O% B1 @5 _" F9 F& q
1804378 ALLEGRO_EDITOR 3D_CANVAS Bend area issues in 3D Viewer5 q* I" [) ~/ ^. g7 r1 U
1795312 ALLEGRO_EDITOR DATABASE Cannot unlock symbols as status is changed to View on opening design
, }; @/ ^. c. q; G( w( |1803262 ALLEGRO_EDITOR DATABASE Donut pad With DYN_THERMAL_CON set to FULL_CONTACT has connectivity issues
: A6 Q. g$ ^: U; G3 Z N1 R& l+ X1802183 ALLEGRO_EDITOR DFM Using mouse wheel to scroll error information in DRC Browser changes font size( Z3 s/ {/ i4 X! r+ h, N1 R" \
1797222 ALLEGRO_EDITOR DRC_CONSTR Updating DRC results in error 'SPMHDB-403'
' L) A% B; z) q( }% D- s1792163 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on moving components# N3 f% j1 [# G
1806640 ALLEGRO_EDITOR INTERFACES Step Mapping not working in release 17.2-2016 Hotfix 025" o# o5 G& `0 [, R5 x3 Y6 u8 |
1807278 ALLEGRO_EDITOR INTERFACES Running 'step_export_product_asm.exe' displays 'vcruntime140.dll' missing error' v$ N5 T: a% h, _! r
1807286 ALLEGRO_EDITOR INTERFACES The facet file (.xml) for the STEP model 'modelname.step' cannot be found.% W! Y* V% T1 H2 X2 d, ?
1808006 ALLEGRO_EDITOR INTERFACES Facet file for step model cannot be found; ?7 n$ p1 ^" u0 q1 l; ?' h7 z9 I
1704335 ALLEGRO_EDITOR MANUFACT Documentation Editor shows an error about backdrill while no backdrill was used in the design
3 @1 z+ g: S7 B% U1800115 ALLEGRO_EDITOR MANUFACT IPC2581 Export giving error that backdrill is out of date even though no backdrill is defined in the design1 y4 r# m% a$ L1 ] n
1799444 ALLEGRO_EDITOR PLACEMENT Via Array - Boundary placement fails with error
& s9 g% R' j/ A' m9 W1725242 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
( a- z3 l) U& H1804129 ALLEGRO_EDITOR SHAPE XHatch Shape not voiding properly" B$ F p: C0 }( r% I1 k
1805238 ALLEGRO_EDITOR SHAPE PCB Editor crashes while importing netlist6 m! H8 p7 X( X1 }! V
1803542 ALLEGRO_EDITOR SKILL Using axlPadstackEdit to change drill size causes via net to change in release 17.2-2016 Hotfix 025' F3 v Y6 v9 w8 w1 S
1800774 APD STREAM_IF Only one pad in GDSII when running 'stream out' with the Flatten Geometry option, R; b2 J* T) i; P9 O
1804196 APD STREAM_IF Component is mirrored by X-axis instead of Y-axis on enabling mirror geometry! {: E1 E( n! s; H* W n
1803375 ASDA IMPORT_BLOCK Import HDL Block fails with message regarding Xnet states and DML independence
, Y, ^. V6 x2 |; C# ~1807423 ASDA NEW_PROJECT SDA CPM file has erroneous date/ R+ c+ Y3 E3 r- @7 M$ V# z; m
1789400 CAPTURE SCHEMATIC_EDI Capture schematic opens unannotated pages on search
" }, g$ V7 U" a+ C. X) b8 u1801573 CONCEPT_HDL CONSTRAINT_MG Upreving release 16.6 design to 17.2-2016 adds NO_XNET_CONNECTION to some components6 x" P4 w5 V1 Z+ E
1810586 CONCEPT_HDL CONSTRAINT_MG DE-HDL crashes when transferring XNET properties to similar components in a read-only block( [' s/ u' E7 [6 U" t$ B
1794169 CONCEPT_HDL CORE _automodel command crashes DE-HDL if PACK_IGNORE is set: W: r( p/ c2 u* \
1798672 CONCEPT_HDL CORE Dashes in design name creates an extra design folder in worklib after upreving to release 17.2-20163 [# h( L! N3 B& _9 I8 ]) c/ i
1802258 CONCEPT_HDL CORE Locking unlocked components results in a warning (SPCOCN-3403); ^. N$ w5 {5 M' Q6 M% p: K
1803019 CONCEPT_HDL CORE DE-HDL crashes on backannotation
6 C V5 q! x& Y V' z$ _1803615 CONCEPT_HDL CORE After running 'Mark for Variant', the block cannot be changed to blue3 }1 i" j8 ]" `+ x5 E, a, l/ M6 W
1804029 CONCEPT_HDL CORE Visibility issues when using the LOCK functionality
" \/ J; W* N) T- s! C$ R1806352 CONCEPT_HDL CORE Group Mirror is causing design corruption.6 _& D- n( [( o' }
1806978 CONCEPT_HDL CORE Cannot mirror a group of objects7 _0 E; ?$ P5 u# _9 d
1810387 CONCEPT_HDL CORE Mirroring groups causes erratic display and may corrupt database if project is saved
+ P8 L0 n+ X, [7 g1812811 CONCEPT_HDL CORE Schematic group mirror not working
1 C& N7 t* Z- |) y: c1810401 CONCEPT_HDL INFRA Add Signal Name: Cannot select suggested net name
( _& _ f6 O5 y1 ^2 f1787409 CONCEPT_HDL PDF Minus character at the end of netname causes unexpected string concatenation during PDF Publish) C0 W* e6 ^& C& z7 D
1800931 CONSTRAINT_MGR OTHER Even after removing NO_XNET_CONNECTION on parallel termination, topology extracted has duplicate capacitors
8 P6 z6 d/ g! f1790106 CONSTRAINT_MGR SCM Cannot find the constraints file (0) in the schematic project
3 B. \2 N( }2 B" \, n! M, f1787117 CONSTRAINT_MGR UI_FORMS Creating bundle in Constraint Manager crashes PCB Editor( j F3 x0 K c F
1797384 ECW METRICS Pop-up metrics value tool tip is translucent, making values hard/impossible to read+ [; g; `9 t) F2 D- X, X8 F% [
1803226 ECW METRICS Pop-up metrics value tool tip is translucent, making values hard/impossible to read
0 J% \8 m/ _. \, I1664059 ORBITIO ALLEGRO_SIP_I Incorrect connectivity after .brd import9 ?8 r3 u6 V/ e
1799338 SIP_LAYOUT DRC_CONSTRAIN Multi-threaded DRC fails with internal memory error even after setting shape_cache_size* E- P2 ?6 v) h- N" Z
1799499 SIP_LAYOUT DRC_CONSTRAIN Multi-thread DRC fails
+ n1 `3 H/ U" m5 y/ R J, |1806585 SIP_LAYOUT DRC_CONSTRAIN Multi-threaded DRC update aborted: internal memory resource depleted7 i2 T# |6 B5 A' @' r7 {: n7 I( e
1809804 SIP_LAYOUT DRC_CONSTRAIN Error message while updating DRCs in release 17.2-2016 Hotfix 026 regarding shape_cache_size
1 n8 I; T$ \# a' w* f& e3 q0 Y1788770 XTRACTIM ENG Translated bump / ball conductivity is wrong (PowerDC and XtractIM)
+ T9 p- O b- s; G# X3 X, l9 F+ b2 z) n& Q. Q
' S# o( I6 `5 y; {- _
Fixed CCRs: SPB 17.2 HF026( A+ k0 z% b7 c7 Z9 g. k
09-15-2017; {) i7 }* q6 M
========================================================================================================================================================$ G0 ?* e, r2 t
CCRID Product ProductLevel2 Title
. {. \/ j- v6 s$ q8 Y========================================================================================================================================================
2 ~8 i+ |6 H9 v6 @4 }7 b1765398 ADW DATAEXCHANGE Duplicate MPNs are created when updating MPN classification properties with data exchange
2 v& {6 \5 F4 {1780147 ADW DBEDITOR 'Associate Footprint from Tree' does not log the information9 i" o, }* y2 l" y, }, \( E2 r
1790134 ALLEGRO_EDITOR DATABASE Correct spelling in Layer Function definition
/ D8 W, i) U2 u, ~1792345 ALLEGRO_EDITOR DATABASE Pastemask is added to bottom layer on backdrilled pins
* U+ c+ D6 c- W% Z& q0 o$ q1792930 ALLEGRO_EDITOR DATABASE Uprev required for all libraries and padstacks to use release 16.6 DRA in release 17.2-2016! A8 r% d3 u8 y* J" K1 V8 \
1781203 ALLEGRO_EDITOR DFA DFA Spreadsheet Editor not starting from Windows Start menu" F" H9 v! I, w+ ~: [. X# G
1797422 ALLEGRO_EDITOR DFA DFA Spreadsheet Editor not starting from Windows Start menu5 ^# J! @" T4 r* R% y
1770694 ALLEGRO_EDITOR INTERFACES Incremental IDX does not place unplaced components
% |- s: V4 K6 w- j1776791 ALLEGRO_EDITOR INTERFACES STEP file not displayed in PCB Editor for mapping
, a. t) N% B! H3 ^1783515 ALLEGRO_EDITOR INTERFACES PCB Editor reading step model incorrectly% `8 D' J! W% i! s! H, N+ G2 \
1781485 ALLEGRO_EDITOR MANUFACT Setting ipc2581attrpath results in error 'E- ipc2581attrpath: Variable not defined'# U5 u2 j; ^( o# A( \9 I
1772713 ALLEGRO_EDITOR MULTI_USER Allegro Symphony Server rejects group moves6 r3 v+ I6 x4 A7 @8 N
1789853 ALLEGRO_EDITOR MULTI_USER Symphony Server rejects updates and hangs frequently
8 y4 [( L: q& G) k- c k7 U& R1725591 ALLEGRO_EDITOR OTHER File - Export PDF crashes on the design attached4 ?1 o( v6 Y- C5 E2 j
1736324 ALLEGRO_EDITOR OTHER Export - PDF fails to export PDF; R/ G2 c9 J1 m0 L, n1 M/ a
1794071 ALLEGRO_EDITOR PLACEMENT The placement of component is very slow and takes around 3 to 5 minutes per component.# c6 ?5 q$ _" I5 L$ F1 g; G: l# |; p7 q2 n
1496199 ALLEGRO_EDITOR SHAPE Overlapping route keepouts result in a broken shape.
' g6 b, }; S6 h; }5 Y, y& }. \1760146 ALLEGRO_EDITOR SHAPE Void offset in Artwork but not in board for a particular instance only
, U! X, p9 z( }6 N8 E$ b' T1770372 ALLEGRO_EDITOR SHAPE Overlapping shapes merged in artwork shifts void causing a manufacturing short
4 d4 `- s* U/ a- }1793419 ALLEGRO_EDITOR SHAPE Unexpected shape void in artwork in release 16.6
- B/ K! D# k" S- C2 i1796666 ALLEGRO_EDITOR SHAPE DRCs for out-of-date shape while placing single via% D/ O( Y4 ^2 v: T' k
1786386 APD EXPORT_DATA Exported dra and pad files do not have right stackup
2 C$ ^+ v: S& F, g, a+ E4 ^: }- d1765673 APD SHAPE Shape in Cu1 and Cu3 cannot void correctly3 @- {$ `: L# C. O
1782418 APD SHAPE Artwork is showing unnecessary horizontal lines
% f/ F$ T, E) }5 Q- L4 r! Q1778366 CONCEPT_HDL CHECKPLUS CheckPlus not printing logic design name+ G- R5 G, j: ]7 N3 [. _) Q
1723855 CONCEPT_HDL CORE Cannot use Rename Signal for unnamed wire segment if the wire has a branch to the same instance
9 u& I) v# }- b) o# E. c: u1755174 CONCEPT_HDL CORE Unable to create XNETs on the read-only blocks
' ]0 d4 S" n& l; M1765533 CONCEPT_HDL CORE Strokes are slow to respond in release 17.2-2016
# H: H- a( f+ }1780253 CONCEPT_HDL CORE In Windows mode, with copy command still active and symbol on cursor, DE-HDL stops responding on pressing Delete key
( G; n6 Q8 `6 d4 |+ F1785069 CONCEPT_HDL CORE Warning box for SPCOCN-2251 needs to be resized and the text formatted correctly
. J# z+ h$ B& u7 M" p2 Z1786030 CONCEPT_HDL CORE Packager fails in release 16.6 but runs successfully in release 17.2-2016+ k$ r8 K" M7 B2 [- R9 [% q
1788077 CONCEPT_HDL CORE Creating new window (new tab) in DE-HDL resets view of original window2 a8 i) Z R$ u2 w
1788591 CONCEPT_HDL CORE Wrong pin number displayed after running packager' d( ^7 g$ U! D
1776774 CONCEPT_HDL CREFER CRefer crashes without error entry in log file
; s! s' k. W/ T8 w; `1328320 CONCEPT_HDL PDF Cannot select/search sig_name in published PDF
" B; z7 E4 z9 a% S& q* E1787409 CONCEPT_HDL PDF Minus character at the end of netname causes unexpected string concatenation during PDF Publish6 S6 h7 D4 l4 M- L: U. P
1758122 CONSTRAINT_MGR ANALYSIS Extracted topology for a differential pair is missing a pin-to-pin connection in the top file
; [2 m, _. n) k5 F: u- y1786161 CONSTRAINT_MGR CONCEPT_HDL Random crashes in release 17.2-2016 while working on the schematic editor along with Constraint Manager1 T+ v. |: A; R; _$ o
1788877 CONSTRAINT_MGR DATABASE Constraint Manager API cmxlImportFile looks for sub-string during replace mode and not explicit names, J! K% R2 O: p
1800263 CONSTRAINT_MGR OTHER DE-HDL and CM crash when deleting regions
- M$ ~$ ~8 i# x6 a% l# n1792000 CONSTRAINT_MGR UI_FORMS Data type of constraint not shown in GUI
+ ], F1 Y+ c" _$ R! _1744828 FSP CAPTURE_SCHEM Button appears during 'Generate OrCAD Schematics'0 T5 O# O0 t+ w, \
1747568 ORBITIO OTHER Import of .oio file in SiP Layout takes a long time
/ b$ k# ~( d0 r0 ]" |! E8 X, u1 t. _1765229 PSPICE AA_FLOW Not able to run PSpice MC after setting Assign Tolerance' {2 g" y% u" ]5 n; z" ^! G% [
1770174 PSPICE MISC Issues with DMI Template Code Generator
! w0 I, B- k9 ]6 G2 r1 F
9 b0 n1 E7 o: b; Y6 F9 J {8 p( D' }" X3 v1 P! O+ U, _+ i
Fixed CCRs: SPB 17.2 HF0259 \8 U" V& r y& ` A# z
08-25-2017
; ^! q) f* g. L2 w========================================================================================================================================================6 i) A9 t: Y$ a" x
CCRID Product ProductLevel2 Title
* w& J9 S: E6 T Y! Z0 u& c========================================================================================================================================================
1 I2 `. S. ?" u4 `2 Y* y) `+ C# F1258913 ADW ADWSERVER Copy project message: Unable to locate tools.jar
; |2 q( c. W# }( k" u/ A$ b6 t1760866 ADW ADWSERVER Metrics dashboard in Allegro EDM Configuration Manager does not show updated SPB 17.2 hotfix
- I* z' v; E$ D: Z- ~1055946 ADW ADW_UPREV Set PTF_SUBTYPE SEARCHABLE to false and default value to exclamation mark
* R" ~* n/ |/ A# f( m# S/ M1508163 ADW COMPONENT_BRO Manufacturers Part tab disappears on clicking anything other than the part number in the left tree4 z# C% n z: a, k, x: {
1774164 ADW COMPONENT_BRO In release 17.2-2016 Hotfix 22, DE-HDL crashes on using Generate View6 C; ~" I4 O0 ?; ~2 x1 W
1345018 ADW DBEDITOR Database Editor does not catch empty mandatory properties if no changes are made to the part
4 F1 ?$ p# _, V4 K3 d! S t1586858 ADW DBEDITOR 'Access Denied' Error while opening Datasheet Model using Launch Viewer in Database Editor c0 X; A( m' q; m. ?$ Q5 [1 ?
1754185 ADW DBEDITOR Max Height value in DBEditor is different from PCB Editor- @( X* ]& p+ F# R
1719260 ADW FLOW_MGR Configuration error on a fresh install of EDM in release 17.2-2016 Hotfix 014
) y" {: |/ ?1 \, C1743730 ADW LIBDISTRIBUTI .lis file error in install_model while using MLR." P4 a0 y; D' `/ T; l" n1 I
1757178 ADW LIBIMPORT back-end libimport failed, crash and existing flashmodel not found
4 D" A1 h' G5 I/ o# B1648609 ADW SRM PCB Editor stops responding when launched with -s option in release 16.6-2015 Hotfix 078
- O& W. [' i, Q }1731152 ADW TDA TDO coredumps after a new object has been checked in as minor and deleted.
$ K' h: S- n/ R7 \1766998 ADW TDA TDO-ASA: Cannot enable the project for team design until a component is added to the new ASA/SCM design
9 Q( B% E/ [$ j& _' n1695240 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D View of a package symbol not showing the correct mapped STEP file attached to the package symbol: x U+ U" ~9 a9 A$ n6 C
1698148 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Viewer crashes on Windows 10
# G7 c! ]8 n( Q# T1738655 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas crashes on Windows 10
4 ^+ C+ a. d: s' M! D: X1 P1750001 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D Canvas crashes on selecting in symbol view) b% r: x: ` D8 [7 q3 P
1751796 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas shows component placed at wrong layer for Embedded components3 S: \ N- q4 I( i% W
1768775 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D canvas closes when Update Symbol is done and cannot be re-invoked& X, ~# O! l& V& S
1695025 ALLEGRO_EDITOR ARTWORK Artwork film show shorts.. g7 G' X4 j6 Y' e
1708674 ALLEGRO_EDITOR COLOR Dehighlight all should disable the check boxes in the color dialog/nets/ w( O' Q1 E5 y" O) F4 V, Q% Z% Q
1735522 ALLEGRO_EDITOR COLOR In release 17.2-2016, PCB Editor crashes when not being able to write the CVSettings.xml file.
9 S1 d9 |! e9 }% V( c8 W1764475 ALLEGRO_EDITOR COLOR Allegro PCB Editor hangs when selecting OK on the Color Dialog form
( C! o# `" i" n+ W! X: ^1718438 ALLEGRO_EDITOR CROSS_SECTION User interface is inconsistent for the Mask Layer Subclass site file editor.
7 a3 d+ l; p# y g! g R' o. R1765387 ALLEGRO_EDITOR CROSS_SECTION Cross Section Editor does not retain or remove layers added/removed from Setup-->Subclasses S1 N! y* Q4 y6 M4 F
1714910 ALLEGRO_EDITOR DATABASE PCB Editor crashes with blank allegro.jrl file when a release 16.6 board is opened in release 17.2-2016 Hotfix 013
' R a b1 ? N8 O1769534 ALLEGRO_EDITOR DATABASE DBDoctor unable to delete invalid subclass6 n- ]+ L% X ?7 S1 B
1775705 ALLEGRO_EDITOR DATABASE Updating stackup in PCB Editor does not change backdrill status to 'Out-of-Date backdrills'; N8 g, W1 l s' E% }8 i5 T
1778608 ALLEGRO_EDITOR DATABASE Rigid Flex design: Components with pads defined on the TOP and BOTTOM layers are not placed on the correct layer3 W/ c% S* C; u: L" O: o6 {
1778644 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes while trying to place dimensions$ @* a# b: J- ^& z& @
1698695 ALLEGRO_EDITOR DRC_CONSTR Line to Mech-Pin DRC not displayed
* d0 j. V& N2 r2 u/ ` |3 d5 _1705214 ALLEGRO_EDITOR DRC_CONSTR Shape to drill DRCs not getting void and 'cns_show' does not report constraint value
( ^# V6 M' q9 B5 d- g+ {2 Y% o1722841 ALLEGRO_EDITOR DRC_CONSTR Inconsistent soldermask to soldermask DRCs on vias as compared to board geometry/soldermask$ u4 b1 b$ t+ \5 j. L
1736116 ALLEGRO_EDITOR DRC_CONSTR Shape Voiding and DRC error on layer with no hole or pad definition1 i3 H5 o5 G+ s6 ?# A
1744248 ALLEGRO_EDITOR DRC_CONSTR Release 16.6 to 17.2-2016 DML Independent Flow does not resolve differential pair pin pairs Correctly
+ \7 o; Q8 D1 A u; j1776848 ALLEGRO_EDITOR DRC_CONSTR Negative plane island DRC reported in release 17.2-2016 Hotfix 23/ d& c n) N; C( m/ o) b' S, w
1730806 ALLEGRO_EDITOR EDIT_ETCH Element 'vias_allowed' is not valid for content model adding high speed via structures
9 S9 S8 j5 U7 Z3 }* u, i3 S- F1745332 ALLEGRO_EDITOR EDIT_ETCH In release 17.2-2016, PCB Editor crashes when starting Add ZigZag Pattern% t* g( Q3 ~1 n: N+ \
1765555 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes during contour routing7 F/ {, d; r4 R8 f
1644401 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes on running the z-copy command
0 l3 X& U9 U; F! [1657621 ALLEGRO_EDITOR INTERACTIV Copy cline and via cause redundant vias
+ z) _8 b* w2 o# m9 G1688556 ALLEGRO_EDITOR INTERACTIV Limitations with editpad boundary5 r* e5 P# Y- c* ~! s
1704901 ALLEGRO_EDITOR INTERACTIV Changes cannot be done when 'Design outline' is selected
) W$ E. ]: C" r3 `' ?1710731 ALLEGRO_EDITOR INTERACTIV The Edit > Change command does not select or change the text on a block
5 L) ?% N J5 y* y1714855 ALLEGRO_EDITOR INTERACTIV Placing two objects on the Design_Outline subclass causes PCB Editor to crash* x/ V. ]( @; C9 F5 G+ p7 L
1725736 ALLEGRO_EDITOR INTERACTIV Edit>Change cannot change silkscreen line to a different class, but works in preselect mode }4 N! B5 E: x% @
1728004 ALLEGRO_EDITOR INTERACTIV Text cannot be edited if the Design_Outline subclass is in the selection box
" p! v9 D& o% p: f' w+ i1728794 ALLEGRO_EDITOR INTERACTIV The Oops command and the Esc key do not work when moving components in the Temp Group mode% o+ v; e. k; K; O0 L, f
1738070 ALLEGRO_EDITOR INTERACTIV Copying shape after Shape Operations results in error 'E- (SPMHDB-72): Current active shape must be filled first'
+ X$ H* h0 [) Z/ w, E1750696 ALLEGRO_EDITOR INTERACTIV Add notch angle option fails to update if changed while add notch command is active.
1 E" J/ |* e4 q$ @) [: O2 L9 S1755240 ALLEGRO_EDITOR INTERACTIV Copy via does not work
6 i+ q5 L8 `: c7 |1777416 ALLEGRO_EDITOR INTERACTIV Running shape operations results in database corruption
7 P- N, T, Q2 N* v! M1715835 ALLEGRO_EDITOR INTERFACES When IDX is imported in PCB Editor, all the shapes are created on package keepout on all subclasses
# P1 V! I4 Y# h2 R+ ~( m+ o1744111 ALLEGRO_EDITOR INTERFACES Pads rotating 90 degree when exporting DXF file from Allegro PCB Editor1 V7 b; D0 N$ Q3 C5 L' _
1736045 ALLEGRO_EDITOR MENTOR Third-party import crashes PCB Editor with error stating that .SAV file will be created
! f" z! D% p- G, [: m1751914 ALLEGRO_EDITOR MULTI_USER Find Filter options get disabled while creating symbols
5 t# G9 T+ o/ @- m( ~/ j0 ~( [1770811 ALLEGRO_EDITOR MULTI_USER In release 17.2-2016, axlTriggerSet('exit 'routine) causes a crash while exiting& @% `- ~- U% {% U
1736545 ALLEGRO_EDITOR OTHER Spelling mistake in description of no_dynamic_zoom variable in user preferences Editor/ e& K* }7 h, g( O, p
1761610 ALLEGRO_EDITOR OTHER Dynamic shape is not voiding as expected. U: j3 \2 O9 s4 U3 h( J
1702535 ALLEGRO_EDITOR PAD_EDITOR After modifying a padstack in Pad_Editor, the Update to Design function fails to update the dra file
' E" @: ~* m: n$ g9 ^1 t; @1713461 ALLEGRO_EDITOR PAD_EDITOR Padstack editor default geometry not working when cell is preselected
7 f" h4 W# ` [# `5 q n4 p: K1715702 ALLEGRO_EDITOR PAD_EDITOR Donut shape is lost on cutting the pad shape of the donut pad
% d1 M( l& Y# W' a5 u# G( g1720300 ALLEGRO_EDITOR PAD_EDITOR Multi-drill staggered pattern: Different hole placement for first and second rows for releases 16.6 and 17.2-2016
/ {7 ~" u# q9 t$ l1724896 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor shows flash symbol for regular pad on selecting 'Shape Symbol'/ k- d* c7 X* I, x
1714839 ALLEGRO_EDITOR PLACEMENT Selecting an alternate symbol (alt_symbol) in a group, in the Placement Edit mode, removes the symbol from the group
( t7 j' v3 I+ @) Q1781502 ALLEGRO_EDITOR PLACEMENT Quickplace by room crashes Allegro PCB Editor
7 p# f: s, e# |) p. L" c6 l! n1699690 ALLEGRO_EDITOR SCHEM_FTB 'view_pcb directive' no longer working as expected
) V" v7 V& i7 g) K8 j& w7 w! M1758796 ALLEGRO_EDITOR SCHEM_FTB PCB Editor launched from Project Manager does not read the relative paths specified in the view_pcb directive" t: n0 _1 e; s2 m+ c( P1 o/ |" o3 R
1761101 ALLEGRO_EDITOR SCHEM_FTB On saving a board after import logic in PCB Editor, the file is saved in the cpm location and not in the physical folder
+ Z; @& R5 X, `2 ^4 @6 ]6 Y1761394 ALLEGRO_EDITOR SCHEM_FTB Working directory for PCB Editor changes after import logic
$ g# T0 \0 n) U3 l" }0 |1 c1714922 ALLEGRO_EDITOR SCRIPTS Running script in the non-graphic mode runs the tool graphically
4 ~- h v; q2 P1726550 ALLEGRO_EDITOR SHAPE Shape failed to connect to pin
- [/ ]( P: F; g1 F5 w1754945 ALLEGRO_EDITOR SHAPE In release 17.2-2016, Delete islands fails to add DYN_DELETED_ISLAND to voids on Windows 10 systems
+ Z$ U, Z7 b3 X- V5 P u3 F1766280 ALLEGRO_EDITOR SHAPE SPMHGE-300 Polygon operation failed because of an internal error
2 m G9 L R: }1 R) w [1768307 ALLEGRO_EDITOR TECHFILE Properties defined in the technology files are not being imported in a new design
' I3 A- ]$ A/ H/ p, w! @1771584 ALLEGRO_EDITOR TECHFILE The tech file import command does not update user-defined property immediately w! p- U4 t8 e3 {8 D1 Y
1730104 ALLEGRO_EDITOR UI_FORMS Change description of Title bar option variables in User Preferences( d3 \$ p2 L. P' }: ?
1749272 ALLEGRO_EDITOR UI_FORMS etchlen_ignore_pinvia variable needs to be updated
$ Y, M( e0 [" ~5 j0 [+ T7 X) m2 B1649254 ALLEGRO_EDITOR UI_GENERAL Using wildcard to open padstack file generates error SPMHA1-161 in Padstack Editor in release 17.2-2016
4 A) K) D" P. c4 O8 L: a' t/ D1685985 ALLEGRO_EDITOR UI_GENERAL Funckey not working for Display - Measure
4 w: R1 T6 @& E$ x4 w1 h; l1687073 ALLEGRO_EDITOR UI_GENERAL Show Measure command shifts focus to Search field in result window after selecting first element& H3 c1 q* U0 b9 X
1699272 ALLEGRO_EDITOR UI_GENERAL File Viewer not displaying HTML files correctly when 'allegro_html_qt' is enabled6 i) k% o7 b" f& r& T/ @/ T9 \
1711321 ALLEGRO_EDITOR UI_GENERAL Database settings do not change on changing color settings using the SKILL function axlDBDisplayControl()- P; Q( U( @: r- Z( j
1728468 ALLEGRO_EDITOR UI_GENERAL The Show Element window takes the focus away from the PCB Editor window
9 s8 ^- ~5 ? K& W. d1733690 ALLEGRO_EDITOR UI_GENERAL Performance issues in Visibility dialog if called repeatedly in release 17.2-2016, Hotfix 0175 D _; S4 Q+ n2 B0 |
1734176 ALLEGRO_EDITOR UI_GENERAL Unable to sort padstacks to open in the padstack editor using wildcards
1 M+ M6 J4 o1 g" P8 y1735733 ALLEGRO_EDITOR UI_GENERAL RAVEL checks slower in release 17.2-2016, Hotfix 017
. Z. w" U" M2 U' ^: J# w1737545 ALLEGRO_EDITOR UI_GENERAL axlVisibleSet is slower in release 17.2-2016+ S# a r6 p# P1 U
1744655 ALLEGRO_EDITOR UI_GENERAL SKILL code with axlVisibleSet slower in release 17.2-2016 compared to 16.6
# I& Y; g( [3 H# {& e$ {0 G% ]1759380 ALLEGRO_EDITOR UI_GENERAL axlLayerPriority API changes layer visibility and colors
) \5 X8 ^4 x, b% P$ K1775071 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, dialog boxes are not displayed in the right order on using SKILL
! D F9 n4 E! _% z# B; }+ y1708554 APD GRAPHICS MCM shape lines are almost short and different with DXF and Gerber files$ C# `/ w" ?; _" u
1678824 APD SHAPE Updating dynamic shape fails to void all elements on layer L2.
- Z0 ~# V% x% B' w1742335 ASDA COMPONENT_BRO Libraries missing from new Component Browser6 k9 ?$ L# w/ u* V* q3 p
1779777 ASDA CONNECTIVITY_ SDA: Net name and physical net name are different* O' [) Q9 O- ]2 E0 s
1721919 ASDA CROSSPROBE Cross-probing a net from the .brd file highlights the entire bus in the schematic" I% N" q# u8 @" o9 e
1714313 ASDA EDIT_OPERATIO Filter does not work correctly in the Change RefDes form
. [; w" K' F# w1 i9 l1730809 ASDA FORMAT_OBJECT Image transparency slider does not update the number in the combo box correctly
) q7 H2 m2 H, j/ w4 d( ?1747397 ASDA GRAPHICS Pop-up DRC descriptions are too small and cannot be read
$ h T$ ]0 E0 z2 Y+ [/ W1640061 ASDA HIERARCHY Incorrect message received when invalid characters are specified for subdesign suffix& m8 x0 [4 E5 H+ W- |/ \! D! o
1723535 ASDA MISCELLANEOUS Clicking in the Command window should place the cursor at the last line to avoid editing previously run commands
0 u4 C) P5 z+ G1699936 ASDA PAGE_MANAGEME Page gaps created while moving pages. ~0 x& @; S) \( N" P6 u& Q# x& X
1737180 ASDA VARIANT_MANAG Deleted variants are removed from the variant.lst file but displayed in SDA
A8 A7 \! G7 ?$ L1763247 ASDA VARIANT_MANAG Changes in Variant Editor are not reflected on the schematic page.1 M' M* N" E* G' ?1 O
1733971 CAPTURE CONNECTIVITY Auto connect to bus not working in the attached design! Z& S }- w) |$ V" c
1236010 CAPTURE DATABASE Capture is very slow in processing designs. d- I- C0 F7 c! B1 U9 o7 y7 ^+ B& W
1518560 CAPTURE DATABASE Large schematics are slow to respond. C( b% E/ W7 x! U0 ~& w5 J- B, }% N
1705592 CAPTURE DATABASE Capture hangs when switching between schematics that contain nested netgroups
( J$ O' ^, M3 X( d2 i4 r! `4 `/ H1770687 CAPTURE GENERAL In release 17.2-2016 Hotfix 021 and 022, selecting Help - Learning PSpice throws Java Script error/ e' Q- n! H( a. F" u- d( m
1692435 CAPTURE HELP Version Info Window is empty4 i, a1 h4 w: j$ r' g, x
1767374 CAPTURE NETLIST_ALLEG Capture crashes on canceling the netlisting process
, \9 l! R$ j# T7 @. l2 a1719613 CAPTURE OTHER Moving a wire in OrCAD Capture CIS or Allegro Design Entry CIS results in design crash
% O: j* O% O, l/ W2 r/ o1746663 CAPTURE OTHER Capture slows down significantly in release 17.2-2016 Hotfix 017 and 018
1 P0 k- E2 Z% v! H4 j1709179 CAPTURE PROPERTY_EDIT Unable to delete unwanted properties associated with Ground and VCC nets.9 u3 j" G9 z ?- a
1714121 CAPTURE SCHEMATIC_EDI Mirroring and moving a symbol resets the position of a newly added pin property$ |% d8 t" w3 Y$ p5 @9 w4 h
1729861 CIS OTHER The 'Refresh Part Types' icon is alternated with 'Refresh Symbols From Libs' icon
v% O0 J |% Q! [9 g: S$ M1333600 CONCEPT_HDL COMP_BROWSER Sort the sections numerically in Part Information Manager8 g) O2 m3 y. |5 r1 S
1758761 CONCEPT_HDL COMP_BROWSER Incorrect Version showing in Component Browser in 17.2
5 x* M+ i0 z. o& ]! I1769591 CONCEPT_HDL COMP_BROWSER Modify Component / Project Information Manager (PIM), parts take longer to load in EDM
. A4 n4 j% L% {3 v/ p1479711 CONCEPT_HDL CORE Mirroring symbols causes alignment issues
* J* n+ @1 M v e1696208 CONCEPT_HDL CORE Display issue with the grid visibility after a save hierarchy0 h5 r: f4 _! L3 r/ l% ~
1698802 CONCEPT_HDL CORE Pin number overlap with the pin stub when the component is mirrored.
- l$ C4 o1 v& |, z1708917 CONCEPT_HDL CORE nconcepthdl crashes on a design with a core dump& A2 z; m r5 J! o5 F
1744815 CONCEPT_HDL CORE Deleting a page crashes DE-HDL2 r V+ P0 }, I4 K E7 O
1751863 CONCEPT_HDL CORE 'Move' does not move body but only properties of selected part
' ^) D2 \+ d! i$ T/ j1763556 CONCEPT_HDL CORE Component Alignment and other graphical feature not working in Windows 101 m* [ F0 ?$ Q2 ^( @. b% r" h
1725121 CONSTRAINT_MGR CONCEPT_HDL Audit report of ECSets reflects some gaps in certain columns
2 z3 ~( X3 c" V/ _1758740 CONSTRAINT_MGR CONCEPT_HDL Extracted topology does not populate the gather control used in the ECSet
% `4 [1 \3 {7 q7 G1759580 CONSTRAINT_MGR CONCEPT_HDL Class to Class assignments are incorrectly displayed in the 'CSet Assignment Matrix'
: V j2 q2 T! s1759590 CONSTRAINT_MGR CONCEPT_HDL Unable to create bookmarks in Constraint Manager/ p8 c- L d; v* Q9 R, S0 S
1764597 CONSTRAINT_MGR CONCEPT_HDL Copying constraints from a SKILL-defined CSet copies the automation flag/attribute ('A' in UI), as well.2 q, t# X' ~" C$ w8 ~
1771427 CONSTRAINT_MGR CONCEPT_HDL Decimal units specified in the precision settings are not applied correctly- c7 h* F% N+ F2 W
1700402 CONSTRAINT_MGR DATABASE Parallelism violation DRC not reported until cline is moved/ l1 d5 r! h/ x! f
1700370 CONSTRAINT_MGR OTHER Constraint Manager: Expanded nodes collapse on restart
3 e3 h1 f' N& B. P* X5 j* L1735636 CONSTRAINT_MGR OTHER Inductors are extracted as resistors in the topology
& T h' X/ l+ L. P: _$ ^' R1776917 CONSTRAINT_MGR OTHER Creating advanced formula causes the tool to crash8 P8 Y; N* r; O" X4 n
1762979 CONSTRAINT_MGR TECHFILE Constraint Manager does not retain values after importing tech file
; \+ o! n1 L, K) F# D2 O* }1699275 CONSTRAINT_MGR UI_FORMS Constraint Manager: Dialog boxes opened from the File – Import menu show files and folders in incorrect order
0 k1 U9 v8 ^) k1 a1699312 CONSTRAINT_MGR UI_FORMS Typing *.* in the File name field does not display all the files in the Import Constraints dialog box8 k9 F3 g1 J. r6 e* s1 d1 T9 ^' O: i
1742134 CONSTRAINT_MGR UI_FORMS Editing a cell from any of the constraint set in Constraint manager is filling other cells that should not be selected
( x* {& H$ p, S& v9 A D# R( w1755576 CONSTRAINT_MGR UI_FORMS Constraint Manager: Physical CSet filter not working correctly
; L' q* n* T* ?( U3 k4 O0 _* e- W1775333 ECW DASHBOARD Activity Log is not accessible to ECAD_Integrators if they are not part of the project team
+ u% b; |4 u9 R% @3 Q1749220 ECW OTHER Remove 'Role' column from Users web parts
y- N+ [, q* L0 F1716527 ECW TDO-SHAREPOIN Allegro Pulse: Mismatch between metrics with components on schematic and components in layout
8 h$ k! a4 v0 M1724195 FSP SYMBOL_EDITOR Device pins are not correctly aligned after being moved in Schematic Symbol Editor
2 y+ E) |! \. S5 i0 E# P1725479 INSTALLATION DOWNLOAD_MGR Download Manager error prompts user to close downloadmanager.exe( v% B+ p/ a0 |7 Y
1738952 PCB_LIBRARIAN SYMBOL_EDITOR Pin table must allow for Copy/Paste of Rows
5 }+ R8 s9 E' ?7 ~; d$ Y1638740 PSPICE FRONTENDPLUGI Set minimum height for the search field in PSpice Part Search# E. W! ^$ t( @- M4 T7 ~
1699822 PSPICE FRONTENDPLUGI Set minimum height for the search field in PSpice Part Search! \8 y" ]% x s5 }# t5 k$ h
1652265 PSPICE MODELING_APPS Cannot place PWL source from PSpice Modeling App
: z: S' Q, s9 h i- e) F6 \* g' E1685967 PSPICE MODELING_APPS Getting error when trying to place PWL source from PSpice Modeling App
+ G/ C5 A. k/ F! O) k2 n: t$ @1716313 PSPICE MODELING_APPS PSpice PWL Sources not working correctly in release 17.2-2016 Hotfix 014
" R+ x* Y# L& f+ q, Z1738747 PSPICE MODELING_APPS Inconsistent file type for PWL part in modeling application and source library
8 u( n! C' E9 J0 l% P* q: k3 E3 ?- N6 X1762202 PSPICE MODELING_APPS PSpice modelling app Tcl issues$ K$ o! J3 {1 @4 E0 S
1736605 PSPICE SIMMODELS BSIM4.6 model parameters incorrectly handled by simulator: ]) ^, q" W+ h% _8 b9 N, X1 C. M3 c
1442623 PSPICE SIMULATOR Bias points are nor correct in attached circuit; C" t8 T: u8 v5 `1 P
1618815 PSPICE SIMULATOR Bias Point calculation appears incomplete% [& _. C' G+ t3 A
1723039 PSPICE SIMULATOR PSpice crashes when curly braces are specified for the ETABLE parts
/ L, T4 W& K# J9 }1782353 SIG_INTEGRITY SIGWAVE SigWave crashes when opening .sww file in release 17.2-2016 Hotfix 023: S2 W7 R1 A* t
1745940 SIP_LAYOUT DATABASE Cutting a part of a tapered cline does not remove the connectivity on the dangling cline
5 g; j& Y3 n# g- h- @. g% k' O7 n1780072 SIP_LAYOUT DIE_ABSTRACT_ Export->Die Abstract File causes a crash
4 C. T) ^ |7 T/ @# E1736396 SIP_LAYOUT SYMB_EDIT_APP 'No such child' error message when deleting pins in symed
; x3 R2 P4 v' X" k6 {9 \: m1769728 TDA CORE Default policy file needs to be fixed4 {' v8 @9 Y, n: i- a1 v; X8 @8 M
1735682 XTRACTIM GUI XtractIM translation is incorrect: adds anti-pads* B) s: t& Q T& q+ `. B! S2 n
7 {1 ]" M! K7 `! t7 N" r0 X z! g3 U' Q- \, w: Z2 d% M
Fixed CCRs: SPB 17.2 HF0248 A" h3 o/ v$ N- W; p/ }
07-28-2017
2 ]. t% n% h0 G/ `2 k========================================================================================================================================================
9 s: d' V5 A/ }+ O; q! WCCRID Product ProductLevel2 Title
& Q8 D* _9 F3 v# B% X========================================================================================================================================================% [: K m3 x; ~" j% z
1762143 ADW COMPONENT_BRO Part placed using the 'Add' button does not populate 'PART_NAME' property
/ a# u& N- E$ z, @1765790 ADW PART_BROWSER Fail to extract component part number and footprint information/ l. v! i& Z P8 r! L6 g
1757719 ADW TDA TDO and Windchilll Work Group Manager out of sync at times7 S4 _" G; |* N$ T% z
1760607 ALLEGRO_EDITOR DATABASE Value for number of decimal places changes in Pad Designer in release 17.2-2016% c3 ]3 d4 G6 Z
1775160 ALLEGRO_EDITOR DFA Loading DFA spreadsheet crashes PCB Editor in release 17.2-2016% U/ I9 I9 U: ] i, p
1765984 ALLEGRO_EDITOR OTHER Cannot view System Info
% z" s3 R/ f$ K: }1729350 ALLEGRO_EDITOR REPORTS Net loop is not listed in report1 U. B5 x7 z- U# ^* u o
1725242 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
7 l, ?3 K# ~$ H9 n! o3 T4 x7 }1754402 ALLEGRO_EDITOR SHAPE Illegal arc radius error (SPMHA1-85)
) s2 i- }; H% T- ~2 c2 }1762888 ALLEGRO_EDITOR SHAPE Border line missing for some crosshatch (xhatch) shape voids6 p$ e! @7 D' E5 Y
1769188 ALLEGRO_EDITOR SHOW_ELEM 'Show Element' with the 'Groups' option used on certain modules crashes PCB Editor
5 g& b/ Y4 H: C1767690 ALLEGRO_EDITOR TESTPREP PCB Editor crashes when running automatic Testprep- t9 M |( f9 ~
1737337 ALLEGRO_EDITOR UI_FORMS Pinned Show Element window closes when opening new design in release 17.2-2016
- q( | j: r4 a: X1736642 ALLEGRO_PROD_TOOLB INTEGRATION Cannot change accuracy to 4 for 'Change Width' in Productivity Toolbox
- m: O9 \% U k9 H1685216 ALTM_TRANSLATOR CAPTURE Third-party translator placing symbols off grid
7 b3 i% x/ q& l: W2 A1738679 ALTM_TRANSLATOR CAPTURE Connectivity loss in imported schematic
! W/ X2 X% S9 j% s; d; T1738705 ALTM_TRANSLATOR CAPTURE Connectivity loss in imported schematic
. D% f D7 K/ h1748583 ALTM_TRANSLATOR CAPTURE Crash on importing design using third-party translator7 ]( i- q; }% q2 ]$ U# E9 E$ I
1679310 ALTM_TRANSLATOR PCB_EDITOR Third-party translator should fix off-centered connections9 _0 J) S- Q( X2 u7 r9 i
1686845 ALTM_TRANSLATOR PCB_EDITOR Third-party translator does not place parts after successful translation
5 r- b8 M' w% h! i" F: c6 ~1723141 ALTM_TRANSLATOR PCB_EDITOR Placement outlines are rotated in third-party translator4 g; s2 e' K$ \) _4 W% s) i
1723164 ALTM_TRANSLATOR PCB_EDITOR Third-party translator creates board with missing data: vias, traces, and so on
& O/ l+ G: Z- f3 t4 u) m1723190 ALTM_TRANSLATOR PCB_EDITOR Third-party translator changes design origin
& P( v& Z0 D% u7 P2 a1750496 ALTM_TRANSLATOR PCB_EDITOR Third-party board with arc tracks not correctly converted to arc clines/ ^5 _$ |1 Z* D' h' V, G
1769624 APD DATABASE Attempted symbol delete crashes APD- X; y" G$ F$ w0 b
1727206 APD SHAPE Merging two shapes results in an incorrect shape
9 j0 ]% }8 s) `' ~1707756 ASDA VARIANT_MANAG Scrolling in Create Variant closes tool- I+ z2 W8 Q/ q" v" K
1753699 CM RELEASE installDebugger() does not work in release 17.2-2016 as SKILL kit is not installed) l, F/ t s7 o: w
1741534 CONCEPT_HDL CORE DE-HDL freezes when selecting a net that contains many connections- o( x+ c' d. b/ F* i3 q+ k b
1752687 CONCEPT_HDL CORE The move command changes the connectivity of the schematic& T$ @/ H. g% c- I
1763525 CONCEPT_HDL CORE Genview crashes when generating split symbols; k5 }. _ b3 H: `! @/ o3 ^) Z4 |
1766797 CONCEPT_HDL CORE Schematic not refreshed after using the clear xnet overrides feature
# M! u& B% g" p8 v+ S1770852 F2B PACKAGERXL ERROR(SPCOPK-1138): A hard location was found on instances of different physical part types
. F# D6 f2 g% E$ a" q* t/ E1754473 FSP DE-HDL_SCHEMA Provide an option to generate symbols with custom attributes& e: C n$ \4 R! {7 E
1748106 FSP OTHER Create protocol from existing protocol error message needs clarity
. M6 @/ A* W2 f" P1724201 FSP SYMBOL_EDITOR Unable to change 'Pin Direction' in symbol editor, _% g0 h. D" s1 {" ?, {. E& U/ d6 M) h
1772429 ORBITIO ALLEGRO_SIP_I Import - OrbitIO: Translator cannot create bundle in PCB Editor
. D8 o/ z- x4 H: L; L2 e- i* j; b! D& W1725759 SIG_INTEGRITY OTHER PCB shape/plane capacitance4 I2 Q9 Z7 S5 A% _! ?+ b0 n5 j/ H
1760924 SIP_LAYOUT DIE_STACK_EDI Package height of die .dra file reset to 110um when placed p# D/ R* y0 B; Q% e3 a( v& K
1764385 SIP_LAYOUT MODULES Embedded components are unplaced in created modules (.mdd)5 j; c. a& \' a; D
1733679 SIP_LAYOUT OTHER 'metal density scan' does not use select window: T& `' H! h( |
1763707 SIP_LAYOUT OTHER SiP Layout exits with error message in release 17.2-20160 w9 q5 ?) c9 U, @5 z& G
1763515 SIP_RF DIEEXPORT Virtuoso writes incorrect width for 45 degree path segments in XDA file
. _& e# h! y8 i' O+ Q7 L1772397 TDA DEHDL DE-HDL crashes if license is not available for team design+ j7 j3 g. E7 }9 g2 y) T
0 h& N7 X1 g) d# m5 J `: j7 O3 \
1 u( t- J9 I1 `- P0 q3 c( NFixed CCRs: SPB 17.2 HF023
$ D* a$ J6 T0 t! O07-7-2017
! D' [9 k9 ^$ q- d/ ^========================================================================================================================================================
" {& f- Z4 ?4 I! ~CCRID Product ProductLevel2 Title
+ n( u$ G( B( y0 O========================================================================================================================================================* E( ]6 _1 ]. |% S* ^; ?3 ^
1703281 ADW ADW_UPREV Design_init needs to support the -cb command% P6 ]. a. r4 A, L
1762238 ADW COMPONENT_BRO DEHDL crashes without reason
# R1 j! a2 T! G+ F5 z# J1759467 ADW DBEDITOR DBEditor does not recognize that 1.10 is a higher version than 1.9
) N, p" L/ ^6 j, p- a! S1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager
+ J/ T+ d# ?: g% u1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager
9 }+ U# w9 J3 X, x9 V1757443 ADW LIBDISTRIBUTI Blank PHYS_DES_PREFIX in PTF file& t* r" I: I) n. i6 `9 t! z
1752126 ADW LRM cache not getting updated with std models when moving from 16.6 to 17.2
- {( Z' }. d8 Y# O1754444 ADW LRM Update Standard library in LRM causes an error, "Cannot proceed with update as don't have permission to delete."
# g6 e- s q4 e: m* V* f1715861 ADW SRM symbolrevchk.par has incorrect variable name for SRM to ignore the tool version
+ P2 Y0 v) R- @0 P1628403 ADW TDO-SHAREPOIN Objects remain checked-out after multiple failed 'check in hierarchy' attempts
. w' E; |9 J+ n9 R; {1759250 ALLEGRO_EDITOR DATABASE Flex-rigid placement does not move bottom pads to nearest layer
# T$ k7 k# [3 f1762782 ALLEGRO_EDITOR DATABASE PCB Editor crashes when creating artwork
0 [% ]; u) c$ N; ^7 r$ x I1746665 ALLEGRO_EDITOR DFA Cannot scroll in DFA Constraints Dialog if the DFA constraint file is read only
) |4 N$ }: E) e1750084 ALLEGRO_EDITOR DFA DFA spreadsheet disappears from the DFA library if hyphen is present in the name% ^: V$ [* m9 J# u; D0 S
1697155 ALLEGRO_EDITOR GRAPHICS Position and size of Show Element and Measurement windows not saved in PCB Editor
1 R3 U" t1 P' z/ U1734282 ALLEGRO_EDITOR GRAPHICS Placement of reports and pop-ups not retained in PCB Editor
. e- T* n s q9 _, z0 p- v4 ^1740863 ALLEGRO_EDITOR GRAPHICS Show Element and Measure windows do not retain position
5 B; O2 ~) c; ?1749687 ALLEGRO_EDITOR GRAPHICS Position and size of Show Element and Measure windows are not saved in PCB Editor in release 17.2-2016, ~; R f4 D4 H' x
1764124 ALLEGRO_EDITOR SCRIPTS Replaying recorded script file crashes PCB Editor
+ M$ i$ b& j; N% @6 M# D1762888 ALLEGRO_EDITOR SHAPE Border line missing for some crosshatch (xhatch) shape voids; `. R$ I. B, |. }
1763619 ALLEGRO_EDITOR SKILL Incorrect text block name when extracting text parameters using SKILL
6 c3 }- l( Y t. s- D1685826 ALLEGRO_EDITOR UI_GENERAL Reports when opened from Status Form disappear behind PCB Editor canvas when clicking on canvas! v$ U* O% m, u: t; ^5 G! V! ?
1733552 ALLEGRO_EDITOR UI_GENERAL Although F1 is defined as an alias for another command, pressing F1 opens help! v! ]9 v+ q9 D* c# ]
1735098 ALLEGRO_EDITOR UI_GENERAL axlUIYesNo displays garbled text when customized for Chinese in release 17.2-20161 H M p; I& s. c
1753430 ALLEGRO_EDITOR UI_GENERAL 'Tools - Quick Reports' opens only one report at a time; O& I m1 {* p' ]
1754283 ALLEGRO_EDITOR UI_GENERAL Call multiple reports from a function key
4 X) {( v* n) v# _" ?6 _2 I1742822 APD STREAM_IF Component pins are not mirrored properly when mirror geometry option is checked and component is mirrored at 90/270$ B3 e3 n6 H6 D" I c7 I% p
1762284 ASDA COPY_PASTE Copying testpoint crashes tool and eventually the operating system
2 _; h% k9 Y8 {6 ~* G# d1655057 CONCEPT_HDL COMP_BROWSER ADW Part Manager and Component Modify hangs
- y/ x6 f) g% e; ]1689740 CONCEPT_HDL COMP_BROWSER Bad response time using Dehdl component browser
8 W, T" {1 G( f# p' ]3 r1735332 CONCEPT_HDL COMP_BROWSER Sort in mathematical order Symbol list in Component Browser
% V9 p, S3 j( n9 T1739197 CONCEPT_HDL COMP_BROWSER Part Information Manager can`t sorted symbol version
6 h' t5 x) u- b9 s0 ?! P1764605 CONCEPT_HDL CORE Signal added from the console should be 'Left Aligned' instead of 'Center Aligned'
: I) N0 G1 v- l0 I$ a1761706 CONSTRAINT_MGR CONCEPT_HDL cmDiffUtility has a typo in the usage statement
. w7 i, u# t; ?1758426 ECW DASHBOARD Behavior of 'Apply Label' for Dynamic and Status labels should be same in TDO and DE Webpart" c) X7 [% h( Z! E9 V; \" r: g
1764096 ECW PROJECT_MANAG Renaming project using the ETD window randomly hangs the edit window, refreshing bring backs the page" B j: j7 o/ X [
1764070 ECW TDO-SHAREPOIN Join Project: Multiple entries shown for workspace/project with multi-hierarchical structure4 h; G6 x3 p# Z2 J7 N( G
1754473 FSP DE-HDL_SCHEMA Provide an option to generate symbols with custom attributes
1 Y8 {0 x2 s0 S/ ~ K- G, z1 V7 [1724124 FSP DESIGN_EXPLOR Provide Tcl command to filter data in Design Connectivity Window% V6 B" [7 { L$ Q/ o. a, u
1726548 FSP OTHER Unable to open FPGA system planner if username/log file path has Cyrillic letters4 \6 o* W! D; b$ f& T
1719133 SCM SCHGEN Voltage symbol not getting placed for some of the voltage nets/ i) ~; }* ~, @1 ~3 j
1680989 SIP_LAYOUT ARTWORK Artwork film set-up: Match Display including invisible layer
# F1 t% ^* B+ H8 A, S1732218 SIP_LAYOUT DEGASSING Shape will not degas as needed - not all voids degassed
, u, A% F4 i L; _9 y' V$ J% X1763280 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout does not recognize width of segment when importing .xda
. ?" G k/ Q* X1762992 SIP_LAYOUT OTHER Saving a design after adding a solder mask layer in the cross-section crashes tool& L3 f2 {. U& ~0 [
: A/ z- b2 g% F7 S8 ]5 J3 q3 i& N; w. N
/ y3 g9 E- k$ C; b- i. @2 C$ g1 PFixed CCRs: SPB 17.2 HF0229 Q# K; I8 v6 H3 t. x$ W4 _: t
06-16-20176 T% L# C4 k* a. j
========================================================================================================================================================
: `6 C) Y Y5 ~. j( I. KCCRID Product ProductLevel2 Title# m" g, d( w4 J" x8 B$ t3 N% U
========================================================================================================================================================
5 ^% e+ J' E" G6 I: K' A" e1755789 ADW DBEDITOR Checking in HSS Block returns 'Failed to create archive'
: j# S. N4 l% T& K, g1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager
0 o) N0 K: _2 l) n% R/ o1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager
5 D' g$ r4 t" J, a# @$ H% s$ S9 U1744081 ADW FLOW_MGR Error regarding configuration file when trying to open Workflow Manager/ C9 K& a2 ~, z1 k! d& b
1756727 ADW LIBIMPORT EDM Library Import fails with java exceptions when merging classifications" ~6 ?* b; _5 k) \
1743763 ADW SRM Find filter is grayed out when Allegro PCB Editor is opened from EDM Flow Manager
( A: L/ \+ c& g! ^1748399 ALLEGRO_EDITOR DATABASE In release 17.2-2016, end caps not visible for certain clines in PCB Editor! ]5 Q! `7 i- M
1748522 ALLEGRO_EDITOR INTERACTIV A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it, K o) v0 D6 B8 T! p1 d/ X7 k
1734983 ALLEGRO_EDITOR INTERFACES Secondary step model does not stay mapped after drawing is reopened
# \9 g; h+ R) A, C1 M8 R3 F y1753704 ALLEGRO_EDITOR REFRESH Refreshing symbols crashes PCB Editor
9 D2 [. l* i( B2 f/ R/ p8 y, C1493721 ALLEGRO_EDITOR SHAPE Voids on negative planes are not adhering to constraints
3 U- u7 _% [$ ^9 A- J i4 |2 i1711242 ALLEGRO_EDITOR SHAPE Route keep out leads to partly unfilled shapes with gaps, o( S' E6 Z; l
1726865 ALLEGRO_EDITOR UI_GENERAL Pop-up Mirror command does not mirror at cursor position
5 d% l9 U) |* T7 ]" O! d$ i+ I1752987 ALLEGRO_EDITOR UI_GENERAL axlUIViewFileCreate zoom to xy location not working while in user created form.4 m' M0 f& ?4 B' @" Z8 V+ q8 s: y
1755638 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run; y4 z. W0 y; m6 l( f9 x, f
1719792 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC hangs or crashes PCB Editor
4 q" X' [/ v" o" Y2 ~) K1624869 ALTM_TRANSLATOR CAPTURE A structure file is required to translate a third-party schematic to OrCAD Capture. |9 [- z' \9 `6 v+ A E: P6 t
1707416 ALTM_TRANSLATOR CAPTURE Missing components and pins in the OrCAD Capture schematic translated from a third-party tool
3 S( L# _' o% p2 X0 q1708825 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate the schematic4 Q1 X- m* g1 J% j+ C+ c; _
1719200 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate all the pages of a schematic
3 f \& J: i/ Z) Q+ ]5 p8 u5 q, ]1546070 ALTM_TRANSLATOR CORE Third-party to DE-HDL schematic translation fails9 l* |6 q( d7 @, \# |2 q6 p& e
1700508 ALTM_TRANSLATOR CORE Third-party PCB translator does not work in release 17.2-2016' a% w$ s3 Z, }7 L, ?8 t
1699340 ALTM_TRANSLATOR DE_HDL Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor
7 h1 ?- s% W( r6 Y1630379 ALTM_TRANSLATOR PCB_EDITOR Third-party translator is not importing clines and vias- N& c. M2 E1 `% a. C+ |3 w( P1 k
1708615 ALTM_TRANSLATOR PCB_EDITOR All items of third-party PCB not imported in release 17.2-20166 ~1 ^* A( _6 r6 O8 E5 I
1758296 APD DXF_IF DXF OUT: Rounded rectangle pads mirrored incorrectly' s% r" J [, H; ]7 n7 t
1756040 APD IMPORT_DATA The 'die text in' command ignores values after the decimal point9 u5 Q5 y0 i- b
1727206 APD SHAPE Merging two shapes results in an incorrect shape
- u- ?9 g! u% W' {- [) p" k1753682 CONCEPT_HDL CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL! A. [4 E* {0 j" N3 G* w
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic, b( H# Y- b* g9 d6 q
1747559 CONCEPT_HDL CORE Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)
- B* U) Y; S3 g, l; s1749644 CONCEPT_HDL CORE In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes: v0 ]" R* \ ?; e9 h
1746910 CONCEPT_HDL GLOBALCHANGE Global Component Change unable to identify part data when using schematic pick option
8 x& e3 E: P9 s4 @' W1743572 FLOWS PROJMGR Project Manager displays incorrect values in Project Setting
+ X8 A1 O+ ?) Z2 _1724124 FSP DESIGN_EXPLOR Provide TCL command to filter design connectivity window- k8 B# H/ ]4 O" j8 X! X
1719105 FSP GUI Tabular sorting not working in FPGA System Planner. S! Y/ D3 ~5 F, W) O3 P) [
1755750 PCB_LIBRARIAN GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor
1 L& I. y* e9 C( b, I1 e! ]( D1722993 PCB_LIBRARIAN IMPORT_CSV Part Developer crashes while importing part information stored in a .csv file
" j0 h. O4 @4 n1 ]+ Y; C5 Q- `7 U1758856 SIP_LAYOUT 3D_VIEWER Correct the spelling error in the 3D Viewer Design Configuration window
# b. e; ~3 g2 f1755179 SIP_LAYOUT ARTWORK PCB Editor crashes when creating Gerber files: F9 ]( Q; }+ D# K" h
1743511 SIP_LAYOUT MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check
* D$ N6 E9 m! X/ T5 [
2 \8 d( I- v$ Z4 S6 v6 ]( ~5 N
Fixed CCRs: SPB 17.2 HF0210 \6 k2 `) g' o2 b; [# v" C. X
06-3-2017
$ S/ T" Q x/ y; `( @- k) J========================================================================================================================================================" G: ]9 \& T8 Y, n
CCRID Product ProductLevel2 Title: { O: J+ `4 g3 S
========================================================================================================================================================
. F8 D& v$ M/ Y @9 \8 E2 X1401318 ADW DBEDITOR Bulk Edit - Previously modified cells do not turn blue when selected, _$ @! Z1 a$ y. H! x& i7 ^
1621446 ADW DBEDITOR Bulk Edit - sorting highlights incorrect cells to mark them as changed' V' l- J4 W: y
1743997 ADW LIB_FLOW Match file for standard models is incorrect! Z+ X$ m3 F/ T4 i8 C, \
1746052 ALLEGRO_EDITOR DATABASE PCB Editor crashes when applying no drc property
( L! x, p% B8 K' M; d/ h0 D1736067 ALLEGRO_EDITOR DRC_CONSTR Interlayer checks not reporting DRCs between cline and mask layer% C: U, \' k f7 {9 e, X9 Z
1738587 ALLEGRO_EDITOR EDIT_ETCH Line width changing on slide for ETCH - Conductor (Not on a NET)
0 v% C) Z% m; O1745277 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using the slide command
) o0 W1 l# o' P) S1 b1747942 ALLEGRO_EDITOR EXTRACT Fabmaster Out does not export arc in pad_shape
7 S, _7 O2 D- y5 K2 X* |6 Q9 W1737202 ALLEGRO_EDITOR GRAPHICS Setting the variable display_raster_ops
0 ~3 N' E/ r* U& [% F1744042 ALLEGRO_EDITOR GRAPHICS Unused pad suppression is not working on few nets) t6 M$ {9 P5 U1 H' v0 p! p
1703848 ALLEGRO_EDITOR INTERFACES IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty7 w7 H8 D8 K! X( w) s* A
1743899 ALLEGRO_EDITOR MANUFACT Glossing dangling vias crashes PCB Editor8 {/ q; m, [& c/ m8 ^; K+ Y
1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor# c0 w- `3 }( Q6 `- m6 e% S5 n
1748520 ALLEGRO_EDITOR OTHER TDP fails to load on an empty database: q8 Z/ W% z# \) ?% v
1748581 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when changing default pad geometry1 r) t- N4 {3 V1 I/ A# G
1751469 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes/freezes when browsing for a shape symbol: e8 u# g. H o: x
1725948 ALLEGRO_EDITOR SHAPE Shape differences after conversion from release 16.6 to release 17.2-2016
5 [+ V; _& g6 c& f( p1729306 ALLEGRO_EDITOR SHAPE Seting shape_rki_autoclip variable causes no void to be generated1 y# p. C9 X( @. ]- O; _
1698876 ALLEGRO_EDITOR UI_GENERAL Tabs are large and text is compressed in release 17.2-2016: n: A4 t! ]- j8 y+ l( y8 x% |
1698883 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors% ?# |4 X7 b, n( o
1707933 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not locating menu as per x_location" _# H: B1 m% j* d. ^; ]; f/ E( g- D
1741460 ALLEGRO_EDITOR UI_GENERAL Right-click, context menu options grayed in some cases after choosing Edit - Copy
. F0 z9 x" ?3 ?, h1747588 ALLEGRO_EDITOR UI_GENERAL Interacting with PCB Editor by sending messages is not working
! @2 ?3 t/ G9 ~" a! `1747488 APD EDIT_ETCH Route connect is improperly affecting existing routes in locked high speed via structures
/ n Q4 c9 G6 P2 Y2 H8 e- r1750182 APD STREAM_IF The stream out settings are not saved& |% y+ s: I) B5 u
1752067 ASI_SI GUI Links to differential waveforms do not work in Sigrity SI report: X6 F* X0 e( s$ v: Z7 K. l0 [8 l/ R
1752131 CONCEPT_HDL COMP_BROWSER Symbol view in part manager doesn't match the symbol version
% e. o3 m. L1 l, ~7 I9 {! ?3 E1754116 CONCEPT_HDL COMP_BROWSER Default Symbol selected is n°2 instead of n°1 in component Browser
- f# i% |. y% Y1 Q- u: }4 v$ J1754949 CONCEPT_HDL COMP_BROWSER Part Information Manager displays preview window with the wrong symbol and missing footprint
6 I1 U/ y- Y+ j: x! ?7 d1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic! \) e# u4 j' | u" `1 e: C
1750916 CONCEPT_HDL CORE DE-HDL crashes when trying to uprev a project in release 17.2-2016) g1 b- O O' q! \
1711487 CONCEPT_HDL INFRA Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design6 z/ y) }, P; @4 ?
1746915 CONSTRAINT_MGR CONCEPT_HDL Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow
) j! P/ b7 c2 H3 M1743523 CONSTRAINT_MGR DATABASE Suppress warning pop-ups from the constraint automation script# T* b0 m! C- X4 ~& K: m
1746941 CONSTRAINT_MGR UI_FORMS 'Go to Source' from DRC tab is not working in release 17.2-2016
0 Q) B' z0 e: w$ ]* @% Z7 `1753010 ECW METRICS Metrics not getting collected due to old license in use8 |' v. q% R! K& J2 D" Q2 L
1713052 FSP GUI Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance: A% B/ U# S2 |) O6 j p# U6 B* e/ R
1719099 FSP GUI Net naming wrong after building block9 T6 F N; g, d, k4 J
1719105 FSP GUI Tabular sorting not working in FPGA System Planner' Q1 x9 O. W8 N, _) Q$ |# k
1720479 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems9 h. n7 u) d9 |( J
1723411 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems! M; Q( _9 W% q6 {1 }4 E
1746628 PSPICE ENVIRONMENT PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016
$ T& w8 F' }- D F& n1745976 SIG_INTEGRITY GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing
6 q2 n: H* R+ q; L5 `1690820 SIP_LAYOUT PLATING_BAR Cannot add fillets to pads with plating bars in release 17.2-2016
{6 \6 _+ v: \9 Z3 }8 H% ^6 m1725042 SIP_LAYOUT PLATING_BAR Creating a plating bar removes dynamic fillets' t/ {1 n, n0 U) ?! y
1747534 SIP_LAYOUT SHAPE Moving fiducial crashes SiP Layout4 I5 x2 H, V, U
( b" c1 w5 V5 H( e# p
+ Q& M" i3 M2 N6 a- X% |
Fixed CCRs: SPB 17.2 HF020' g8 G* I! Z) ~( |3 ~6 _9 E( v
05-21-2017
4 l) o9 B8 Z4 f3 t5 h& R' L8 K* q========================================================================================================================================================
, S% Y3 B8 {2 W# oCCRID Product ProductLevel2 Title
/ L' S' R; y4 M( J========================================================================================================================================================
; _) y; _7 l; `; a1737443 ADW DBEDITOR Revising the schematic model classification for one category causes all parts in the library to be revised; t, L, p6 Z% Q5 f4 f& ]
1734123 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas crashes Allegro PCB Designer in 17.2 S016! L' e7 A4 p9 O* U3 V" G
1742084 ALLEGRO_EDITOR DATABASE Running DB Doctor on DRA files with custom pad shapes resets some of the custom padstack shapes in release 17.2
$ C" ]$ B8 \$ B3 T2 R, H& J1739397 ALLEGRO_EDITOR INTERACTIV In release 17.2, running the SKILL function axlImportXmlDBRecords causes Allegro PCB Editor to crash. j0 Y A8 @- C" d
1724588 ALLEGRO_EDITOR MANUFACT Backdrill Route keepout suppressing existing Route Keepouts! m' m5 Q: p" A3 k. ~, \* O
1740036 ALLEGRO_EDITOR MANUFACT Generating the cross-section chart does not provide information about the overall board thickness
/ K5 r. w! r, O i7 [ R1743726 ALLEGRO_EDITOR OTHER IDF file export: In release 17.2, only one design outline is exported as against multiple board outlines in release 16.6
% O% b$ U' V% P1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor9 z" H+ V' o2 L, Z
1729350 ALLEGRO_EDITOR REPORTS Net loop report is not working.: B) ^1 L/ t" h
1713014 ALLEGRO_EDITOR SHAPE Incorrect behavior of donut shaped pads at certain rotations
! @4 d& w* H0 M& |1739870 ALLEGRO_EDITOR SHAPE The artwork is different from the PCB in release 17.2 Hotfix 172 c9 i8 q: ~$ _% E B# ?/ m U
1698869 ALLEGRO_EDITOR SKILL PCB Editor crashes when trying to open another .brd file after running SRM on first .brd file3 n, H) p9 [1 [1 T' T
1739307 ALLEGRO_EDITOR SKILL axlCNSDFAExport fails after first run$ N& ~7 d6 g; g `& s
1743385 ALLEGRO_EDITOR SKILL SKILL APIs for STEP model mapping are not available in release 17.2 Hotfix 17 or 18
+ M0 Q2 R, y, r3 l; l1685826 ALLEGRO_EDITOR UI_GENERAL Reports when opened from Status Form disappear behind PCB Editor canvas when clicking on canvas
# \0 n9 j' o0 G1687797 ALLEGRO_EDITOR UI_GENERAL Cannot open two HTML windows, one after the other, while using SKILL function+ Q) p |' e5 \
1696229 ALLEGRO_EDITOR UI_GENERAL Setting the 'allegro_html' environment variable in User Preferences Editor overwrites existing popup text windows! m$ ~- I5 i7 P* ` N" z4 T5 j
1708636 ALLEGRO_EDITOR UI_GENERAL In SPB 17.2 release, keyboard focus automatically shifts to the newly opened dialog box
% v/ E6 `3 A# v% t$ Y1711367 ALLEGRO_EDITOR UI_GENERAL Launching two report windows using SKILL is not working in 17.2
- M% S' W! J! M( o8 b+ c, C3 M1742856 ALLEGRO_EDITOR UI_GENERAL Allegro PCB Editor crashes if Project Manager is open for a design in release 17.2 Hotfix 18% x0 v" R u3 K) W
1729519 APD SHAPE shape degassing does not generate all voids to cover entire shape
4 Z: e; _! ^( g7 A9 s0 M& ?/ u1711375 CONCEPT_HDL CORE Copy-paste of schematic between two instances of DE-HDL is not working as expected
8 j/ P$ N/ X9 |7 Q1737230 CONCEPT_HDL CORE On the Linux platform, copying of schematic objects does not work between designs of releases 16.6 and 17.2
# Y, J2 T' O3 j1741375 CONCEPT_HDL CORE Inconsistent behavior of the Move command when moving a symbol
; L/ w, X! ^+ s- T1743992 CONCEPT_HDL CORE Inconsistent behavior of the Move command when moving a symbol; o7 H5 ~4 }8 _/ L
1736093 CONSTRAINT_MGR CONCEPT_HDL Incorrect topology extraction and mapping errors related to MUX parts
* ^2 q5 Z+ B( C. ?- {8 Z1743518 CONSTRAINT_MGR CONCEPT_HDL Lag observed in expanding and collapsing the net classes in Constraint Manager
b) M0 x! h, m8 {1730159 FSP ALLEGRO_INTEG FSP diff engine does not read PF Thevenin connections in FSP8 `4 K) K' X; P' F2 o
1664070 ORBITIO ALLEGRO_SIP_I Display pads of SMD components on correct layer" b5 @( |1 G8 G( Y$ T5 Y
1709319 ORBITIO USABILITY OrbitIO issues an error about Device template while importing brd with Bundles: j" ^$ K1 z7 h0 [- |' N0 z( w3 W3 E
1741150 PSPICE ENVIRONMENT Need a way to prevent the 'pspSimSetting.js' file from being overwritten by a hotfix installation in 17.2
6 X, N% l! u% F% b1735354 PSPICE SIMULATOR Access to custom nom.lib is not working as expected) o k4 [0 w9 P2 r/ A" ]
1716523 SIP_LAYOUT COLOR Tool crashes on using the PageUp, PageDown, and Tab keys in the Color dialog box.$ C& m% g& j; A8 l6 v
2 N' q- S7 T: I& S
3 W4 n1 ?1 N+ }
Fixed CCRs: SPB 17.2 HF0190 b, i5 B; t' X2 A. B/ r
05-6-20172 o; ? [9 }) X
========================================================================================================================================================3 \6 n; K' @! T
CCRID Product ProductLevel2 Title) H' _, U0 a6 {, p
========================================================================================================================================================
5 }2 A: g: h- x( W8 O. }" s. ]$ n1701785 ADW ADWSERVER Getting 'Unable to locate tools.jar' error while using 'Copy Projects'4 v6 C4 y' w4 W% ^
1706782 ADW ADW_UPREV Design uprev failed with error 'ERROR (FM-107): Failed to run adw_uprev'
3 X$ `( C) Z8 w6 ~* o1508159 ADW FLOW_MGR Flow Manager 'Open Last Project' option points to a deleted project( M% D" Y9 X6 J
1690903 ADW FLOW_MGR Flow Manager library project list empty after 'Remove From List'
Q9 |8 E4 q2 U7 d5 O* B2 U+ d( V1705224 ADW LIBDISTRIBUTI Cannot migrate Library Footprint Models having subdirectory to release 17.2-2016
, L( b. l/ R2 M9 V9 ~& e1672037 ALLEGRO_EDITOR EDIT_ETCH Add ZigZag Pattern crashes PCB Editor
- f t( M, @" d- ^% d4 S# G0 G! x1695711 ALLEGRO_EDITOR EDIT_ETCH In release 17.2-2016, Fiber Weave Effect - Add ZigZag Pattern crashes in Windows 10, Q, w5 N/ z9 r% e, a8 Z
1706522 ALLEGRO_EDITOR INTERFACES DFX import displays error message '*Error* eval: undefined function - cloneID' but imports outline
9 O v# W# C2 j5 S- E3 g1716336 ALLEGRO_EDITOR INTERFACES DXF file is not correctly imported into PCB Editor+ y% ~, l0 n+ h( V, l
1720290 ALLEGRO_EDITOR INTERFACES Incorrect rotation of padstack after dxf import
" m1 D; c/ A* ^" z& c6 z1724683 ALLEGRO_EDITOR INTERFACES DXF OUT: incorrect Rounded/Chamfered rectangle pad rotation
2 M" ?! h6 X( E3 q6 u1732587 ALLEGRO_EDITOR INTERFACES Format/content of ipc356 files exported in release 17.2-2016 different from release 16.6
( U$ T( N/ F' ~/ i1737516 ALLEGRO_EDITOR INTERFACES IDX Import works differently for placed and unplaced parts5 c- r) o% z7 V
1715152 ALLEGRO_EDITOR SCRIPTS Clicking Layout in Project Manager fails to load PCB Editor and gives message 'Word too long'. |7 D7 E5 u* E o7 l/ [
940699 ALLEGRO_EDITOR SHAPE Update shape to smooth fails to void a few clines.! m3 T% Q- {5 I) K& N7 l4 t
1706581 ALLEGRO_EDITOR SHAPE Dynamic shape void clearance errors with vias$ |. P3 C# `, u# y. |3 I
1638300 ALLEGRO_EDITOR UI_GENERAL Version information set in $cdsversion truncated on title bar for some tools1 F. O$ G, E' \
1697732 CONCEPT_HDL CORE Pasting a signal name results in warning (SPCOCN-922) if the wire is too close to the edge of the page border! k$ G# n1 A8 }$ y, ?# ?( u; z3 V
1729510 CONCEPT_HDL CORE Changing the name of a split block adds pages that are part of the page gaps- G5 T6 A+ |1 q9 z7 k C
1721065 CONSTRAINT_MGR CONCEPT_HDL Physical import errors on changing plane to conductor in stack-up5 W. I: Y: j& h) {) C
1734875 CONSTRAINT_MGR OTHER 'Create Spacing CSet' crashes tool from existing CSet context and grayed out in design context# j1 {% ^) N; P4 j! E
1473104 ECW PART_LIST_MAN Pulse does not filter capacitor values correctly& I# o2 l2 L- `. f- R0 m9 H7 l
1736580 PCB_LIBRARIAN SYMBOL_EDITOR Grids are not displayed correctly in Symbol Editor
! [6 V0 q) ~" s# |1738955 PCB_LIBRARIAN SYMBOL_EDITOR Need ability to edit Symbol Properties
8 A. T" x9 }! L1735215 PSPICE FRONTENDPLUGI PSpice part search customization CDN_PSPICE_ODBC_SRC environment variable is not working4 o* t, v6 A/ ^2 W5 e$ y
1733198 PSPICE PROBE Probe crashes when exporting trace expressions with multiple plots to CSV files, x& d. a: o! ]( O
1737060 SIG_INTEGRITY SIGNOISE signoise fails for the AllegroSigrity_HS_Base_Suite option in release 17.2-2016 and release 16.6-2015
/ `8 |" v) C3 Y# Q- R1707443 SIP_LAYOUT WIREBOND Moving bondfingers violates spacing constraint
5 w8 }% t/ c2 \/ H
+ C2 K1 F0 w- D g% h3 I
1 y4 c+ H8 g. {) U, sFixed CCRs: SPB 17.2 HF018
( F% u2 _2 E6 F$ |3 s+ h04-23-2017
% I6 y! O, U) z. ] K% F: j========================================================================================================================================================
5 e: c2 x% M8 j5 ?- d! _! zCCRID Product ProductLevel2 Title
' y: n- a. e2 b' `7 w( r6 }7 H: y======================================================================================================================================================== I6 Q* J* g, }4 Q( G) W7 |4 V4 ]- I& x
1721773 ADW ADW_UPREV adw_uprev updates all versions in history log to the new version. Should only insert note about uprev.' Y" Y9 M* f9 ~# V, }' r
1684346 ADW LIBDISTRIBUTI lib_dist_client fails for new release 17.2-2016 design server
3 l/ s% O1 L8 |1696632 ADW LIBDISTRIBUTI lib_dist_client fails on release 17.2 Designer Server having release 16.6 Master Server
3 M, I* l" v* m7 y9 v1 H1705224 ADW LIBDISTRIBUTI Cannot migrate Library Footprint Models having subdirectory to release 17.2-20161 {2 H' _, k! {
1721017 ADW LIBDISTRIBUTI adwserver -install fails intermittently during Master Library Server or MLR distribution
' r5 e9 m- N3 D; q! s, T1711373 ALLEGRO_EDITOR COLOR Cannot interact with Allegro PCB Editor when Color dialog is open
- U5 \/ H) `5 W6 u; u1710772 ALLEGRO_EDITOR DATABASE Mirror command not working on zones
, b0 h7 {. H8 |' {, q1725621 ALLEGRO_EDITOR DATABASE PCB Editor crashes when moving a group of components or clines
# @. H" n4 L8 q+ U7 G, Q1699796 ALLEGRO_EDITOR EDIT_ETCH AiDT fails and reports there are no timing constraints even when propagation delay is set
2 C9 F6 A* H, l% B7 j1726483 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashing when converting corners to arcs" q" S" |! |. `' l o
1726678 ALLEGRO_EDITOR INTERFACES IDX copper layer export does not export all pin pads
0 t1 R; e5 i$ K5 Y! S1691036 ALLEGRO_EDITOR MANUFACT Fillet not centered on trace) M2 g9 d" v; D& z: c8 I1 G
1732304 ALLEGRO_EDITOR MANUFACT Countersink does not have drill figure on NCCOUNTERDRILL-1 subclass
9 P/ v# V, W* U# ^0 F5 `) e1719564 ALLEGRO_EDITOR OTHER Cannot open PDF published in release 17.2-2016 in third-party software
$ S! o3 }! c8 a" h1723065 ALLEGRO_EDITOR OTHER PDF out does not print the outline correctly$ j# ^+ n8 M" H
1729247 ALLEGRO_EDITOR OTHER Cannot delete shape on Route Keepout layer3 l3 `; Q. z0 M6 Q
1722747 ALLEGRO_EDITOR PAD_EDITOR Option to enable 'Connect by Touch' in Pad Editor
: c( U, I/ i# C5 B) P8 S1731643 ALLEGRO_EDITOR PAD_EDITOR Changes to secondary drill are not saved on padstack update
# {! ^* S- Z: O7 b1727303 ALLEGRO_EDITOR REPORTS The 'Shape Dynamic State' report has changed to 'Shape Dynamic Status' in release 17.2-2016 l8 K0 G6 k$ ~% `/ l; e8 U) W q
1695879 ALLEGRO_EDITOR SHAPE Dynamic shape priority error creates shorts.$ m! f$ Z; V) J" D* K' S
1713014 ALLEGRO_EDITOR SHAPE Incorrect behavior of donut shaped pads at certain rotations4 j, O7 P: f3 ?( |: ?5 Q" _& y p. W
1588769 ALLEGRO_EDITOR UI_GENERAL Alt+key shortcuts are not available in release 17.2) b/ s# |4 L: h$ t4 B$ h1 t; K
1602563 ALLEGRO_EDITOR UI_GENERAL Shortcuts to menu items not working in release 17.23 l9 e5 E/ r# Z2 l8 I
1603776 ALLEGRO_EDITOR UI_GENERAL Alt key not working with menu commands: Z: {6 a y6 q/ r
1611516 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts have no response' }" @' @9 x0 }( T, a$ _8 }
1647271 ALLEGRO_EDITOR UI_GENERAL Preselection is not working for docked Find window r0 I" ]7 e; h5 L
1650044 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts are not working properly in release 17.2
( v/ e8 m7 C/ W1651912 ALLEGRO_EDITOR UI_GENERAL Inconsistent response when using the Alt key6 p/ N; F3 `. z+ L- c
1679964 ALLEGRO_EDITOR UI_GENERAL Many dialog boxes are blurred in Allegro PCB Editor/ L& E$ U& j# {. m/ m% D
1692416 ALLEGRO_EDITOR UI_GENERAL Underscores in menu commands denoting shortcuts are missing in release 17.2
. v9 R; C+ r+ f7 g7 Y+ E+ _1693055 ALLEGRO_EDITOR UI_GENERAL Reports with html links end with an extra > at the end: l8 R2 ?' o, f
1693968 ALLEGRO_EDITOR UI_GENERAL Batch process that uses SKILL is taking too long to process files and generate reports1 W7 X; ^' Y* C. c p @6 v
1698840 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016 Waive DRC report, selected coordinates of a Waived DRC remain blue) u% g( e, _( @ C& r
1703065 ALLEGRO_EDITOR UI_GENERAL Menu shortcuts do not work as expected
4 p. Q1 u& B% }$ u# z1707547 ALLEGRO_EDITOR UI_GENERAL Release 17.2: The Alt key function is not working in PCB Editor
V/ ~4 y; J% C4 I+ p+ P1709280 ALLEGRO_EDITOR UI_GENERAL Alt+Function key not working in release 17.2.
: Q) V; C% M- U* s$ X# G' q1 R1711203 ALLEGRO_EDITOR UI_GENERAL Color does not change for selected coordinates in reports and Show Element: Y, O& e: k: S2 g# n) K
1711724 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, custom interactive menus stop responding when invoking another custom command
' o9 p+ ?- I. D7 q$ p2 v, U1715613 ALLEGRO_EDITOR UI_GENERAL With undocked Options window there is a mix up of entered text and funckey
, ]$ F! }0 m% _: Q0 q1 A% K E9 ^- k- I2 Z1719301 ALLEGRO_EDITOR UI_GENERAL Selected coordinates do not change color in reports and Show Element( E- W9 L) l6 ]
1724197 ALLEGRO_EDITOR UI_GENERAL Short cuts and hot keys not working in PCB Editor in release 17.2-2016
, K& ] z8 A( ]7 u2 c1728724 ALLEGRO_EDITOR UI_GENERAL Funckey is not working in release 17.2-2016
* F3 ~+ N* W7 ^1673703 ALLEGRO_PROD_TOOLB OTHERS Design compare not reporting the Top and Bottom layer differences( R) i* S( |) H
1704474 ALLEGRO_PROD_TOOLB OTHERS When using Productivity Toolkit - PCB Design Compare, 'Override undefined width' is incorrectly applied1 l. x4 K3 U/ r7 Q( H) V
1571035 ALTM_TRANSLATOR CAPTURE Circles in third-party schematics not getting translated into Capture
* F1 L% [3 m, e6 @8 R( d! G1588911 ALTM_TRANSLATOR CAPTURE Capture crashes when translating, project and libraries are empty
1 P. z" q9 a# k& Q8 y1589394 ALTM_TRANSLATOR CAPTURE Schematic getting shifted off the page after translation
" V6 c. W+ u6 f8 B. c( g1631294 ALTM_TRANSLATOR CAPTURE Errors while translating third-party design when original design is in metric units
4 k I+ Q: a% ?2 g: d8 }+ A1663176 ALTM_TRANSLATOR CAPTURE Only first sheet of design getting translated from third-party schematic into Capture2 T+ W$ ?' I) X: k' j W+ s( b
1694363 ALTM_TRANSLATOR CAPTURE Capture is unable to translate third-party designs# S; J. m1 n! T: U$ t: z
1539739 ALTM_TRANSLATOR CORE Capture crashes on importing a third-party project
7 G6 G0 B, p$ x( D1542860 ALTM_TRANSLATOR CORE Capture crashes on clicking Translate after selecting a third-party design+ V7 U+ C4 e5 e s( G) t! M
1551642 ALTM_TRANSLATOR CORE Unable to import third-party schematics into Capture- R9 x: g( x, [
1572929 ALTM_TRANSLATOR CORE Footprint names getting altered during translation1 ]+ }+ k2 ~* t! Z- [3 x7 E
1568436 ALTM_TRANSLATOR PCB_EDITOR Unable to translate third-party layout data into PCB Editor+ N# B% ?8 u( ~% i
1629256 ALTM_TRANSLATOR PCB_EDITOR Getting empty symbol and devices folders when importing into PCB Editor
" |% A7 a- x% ]8 d1664120 ALTM_TRANSLATOR PCB_EDITOR Import from third-party to PCB Editor is not translating data correctly
) z1 i! u4 i/ R+ z* |8 p. b" a0 s1701537 ALTM_TRANSLATOR PCB_EDITOR Import does not complete and reports errors
0 w: r2 v& k- W. C6 h; h1698706 APD DIE_GENERATOR When using Compose Symbol from Geometry, circle from DXF cannot generate to pin
: [3 y% N+ c4 ^0 @# J1714528 APD DIE_GENERATOR Getting 'illegal pad pointer' warning when creating die from geometry2 P3 V: T9 a1 @) |" w
1714532 APD DIE_GENERATOR Compose Die from Geometry creates incorrect pad shapes
, ?9 { X( H1 w0 [% v" ~) U1734310 APD MULTI_USER Symphony server mode malfunctions when die layer present.
/ s) u: U$ w, h# j2 B/ Z1 F$ P1 O1725506 APD SHAPE In release 17.2-2016 Hotfix 015, void is not generated in Artwork for BC7 layer causing short# d9 p: M& c3 ^1 s2 V- J# d
1724395 APD WIREBOND Running axlBondWireDelete returns error message0 f' j& R7 Y) \2 W$ V& S% T& n6 c7 ]- [* K
1726609 ASDA CANVAS_EDIT Paste should not be allowed in the Current Refdes column of the Change Refdes form
2 X* \+ J- n0 ^* g7 Y1719754 CONCEPT_HDL ARCHIVER Path stored in the compressed file starts from /home instead of the current working directory
B" a; h! {* t" P- X1726570 CONCEPT_HDL CHECKPLUS Checkplus crashes on Windows 10
9 |; }* y$ V0 s" F6 B5 U5 v/ Q7 n7 N1697977 CONCEPT_HDL CONSTRAINT_MG Differential pair disappears when it is packaged* w# j# s6 V" ]( U
1679575 CONCEPT_HDL CORE Page numbers are duplicated in Hierarchy Viewer when editing page names
& c3 M7 \0 @+ {7 I1697732 CONCEPT_HDL CORE Pasting a signal name results in warning (SPCOCN-922) if the wire is too close to the edge of the page border5 F$ J( Q& j$ ~% ~- R
1711564 CONCEPT_HDL CREFER CRefer crashes while processing a hierarchical design containing subdesigns
8 _/ L$ \' n% k+ U) |0 [# O1730736 CONCEPT_HDL OTHER Crash on generating BOM from design
) t) A5 ^- {5 P2 g4 I1608350 CONSTRAINT_MGR CONCEPT_HDL Name of buffer model is not passed from Constraint Manager of DE-HDL to SigXplorer
- X! l! _( y9 |& P) x& Z1 i1715803 CONSTRAINT_MGR CONCEPT_HDL Extract a net from constraint manager to SigXplorer, the models assigned are not displayed in SigXplorer
& v% S+ N/ b6 f. j: j5 ]" W1 D; n1718073 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors on an upreved design in release 17.2: Pins in XNet and CSet do not match% p5 s( O- d% L6 N6 v
1720886 CONSTRAINT_MGR CONCEPT_HDL SigXplorer does not extract assigned model from the schematic
5 V T$ |/ u0 [3 U+ `% d1718514 CONSTRAINT_MGR ECS_APPLY Extracted topology does not use the PINUSE overrides specified on the canvas
1 l1 [" c3 N j( S( |& B) t( U1722306 GRE CORE Boards with Total Etch Length constraint only should not include z-axis when budgeting pin pairs* e* f; f# \% ^. Z
1710049 PSPICE SIMULATOR Functions are not taking parameters in correct order
7 f0 Q; J% ?8 L2 E1693021 SIG_INTEGRITY OTHER PINUSE is not updated correctly at model assignment with specific steps) x$ O# R. U% d1 d- |2 c D
1730854 SIP_LAYOUT SYMB_EDIT_APP Cannot delete all the die pin from a symbol using the Symbol Edit application mode' C: m7 H- B5 }2 I; M; I5 i
" X2 ^9 Q7 i5 |
( Y- C5 ]) M' _6 |/ v
Fixed CCRs: SPB 17.2 HF017
/ ?8 p4 i6 t- Y; F5 ^$ N0 k04-13-2017
) ~8 e; I7 ~* ^# N0 a: I/ l2 e========================================================================================================================================================
9 t+ r( V" }8 HCCRID Product ProductLevel2 Title6 y8 \4 x+ u7 u _5 a f
========================================================================================================================================================
! V& y0 r4 L+ T2 p' N6 i! ~- b* O1732877 ALLEGRO_EDITOR SKILL The 'axlXSectionGet' function fails in release 17.2 Hotfix 016* f9 x$ q a2 d( d1 I
! F& U( h. G& Z: A; L1 X
6 @& _( [& `3 o7 A' U; h; Y0 r+ dFixed CCRs: SPB 17.2 HF016
1 \- N, w" g& ^" c04-6-2017
! h# P6 g. T- Q, Q========================================================================================================================================================0 O0 q8 _- W0 ~9 c6 [2 X# f
CCRID Product ProductLevel2 Title; D8 @, l @1 l9 z7 O0 u
========================================================================================================================================================
. G [% o; S. J; k0 I7 [1673128 ADW COMPONENT_BRO Directive is saved in project CPM
$ e1 u/ ^5 V; T: h1 e8 q$ v3 d1673510 ADW COMPONENT_BRO Lifecycle status color column is not sorted correctly in Component Browser search results- ^; l* |, K) I2 C0 ~
1604734 ADW DATABASE Parts displaying non-key properties and values in the Component Browser in ADW0 k* ?8 W5 S J5 b% B( \4 M
1142957 ADW DSN_FLOW No Help available for schematic design verification
' i2 r& `/ F1 F4 z1609186 ADW DSN_MIGRATION ADW Design Migration utility should handle ADW board reference projects and manage atdm.ini
& D2 ?+ o# B1 }& S+ u$ z! E) O5 v9 P1591757 ADW GENERIC_UI Running 'Create Test Schematic' in ADW Flow Manager results in Error SPCOCN-1736
! X5 @4 A Y& i$ s1588111 ADW LIBIMPORT Library Import fails with Java errors while processing .csv files
" n, c. J' Q" \3 f1642367 ALLEGRO_EDITOR 3D_CANVAS Component height is not correct in new 3D Viewer' Z# j* O+ F3 i( N9 w
1642668 ALLEGRO_EDITOR 3D_CANVAS The new 3D canvas does not show STEP model of the drawing (.dra)- p e$ W( s! |( d4 x. @' L, G1 W
1653247 ALLEGRO_EDITOR 3D_CANVAS New interactive 3D Viewer shows wrong placement
$ h8 ?2 Q+ D2 L' p. c1658275 ALLEGRO_EDITOR 3D_CANVAS Components on the bottom side are shifted in the new 3D view
4 G- V9 O& Q, X! f; ~& G6 V& l1639244 ALLEGRO_EDITOR ARTWORK When importing an artwork, a sub-folder is created with the value of the ads_sdart environment variable
- v* a2 q z, M; \3 V0 y1658173 ALLEGRO_EDITOR ARTWORK ARTWORK: Value of Scale factor for output.' ?3 q( L% g( ^! ^& b
1661760 ALLEGRO_EDITOR ARTWORK Import artwork to Design Outline layer does not give error in Allegro prompt.: h! ?! |0 }" e
1667778 ALLEGRO_EDITOR COLOR Add option to set FORM mini dehl_retain_color to NO
( S( s4 r- K: G+ i1 g/ I1669462 ALLEGRO_EDITOR COLOR Changes made to the Visibility tab are not reflected in the Color Dialog window2 K2 V$ ]: ]/ m! d; b
1641265 ALLEGRO_EDITOR CROSS_SECTION The differential impedance value for a layer is not getting updated
; |" R; {: x- C5 U/ b1648149 ALLEGRO_EDITOR CROSS_SECTION Getting warning when calculating impedance in mixed stackup" Y1 T% a) }: z! H7 k) b1 ?
1671441 ALLEGRO_EDITOR CROSS_SECTION Enhancement request for cross section dialog box( S9 X- m2 z8 }7 x1 ?" I* t* ^ X
1673320 ALLEGRO_EDITOR CROSS_SECTION Diff impedance calculation fails( c6 V: L4 U5 ?2 `9 [& _2 x+ K
1690021 ALLEGRO_EDITOR CROSS_SECTION How to keep settings of expanded/compressed columns in the Xsection, l3 u. F5 x+ e& d8 ?/ {
1703831 ALLEGRO_EDITOR CROSS_SECTION Calculation of Diff Z0 fails in flex designs: H; W& N. o0 @ H0 {
1711484 ALLEGRO_EDITOR CROSS_SECTION ShowAll Column does not retain its status
$ ^" g& _" }& J; {+ \1672841 ALLEGRO_EDITOR DATABASE ERROR(SPMHDB-153): Table corrupt; current/maximum mismatch
& J: m2 |# i# j6 T1673613 ALLEGRO_EDITOR DATABASE COVERLAY_TOP not present in the Non-conductor section of Color Dialog window% G3 x1 f- b" u0 ^0 X! V
1688123 ALLEGRO_EDITOR DATABASE Drill Plating Issue
( }+ Y% ?- m e0 |1701995 ALLEGRO_EDITOR DATABASE When upreving a 16.6 brd to release 17.2, lines drawn on OUTLINE are translated to CUTOUT and not DESIGN_OUTLINE
+ x$ g7 w1 o3 L u3 g4 F1710772 ALLEGRO_EDITOR DATABASE Mirror command not working on zones
! f" ]$ v1 Y5 ?2 X/ }& s1713335 ALLEGRO_EDITOR DATABASE Defining Adjacent_layer_keepout_above and/or Adjacent_layer_keepout_below and then saving the .dra file giving error l4 |- \1 n* C
1693289 ALLEGRO_EDITOR DFA File - Save As script does not save the DFA file2 r9 m9 H0 Z& z" V Y3 N2 H
1644004 ALLEGRO_EDITOR DRC_CONSTR Unreported DRCs from dynamic copper to line and dynamic copper to SMT pin
2 x7 Y+ s! {% u4 ^- _% B. s; O1651425 ALLEGRO_EDITOR DRC_CONSTR The .brd file crashes when moving text controlled with minimum metal to metal constraints- S$ p% u( q- Y7 X) {6 b9 Z
1663494 ALLEGRO_EDITOR DRC_CONSTR Reported Mechanical Pin to conductor spacing DRC constraint value is incorrect leading to false DRCs6 T5 T8 s# E( n- r
1687049 ALLEGRO_EDITOR EDIT_ETCH Create a Via Structure disconnects nets
/ x& m& Y% ~) e0 T2 X; z1704296 ALLEGRO_EDITOR EDIT_ETCH Asymmetrical fanout created for BGA Quadrant style1 n) x: t2 b; o: X a, q+ k+ _, f
1686873 ALLEGRO_EDITOR EDIT_SHAPE Merge static shapes deletes both the shapes selected.) i. U% v: L2 Q: H
1629925 ALLEGRO_EDITOR GRAPHICS Errors reported and no layout data drawn in PCB Editor in release 17.2 Hotfix 003 on Ubuntu 14.04* Y& D& e+ T/ _# I5 r/ {5 l
1628895 ALLEGRO_EDITOR INTERACTIV Shape Edit mode: An error message is required when attempting to edit a Shape with the FIXED property/ {9 x. n( U8 z: b s# `' B
1666379 ALLEGRO_EDITOR INTERACTIV Place replicate is not working on the attached test case
( E" C! G5 e5 O6 x7 Y5 a1668282 ALLEGRO_EDITOR INTERACTIV Grid display incorrect for repeated grids
0 @4 n( b* D/ D6 n- _1675531 ALLEGRO_EDITOR INTERACTIV Design Entry CIS: Cross Probing with PCB Editor and Constraint Manager is not working
2 l. n+ C) ?. o( z1694470 ALLEGRO_EDITOR INTERACTIV Update description of variable padstack_nowarning_display
7 I z# S! L7 D8 K4 J& U/ P1696855 ALLEGRO_EDITOR INTERACTIV Mixed grid setting is not displayed correctly on Define Grid screen.$ R, E' d2 D' H, p: j; v& J. \
1698192 ALLEGRO_EDITOR INTERACTIV Deleting and replacing a component causing database corruption in Hotfix 0098 G7 o6 ~5 n7 p" a$ A/ l0 @ {
1703671 ALLEGRO_EDITOR INTERACTIV An error occurs when defining grids with zero increment value/ z+ M" p- A, Q6 O, L
1703812 ALLEGRO_EDITOR INTERACTIV Crash during move when using the 'snap pick to' option set to symbol origin* G. @6 b4 Y* p( B6 k4 P
1719276 ALLEGRO_EDITOR INTERACTIV Setting variable grid for 'All Etch' displays an error in the Define Grid form
& v1 L& @3 c ?/ U( G1663422 ALLEGRO_EDITOR INTERFACES Shape loses group membership after importing through sub-drawing" y( d X0 Z& \; W$ L
1637959 ALLEGRO_EDITOR MANUFACT Thieving uses different clearance values around the route keepin.
+ V; P: Q# O' N) k7 H0 |0 Q9 J1716431 ALLEGRO_EDITOR MANUFACT Test points generation stops due to an error
: W9 I: d2 Z5 J) ]1641994 ALLEGRO_EDITOR OTHER DB Doctor: Incorrect spelling of 'eliminated' in the log file messages( v' W# R9 n* ?) ` R) B2 G
1660496 ALLEGRO_EDITOR OTHER SiP Layout crashes when trying to generate abstract level view by using export chips and connectivity
# r0 d; |5 l4 k' y1685464 ALLEGRO_EDITOR OTHER The 'alias ~S save' command is not recognized when set in the local env file
6 m; m3 a9 I6 y( f p3 \7 T1696486 ALLEGRO_EDITOR OTHER STEP export results vary between releases 16.6 and 17.22 h4 ~! u9 W/ T6 O# A% M2 |
1706623 ALLEGRO_EDITOR OTHER axlBackdrillGet crashes for invalid argument# U( T8 c. u6 H/ W2 b
1586957 ALLEGRO_EDITOR PAD_EDITOR In Pad Editor, selecting a pad geometry is not showing up in the Design Layers tab7 p/ C7 F4 T% d) u! r2 w* w. L; v- b
1610984 ALLEGRO_EDITOR PAD_EDITOR Geometry set in tabs not read, only initial value set in Start page is used
' e0 x' \4 w! J- b p2 O ^: `1614015 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor in release 17.2 does not auto fill geometry in design layers
' W3 Q; T* t$ j7 `$ d! }) R, e6 s1636012 ALLEGRO_EDITOR PAD_EDITOR Keepout should not be allowed if antipad is not defined for outer layers' N( I [/ X( A) G
1641973 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor: Path to the previously opened .pad file is not seeded in the File - Open dialog on a fresh launch
6 |- n* P- o' d% U1642789 ALLEGRO_EDITOR PAD_EDITOR In release 17.2, 'Units' and 'Decimal Places' in Padstack Editor are not updated as per the .pad file% Y+ ?0 r% K n( B, ^+ B; J
1646914 ALLEGRO_EDITOR PAD_EDITOR The 'Save' button is grayed out in Padstack Editor1 g. L* |! @% ~% g6 e Y1 U" J
1657553 ALLEGRO_EDITOR PAD_EDITOR No possibility to specify Padstack Editor default library path at invocation1 G. y* d2 V _2 p/ r$ @0 ?
1657609 ALLEGRO_EDITOR PAD_EDITOR Changing Tolerance field in Padstack Editor does not activate the Save button4 }2 o9 C0 V y2 j! V8 r& c
1662225 ALLEGRO_EDITOR PAD_EDITOR Padstack editor dialog message doesn't match available options4 |1 j* B# k4 r5 M, ~8 N5 ^
1667062 ALLEGRO_EDITOR PAD_EDITOR Padstack editor does not retain the decimal places from the previous session; G+ Y8 b3 _2 H9 n7 q$ A. R
1672774 ALLEGRO_EDITOR PAD_EDITOR Pad Editor graphics appear to show offset incorrectly
' \% E2 z8 ~* x* e8 c1674157 ALLEGRO_EDITOR PAD_EDITOR Update Symbols does not update Pad Type Information
8 [% S! j% o7 p7 Q1 F0 v1675438 ALLEGRO_EDITOR PAD_EDITOR Drill hole size warning for the SMD pad1 O' `" l4 D" O0 Z! g
1684376 ALLEGRO_EDITOR PAD_EDITOR Pad Editor issues with settings, such as decimal places, layers, and so on1 T, w5 X9 M3 _: q% l
1690376 ALLEGRO_EDITOR PAD_EDITOR Variable padstack_nowarning_display fails to suppress warnings
. n1 v5 R5 H ]' K }* [+ k1694649 ALLEGRO_EDITOR PAD_EDITOR Change Cancel button to No in warning generated when updating padstacks in design layout- K$ u/ I9 y/ y, J- y: n
939242 ALLEGRO_EDITOR PLACEMENT Cross probing between Capture and PCB Editor is inconsistent
3 Y! Y5 N( H6 O1103945 ALLEGRO_EDITOR PLACEMENT Place Replicate Create does not include the etch connected to pin
4 M: Q0 `1 ?+ e+ N9 A1233019 ALLEGRO_EDITOR PLACEMENT Allow cross probe object selection apart from highlighting during place replicate& E: B% J' W% n* X5 Y9 @! R
1643078 ALLEGRO_EDITOR PLACEMENT PCB Editor flags an error message when a module is placed at a specific angle
- q" `2 ]$ B: A2 C7 a1696932 ALLEGRO_EDITOR PLACEMENT Inconsistency with Snap pick to when selecting Segment Midpoint* }/ ~* A- \. ^
1654500 ALLEGRO_EDITOR REPORTS In release 17.2 Hotfix 006, display of Netin (back anno.) report fails when variable ads_sdreport is set
7 {' B( w, s% \2 T7 [1643992 ALLEGRO_EDITOR SCHEM_FTB Export Physical fails with the 'netrev.exe has stopped working' error
' {. ]; X' m0 x8 ?1653400 ALLEGRO_EDITOR SHAPE Dynamic shape does not void a via. Q% \; P! Y& o+ p2 u4 L0 D
1668262 ALLEGRO_EDITOR SHAPE dynamic shape does not void custom route keepout with arc; C' G% K: u8 |
1682569 ALLEGRO_EDITOR SHAPE Variable 'dv_squarecorners' not working correctly.: q7 |6 T! S# j2 w
1696240 ALLEGRO_EDITOR SHAPE SKILL error when merging polygons
6 G! c8 u4 z% X; A; _1709968 ALLEGRO_EDITOR SHAPE In release 17.2, DB Doctor reports error in shape when no error was reported in release 16.6 for the same shape" z, X' A0 W4 {/ {7 Q# v, P
1632505 ALLEGRO_EDITOR SKILL In release 17.2 Hotfix 004, PCB Editor crashes after SRM update and save
7 o+ b) a, Z' p2 y+ }' z; ?1651701 ALLEGRO_EDITOR SKILL Cannot set the etch factor value in the cross-section using the axlXSectionModify() SKILL command+ l e2 D9 W0 D
1658419 ALLEGRO_EDITOR SKILL PCB Editor crashes after running SRM
* Z7 q+ h/ i) F( @6 @1658948 ALLEGRO_EDITOR SKILL axlIsLayerNegative() is not working in release 17.2
+ U) g: G) @9 Z, C$ w1670956 ALLEGRO_EDITOR SKILL axlIsLayerNegative() always returns nil- `! }! q, g/ F m6 l6 E9 @# R
1687239 ALLEGRO_EDITOR SKILL Problem with SKILL function axlCNSGetPhysical - incorrect parse string
' I9 P1 N( ~+ n m1692345 ALLEGRO_EDITOR SKILL The axlGetParm documentation example for deleting an artwork record is incorrect.+ w) R5 }- V! y6 `# ]2 U
1707878 ALLEGRO_EDITOR SKILL Object rat_t does not work with axlDBPinPairLength.( y1 Y8 H" v9 n
1598061 ALLEGRO_EDITOR UI_GENERAL Adjust menus to allow side by side view# @- R: C; U4 S! }! T! H
1599901 ALLEGRO_EDITOR UI_GENERAL Color Dialog box is not updating according to visibility tab.
7 R. t6 x' | Y1602563 ALLEGRO_EDITOR UI_GENERAL Shortcuts to menu items not working in release 17.2
# P [/ f. s- m1603776 ALLEGRO_EDITOR UI_GENERAL Alt key not working with menu commands1 P# Y# M5 I9 N. y
1611516 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts have no response$ ?" ?6 q, `# q; f+ t6 l: D9 u2 Q* V: r
1614763 ALLEGRO_EDITOR UI_GENERAL Cannot scroll to the bottom of an undocked command window in PCB Editor: Y$ ?$ _/ o# ]' k
1619873 ALLEGRO_EDITOR UI_GENERAL Command Window scrollbar does not reach its end/ h1 |7 ^; V! X2 ]
1624617 ALLEGRO_EDITOR UI_GENERAL Dialog box title under Setup > Outlines > Design Outline... Design is misspelled as "Desgin"! s9 T" F, m- M) a9 N' {5 `
1631646 ALLEGRO_EDITOR UI_GENERAL Visibility pane not retaining the correct layer view/ s: L( | X6 r2 c
1637062 ALLEGRO_EDITOR UI_GENERAL The last line of the floating command window in release 17.2 is hidden behind the command window frame
P+ ?# o! N6 U2 `- c( E1642645 ALLEGRO_EDITOR UI_GENERAL Cannot scroll to the bottom of an undocked command window in PCB Editor7 L' x! X( g/ I. l; l
1645335 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes in Hotfixes 004 and 005 if ODE and Allegro Manufacturing options are installed. ]( ?: K1 X5 \5 n$ i; d# N% U4 J
1647520 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes after installing release 17.2 Hotfix 005: @3 i* k3 i0 Z* X1 I; r
1647541 ALLEGRO_EDITOR UI_GENERAL Release 17.2 Hotfix 005: PCB Editor crashes immediately after launch; p/ h( Z7 ^/ ~* F
1650044 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts are not working properly in release 17.2. F' a' I3 c) h, \! I. i! u
1651912 ALLEGRO_EDITOR UI_GENERAL Inconsistent response when using the Alt key
7 W" S# [3 T; W* A! r; [. U9 K1652423 ALLEGRO_EDITOR UI_GENERAL Using the F1 key does not display the help document" `& [3 j: s# d p! |4 f6 u: X
1654600 ALLEGRO_EDITOR UI_GENERAL Spelling Mistake in "Design Outline" dialog box, Setup->Outlines->Design Outline, misspelled as "Desgin"
% H: f( E7 B/ _! _" B; [ p3 W- L2 ~1654777 ALLEGRO_EDITOR UI_GENERAL Reports UI does not work properly when writing a report file.$ |0 {& \+ @& y$ |9 H* {( F9 U) u
1655500 ALLEGRO_EDITOR UI_GENERAL Visibility selection ignored after color change, a! h# H, N! v/ V- g9 U) T
1655514 ALLEGRO_EDITOR UI_GENERAL Artwork Film is available in the View section only after you restart PCB Editor
; n" s! T3 ]. E( t) a* N+ A* t& O1663819 ALLEGRO_EDITOR UI_GENERAL In release 17.2, SKILL function, axlOpenDesign(), does not work as expected
) _6 \, `9 |" v% M' V9 Q- l* h1671334 ALLEGRO_EDITOR UI_GENERAL Design outline is not shown in 'World View' window
; i# k* R3 C; ?: e, B% h+ a5 ^1672148 ALLEGRO_EDITOR UI_GENERAL Add option in release 17.2 to change the placement of the Find, Visibility, and Options tabs similar to earlier release' e# X- ^& D) A7 Y' ?
1679418 ALLEGRO_EDITOR UI_GENERAL On choosing Edit - Move, the 'Symbol pin #' box is obfuscated( m" D- m. f+ @' r k# j) z
1679761 ALLEGRO_EDITOR UI_GENERAL Choosing Edit - Spin hides 'Symbol pin #' partially3 Q) O1 Y! B4 A+ H5 ]( ^/ ?1 x
1686887 ALLEGRO_EDITOR UI_GENERAL Hyper Text no longer selects coordinates for easy copy
7 c' \; a, N& a1687286 ALLEGRO_EDITOR UI_GENERAL In 17.2 Hotfix 009, the Static Phase meter shows up in the middle of the screen instead of the lower-right corner
. ~( q/ J4 C3 L1692416 ALLEGRO_EDITOR UI_GENERAL Underscores in menu commands denoting shortcuts are missing in release 17.2: K0 n0 x( g7 Y) q3 }
1693968 ALLEGRO_EDITOR UI_GENERAL Batch process that uses SKILL is taking too long to process files and generate reports
8 A: ]4 F1 a9 Z- e# `- z, v+ E( j4 D1702420 ALLEGRO_EDITOR UI_GENERAL Unable to maximize reports viewer in 17.2
3 q4 v. U& j1 C. u; A p* |1703065 ALLEGRO_EDITOR UI_GENERAL Menu shortcuts do not work as expected& o0 T4 j" B9 v, {# g0 i
1703107 ALLEGRO_EDITOR UI_GENERAL Scripting using regional settings for decimal separator
$ o) A( @& e. X! t& U! v0 l% H9 L) A1707547 ALLEGRO_EDITOR UI_GENERAL Release 17.2: The Alt key function is not working in PCB Editor3 ~7 C; t8 E6 T# v2 A8 C
1709280 ALLEGRO_EDITOR UI_GENERAL Alt+Function key not working in release 17.2.# W# R: w7 g+ k/ W9 G& c0 ?9 ]
1639896 ALLEGRO_PROD_TOOLB CORE MFG collector does not move files to subdirectories
; _$ T* V9 G$ l' Z- t% f$ F1608804 ALTM_TRANSLATOR DE_HDL Translation issues in symbols with multiple physical pins mapping to a single logical function
% w1 }( |) _2 x% J, }1658525 ALTM_TRANSLATOR DE_HDL Invalid characters in pin names8 Z- k" x" h O5 ?# K
1658536 ALTM_TRANSLATOR DE_HDL All cell names should be generated in lowercase letters
M. M# r" c* Y5 F/ u* e% `, ~1609962 ALTM_TRANSLATOR PCB_EDITOR Errors reported during design translation
/ }9 Y$ W4 d# L3 L, B1661562 APD DRC_CONSTRAIN The wrong space calculation on finger to trace
4 @" F) A: i. `6 M% M: h; }3 T1682398 APD SHAPE Deleting islands causes out of date shapes
4 n) _: b! g4 y2 q8 J6 C1638112 ASDA CANVAS_EDIT Unable to rename multiple selected buses using the 'Assign Name' command f3 t6 F: C1 z3 m$ Z
1645571 ASDA CANVAS_EDIT Various routing inconsistencies with synonym bodies on the canvas
4 |' S9 z0 K: Q) X* a$ R1 F1656336 ASDA CANVAS_EDIT Presence of illegal characters in the net name removes the entire net name/ s5 D2 ^/ S6 ~( Z' \ @1 Q
1667176 ASDA CANVAS_EDIT Unable to add the port symbol in a specific scenario3 k3 z. P9 P! X5 a( u( m
1641473 ASDA CONSTRAINT_MA Importing a tech file into SDA makes the tool unresponsive
' w* X+ J! s: n: Q# i9 T' P) m1661350 ASDA CONSTRAINT_MA Unable to create physical & spacing class from the docked CM1 ?% c" z2 _. S0 { X; n4 Q
1645557 ASDA IMPORT_DEHDL_ Importing a DE-HDL design into SDA adds the COMMENT_BODY attribute to nets" s3 k. P5 k$ h& o3 k( ~4 w# m
1652753 ASDA MISCELLANEOUS Tcl command window should display correct casing for autocompleted command
+ d% P$ r D+ S5 _; d9 I6 }1654973 ASDA MISCELLANEOUS If there is a casing mismatch in the Tcl command name, correct command is not picked from the list
* n# D6 Y# o6 k: U$ M( p* ^+ b2 \7 c; B1652718 ASDA PAGE_MANAGEME Page numbering on the page border does not update correctly when pages are moved, added, deleted
% T( {9 B* x4 z3 S1699454 ASDA TABLE In the table object, cursor skips a cell on the first use of the TAB key. |0 a3 N2 W1 d. [- u, C& k* c+ n
1702702 ASDA TABLE Copy-pasting table objects to a new page fills the headers and rows in black7 s# I3 k, ?- S* N
1668877 CAPTURE ANNOTATE Using Ctrl+drag does not preserve the reference designator value
" L( R* M" o1 f1665454 CAPTURE NETGROUPS Incremental copy for alias does not work anymore.; @: L: F) i- _- c; V
1634598 CAPTURE OTHER The ‘OrCAD_Capture_CIS_option’ license not released even after selecting another product option6 b& l+ C8 j9 L
1636090 CAPTURE OTHER Capture crashes after switching from release 17.2 Hotfix 003 to 004 due to some Tcl files. H. r9 G/ z) D( f8 p) w
1650029 CAPTURE OTHER Crash while archiving a newly created PSpice project without adding simulation profile2 ~3 ]5 ~; _! o+ i4 g8 H, E* \. v
1659602 CAPTURE OTHER Saving CIS BOM via TCL command window' O( P' y/ _# ], t4 z$ I }9 b
1678715 CAPTURE OTHER Capture.ini [WebResourcesMenu] is not working in release 17.2
% R( [3 W, w( C/ L. U' | ~, W- u- n1619449 CAPTURE PROJECT_MANAG Search not working in a PSpice project* A6 [- Q6 U% Q: R9 Y
1670133 CAPTURE PROJECT_MANAG Start Page showing wrong Software Version$ F: _& l( B! [! L b8 x
1670766 CAPTURE PROJECT_MANAG autoreference does not work properly
, [4 C6 [; |6 I/ F! A- X4 |; s1676095 CAPTURE PROJECT_MANAG (SID:22758) OrCAD Capture Start Page reporting wrong hotfix installed6 O6 f0 _3 I" L4 l4 \5 d- c
1658315 CAPTURE TCL_INTERFACE Inserting text with double quotes is not working as expected in PDF created from Capture
+ n% M: V8 j" P& E. t& t$ \! L1642601 CIS OTHER Design Entry CIS: SQL server password is required each time the tool is launched! J8 k. ~, n1 @& X
1712279 CONCEPT_HDL CONSTRAINT_MG Differential pairs are dropped from Net Classes when upreved to release 17.2-2016+ P) p" I, Z' c) ]* i/ o q
1665449 CONCEPT_HDL COPY_PROJECT Copy project fails with error COPYPROJ-777 K& t2 k; r, h" F
1661778 CONCEPT_HDL CORE Advanced Find will not find pins with the SIG_NAME property attached D) s0 {6 d# R$ F p
1666084 CONCEPT_HDL CORE All user-defined properties are not listed in the Customize columns in Variant Editor9 u1 M* Q* z$ I* g. q6 T
1667043 CONCEPT_HDL CORE Incorrect information in cpm.log file
6 v# ?0 o1 j% i) ]' {' W1670659 CONCEPT_HDL CORE SIGNAME text off grid when pasting copy using ctrl+v.! p7 D2 g; S0 z: M
1697732 CONCEPT_HDL CORE Warning (SPCOCN-922): The object is being placed towards the left edge of the schematic. Ensure that the objects are pla
& G& e9 L" |7 r! j) E1697955 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net( F& N- s6 h- F* P0 e
1711635 CONCEPT_HDL CORE The arrow keys do not work as expected in Windows mode
/ c9 Z* J8 v- {. z3 s6 x' A# \1713091 CONCEPT_HDL CORE Difference in the behavior of 'Add Signal Name' in DE-HDL between releases 16.6 and 17.2
Y- P1 @- y# m; o' z/ C) f1708820 CONCEPT_HDL OTHER In a board cache flow, component bodies are missing when importing another board cached flow project.
. z5 T+ L% [0 } @$ |$ O. {+ @$ J1639928 CONSTRAINT_MGR CONCEPT_HDL The '-filterFile' argument is not recognized when cmDiffUtility is run as a command line operation5 T3 o: f' g" T* R
1657048 CONSTRAINT_MGR CONCEPT_HDL Unable to navigate through the search results in the CM Reports
3 O: y) ]0 R! B4 ~0 w: I3 p1718073 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors on an upreved design in release 17.2: Pins in XNet and CSet do not match
1 s1 G/ F" {/ X5 o% P1717336 CONSTRAINT_MGR DATABASE Netclass members change during logic import; it's a toggle switch& c- }5 k8 Z! t2 }
1718514 CONSTRAINT_MGR ECS_APPLY Extracted topology does not use the PINUSE overrides specified on the canvas
& R% L/ a2 z9 `. d. y- r1682885 CONSTRAINT_MGR INTERACTIV Constraint Manager worksheet switching does not work correctly in Linux
! ~& t5 G, n* a2 U1669523 CONSTRAINT_MGR OTHER Select is disabled in Constraint Manager when a command is active in PCB Editor
/ J- [; T. L; b- J( o9 F4 J1670802 CONSTRAINT_MGR OTHER Selecting a list of nets using the shift key does not work in Spacing and Physical domain+ j3 p; K# n, S
1670922 CONSTRAINT_MGR OTHER Title of the Layer Remove window is Constraint Manager
, U/ |9 N/ B% F4 Q5 a" l" C; \+ J1678235 CONSTRAINT_MGR OTHER Select option grayed out in Constraint Manager if a command is active in PCB Editor, r0 M5 z l( Q* K5 K4 m4 V
1680917 CONSTRAINT_MGR OTHER In release 17.2, nets cannot be selected in Constraint Manager when a PCB Editor command is active" k d6 K' Y; s
1691125 CONSTRAINT_MGR OTHER Highlight command no longer selects the net in CM* I! x { y4 }* s& a
1703791 CONSTRAINT_MGR OTHER Cross highlighting and assigning color to nets between PCB Editor and CM does not work
: p. S9 @1 Q4 h6 K# ~5 l$ \1649603 CONSTRAINT_MGR UI_FORMS Expand and Collapse commands do not work when multiple objects are selected3 g' x6 D' G. B5 G
1654931 CONSTRAINT_MGR UI_FORMS Expand, collapse only works on one of the multiple selected objects.$ d7 J( x% e0 j
1668794 CONSTRAINT_MGR UI_FORMS Incorrect via name shown when filtering via list
+ T/ C; F- |( e" s# f- D s1678305 CONSTRAINT_MGR UI_FORMS Unable to use the CM worksheet customization (wcfx) from the CDS_SITE area
% @: i- S8 P, h$ O1679909 CONSTRAINT_MGR UI_FORMS Incorrect layer order getting saved when defining BB vias in Constraint Manager PCSet: k8 Q$ u/ j' c# _
1691906 CONSTRAINT_MGR UI_FORMS Display Issue: When you use the filters, the horizontal scroll bars are duplicated) |; z2 u; p9 K' P3 _0 O
1677893 ECW INTEGRATION Integrations list update is not working as per scheduled time
2 j+ u8 j$ ~5 m5 [) x z1 r1652707 ECW METRICS Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart
4 f. x5 |5 i& \( {0 [1 d) V1654512 ECW METRICS Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart
# [4 i4 w: K, v) T, z7 o, }1 v- L/ ^1668953 ECW METRICS IE11 Swedish only: Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart1 N, P$ Z8 k) v+ g2 l" Z: Q" J
1677443 ECW METRICS Queued up metric packets on Pulse server are not processed if there are any packets related to a deleted project
6 z: P! Z3 `5 U: h2 a1663676 F2B PACKAGERXL Physical net name (PNN) errors in the log file6 {3 i3 V4 g; G( b
1669583 GRE DETAIL AiDT always fails push when there is a connect shape attached to the cline being tuned$ g# q6 u6 J2 p
1686350 INSTALLATION SPB InstallDiagnose fails to repair some errors
1 Y( Z% e: ^, a! R1672369 PCB_LIBRARIAN EXPLORER Cannot create a New library build in Library Explorer.5 c6 e) l" C; o7 _% U
1631034 PSPICE ENVIRONMENT When simulating the design in release 17.2, Capture crashes but works with release 16.6
, [6 U) W3 j7 j D8 z$ I1 f2 W1648284 PSPICE ENVIRONMENT PSpice project crashes when a design is opened in release 17.24 ^4 \; W2 D( Y! Z( U. X8 y
1663336 PSPICE MODELEDITOR Ibis translation not supporting paths with spaces# d, l2 R( o' b1 |9 s
1679376 SIG_EXPLORER OTHER Topology created in OrCAD PCB SI license cannot be reopened with the same license/ f& m7 s k, n
1666484 SIP_LAYOUT CROSS_SECTION On converting a design from release 16.6 to release 17.2, a Dielectric thickness of ‘0.2032’ is added to another layer.
. u# G N6 D" u7 ~ L) \$ ^1687988 SIP_LAYOUT DIE_GENERATOR 'compose die from geometry' does not retain the user-defined padstack name
8 v7 y, ]; M1 e; L1 s) B& Y1715016 SIP_LAYOUT DIE_GENERATOR Using Die Text-In wizard to replace a die reconnects wire bonds to the wrong die in stack-up
?3 R; n* I! P4 y+ j# P1 |1620601 SIP_LAYOUT MANUFACTURING Need the ability to create LINES with round end caps in the same way as the LINES appear in the database3 t) [3 A) ?0 K& z; @& s
1705963 SIP_LAYOUT PADSTACK_EDIT Pad Designer: "None" changing spontaneously into "Circle 0.000" in a pad stack definition and unable to save! W9 F. ^9 V3 m
1713767 SIP_LAYOUT REPORTS Reports in release 17.2 for the Verilog Port Name are adding incorrect data that was not found in release 16.6
9 S$ b4 i2 d* ?9 @& a! B, V1696218 SIP_LAYOUT SKILL SiP Layout crashes on reassigning nets9 d0 s# A+ V: W
1695885 SIP_LAYOUT UI_GENERAL Visibility Tab check box: unchecked "All" disables access to "Shp" check box' Y9 O6 ]8 _. f/ P- }1 {
1639838 SIP_RF DIEEXPORT Enhance the error message, SIP-1507, to include that overlapping pins within tolerance are included during die export) q9 }; t( b- s& Y$ ]
1653894 SIP_RF DIEEXPORT Redundant error message for die export, when view name is other than "layout"6 n i4 U/ z% \
1681332 SIP_RF OTHER Running die export causes Virtuoso to crash8 R5 m K5 k5 b7 V- x0 n
1679336 SPECCTRA LICENSING Min/Max Propagation Delay cannot be routed by PCB Router using OrCAD PCB Designer Professional
s5 o# U k/ H$ T+ ? e+ v
& s6 F2 {5 N: H% R" o' M4 U. c& S8 }5 l* g M
Fixed CCRs: SPB 17.2 HF015) p3 o p/ l2 e' O9 O0 V
03-16-2017
3 m0 @& X I b6 s========================================================================================================================================================/ h D# M( e3 C
CCRID Product ProductLevel2 Title
2 N- v! N6 m+ L4 c" e! m K+ z4 w7 f========================================================================================================================================================1 I2 R( _1 z9 x% g. `
1653366 ALLEGRO_EDITOR INTERFACES Unable to attach step model to symbol
: S, |$ ], O0 p1 V) r1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model# l. O4 L/ y2 G- E
1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function
7 @4 I4 ~7 ~/ L( L2 q$ _% u' K1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file+ r P( x: d# v/ _' m, T
1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting Padstack Editor results in incorrectly scaled forms2 j2 n8 l, o, }
1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design/ b' p7 \" o0 S
1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees, X* @1 K P% H2 v
1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.
& x: t1 S. f4 D+ L I# v* z( \1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
( b2 G6 j% |2 L% }- x: U1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
' G$ V. x3 D j- B; {6 }, W' t1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not. C3 G- n$ a1 g% B$ p0 C& A
1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used
% ]) s7 M% H% v$ ^2 F; F- X8 G1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places* b' V6 C" }) L' W/ U6 B
1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value
! q( L# @2 z1 m" U( E {1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
8 N; a* M' ^/ `% h; A1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad
0 X3 M4 ~+ p D8 G4 ~1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout& N, h# _ `& L
1698697 CONCEPT_HDL COPY_PROJECT Copy project corrupts the .dcf file
6 r$ ~! f" h- ?/ v1 ^# c' G/ G- S1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084
: }( n% A$ G2 I1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position8 l8 {: \+ d" x1 p! \' u3 c
1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net
6 i3 m8 T/ z! P) r2 o1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer) m2 u. I3 g7 i
1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation/ w9 z9 U1 O/ C) _3 q8 U* ^% Z* ^
1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates, J3 @. a* r% X4 ^# K, Q ]
1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode
% X) d1 ?. b+ n7 L# Z+ i$ e, N7 F% X* Z: \6 W" s* R
r1 Y8 g8 m3 ?
Fixed CCRs: SPB 17.2 HF014
! @- m: F4 [) j O! z+ R03-4-2017
9 `+ ~# Y; y$ E8 c0 Y+ j. J========================================================================================================================================================
* R& f* U9 U' o1 g/ sCCRID Product ProductLevel2 Title& v# C) E( {$ g% C3 r& D( E% z
========================================================================================================================================================, m$ t) M1 b) l6 I: b9 }! ^: y
1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships
$ k& G/ w0 O" T2 h1 Q1 ^6 v# O1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity/ Q; [' f8 C6 N8 A$ X8 F8 |
1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-2686 j, p( }) K: D v- S2 }6 u/ Y
1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data# w* R% M% J$ K2 E/ _1 [
1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data0 r( d# u6 H+ J9 z
1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors
1 p$ m% A: [: m: o1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.$ j5 E- ]+ l( J$ _6 c, w Z
1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted
9 s8 r3 k8 o4 h/ z6 @1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location
5 Q" j) o! u' [2 m4 i0 I( k1685995 ALLEGRO_EDITOR SKILL All film sequence numbers are returned as 0 when using the SKILL function axlGetParam4 d" C$ l* ~) ]2 u
1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately
: N8 R4 p$ `, J( B& [& c( x1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6
, }; N* c7 r; ~& a. }" j1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one
6 B1 L* o1 R3 `: D: m5 A1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled
) p: r+ d5 T6 L" z- ]1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved
5 q7 a! `! {9 L& Y1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components o: O& n0 [$ i) w- o* i, C
1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers* B6 Q) h6 g Y: r4 }
1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase8 j1 Y/ W- ]) u i! Q, n
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement8 B8 @7 I( z1 Q0 A; R4 M
1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message
! q# Y/ g2 t: i* c1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011
) w2 L% {4 M# G8 [1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2; w H0 d" ~) d3 {* P6 H9 k! ]" [
1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers" M; B2 g: Q0 a( d4 {( f* p
1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016
0 ?0 V g+ d& h& P! F3 x! L1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design
4 Q8 U' z! W# s7 |/ K1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors) g5 u7 J' w- \7 k: C/ p0 a
1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters
- l/ F: L. D0 i9 D! Z1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP' v8 w; x5 f; l! P$ [" h2 ]
1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'
% f5 m% Q( v3 l1 V/ x. V/ A* M1705265 INSTALLATION DOWNLOAD_MGR Problem installing OrCAD Library Builder from Download Manager
! U6 ^! R) @3 J, P1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script
% K) p, ~# {( H; ?, N" B
3 L- B6 X: q4 f" q& R& P" E( ?1 l# v+ `) p1 O/ x# b
Fixed CCRs: SPB 17.2 HF0137 Q/ R( ]3 S, w5 X7 N
02-17-2017$ U6 v$ i( o, `6 }2 [+ S9 I1 S
========================================================================================================================================================
+ j* {" h* A# f. v4 YCCRID Product ProductLevel2 Title
+ u8 {5 h$ T e/ R========================================================================================================================================================7 f7 g2 f+ F& G0 t I& f) J1 W
1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm
, l9 y ^3 w( \, p( O4 i# \1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer; o: p; T& H2 |
1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
+ f# h4 Z9 A3 U$ K4 e& b& F4 x. H1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated
3 W' X5 n$ L6 m! d# H/ k6 H7 M1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated
( x3 I' n- e$ [ c9 r3 s6 B x1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board, H* R& N4 A" j( a0 c
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
5 D& n& f* K4 r1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol5 l$ b4 h+ C# q8 J! |
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
% |) V9 @8 B. A+ m% V1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components" Z% }6 S0 C/ \+ Q9 e
1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components
# @% |; N# ?7 x1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets
, u5 b& I! t; t& x1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets
; ?. d T8 f" r5 Q& z7 m1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF
& F' m. D' T; {% ^/ F; X5 d, t1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement
) x- Z+ A1 k& c2 v. ]' ~* ~" q/ y1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.
, y# P7 \+ N9 S1 W8 @1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file2 W* f) o$ _/ J7 U2 U
1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.
, E2 u0 n R' M1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker
4 l/ F& D0 D/ V1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates
% q5 e$ I; B. Y) s$ F/ m9 n/ A1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes5 S* v) v6 j4 d0 K! ~/ h. b/ ]& O
1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.6 `0 w2 s8 b" ~0 \
' z4 ?; y* R H( G/ Y6 }" }+ f1 T! s" x7 Q) B$ O# H
Fixed CCRs: SPB 17.2 HF012/ j9 ~ p) G2 p* F
02-3-2017: E, I% a* s& f: m+ j! a4 g
===================================================================================================================================
1 W8 ~/ P0 [' CCCRID PRODUCT PRODUCTLEVEL2 TITLE
: t6 c, c4 l' v; c5 w0 m% ~5 r===================================================================================================================================7 V" V$ z4 q Q3 J1 M
1659641 ADW FLOW_MGR Documentation Editor does not invoke when a .brd file is opened from EDM Flow Manager
6 Z) s6 i1 m- N% {* W1661632 CONCEPT_HDL OTHER Page skipped in DE-HDL when navigating using the Page Up and Page Down keys0 V. U* j% O. P: v
1668325 ALLEGRO_EDITOR SHAPE Updating shapes to smooth creates erratic voids.0 J% R7 |1 w; r! _, i x& k ^
1670082 CONSTRAINT_MGR ANALYSIS Inconsistency in Constraint Analysis Modes - Electrical in OrCAD PCB Designer Professional 17.2
5 t' \# K) i( v. c& p1674231 ECW METRICS Re-upload for local metric packets that failed on first attempt is not working when Pulse server name contains dots: o) E) K6 ^5 g8 B4 l2 u
1674338 APD SHAPE Shape is not clearing slivers that are smaller than the 'Minimum aperture for gap width' of '18 um'
- b) @9 T/ X: M6 A! w1675677 ADW DBEDITOR DBeditor Issue-Searching by using the Properties method c( Q# q" `: T7 G% y( N
1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers
7 C. G9 ?8 y Q7 c7 m, Q' [ A7 v1679351 ALLEGRO_EDITOR REPORTS Missing Fillets Report is not showing missing fillets on the bottom layer
9 A2 a! K7 C- {* r4 \1681002 ALLEGRO_EDITOR OTHER 17.2 STEP output fails to produce an output similar to 16.6* r- y& r. H& p, M3 w
1682287 ALLEGRO_EDITOR EDIT_ETCH Auto-interactive Delay tune (AiDT) rips lines that have been routed# |0 Y2 l5 ?. W3 r% l1 h
1682900 ALLEGRO_EDITOR PLACEMENT Moving a symbol by snapping to segment vertex with 17.2 Hotfix 009 crashes PCB Editor4 u* a; \7 B0 f7 p# W
1684117 CONCEPT_HDL CONSTRAINT_MGR Property deleted from Constraint Manager is not getting updated in the DE-HDL canvas
1 v) D4 E8 a7 J3 v D T6 H- v1686803 ALLEGRO_EDITOR INTERFACES PCB Editor crashes if the 'ipc2581_group_drills' variable is set.2 E9 [6 x- ?0 M
1687816 ALLEGRO_EDITOR PLOTTING Export PDF Vector text option does not work
1 o: D7 V7 \2 w: t' O1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.* K. h5 G* J% H9 E
1689881 ALLEGRO_EDITOR DFA Record and replay script for loading DFA spreadsheet not working
/ L; x; G) c8 V1 ]% [1690958 ALLEGRO_EDITOR SKILL SKILL command axlDBDelLock is not working as explained in the documentation
+ ?. D5 v7 U5 U- `$ I1692166 APD DATABASE DB Doctor returns 'ERROR(SPMHDB-252): A corrupt database pointer was detected' for a specific design( I$ ?" u* |0 ] B" ?
1693431 ALLEGRO_EDITOR SKILL Running axlXSectionModify and axlXSectionSet results in warnings and corrupts multi-zone cross-section
; D( X3 o5 c, d5 b; ~1693719 ALLEGRO_EDITOR MANUFACT Incorrect suppressed holes information in the drill file created( N7 m' T8 q# z
1693846 ALLEGRO_EDITOR MANUFACT PCB Editor crashes when running the gloss command8 z( i" ]" G; G' q3 [
1694151 CONCEPT_HDL CORE Rename Signal for unnamed net added the sig_name at the incorrect position with small text size.7 Q4 Y* {3 y. d# b$ O7 s ~1 C4 Q1 J
1694867 ALLEGRO_EDITOR SHAPE Void is deleted by the shape merge command2 ^- L) k- p1 T7 Q) x9 K: _
1695131 ALLEGRO_EDITOR SKILL PCB Editor crashes when using the axlSpreadsheetDefineCell SKILL function9 L. S% V5 M! N* G0 k; I% H
- S* X% C) m/ h5 ]& r
4 j4 m; R1 J: y8 `, V0 j5 ?Fixed CCRs: SPB 17.2 HF011: |* c( O5 N1 S( I* j3 P
01-20-20178 X; q6 |5 o9 a" G! K* p
===================================================================================================================================+ |2 Y4 E$ T" }, M% Y
CCRID PRODUCT PRODUCTLEVEL2 TITLE! Y' S R u( A$ M1 n
===================================================================================================================================% N) B. p$ L& u6 y- t) n6 R" q
1618986 CONCEPT_HDL CORE Information required about the DONT_FORCE_ORIGIN_ONGRID directive& G9 I. \% Y, ^! b5 G2 ^( g4 k
1629696 PSPICE PROBE After successfully exporting traces to csv, PSpice crashes on a subsequent attempt to export traces
8 c7 M2 ], w% s$ d- N. _4 m, ~1667213 CAPTURE NETLIST_ALLEGRO Tools - Create Netlist stops responding on Windows10! y8 d( u8 V" g, v
1667599 APD OTHER Wire Bond operations taking longer than expected to complete
5 B/ P% c/ N* R3 I C8 o, b1667678 MODEL_EDITOR PARSE Signal model assignment creates ESpice models that do not pass Model Integrity checks, m0 {. x/ I, H: o' b1 s
1670120 ALLEGRO_EDITOR UI_GENERAL In 17.2, the Static Phase meter shows up in the middle of the screen instead of the lower right corner7 Q m: O$ d% r/ ~) s6 O7 m
1670927 ALLEGRO_EDITOR DRAFTING Using zcopy to create a Route Keepin results in database errors* V1 [6 O6 r5 i! a$ l. v3 o+ U. ?
1675359 ALLEGRO_EDITOR ARTWORK Subclass ETCH/WIRE is added to artwork definition though the visibility of 'ALL Layers' is turned off
) K0 H- E }' J9 S4 a5 @1675619 ALLEGRO_EDITOR MANUFACT Differences observed in IPC-D-356A between releases 16.6 and 17.2
# a3 L7 K% a6 D- i) W4 U1676161 ADW FLOW_MGR Opening a project in SPB 17.2 flags the 'Operation load JNI code failed' error
4 o+ B: X5 u$ a& P6 k, H ?" d1677405 CONCEPT_HDL OTHER When moving a wire with a dot, the dot is not removed directly
3 W& P7 S7 l! r5 j7 F0 M6 o! q: q1678061 PSPICE SLPS Simulating an SLPS co-simulation with a Fixed-step solver with a value smaller than 1E-4 results in a crash2 i" D1 D5 `5 ~$ A
1679347 PSPICE SLPS SLPS crashes when co-simulating without opening OrCAD Capture or PSpice. M: _6 \8 ^3 d$ u1 p: U0 A1 G8 ^7 [
1680113 ALLEGRO_EDITOR SHAPE Irregular void created on dynamic shapes* F4 [# D$ D- N$ d; |5 q
1680802 ALLEGRO_EDITOR DATABASE A 16.3 database locked with disabled export of design data should be view only in 16.6' t1 B, l- z1 l7 a
1681129 ALLEGRO_EDITOR DATABASE Match Groups in the DE-HDL design are not getting transferred to the board file
8 N% |: d& _) e6 e: H' Z4 K1681514 ALLEGRO_EDITOR UI_GENERAL Opening the Dynamic Shapes State report hangs PCB Editor in 17.2 Hotfix 009
5 V: P: j: k2 |! l8 N8 m5 e1681727 CAPTURE NETGROUPS In 17.2, Capture crashes when closing a design that has assigned Netgroups
+ Y3 t! F( |" G- K) A& S/ \1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
& ^4 y4 d/ S! S2 x% v7 L# c1682447 CONSTRAINT_MGR CONCEPT_HDL Extraction issue on differential pairs in the given design
% {. l; U+ ^8 n4 ?1682454 CONSTRAINT_MGR CONCEPT_HDL Design with NO_XNET_CONNECTION property on parts is exported to PCB Editor; many other components get the property
, V" J( c/ p" {* J1682469 CONSTRAINT_MGR CONCEPT_HDL Creating a CSet from an existing CSet leads to invalid CSet names in Constraint Manager connected to DE-HDL
2 }$ v( w; Z i; {6 M$ f/ q1683919 ECW TDO-SHAREPOINT Site Minder integration for login from TDA not working after SSL certificate update
`* Y% i q; P0 C/ V7 d1684111 ALLEGRO_EDITOR SHAPE Dynamic Shape not voiding overlapped static shape
# f( E$ R% u7 [- w! g" L1684508 ALLEGRO_EDITOR AUTOVOID Allegro PCB Editor stops responding when deleting a via) p3 ~" z+ r! q. f9 u% H( |
1685540 ALLEGRO_EDITOR OTHER If text is attached to an object, the object is also printed in the PDF
E8 e0 e: \' ?2 r4 ~1685810 ALLEGRO_EDITOR PAD_EDITOR In 17.2, Padstack Editor does not save adjacent layer information for BOTTOM pads: M$ \% x5 t7 y1 z3 m( x
1685986 ALLEGRO_EDITOR PADS_IN PADS Translator-generated output shows incorrect unit for the soldermask oversize option
1 j5 J& b' C* ?+ ~1686127 ALLEGRO_EDITOR SHAPE The void of shape missed in artwork.2 U7 B8 B6 U! F8 a$ \
1686791 ALLEGRO_EDITOR OTHER Searchable property unavailable on bottom layer pins in the generated PDF5 _" p; L+ P% O
7 `9 T: R. D' q8 X
' V9 r- o9 g- A6 iFixed CCRs: SPB 17.2 HF010
7 Q6 C! t$ i* V% W. V01-6-2017 - ]( T' K+ d* h w1 v1 ]8 q
===================================================================================================================================
! |/ ~: @% \. ^# kCCRID PRODUCT PRODUCTLEVEL2 TITLE
8 w! m/ @8 h0 `3 d7 Z) k===================================================================================================================================
+ u# [8 A5 J: b( v F5 i1524700 F2B DESIGNVARI Variant file cannot be loaded
) u) j7 r* C( _1 S1597787 CONCEPT_HDL MARKERS Save As in Marker dialog causes DE-HDL to crash) |# C" g- e2 q s0 E
1599843 CONCEPT_HDL INTERFACE_DESIGN Moving NG causes extra elements added to it to move$ A- H! m4 T1 H8 n7 y
1620017 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053) when $PART_NUMBER property for components has a value
- v' L, ~- j, C( h1 H1632977 CONCEPT_HDL INTERFACE_DESIGN Connectivity error when moving NG members8 g4 n7 I$ j0 l7 q( a
1635941 ALLEGRO_EDITOR INTERFACES Shape created by IPC 2581 for negative film is not same as the shape on board
: F* s0 G$ U+ e; T. v `1656357 CONCEPT_HDL CORE Pasting a signal name across pages causes the name to overlap with the wire segment* t) d2 s& ]& n" s6 M& i
1657346 CONCEPT_HDL PDF Wire Pattern set to two-dot chain line in a schematic appears as a solid line in the PDF output
- i. s7 E0 {+ O: U6 x" k& p2 k9 ~& U; h1658048 ALLEGRO_EDITOR COLOR color_lastgroup is not working in SPB 17.2
3 V) Z- c# u8 ^% o% ^1658874 CONCEPT_HDL CORE 'Insert (n) Pages' command does not work when the CONFIRM_WRITE directive is ON
; x3 U3 p2 w8 r1659030 RF_PCB LIBRARY Offset is not calculated from the center if using negative values for input pins when placing MSOP symbols. @0 F X# P2 j
1659097 CONCEPT_HDL CORE Mouse stroke fails to be enabled on startup with left mouse button (LMB)% c9 h( h+ S5 \& }; g4 {( p
1659532 CONCEPT_HDL CORE About Import Design command with the CONFIRM_WRITE directive
# v {( |2 h& k4 Q* H1659929 CONSTRAINT_MGR UI_FORMS Using wildcards in filename for Import Constraints does not work in 17.2
& q" l- w f# R1660200 ALLEGRO_EDITOR UI_GENERAL Move by Sym Pin # edit box is obfuscated
! I8 S8 u$ q) M1 L: N* d' N1662821 ALLEGRO_EDITOR OTHER Cross section chart does not show stack vias in 17.2( @0 t, |# P# c3 ]& H' _ v
1663641 CONCEPT_HDL COPY_PROJECT File - Copy Project in Project Manager creates two designs if there are dashes in the design name
0 _( d8 t9 X$ e8 M: }1 I, A1665652 ALLEGRO_EDITOR SHAPE Critical fillet and shape issues in 17.2
" C- I- V1 j4 W1 K1665918 CONCEPT_HDL CHECKPLUS Error (100) Program Internal Error 'Create_flat_node' with checkplus run
4 r5 P1 P( H" L! G f6 M$ W1667056 ASI_PI GUI Power Feasibility Editor does not list capacitors connected to selected nets/parts$ y' Q2 E( F( S [" V: K
1668137 ALLEGRO_EDITOR SCRIPTS PCB Editor crashing when running Script Replay) F9 Q) e* M; l9 T0 f# @
1669651 CONCEPT_HDL CREFER CreferHDL values are invisible% d; t f" a0 i. o- C
1669707 CONCEPT_HDL CORE Pin numbers not visible on the canvas after replacing a part with the same symbol but a different part property! S; F5 L9 T3 W/ c9 S
1670339 ALLEGRO_EDITOR OTHER Small shapes defined on the mechanical symbol Board Geometry - Outline are not converted to the Cutout subclass.
: ~, w, _* u- ^ N1670564 ALLEGRO_EDITOR MANUFACT Exported Gerber file cannot be imported in brd
& H7 [4 E; @/ X$ n9 W6 ~5 \1670687 ALLEGRO_EDITOR NC nclegend.log reports missing columns which are present in the NC Legend
0 J1 w/ L) w+ B5 l4 w( \1670811 PSPICE AA_MC AA MC Plot settings options
- ~* E, t r) M& R& n$ x8 w1671428 ALLEGRO_EDITOR UI_FORMS Display origin checkbox position changes in Step Mapping dialog# @- c+ F) {* v: w2 B& o1 c
1671728 CONCEPT_HDL CORE Option requested to reload preferred_projects.txt without re-opening DE-HDL, e& g% G5 q9 f+ y' K$ L* D
1671901 ALLEGRO_EDITOR UI_GENERAL Toolbar and menus are locked or greyed out& v! _' [8 A+ e. G* E. k: a
1672477 ALLEGRO_EDITOR DRC_CONSTR DRC generated by Dynamic fillets1 B9 r) ~/ D% F* C1 y+ y5 K
1673499 ALLEGRO_EDITOR DATABASE Drill table title issues of backdrill designs in 17.2) m5 @: f$ p3 J5 B+ J
1673681 ALLEGRO_EDITOR UI_GENERAL F1 for Help not working in PCB Editor 17.26 V( b! R3 o" \2 U+ V. A
1675499 ALLEGRO_EDITOR DATABASE Running the Gloss command causes PCB Editor to crash...6 c4 t$ E: c4 C9 O
1676480 ALLEGRO_EDITOR MANUFACT Creating Variant Assy_Bot Drawing showing Variant Assy Top Drawing
7 |# ?6 P: F4 F3 m# {# v0 H1677431 ALLEGRO_EDITOR DATABASE Get ERROR(SPMHA1-141): Invalid sector row. Contact cadence customer support when opening DRA File
_: F! c! v" n7 p6 E1677651 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crash on design after successful packaging
. K5 T0 x6 O) p! z7 K0 z8 h& {1 M1677672 CONCEPT_HDL CORE Whitespaces in URL links are not resolved correctly on Linux with Firefox
W% R0 Q Z3 H" K) ]1680837 ALLEGRO_EDITOR SHAPE Updating the shape makes the shape disconnect from Thru pins of same net, F, Z" s1 t) J( [& n3 A8 X/ G
1681059 ALLEGRO_EDITOR SHAPE Shape Voiding using DV_SQUARECORNERS environmental variable does not always produce voids with square corners.
- a7 c+ n- [# R) j+ H1682312 SIG_INTEGRITY LICENSING Allegro Sigrity SI/PI Product Choices window is blank after installing 17.2-s009 hotfix
; E( s% `: v9 V3 x6 j6 ]' {; V" q1 _
5 k! P8 D. J$ ~Fixed CCRs: SPB 17.2 HF009) U$ |( t9 D/ n! L4 K4 H
12-8-2016
1 [) n& U' _. f' ]6 \===================================================================================================================================
: s& B7 o; h. Q. m8 k `* ECCRID PRODUCT PRODUCTLEVEL2 TITLE
: E4 V! w: X1 ^& @# c3 n: C===================================================================================================================================9 r8 I+ |) M- J' o
1212577 PSPICE MODELEDITOR IBIS translation fails without any information in log file
# ~* W, C; M4 M" @, r3 B- `1311687 PSPICE MODELEDITOR Timeout error while translating IBIS model) j$ n8 h/ z& ~* k$ M0 T
1327174 PSPICE MODELEDITOR Log file should list error details during IBIS Translation
; d% w/ X) T: V* ?. u ?. e1499665 ALLEGRO_EDITOR INTERACTIV Offset Move depends on move setting.
' C) o" `2 g1 X/ \' V1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation
1 r- F/ [3 K% z3 V, X1565795 ALLEGRO_EDITOR UI_GENERAL Search does not work in the Defined Variables window
8 h9 ], Q2 \& A3 G+ E1568817 ALLEGRO_EDITOR UI_GENERAL Padstack editor not accepting comma as decimal separator with system locale set as LANG ru_RU.UTF-8
6 E: o: L6 W" E* D9 Z1569272 ALLEGRO_EDITOR PLACEMENT Get the error message 'E- (SPMHDB-394): Placement cannot be completed ... 'after creating Place Replicate circuit4 ]( W8 s( h" n6 Y8 a) u
1577379 CONCEPT_HDL CORE Packager-XL gives different results when run from DE-HDL and ADW Flow Manager
$ |+ z: a, `: T1578523 ALLEGRO_EDITOR PAD_EDITOR Library Padstack Browser does not refresh preview% e" M4 J& f6 z' G; [
1578533 ALLEGRO_EDITOR PAD_EDITOR New Padstack Editor does not automatically update the geometry0 z) w, K0 H, y$ r3 M4 |
1581129 CONSTRAINT_MGR UI_FORMS Unable to dock the Electrical worksheet in Constraint Manager: S4 I+ l( K- D* L
1582103 ALLEGRO_EDITOR PADS_IN PADS Library Import creates additional filled shape not present in source data3 b1 u+ D& K+ W( H( a) x# U
1591027 ADW LIBDISTRIBUTION Library Distribution redistributes previously distributed models7 M4 }; I! v r) E/ b
1592026 CIS VIEW_DATABASE_PA View database part does not work from schematic pages of an externally referenced design1 e2 C2 L- y9 {! N; m3 i u+ l
1593389 CAPTURE GEN_BOM Include files in Tools - BOM not working
: k0 {' B% V0 F1593404 SIP_LAYOUT EDIT_ETCH Slide command moves via toward the object# D- q) U5 M+ R, `: N* ^6 o
1595872 CIS PART_MANAGER Capture CIS Part Manager PCB Footprint update case-sensitivity issue$ Z2 G q% D. |* J! Y3 K" V h" S
1596955 ALLEGRO_EDITOR EDIT_ETCH Scribble mode is not working as per expectation.& F( m- ]# h* `% w1 u( D
1600936 ALLEGRO_EDITOR INTERACTIV Pin DataTips differ between 16.6 and 17.2
% T& A( C; T! I- P1605961 ALLEGRO_EDITOR COLOR Wildcards not working in the Filter Nets field of the Color Dialog window E) X T0 k0 p$ i: ?' B
1606392 ALLEGRO_EDITOR PLACEMENT Filmmask not shown when component is attached to cursor
6 I" a! A: Z* B8 C1 O' A1607016 ADW TDA TDO crashes after LRM update during check-in hierarchy5 W. D' d( b- w' c9 m7 W# J7 J
1608059 CONCEPT_HDL CREFER Removing crefs from top-level design also removes .csb files from lower-level blocks
( c7 K1 Q# M% ~1608278 CAPTURE OTHER Crystal Reports: User is prompted for ODBC password to create a BOM report
3 M2 D0 H! E0 h! a ~8 Q# ^1610377 CAPTURE PROPERTY_EDITOR Discrepancies between the NET_SPACING_TYPE property (or any other property) text and the actual property
4 p Y; J3 F% y, ?( _4 w8 v2 P1610456 ALLEGRO_EDITOR DATABASE Strip design and selecting user defined subclasses results in database corruption.
! v* ^" r9 r* B- ]5 Q- s0 l1612793 CONCEPT_HDL OTHER Pattern-based auto-distribution of split symbols not working if there are spaces before commas
?* t+ Z( J! b6 C! l0 c3 K+ E1613442 CONCEPT_HDL CORE Signal names are not horizontally centered when the wires are added using different methods
5 O! [! C3 }! |2 n1613559 ASDA IMPORT_DEHDL_SHE custom variables from the BOM Tables are not getting imported
* h, ^* F* v1 F7 o$ Z+ c1614093 CONCEPT_HDL CORE Import Design window has artificial 64 char limit for path - prevents access to some locations' B/ ]+ T5 j, e9 p, c
1614372 CONCEPT_HDL EDIF300 OFFPAGE symbol is exported as PageBorder in EDIF300 schematic" _' r% s' r3 ] C
1615075 APD LOGIC Netlist-In wizard fails to import the net names, but gives a successful completion Info message( Y1 o! [0 {8 F, _
1616131 ALLEGRO_EDITOR PLACEMENT While placing a module, the Mirror command in the right-click pop-up menu is not working: J/ ?& _# U4 d$ g4 h( Y
1617377 ALLEGRO_EDITOR UI_GENERAL Visibility pane does not retain the correct layer view: y c$ _' i g0 c! r0 n* c% r3 V
1617404 ALLEGRO_EDITOR UI_GENERAL axlUIMenuChange does not work as expected in 17.28 V7 a. \6 V3 N1 F
1619412 ALLEGRO_EDITOR INTERACTIV Script to create new padstacks from existing padstack is putting in wrong values for a regular pad0 W/ i- Z! t( J
1621842 ALLEGRO_EDITOR PLACEMENT mechanical symbol without placebound will not place in QuickPlace$ ~6 i5 @. M3 t N
1621874 ASDA PRINT Print - Save as PDF uses the default printer options only/ W- N$ [* |2 H3 a, J
1621887 ALLEGRO_EDITOR INTERACTIV Getting a 'Could not satisfy the snap condition' message when using the Snap pick to option) a# l7 v' t2 _" Z4 V+ k* G# d
1622680 ALLEGRO_EDITOR PADS_IN Import PADS fails with the 'ERROR: *NET* section found. Translation of netlist is not allowed.' message
. t; y% N# p9 H- C; v6 m% d& b& s1623832 ADW COMPONENT_BROWSE Incorrect part placement on schematic in Design Entry HDL 16.6-S073
6 {; x, V! }% S \6 w6 L( }1624813 CAPTURE GENERAL The Value property is always left aligned when placing a symbol on the schematic
# p! `' `2 l o; I3 y: @* i7 }% W1624953 ALLEGRO_EDITOR UI_GENERAL Custom views in 17.2 do not return to original% G" }$ E+ P3 j
1625000 ASDA CANVAS_EDIT File - Save Project does not provide any indication of saving or progress bar) k" |0 E, I% G. o% v6 W
1625163 CONSTRAINT_MGR OTHER There is no status for the analyze command in the Constraint Manager in 17.24 G5 _. o2 `: _. V4 J
1626647 PSPICE ENVIRONMENT Capture crashes when loading a design with two hyphens in sim profile name8 } B! E3 o9 J1 y! |; u
1628357 CONSTRAINT_MGR OTHER Constraint Manager shows differences if exporting and importing constraints on the same board.9 {2 r- v, E( H: @
1628409 ALLEGRO_EDITOR PAD_EDITOR Pad Stack Editor does not remember last used directory$ B# ^% c: F2 U% [
1631443 CONCEPT_HDL ERCDX ERC reports warning due to lower-case value of some properties in chips.prt
$ H0 L v5 b3 v) U1632195 SCM OTHER 'No known page border found' error in cref.log5 F# c; |+ w. N
1632365 CONSTRAINT_MGR OTHER Select command is disabled in the right-click pop-up menu from Constraint Manager in SPB 17.2
3 ]9 b6 M. B* G: t9 f: V) ?1632462 ALLEGRO_EDITOR 3D_CANVAS 3D View (new) and PCB Editor crash when checking collisions
5 P0 M0 Q/ n2 p. c$ h) j1632590 ALLEGRO_EDITOR 3D_CANVAS PCB Editor crashes when 3D View is open and more 16.6 boards are opened
( {1 |' B# I; j8 @3 ^6 ~1633433 CONSTRAINT_MGR UI_FORMS Expand - Collapse feature for multiple objects not working correctly* O4 j8 L+ O4 t
1633454 ADW TDA TDO crashes if DAO throws an exception4 S" T& @7 H% R7 k
1633526 PSPICE AA_PPLOT Spaces in Simulation Profile cause error in Parametric Plotter/ C( a% }( U G2 n) S! g
1633608 ALLEGRO_EDITOR COLOR 'Retain objects custom color' should not enabled as default.; h2 @& _. M" B8 G2 s) v0 w8 }
1636216 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas (Unsupported prototype) is not mapping step model when assigned to device
* e! A. ]% L, b: q( h6 J# w1636899 ALLEGRO_EDITOR 3D_CANVAS The new 3D Viewer is not taking the Package Height set on the PLACE_BOUND layer into account when displaying it.
0 n* V% Q- |3 i. g, g1638185 CAPTURE DATABASE Opening CIS database locks all part libraries none of which are open
1 q1 q y" A- ?8 _1639409 ASDA CANVAS_EDIT Handling of MAKE_BASE property from DE-HDL designs imported into SDA
q" J# f6 Z$ B R( G! P& J2 q1639541 CONSTRAINT_MGR OTHER PCB Editor 17.2 crashes when making changes in Constraint Manager, ^% C1 y# p" z5 q! p/ Y! u
1639613 APD STREAM_IF The stream out command has created sharp angles in the GDSII output file) X' f+ w0 O# ?5 N! U; q) v" x6 X4 E
1640061 ASDA HIERARCHY Incorrect message received when invalid characters are specified for subdesign suffix U( u* t: W8 L# n
1641118 F2B DESIGNVARI Some DNI parts are not identified in the variant view due to the BLOCK
6 g8 `) k n% G+ k3 `" t! N1641410 ASDA CONSTRAINT_MANAG No errors or issues reported when incorrect topology is applied to a net or an Xnet
# z3 B( A9 _2 n- Q1642891 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes randomly while working on Constraint Manager9 A: }, D$ O+ V2 U/ |( F
1643003 CAPTURE PROJECT_MANAGER Start page shows latest as S004 after installing S005
" |% ?! [, a' u5 Y: I/ I `1643532 ALLEGRO_EDITOR OTHER Strip design command fails to delete symbol text in the attached design! J) _5 c9 m0 M# ]% J( h1 ^& \
1645529 ASDA CONSTRAINT_MANAG Unable to delete the diff pair from the nets, l% J+ M: Y& F( e0 p$ y1 X
1645639 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes when the XNET_PINS property value has a trailing comma character
% {4 N" g8 U: y3 _) S1 H1646354 CONSTRAINT_MGR CONCEPT_HDL Cannot select Design Instance/Block Filter from the View menu in Constraint Manager, |/ [( ]! C% E8 l- f/ W
1646612 PCB_LIBRARIAN CORE Generate Symbol option crashes Part Developer/ L& a w4 f7 R. ]: d) l
1646932 ALLEGRO_EDITOR MANUFACT Manufacture - Auto Rename Refdes keeps defaulting to Use Default Grid even if another is chosen
/ ^' y$ Q: T" o3 h0 O1647190 APD REPORTS 'Sorted by Bond Finger' report shows incorrect wire bond connection
9 s1 y0 S9 j5 I. \% z" t& t3 {" i* T1647673 ASDA EXPORT_PCB Two Physical folders are seen after installation of QIR2 r- {+ D2 _6 B$ R
1647729 ALLEGRO_EDITOR SKILL axlFillet returns t when fillet is not added.
2 n/ ]$ p" [/ d$ N2 w1647779 CONSTRAINT_MGR OTHER 'Software Version' in the cmDiffUtility viewer does not show the correct version9 x# L$ t* j# e' J- u
1647843 ALLEGRO_EDITOR ARTWORK Misleading information in command window when artwork import fails: ?5 j3 n' d% F) A
1648575 CAPTURE OTHER Suppress warning setting must be written in capture.ini file9 v1 E" o6 X6 q4 O8 V
1649060 CONSTRAINT_MGR CONCEPT_HDL Rename dcfx to dcf process results in error in log file and dcf not updated
& z# W3 A4 w3 q$ i7 ^% Q; K1650106 ALLEGRO_EDITOR 3D_CANVAS 3D canvas rotates mirrored components in unmirrored angle
6 O4 D0 e2 {) d" x8 M1650238 SIP_LAYOUT WIREBOND When performing 'Adjust Min DRC', the reference bond finger should not move.0 m |7 ~/ _+ \* A
1650734 APD SHAPE Shape on L1 does not flood properly6 G! F6 h5 q* c- [5 f
1650793 CONSTRAINT_MGR CONCEPT_HDL Conflict of XNET_PINS definition between the chips and the SIGNAL_MODEL is not handled correctly
: D; N) Q6 z, b" P1650801 ALLEGRO_EDITOR SCHEM_FTB Running Export Physical with Update PCB enabled in Project Manager crashes netrev.exe" `, ~6 ]& _. l: T# E
1651011 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D viewer shows mechanical symbol mirrored6 O5 x! I" l( Y7 o! W+ f5 z0 g
1651063 ALLEGRO_EDITOR CROSS_SECTION Cross-section preview is incorrect* D" g* p2 n' M0 Q: z) I8 O
1651066 ALLEGRO_EDITOR DATABASE Pins not connecting even after running the Tools - Derive Connectivity command8 N6 }4 G% Y4 B% E6 R( S6 T
1651700 ALLEGRO_EDITOR SKILL Running axlXSectionModify() on a layer removes the value of the material' @. m4 O) q3 X- j
1651925 ALLEGRO_EDITOR ARTWORK Searching for a macro in the artwork data file: Count for the macro does not match the actual count in the output7 [0 ^$ k4 Q! _5 q9 m- s
1652230 CONCEPT_HDL CORE The master.tag and vlog004u.sir files are not created in the entity directory on saving symbols
5 F2 w1 m; d9 d& O& U1 t0 Q1653080 CONCEPT_HDL ERCDX Difference in results from SPB16.6 in 'erc.rpt' when logic_data is renamed as worklib in SPB17.2 on RHEL6.5, ~8 q# K( w1 K$ K1 E, }
1653422 ADW LIBIMPORT Classifications not linked to a Part Number or Cell Model are removed during Library Import
- b8 E+ ]5 P& X- |2 J1653526 ALLEGRO_EDITOR DATABASE Via padstack keepout is not displayed on the canvas when pads suppression is enabled.' d0 k f# g, ?& P- ~7 J
1653951 ALLEGRO_EDITOR CROSS_SECTION Cross Section Editor changes lost despite selecting No to the 'All changes will be lost ...' message
( n& _. D+ o" D6 s' H1656224 ADW FLOW_MGR Copy Project wizard no longer allows dashes in the 'Name of new project folder' field
* B: s( M w( m1656581 ALLEGRO_EDITOR OTHER PDF generated for layer with shape shows undesired voids if film is mirrored and Filled Shape is not selected
6 O# s* G! p" e. n( v1656608 APD REPORTS Incorrect calculation in the metal usage report
4 ^& M0 d& {) E# |* p, O; U1656726 CONCEPT_HDL CORE Interface command always disabled in the Wire menu- v- h5 ] x5 g6 a! c
1656841 CONSTRAINT_MGR UI_FORMS Incorrect layer information is displayed in the Edit Via List dialog when a filter is applied
& ]6 d4 W' r" [ ~1657220 ALLEGRO_EDITOR SKILL axlXSectionGet() returns Primary list of layers and not All stackups
# @, u* V9 [' O- U1657257 SIP_LAYOUT EXTRACT When using extracta, custom layer names not getting retained
+ |& P* n I& ]3 k q# U( D( G1658440 ALLEGRO_EDITOR PAD_EDITOR The location of a drill in the .pad file is different from the .dra file3 j6 {- I) k8 I! {9 D
1658445 CONSTRAINT_MGR CONCEPT_HDL When DCF file is converted to ASCII, no further updates are allowed.
5 \6 a, b. O" \7 `! C' U1659473 SIP_LAYOUT WIREBOND When moving wirebonds they are jumping instead of sliding
7 Y7 v6 d1 `# Q( a6 y A1659498 ALLEGRO_EDITOR INTERACTIV Unable to turn off line on Etch Wire for Jumpers
8 Z; K" _1 D8 u8 }: k- Z9 ]1659644 CONCEPT_HDL OTHER Predefined nets are not listed if 16.6 design is being opened in 17.2
7 P$ } x$ x9 Y2 V( h7 Q* ?5 a1660475 CONSTRAINT_MGR UI_FORMS The CTRL+V shortcut is not working in the Export Constraints window in Constraint Manager 17.2
! \8 L3 I _! o9 N" F1660492 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes when using multiple desktops on Windows 10
/ @3 F4 o: |5 x% m1661133 CONSTRAINT_MGR ANALYSIS PCB Editor crashes if comma is used in the Value field for Analysis Mode
2 c+ s- e" {2 `1661307 CONSTRAINT_MGR CONCEPT_HDL Prevent creation of diff pairs on VOLTAGE nets
9 B' q2 j0 E/ W5 a8 p1 M4 ~1661357 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when using Route - Connect( F' X5 a3 S( k3 F2 ^: l) X+ Z
1661874 ASDA DESIGN_CORRUPTIO Unable to delete the ZERO part from the schematic page3 X' {" c& J# H& `
1662799 ADW SRM Mechanical symbols are not being displayed in the Mechanical tab of Symbol Rollback Manager) @! ~% G8 |% m1 n2 I. O0 i
1664797 SIG_INTEGRITY GUI Unnecessary coupled interconnect models were generated during View Waveform.
% |% P! H- U% B2 E1 I" e1664858 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes during Auto Interactive trunk route.5 s2 c9 N/ ^( h1 e
1664911 ALLEGRO_EDITOR OTHER PCB Editor freezes after DRC Update is performed
0 c& o! I8 `/ S- i; W1666329 CONSTRAINT_MGR OTHER SCM Import Physical process crashes cmfeedback, T) D& x/ p% P) z' a- ]
1666551 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option separates imported artwork to different XY locations
# t7 d# q0 _0 _" V; O- L" x1666723 ECW TDO-SHAREPOINT TDO login is not working with Site Minder because of incorrect characters in the Site Minder login form HTML
" B& |% S$ ~: _) y. D1667068 ALLEGRO_EDITOR SHAPE Update shape removing the shape voiding+ m/ Z' c: j/ y% I$ R
1669828 F2B DESIGNVARI Variant Editor crashes on Windows 10 T540 P laptops but works fine on Windows 10 desktops
/ u$ v ?1 N! _2 O( d1 b1670221 ALLEGRO_EDITOR DATABASE Non-recoverable corruption error is reported when saving the board after adding a layer
; p( ^6 S) L) t8 C: u$ {, z1672134 ALLEGRO_EDITOR ZONES TDP needs FIXED component override
( y$ |+ ?& z; v- g( o P) ^1 Z+ S, l& L6 C) s
: [) b- K. Q6 G) x$ ]4 L( VFixed CCRs: SPB 17.2 HF008+ Q! H) L$ ]& K- t) n8 J4 ~
10-29-2016
& D& l0 q( x! q- x v2 C& C \' P===================================================================================================================================& I+ Y8 A1 V1 P. j
CCRID PRODUCT PRODUCTLEVEL2 TITLE
x& A0 z* g& O8 ?5 c===================================================================================================================================
& b& ~; t H, \% U" X$ n1644406 ALLEGRO_EDITOR SHAPE Alternate symbol placement results in illegal parent identifier error' S m' e( S. L$ d
1647098 SIP_LAYOUT OTHER SiP crashes on symbol copy and rotate7 @4 U) s$ A# V
1647154 APD OTHER Disconnected Clines not working; K) |6 J9 @7 H2 A, P
1648817 GRE IFP_INTERACTIVE Allegro PCB Editor stops responding on adding netgroups to a nested netgroup5 L9 ]! J0 F/ f3 g
1649829 CONCEPT_HDL CORE A delay is observed before the sub menus of the File and Tools menus appear
: U+ m9 m, m! e1652930 ALLEGRO_EDITOR OTHER Command-line version of switchversion not working
' p6 h4 u" ^% s% h4 n5 l5 H- m1653109 ASDA DESIGN_CORRUPTIO SDA not pulling latest library information for part" S1 j; N( n$ A' l
1655377 FLOWS PROJMGR Project Manager crashes on Windows 108 r" i$ j) h# n0 ?+ ]
1 v( M7 L/ n4 r7 U# o/ b+ }" ~% b( _ V* s0 U2 k
Fixed CCRs: SPB 17.2 HF007; R: m" a; ~# j" C# Z+ W" y
10-20-2016
! E7 [4 N/ i7 V8 @===================================================================================================================================) x+ V3 m! P) W
CCRID PRODUCT PRODUCTLEVEL2 TITLE
N' t, Q& t% W9 B===================================================================================================================================' A1 k1 H v; S; r) }1 {) L, g5 v
1582276 CONCEPT_HDL CORE Need the ability to delete an image placed on the DE-HDL canvas# ]% s+ T h6 G0 {; u% p1 h
1594101 CONCEPT_HDL CORE No error or warning issued on specifying an incorrect unit for voltage
9 ^! O9 J/ \4 h2 L9 R1611293 ALLEGRO_EDITOR UI_GENERAL If the Command window is floating, it cuts off text from the bottom half of the last line.
- `0 F6 h$ Y4 v+ d" T1611652 ALLEGRO_EDITOR UI_GENERAL New artwork film not appearing in the drop-down list for Visibility Tab2 a! J8 u" q9 g3 r
1618205 ALLEGRO_EDITOR UI_GENERAL New Artwork film added is not updated in Visibility - View
' R8 J/ e% ?$ L O* S, b1631114 CONSTRAINT_MGR OTHER SKILL functions axlCnsPurgeAll and axlCNSDelete delete spacing constraint sets but not deleting names
+ w/ ~/ E- T- m; ~$ N& c7 G9 V, N1633726 ALLEGRO_EDITOR UI_GENERAL Visibility tab not dynamically updating the view list when artwork film changes
- ^& P: W# l- i1636404 CONSTRAINT_MGR CONCEPT_HDL In 17.2 QIR1, DE-HDL Constraint Manager allows users to enter invalid voltage units
* u) f! ]' K* q3 _1636864 ALLEGRO_EDITOR UI_GENERAL Domain Selection for Visibility does not work with Hotfix 004 unless you save and reopen the board file/ Z' d6 h6 L4 K
1638251 ALLEGRO_EDITOR DATABASE Unplated hole changed to plated hole after uprev from 16.6 to 17.2 version
9 {1 W3 X- l) l3 i5 y* W1639483 ALLEGRO_EDITOR EDIT_ETCH Manually routing discrete components with incorrect constraints causes PCB Editor to crash
5 F* w( Q* ` W; `1641435 SIP_LAYOUT IMPORT_DATA Need SiP Stream mapping layer count to match Virtuoso stream layer mapping count
) x1 ]% x0 t- ~# Z! I# b- h+ E1641483 SIP_LAYOUT WIREBOND SiP Layout - Modify the wirebond report generation for Start and End height when using a DISCRETE class footprint
! a9 U. ^+ R% U5 [% g; G# `! z1644131 F2B PACKAGERXL Option needed to package a DE-HDL design with ptf errors into a board file
: K5 S8 u8 o, z! d1644807 CONSTRAINT_MGR ANALYSIS Unable to set electrical constraints modes with the OrCAD PCB Designer Professional licenses
+ @/ S0 h: M# g4 G1646228 ALLEGRO_EDITOR UI_GENERAL Running the axlUIMenuInsert command to add a submenu after running the axlUIMenuFind command crashes the tool& B$ r2 x! F" i1 S+ r: x2 ?
1647402 PSPICE PROBE Unable to print on Windows 10 as no plots are displayed in the Probe window
$ [% s3 r: F/ ^1648183 ALLEGRO_EDITOR INTERFACES Allegro STEP Export: Using the 'step_3D_copper' variable, pads not exported in the same plane as traces and shapes4 g9 a# Q/ X8 M1 h1 s2 E
1649222 APD ASSY_RULE_CHECK Allegro Package Designer stops responding on running the Acute Angle Metal DRC% X6 \% k+ [2 d8 i+ {" m! ?4 `
) S& `. ]* ~! W6 K V# c& E
8 d' ]! r5 B' F b) ~6 dFixed CCRs: SPB 17.2 HF006
m7 \/ ?( q* _( m0 J6 w- h10-7-2016
7 k! k0 |1 T0 _' [' N0 V7 i===================================================================================================================================: @7 n! W' {0 O1 h4 C, p# o1 N
CCRID PRODUCT PRODUCTLEVEL2 TITLE, P/ p4 a+ s$ ^
===================================================================================================================================
5 ^4 w+ u4 _* l% f" n1585203 ADW DBEDITOR Optimize check-in of footprints with multiple padstacks
& [% `2 r, x9 }- t+ z1 V1607954 ALLEGRO_EDITOR SHAPE Dynamic Shape not updating correctly, g2 R: i& J! \3 D4 ]: J. V
1618173 ADW SRM SRM does not automatically run when a .brd file is opened from EDM Flow Manager in 17.2 Hotfix 003
7 \" L0 C; ~" j k1618832 ADW SRM SRM marks parts as updated even when they are not updated4 p) }0 ^" C+ ~( M" B# r
1623823 SIP_LAYOUT WIREBOND NO_WIREBOND property is ignored by Add/Edit Non-Standard& l" m9 G$ }1 @+ {. l: B
1626001 ALLEGRO_EDITOR SHAPE Shape to route keepout DRCs reported for dynamic shapes in the attached design& n5 z4 C, O% B/ h
1626546 SIG_INTEGRITY FIELD_SOLVERS Extra RL elements in via spice circuit model generated by Via Model Generator
/ P x) X, g' e ?1631792 SCM OTHER The NC net has re-attached itself to another net, RIGHT_LEFT_N, in the design) S+ T7 h3 f* p
1632223 ADW LRM Checking in a hierarchy causes a crash; q0 g0 f/ f$ ~3 K& t$ Z% R- j- X
1632844 F2B DESIGNVARI Part is simultaneously defined as Pref and DNI in Variant Editor with no error
; ^+ t# _& T l' h1633647 ALLEGRO_EDITOR MANUFACT Variant issue: Create Assembly Drawing command not creating filled shapes for keying pegs in attached design
# z; l7 @5 u" s) V$ X% O) ~9 _1633707 ALLEGRO_EDITOR DATABASE Cannot remove Route_Keepout associated with a pin% e+ q: v: z9 g
1634392 PCB_LIBRARIAN OTHER Launching Library Explorer without -proj option crashes the tool
8 w' S- z, Z; c& E! m1 v% |0 p1635049 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes when trying to create layer set from Constraint Manager2 I' s3 W9 j( P9 D2 d
1635593 ORBITIO ALLEGRO_SIP_IF Importing .sip file reports undefined argument error while processing shapes
K/ ]. B! k, ^5 s. U9 c& v1635858 ALLEGRO_EDITOR ARTWORK Get 'WARNING: Null REGULAR-PAD specified for padstack' messages in log file when generating artwork for all layers5 O* _- G+ Z0 a x7 x
1636097 ALLEGRO_EDITOR ZONES Technology Dependent Packaging footprints not updating in the design) ?! w: N/ I" m% Z5 k7 G' @- C# I
1636185 ALLEGRO_EDITOR ZONES Import Placement not placing TDP footprints in zone3 I3 e$ r ]+ t$ r! [ v% S- p
1636867 CONSTRAINT_MGR OTHER Millimeters shown as mils in the Analysis Modes dialog box% ~$ R3 |' W) ^2 f0 }
1638094 SIP_LAYOUT OTHER Cross Section Editor not seeing updated information
2 i' K7 n, i0 r, T" N* v: t1639845 ALLEGRO_EDITOR INTERFACES Step file not generated when board is exported to a folder with special characters in name
- K- k* C& o* ~1640611 APD SKILL Launching XtractIM from SiP Layout with the attached design crashes both SiP Layout and XtractIM
( v" E- W% f7 Q) }. v# ~1 H J6 K, v1641339 ALLEGRO_EDITOR INTERFACES DXF_IN does not show all the subclasses available in the design( r8 O9 T' C( ^3 s7 h4 g$ i0 L
1641879 XTRACTIM GUI XtractIM crashes on extracting a SiP design if 'SI Ignore' is selected for a die stack layer in Cross Section Editor) }. H' R4 y- i
1642012 CONCEPT_HDL CONSTRAINT_MGR Schematic-defined net groups without any members cannot be deleted in Constraint Manager
- N) r/ r* G" w& Q' O3 m5 `, ^( E1 Q* p1642015 CONCEPT_HDL CORE Pin exists on block but no corresponding port exists in the underlying schematic9 v6 K* \6 i, b
1642597 ALLEGRO_EDITOR OTHER Importing .tdp file: Footprints not included in the .tdp file are updated in the design* p3 V+ Y* ~& V9 O; ~8 M( J
1643557 SIP_LAYOUT DIE_GENERATOR Die Text files will not update the design
! n, s% @% D' Z# y; O1646086 ASDA IMPORT_BLOCK Importing a DE-HDL design into SDA results in error 'IMPSHT-42 Alias cannot be created'
" S) X5 t! q2 _, a9 R1647580 ASDA IMPORT_PCB SDA-File Import from PCB Editor has duplicated RefDes on schematic.
) O) P7 L1 M3 g. T4 J! a
) T, c+ _/ V9 l9 n2 i4 E/ A7 Z5 ^' F- Y' I
Fixed CCRs: SPB 17.2 HF005
( S2 b" f, g: y X; W, g+ v09-10-2016
" z' Z, j. G" M3 H0 q x. U===================================================================================================================================* j0 O+ |- m$ V+ `" O
CCRID PRODUCT PRODUCTLEVEL2 TITLE6 b6 R' Q; _6 b' o9 v/ h1 _3 `
===================================================================================================================================
$ F% x8 l! y r4 B, S1 e! Q2 ?1496199 ALLEGRO_EDITOR SHAPE Overlapping route keepouts result in a broken shape O7 h3 S2 ?; @' A% o) c j
1519972 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase DRC at incorrect location" ^4 Z# K" K" W' p
1521940 ALLEGRO_EDITOR DRC_CONSTR PCB Editor not recognizing the correct pin pairs of the differential pair$ M+ [3 W% s& n' ]! o
1536713 ALLEGRO_EDITOR INTERFACES File - Viewlog still checks for brd2odb.log file
: A, ] u5 O! |# K* S9 V1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once
3 u& z/ Z3 u9 R8 @, V6 O" W1586846 RF_PCB PLACEMENT Get an error while manually placing RFCOMPIB part
; R. T) a; o5 W( y0 C1588769 ALLEGRO_EDITOR UI_GENERAL ALT+key shortcuts are not available in 17.2
$ V4 [" q, g7 B) Z1589396 ALLEGRO_EDITOR UI_GENERAL Need option in 17.2 to change the placement of the Find, Visibility, and Options tabs
$ ?* k0 r- f* n E% Z& i! m1593258 ALLEGRO_EDITOR OTHER Adding German letters to database diary deletes all the entries6 i1 d* u$ x/ O8 M0 R
1597413 SIG_EXPLORER SIMULATION SigXplorer crashes when simulating with a via that was added to the canvas: L8 H: J. T d( z j/ o/ f
1599680 ALLEGRO_MFG_OP ALLEGRO_INTEG Documentation Editor crashes on opening a specific database, }- E$ b; Q& W! ]" E' N, a( l. D& _
1606682 ECW ADMINISTRATION ECWBackup and ECWRestore fail when data is 1GB or more
/ Q$ V0 D6 [* y+ r- `1607250 ALLEGRO_EDITOR DATABASE A board file created in release 16.5 crashes when opened in 16.6 Hotfix 69+ O1 c {3 x- F0 ?. R
1607565 ALLEGRO_EDITOR SYMBOL Default values are not consistently converted when adding pins after changing units.6 J1 @# b0 y- W4 C8 D
1607956 ALLEGRO_EDITOR OTHER Unable to generate the model index file from the command line using mkdeviceindex' b N7 {8 H6 @* n. x1 i
1609794 ALLEGRO_EDITOR UI_GENERAL PCB Editor: Shortcut keys to menus are not available in 17.2; K! Q, N. ?$ c0 Z) B, L& _
1609817 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes on opening project! c- [9 u/ n5 }) P7 O$ i
1611446 ALLEGRO_EDITOR SHAPE Inconsistent break in shape when creating voids in a design in 16.6 Hotfix 694 x$ L% I2 V6 |" {+ H- E- t
1613512 ORBITIO ALLEGRO_SIP_IF Unable to read the OrbitIO database file (.oio) in SiP Layout3 I# Z; t+ E& q& Y9 f
1619610 ORBITIO ALLEGRO_SIP_IF Some mechanical pins appear rotated by 90 degrees when imported
8 a& Y. |4 a" y3 E2 ~% f7 j8 f1620814 ALLEGRO_EDITOR PARTITION Etch and Via are not imported with the partition
4 V# K' h' H2 q7 f- f2 }' w/ U: l1621390 GRE CORE Design Crashes during the Spatial Planning phase' Z. F2 g ]* `, B3 D& f% c$ H4 _- s* @
1623112 ALLEGRO_EDITOR OTHER SPB17.2 switch release is unable to identify 16.6 release when 16.6 is installed in All-Users mode
0 c; e2 ?. e" t0 Y7 r1 t7 G1 _1623113 ASI_SI GUI Aggressor waveforms are not displayed in waveform viewer after crosstalk simulation+ o8 R/ ~+ ]$ @/ g0 a" N# }
1623231 CONCEPT_HDL CORE Unable to make the Attributes form part of the standard display in DE-HDL2 A9 G! \' p9 L% ~. `6 R
1623666 APD OTHER Incorrect vector pin syntax appears in the chips file written using 'RF Module - Export chips & connectivity'$ P; w b- r1 }4 ^) D2 w
1623888 CONSTRAINT_MGR CONCEPT_HDL Ambiguous and inaccurate mapping errors reported when an ECSet is applied to a differential pair object
. F5 z- G% o- k: B1 Y% D$ M1623904 ALLEGRO_EDITOR SCHEM_FTB Logic import fails, but no error mentioned in the netrev.lst file
; `9 o; J- A$ F& r r2 G/ S$ Q1623935 ALLEGRO_EDITOR SKILL On running the SKILL function, axlSectionModify, Shield and Etch Factor are not updated
7 _# _5 a8 w. f2 b& J1625610 ALLEGRO_EDITOR SHAPE Modifying a shape boundary leads to other shapes losing their voids, B' D" D! {$ x2 Z
1626716 ALLEGRO_EDITOR UI_FORMS Z-Copy menu is not available with OrCAD PCB designer Professional license
- n4 R$ A/ h B" ]1628403 ADW TDO-SHAREPOINT Objects remain checked out after multiple failed 'check-in hierarchy' attempts
& v" f: ?, }) o9 d t2 ]1630458 ORBITIO ALLEGRO_SIP_IF Import OrbitIO Database file (.oio) in SiP: Bill of Materials report does not include standard dies% f; i, z7 Z# c
1632504 CONCEPT_HDL CORE DE-HDL core dumps during Save Hierarchy on Linux
9 d# y' a! [0 G1633581 ALLEGRO_EDITOR PLACEMENT On mirroring a part, the cursor moves to the origin of the board! w% k/ c! K4 O3 m
1633601 ALLEGRO_EDITOR PLACEMENT Place - Via Arrays - Boundary command: Via arrangement pattern deteriorated in Hotfix 004! Q) m$ d; A6 z# t
" m8 H1 F) c( I: N
* [! s- w6 i; |+ g/ a' jFixed CCRs: SPB 17.2 HF0041 D" V7 ]3 U3 R% z. K
08-14-2016+ t h) A, {8 w! a
===================================================================================================================================
1 U# p9 u# D" B/ u+ TCCRID PRODUCT PRODUCTLEVEL2 TITLE+ L" s5 Z' {: t( x( o) r
===================================================================================================================================
+ F7 s0 F; V E908816 CAPTURE SCHEMATIC_EDITOR Few graphical operations are active even when a page has been locked' l# @0 Q o# [. e( V
1213923 ADW LIBIMPORT Cannot delete parts in the Library Import project (XML)) b2 o) |# H. b6 m( K5 c
1250476 PCB_LIBRARIAN LIBUTIL con2con does not check for PACK_TYPE value set to question mark. f" @# L# V+ p8 c: v* S/ k
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value: I- `& }- l' }$ }. m: {
1322242 ALLEGRO_EDITOR INTERFACE_DESIGN Using Add Connect with the Replace Etch option causes PCB Editor to slow down for certain constraint nets5 u! y+ m: A( h+ Z4 H4 }/ T
1326716 ADW DOCUMENTATION Dataexchange documentation correction needed
1 C/ _/ U+ q6 y! K( h1356948 APD DEGASSING When using the Degassing tool on shapes the size of the file becomes very large
! V! A% h( q2 @! M. E' s& H) M1 j; p1376510 ADW DBEDITOR DX output ERROR after Property Display Ordering of Part Classification.1 J5 o) y; Y$ q
1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file) e2 b, [, q( q1 Z3 |# p1 p
1410485 CAPTURE SCHEMATIC_EDITOR The 'Autowire - Connect to Bus' menu command and the 'W' keyboard shortcut are enabled on a locked design
n" t1 c+ ?6 s* N+ V4 ]1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only$ @' A5 O, C, ` y/ S
1413287 ADW LIBIMPORT Library Import converts all Attributes to uppercase when reading CSV% v, Q0 _& J, ]- S
1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle. ^ z$ x- ?: j3 h% P+ m1 q
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins3 l" ]* Z( n$ _! {( c
1430251 ALLEGRO_EDITOR PLACEMENT Quickplace placing symbols outside of a polygon shaped room1 s% ^6 v7 N* h& \3 }7 L
1440509 ALLEGRO_EDITOR PLOTTING Ratsnest does not follow the RefDes position when plotting the BOTTOM layer with the Mirror option; b, P) F1 R7 n3 _
1441086 PCB_LIBRARIAN OTHER Changes made to a package with sizable pins generated from the 'sym1' view are not saved8 }) t' K0 x4 @9 Y
1443339 PCB_LIBRARIAN PTF_EDITOR ALT_SYMBOLS syntax in PTF file not checked/ L, [, s& _" h# m# }
1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC
! N# @( z- e5 @8 T2 x @9 B) n0 s1451766 CONCEPT_HDL COMP_BROWSER License error message should indicate which license is required
8 }# `3 s/ l; O) {; r, X3 z1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set; j& ^) r4 a$ J3 _
1457138 CONCEPT_HDL CONSTRAINT_MGR devices.dml: difference in content generated by _automodel add command and Constraint Manager launch: R* f" h5 ] k( o' E, ?
1458439 F2B PACKAGERXL The Packager pstprop.dat file reports false conflicts in net properties* K1 V6 z' }4 H# }/ U; L
1464865 CONSTRAINT_MGR ANALYSIS For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM+ i9 ?/ z: L1 s! d5 e( f
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools3 ^0 B0 F& W' V7 n% ^: ^# l& Q
1467826 CONCEPT_HDL PDF PublishPDF from console window creates a long PDF filename
( E) d k0 j' q' t0 C1470106 ALLEGRO_EDITOR MANUFACT silkscreen program cuts auto-silkscreen lines excessively
2 A! }& d9 }* m; s5 F7 u3 x" Y+ L1471287 CONCEPT_HDL CONSTRAINT_MGR Pages imported from other designs with different units should inherit the source constraint units0 q7 O k6 ^; b( s( V
1472046 ALLEGRO_EDITOR OTHER Gloss routine, 'Via Eliminate' - 'Eliminate Unused Stacked Vias' is not removing unused microvias from the stack
+ O. s% o j% Y1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region# U; V% p0 D3 G3 |8 N, r
1472444 ADW ADWSERVER Multiple errors in adwserver.out after SPB054/ADW47
; W; s8 x, ?8 f! q6 g( o1473056 ALLEGRO_EDITOR ARTWORK Gerber export has additional phantom data not on design7 }/ p2 T3 M D; I- Y" Y; @9 P( M, ~
1473900 CONCEPT_HDL CORE DE-HDL stops responding when a hierarchical block with variants defined inside the reuse block is enabled
2 U; Q' x0 R3 y, ]0 ^1474020 ADW DBEDITOR Unable to modify schematic classification when a part is checked out previously by another librarian8 f$ ^% D9 ~7 O3 x5 n5 C
1474066 ADW DBEDITOR Bulk edit performance lags when parts included have a large number of properties. e' {+ |$ g: v; D
1474764 ALLEGRO_EDITOR PLACEMENT In Hotfix 56, the 'place replicate create' command does not produce desired results if a fanout is marked9 j' j3 F. G! h) [0 l! n/ K% n
1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.
4 `$ w$ ^8 W9 |- ?* k% A& Z& f1475650 ALLEGRO_EDITOR OTHER Using Outlines - Room Outline gives WARNING (axlRemoveNet): No match for subclass name - 'BOARD GEOMETRY/__EPB_SCRATCH_'+ y! I; J( D O, o( q t
1476528 ORBITIO ALLEGRO_SIP_IF While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown2 f6 s; w* U- m+ v
1476920 CONCEPT_HDL OTHER Genview consistently fails in some indeterminant manner.
* ]/ @3 F; f1 W+ S0 W9 l1477369 CONCEPT_HDL INTERFACE_DESIGN A significant number of problems are reported when running genview with port groups6 W5 C* T6 \$ @ M: W
1478111 F2B DESIGNVARI Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release! J# e+ a( C: w. H9 v/ D: X6 C
1478200 GRE IFP_INTERACTIVE PCB Editor displays the 'Low on Available Memory' error when updating shapes and then crashes( e* q0 u; v% T0 A
1478680 CONCEPT_HDL CORE Unable to move components in a schematic using the arrow keys) j o( \* W7 i+ a
1479135 F2B PACKAGERXL Hierarchical design reports conflicts when signal names change through the hierarchy& _$ m) O @; q
1479153 CONCEPT_HDL CORE File - Save Hierarchy flags an error and does not update subdesign xcon
, I0 |: p6 h5 L' e8 U1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy5 P3 l3 A/ v3 {. c# n; d
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable& K! f' q% |: X6 T# }
1479569 PCB_LIBRARIAN OTHER hlibftb fails with error SPCOPK-1053% m- i& B" t, P" F3 M* ^
1479785 ORBITIO ALLEGRO_SIP_IF BRD file is not loaded in OrbitIO
" Y" r6 p* E. O y( i0 M1480005 ADW DBEDITOR The DBEditor or DBAdmin GUIs do not allow the same characters in Property as LibImport CSV Files
; d4 J- r z1 G8 t2 E2 B5 _1480367 SIG_INTEGRITY OTHER Differential pair extraction SKILL error% }, @! ?' M7 o& W$ S, a
1480499 ALLEGRO_EDITOR PARTITION Cannot delete partition. A) X' {. K0 G2 Y
1482544 ADW DBADMIN Hierarchical Preferred Parts List (PPL) is not functioning correctly
: U2 M1 _! G+ D7 i8 X1483136 ADW COMPONENT_BROWSE Error flagged when searching a property value with parenthesis or comma in Component Browser in the ADW mode
( r- H0 h( _* t# ~ w, O1483617 ALLEGRO_EDITOR DATABASE Delete islands command crashes database with filled rectangles
' }: x/ u+ B0 Y1484100 SIP_LAYOUT INTERACTIVE SiP crashes when copying and rotating a symbol
" J( H& `: P4 U1 e1 Z1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues0 `0 B: e$ L! U& v9 N+ C! I
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
) T; l& g1 ^# I \, ^: }7 x1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
, o0 z! U! B& y1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project* |4 B Q6 I# _' @. ?/ [5 b" i
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.
: T8 z7 F' q+ @! ]/ ^1486378 ALLEGRO_EDITOR PARTITION Unable to delete orphan partition as it is not listed in workflow manager.
% X% z% B9 W: B% K. J# ?" _3 \4 }1 V1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems
( p& O1 a) g F$ c" ]1487125 ADW COMPONENT_BROWSE Results not displayed in Component Browser for parts with no associated manufacturer parts5 o5 ^5 K6 G4 W; T
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior
8 ^* Z |3 w; r3 N- Q9 S) f1487496 ADW DATAEXCHANGE DX changes checkout ownership when override action is set to remove existing relationships+ W6 q6 R- C: K# L
1487656 ADW LIBIMPORT Pre-analyzing a project reports false warnings
; V. Y/ i* T5 C! K6 f: w- ^7 o1487733 CONSTRAINT_MGR OTHER Export Physical takes more than two hours to update PCB Editor board
% J1 g8 m" I, ~8 ]. c5 e1488753 CONCEPT_HDL CORE Import sheets in a design with no change in models: CM_VALIDATION_ON_SAVE variable is triggered% h% a l+ X; b: E- t; x5 b
1488758 CONCEPT_HDL CONSTRAINT_MGR Disable Constraint Manager launch if CM_VALIDATION_ON_SAVE is set and the database goes out of sync
4 z2 k8 q3 K) g A s1490299 SCM OTHER Allegro System Architect does not update revision properly
+ E# G! E( ?4 c6 h0 j" E- G1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer7 B& m7 G% W7 ^0 a( w
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
8 c& M5 m/ h+ b$ h, \* w1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working0 {4 D2 Q4 V( a$ j
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)' K$ c1 J. D" S( ]' E, ^
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong
' f$ [: f7 F3 Y( b0 |, _1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit7 X/ E, I% H( F$ m% t; \% H4 P3 O
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO crashes on importing MCM5 h4 k. P+ b4 O% z: V, o. o
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL; c! Y) l5 g/ p8 Z( N+ ?+ l
1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs
/ t9 ~( U+ N% c1 h8 V1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size
! h3 \3 K% t6 D6 {2 y1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root) `* e9 W/ s. z& S" p. G
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file
, _6 f' s/ z; x5 l7 \0 J1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60' C5 ^& y8 M' P6 b( s( {. A
1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
, W/ k H9 Z' F. I$ Q* H1500725 CONSTRAINT_MGR CONCEPT_HDL Unable to clear pstprop.dat file conflicts- s/ \( R5 ^) \# Z8 o
1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant: ~# {6 r( d3 }. ?4 O
1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out
& P" I9 \0 w: ]4 I, G1501294 ADW COMPONENT_BROWSE Some tabs missing after the migration to ADW ISR 053 with SPB ISR 0605 M: d7 E a& Z6 Y1 W1 \ F* z
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
8 R. F2 ?/ o. W' }! K2 Q( M1502282 ADW CONF Configuration Manager: Clicking 'Set up or Manage Company & Site' gives an unclear message
) `% ?" s* L# t: \2 h% T. m1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings( t- ?5 G, L9 h1 {- ?7 b
1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized7 a; R) Z }: `# N) g1 g1 V& H
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
6 W. q! y; j2 m' ?5 b1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin0 r0 @ v- q# H( J4 l
1506654 CONCEPT_HDL INTERFACE_DESIGN On moving, Netgroups break- i/ C: h5 r. N/ H: d% f
1507497 ADW COMPONENT_BROWSE Switching rows in Component Browser does not change the graphics of the symbol
+ @7 V! j# i2 V: f4 c- ~1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork
) P) N+ R0 P2 @" M, B w( V1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain- u9 D0 t7 p+ F; E
1510570 ADW DATABASE ERROR: Cannot check in block model because the part with instance id used in the model is not available in the database
3 u* M& S+ W3 @+ V1511180 ADW DBEDITOR Database Editor: Incorrect message about a schematic mode displays when associating a footprint to a part number% ]; j( M1 A2 Z. R6 g
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
4 y. S5 z4 l7 \1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance( N- y/ a! _; t, i M3 Y
1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.5 V. d; `- ~( Z3 Z
1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
p( J5 K: q% j# m: M! ~1513085 CONCEPT_HDL CORE NC symbols in the schematic are being renamed to NC_1 in pstxnet.dat and are routed as one net in Allegro PCB Editor, k. e6 H0 u ]( w
1513092 ADW DBEDITOR Create Footprint Model name is not working properly if it already exists in the local flatlib8 b2 k5 l& H! Y; ]. K4 |
1513737 ADW CONF DesignerServer from a different network domain does not show distribution data; y5 m7 D. s) L7 r
1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property. x3 N* G/ O8 N
1514942 SIP_LAYOUT CROSS_SECTION AIR no longer permitted in stackup in 17.0- }0 f8 i+ t* c h. J5 `
1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly
5 F6 a6 V2 P' o: Q1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol% o4 u! s5 y8 s% N+ \: G- o: w
1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
1 K( ^& D2 o4 z1518032 CONCEPT_HDL SECTION Error SPCOCN-2009 displayed even when the user has not manually sectioned the design9 [9 W8 V7 P0 P0 H, S
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes" l$ U6 w/ G; r) _8 f- x
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.9 d" j, f* _- l) ]: b9 Q1 q' W
1519518 CONCEPT_HDL OTHER Genview does not generate split symbols
7 X6 A" @) {& ]7 ]) K i1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas
9 j' }7 g4 M6 J( ^7 K& [1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default6 ?1 g, Z+ {& }3 ]4 P/ K2 G
1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net
7 z8 W1 h3 R1 Z- y# V1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist+ x; `) C" U' B+ W: d
1520207 CONCEPT_HDL CORE Genview crashes after renaming ports8 F" W( {6 Q) ~0 ~. B
1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
: F) S& t: H/ e; Z; Q( w- f1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor; o J1 k% {, x( y* A1 R
1521871 CONSTRAINT_MGR CONCEPT_HDL Constraint Manager launched from DE-HDL allows space in the name of layer sets
# |6 o( B) N1 ^9 \5 V! u+ @4 x1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.( ~4 K, a7 s1 X; s0 d3 I6 |
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP Layout design- g4 \* ]( g3 l1 }& o
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash" {, r2 Q$ [' ~- V% R' l5 J) \" s, w: X
1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated
# d/ q8 y; \* ~* b$ b1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine4 L; X e# Z7 B% V
1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor0 j* L" j7 q' l. f2 y
1525883 ADW DATABASE Invoking libimport on an existing DB should verify that the 'libimp_su' variable is set correctly
, F4 B& l2 R* ^, i- X1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct$ J s2 o! x" x- N
1526914 ADW LIBIMPORT Cannot import to new library database
5 J$ d+ }9 p) U1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63& n8 Z) ]) j6 H. x
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.' S: u1 D' T/ \
1528235 ADW DBEDITOR Running rule 'Validate Classification Property and Property Values' results in property mismatch error
$ c( M" U6 {) e7 o, t3 g, [1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes: K9 B3 |+ G2 d6 f
1528398 ALLEGRO_EDITOR SCHEM_FTB Netlisting of pins with NC property results in error
3 o2 `5 M1 x" o2 ~7 _4 C6 r1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design. n- D8 A7 ^5 f. y0 }
1528894 ADW DBEDITOR Lack of PTF_SUBTYPE in the classification prevents the release of the part
! r! F: K9 T7 v7 n+ `8 a1529178 SIG_EXPLORER OTHER When an ECSet is created from a net, values are not transferred correctly for PinPairs5 m- H; e7 w4 r9 S! g
1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions- ?5 ?3 c& Z/ N1 }- m N, {
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file
. S/ _3 z f1 X3 x1530445 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when 'Add Connect' is used$ e, z5 v; n2 I {
1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes
# e2 q/ }3 V, z, I1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup+ X3 {* l, e5 A, i4 ? y
1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr2 K7 }3 F/ C# C" A
1533543 ADW DBEDITOR Component Browser free text search returns 2 parts when only 1 exists) O! g9 \9 u% N$ R. j8 S
1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue7 x1 \" |: I+ F3 j; Q7 k
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
& X6 T( f9 H! x' Q* w$ ~' L1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
: w: L1 O1 ?5 Z8 h' p1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform
4 O& f2 I" E4 \1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing 'Layout - Renumber Pins'5 \6 f1 N0 R2 K. ^, [
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
0 p) o9 r$ z% v4 i1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run0 v+ b7 J P5 M& \/ d
1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error
/ E$ C$ t. d* S' c* i# O1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib3 [& m( S7 C ^6 d
1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board
% q' s/ L- o2 d" c0 [1542949 ASDA EXPORT_PCB The Export to PCB Layout form: The file name specified in the 'Output Layout File' field is not accepted% `. E2 Z9 E" \4 b1 M7 b
1543537 ASDA NEW_PROJECT While creating new projects, the new folder name is not visible clearly in the explorer, Z/ l5 W/ L k2 l! R! _" G& g! r
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
! ?% o0 N0 E. i4 x1 E( r1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash! V. M1 ]" u6 v* A2 P4 b ~# h/ d9 d
1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked4 _/ [+ S6 H8 O2 q n4 ]: A' i
1544856 ASDA CANVAS_EDIT Edit > Find places the process (UI) behind the SDA tool.
2 Y. @8 q7 T- U; v' C) e7 }1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
) y/ z h, S9 t" K1546062 ADW TDO-SHAREPOINT Failure to launch TDO Dashboard, need to update error message with more useful information8 l( g x) z& G) n
1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'
/ h8 y* T3 r0 h. S3 b1549658 ADW TDA An unmapped network folder in the Team Design Authoring option results in an error3 l8 T4 G, h$ h( @$ Z/ u3 v
1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols8 C& N2 [8 i0 ~7 {9 @ ?! Q
1551635 CAPTURE TCL_INTERFACE GetSelectedPMItems returns error for design cache objects
: R5 |& t( w; ]1553027 ALLEGRO_EDITOR UI_GENERAL PCB Editor canvas stops responding for tasks such as resize and workspace switch7 z2 g c7 R9 u8 g
1555246 ADW DBEDITOR Part Copy As does not copy AML and reliability model relations.
" z- h4 A: `+ y5 C0 o1555254 ADW DBEDITOR Text in Free Text search box is removed if it loses focus
" _& v1 B4 N5 u8 ^- L) M2 a- {1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon
' V. I w2 C- T+ H. y1573039 ALLEGRO_EDITOR INTERFACES IDX returns control to the general interface prematurely during an incremental IDX export
1 \/ x2 N" C( S( `1580571 ADW DBEDITOR XML files continue to appear in flatlib even after the padstack/footprint models were released7 f) U4 I3 e: z( o+ e$ l" M M
1580580 ADW LIBDISTRIBUTION The .lis file contains references to old models even after they were purged.6 P- ]/ n4 _ O8 J+ _
1582064 ALLEGRO_EDITOR UI_GENERAL User-defined menus not working in PCB Editor 17.2
$ ^( X$ K- H W' Q' X1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes
, N1 n1 Q2 \; E+ h- t4 K4 y2 N9 Z1582856 PSPICE MODELEDITOR Getting 'ERROR: [S2C3471] Base part library does not exist when Export to Part Library', though olb is created
; a2 H" J2 p m) k1584719 TDA CORE Caching errors are flagged for a board-ref project during block update: o% Y- e& \" L
1587045 CAPTURE IMPORT/EXPORT Unable to import PDF file$ ] R( r% \* L% C! C
1587259 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not working correctly for the 'bottom' option
8 h3 a- Z4 J x7 D" g1588736 PSPICE MODELEDITOR The Model Import wizard displays 'Invalid configuration' message when a .lib file is opened in Model Editor
) N) n% r% i; e: K5 n0 d# G9 O1588742 PSPICE PROBE Browse icon is missing from PSpice File - Export - text
* D6 X8 r5 e6 u1 r4 g$ H1590006 ALLEGRO_EDITOR UI_GENERAL PCB Editor 17.2 crashes when multiple browse windows are opened/ \8 `+ m @5 l3 O: [8 w
1590597 PSPICE PROBE Problem with the adaption in the Probe Window icons- u; K) k, X/ i# M
1591264 ALLEGRO_EDITOR UI_GENERAL Film order in Visibility View is sorted alphabetically and does not match the manufacturing artwork
( ~ T0 Y: X' N0 S. \! @( [1592089 PSPICE MODELEDITOR Cannot get the PSpice DMI Model DLL while using PSpice DMI Template Code Generator
' L. t* h: o- G" ~* q1593436 ADW DBEDITOR Cursor does not automatically move to the model name cell when creating a new model
# n0 ^ X5 h! X3 H- [1594076 TDA CORE TDO crashes on concurrent check-ins when one of the blocks was not modified.
; u' ~4 B# b( y2 l' i) i/ }# U1595987 ALLEGRO_EDITOR PLACEMENT Subclasses not getting updated in Placement Edit mode( \4 k8 G3 Y- G. Q2 B
1596162 ASDA IMPORT_DEHDL_SHE Importing sheets from DE-HDL imports the block as well
: r/ Y# z+ C( v% [1597000 CONCEPT_HDL INTERFACE_DESIGN Renaming a NetGroup does not work if several segments of the NetGroup trace have the same netnames assigned.
. y j/ y! W; C1 ]% B2 B% c1597406 ALLEGRO_EDITOR SHAPE Dynamic Shape does not void the traces and voids open areas8 W. w/ Z% X& s' b; V* D J% E
1597957 ALLEGRO_EDITOR PLACEMENT Quickplace: placed and unplaced counts not getting updated1 i6 n3 n) }2 g4 f
1600194 ALLEGRO_EDITOR DRC_CONSTR 'drc update' gives a different DRC count each time the command is given in a multiple-cpu system$ @3 ^2 g' _! G# o C9 f; {1 m( d
1600800 ALLEGRO_EDITOR GRAPHICS LINUX 17.2 operation of Update DRC is not the same as Windows – graphics not updating
7 F0 W2 C; X: E- N1 |1602605 CONSTRAINT_MGR OTHER OrCAD: constraints not getting saved
# g* R" l9 r. M1602801 SIG_INTEGRITY OTHER Dielectric Warning message when opening SiP tool.
7 N! w' Q6 m: P3 P+ b8 z- k1603377 PSPICE ENVIRONMENT Running simulation with the 'At Markers Only' option does not generate the .dat file
4 q0 n" q# P- t1604166 CONSTRAINT_MGR CONCEPT_HDL Audit ECSets does not work from 'Referenced Electrical CSet' column header3 y8 W' w4 U" N. W. D- @0 O
1604741 ASDA CANVAS_EDIT Tcl console changes the present working directory when you open Project Preferences and close it.
7 ]# n1 v( o. u' ^- T1605310 TDA CORE Join Project wizard: Random crashes in the Team Design Authoring option7 ^7 }9 W) p+ C9 u4 r
1606861 CONCEPT_HDL CORE DE-HDL crashes on Linux during the Generate View operation& @0 n( S# u- t6 P% a5 n- I9 J$ k
1606917 CONSTRAINT_MGR CONCEPT_HDL Importing tech file in DE-HDL Constraint Manager is creating a duplicate 'DEFAULT' cset3 d6 X' N5 P2 r" A
1607157 ALLEGRO_EDITOR INTERACTIV Edit - Change allows lines to be copied to Cutout subclass, but that subclass requires closed polygons
) Z4 p2 M( W3 I7 `; w3 e A" z1607330 CONCEPT_HDL CORE Variant view schematic PDF corrupted with attach_props set: R9 y( z7 r0 k1 _; n$ x
1607568 ALLEGRO_EDITOR NC PCB Editor shows wrong drill legend for Top-to-Top drill
5 x, y$ a! F! k a) Z1607986 CONCEPT_HDL SKILL cnGetSetupProjFilePath: The SKILL routine does not deliver the full qualified path and name of the project in 17.2
7 m8 q& {! L/ p& b, [1608524 SIP_LAYOUT MANUFACTURING The Display Pin Text tool fails in the 16.6.073 version with a parseString error.
( k6 U8 E& c- `1609400 ASDA CANVAS_EDIT The 'Assign Differential Pair' right-click pop-up menu command should be grayed out when a single net is selected
! q7 d4 q S* h! R2 C" j q1609809 ALLEGRO_EDITOR UI_GENERAL Crash in Allegro PCB Designer version 17.2-2016 on Linux
5 f# E8 ]* k+ D0 K4 n1609856 ALLEGRO_EDITOR ARTWORK Embedded paste and soldermask showing up in both top and bottom gerber files.
' n# C, w+ f9 U: g& }) ?& K1609922 CONCEPT_HDL INFRA Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only
- E. V( o6 E1 d' I6 ]; {1611226 ALLEGRO_EDITOR SYMBOL PCB Editor gives a crash message while saving a flash symbol
5 W9 q g( u1 S% S4 X4 c7 V1612108 ALLEGRO_EDITOR OTHER Netlist Import is crashing with the .SAV message.
- i7 N i1 d- L) ~# p- x1613123 ALLEGRO_EDITOR SKILL DrillType for Oval Slot should be 'OVAL_SLOT' not 'OVAL SLOT'
7 ?. d I, ^1 D9 ]1614000 ADW LIBDISTRIBUTION Library distribution (lib_dist) does not complete; lib_dist.lck cannot be deleted when Configuration Manager is running3 r% s0 a& I; A6 I0 |
1614667 SIG_INTEGRITY SIMULATION Different results from Probe in Allegro Sigrity SI and SigXplorer: e, A. `: `" m5 s. @
1615601 GRE IFP_INTERACTIVE Delete Bundle then try to delete plan lines results in fatal error1 I+ B" T# k( V
1616235 ORBITIO ALLEGRO_SIP_IF oio2sip import does not map layers correctly. f( q& O7 |. a u+ G
1616540 SIP_LAYOUT DRC_CONSTRAINTS Same net DRC Line-to-Line reappearing after dyn shape update
$ C" x$ M, o" `- v* T1616733 ALLEGRO_EDITOR INTERFACES 'genrad output' no longer working in 17.2. Gives the Error 'extracta process failed. Command terminated'* g9 c/ l0 |; h) ?" z4 P3 Q
1618751 ASDA DRC Zero Node Net errors flagged when DRC checks are run, though RETAIN_ZERONODE_NET is set to 'NO' in Site CPM file3 q* D: t% z$ R- x0 W# u
1618797 ADW FLOW_MGR Flow Manager cannot execute a specific command in 17.2.. ~- R9 ?8 \: I, `2 V* x
1618930 CONSTRAINT_MGR INTERACTIV Hovering over row column cell causes the application to go into a not responding state.- k, c/ H; h9 d8 p$ a- {
1620350 ASDA EDIT_OPERATIONS Pin number is lost on updating the version of a connector pin& A1 Y* R* ]9 J/ M, b( Y
1621963 ASDA SELECTION_FILTER Selection filter: Pins in the symbol used in connectors are not selected9 E9 Z: h8 O# `. o9 s$ S
1622715 CONCEPT_HDL CONSTRAINT_MGR Extracting an XNet crashes DE-HDL
L- D" I" M: D7 p! K1625209 ASDA IMPORT_PCB File Import from PCB Editor shows board differences
) L" U" }$ q, N. t) t4 k/ p! t! {5 s5 @) F, u& y
2 {3 _& J0 I) HFixed CCRs: SPB 17.2 HF003
5 Y% w' L: @+ p9 Z+ |07-28-2016 y% P" ^% V* a: G" N
===================================================================================================================================
p* x7 E' V' J8 p) ?3 a: \# G7 gCCRID PRODUCT PRODUCTLEVEL2 TITLE& q; b4 Q0 l6 M( _' a$ l
===================================================================================================================================
E/ k8 l) y% |9 j5 |6 R/ n5 k0 X1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result+ m! F7 ^* `4 G5 m- M
1461626 CONCEPT_HDL CREFER Cross-references shown to the same pin on different block instances though the signal names differ
9 |$ R2 N3 K+ f% z1472456 CONCEPT_HDL CORE The design connectivity (XCON) file and design data are not in sync/ ~1 w8 {8 Z- i: }. n8 k8 ~
1546151 CONCEPT_HDL CORE Add port, Genview, move pin on block - the pin name disappears6 i+ u2 a% i' ^! ^
1547356 ALLEGRO_EDITOR EDIT_ETCH AiDT gives different results in ISR S034 and S066) E1 P- Y3 [6 } X; |1 J( D! |/ {
1560102 ADW FLOW_MGR Flow Manager: None of the eval commands working
g1 I. U I, g) d( W) h+ J! u6 Q, T1570032 ALLEGRO_EDITOR GRAPHICS 3D Viewer shows flat LED for a specific design% c0 o6 [$ B. d8 A- n. v9 c8 c9 q
1574676 ORBITIO ALLEGRO_SIP_IF Updating the OrbitIO database with a modified .sip file gives errors
; u8 O/ l# S' q" N4 r# X/ K1578876 ADW ADWSERVER Component Browser crashes when trying to show details of a part number" i7 e& n9 @6 E4 F, ^% X
1580744 F2B PACKAGERXL Running Export Physical results in error SPCODD-1148 u2 k- n, R( M" B
1582863 CONCEPT_HDL CORE Generate View creates non-existent ports
; @4 w" l) H% E, d9 z- l& J1584317 CONCEPT_HDL CORE Provide an option to open pxl.log from the Design Sync window when packaging does not complete successfully
5 T7 B, m1 F- ?8 ` c1 k% u: T1587018 ADW FLOW_MGR User is prompted to specify the flow name each time the project is updated: _/ V$ H5 I! G3 E
1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties
( W: i( N& m( i$ ?+ i1 U! F1587498 CONCEPT_HDL INTERFACE_DESIGN Need the ability to tap individual bus bits
/ U/ ]( I0 e; c( y5 U3 r3 W1587718 ADW LIBIMPORT Library Import - The Pre-analyze tool does not report errors
& O4 O; S: U: x# M1588197 ALLEGRO_EDITOR INTERFACES STEP export fails when External copper is selected on Windows 10
9 a4 u) P9 S7 _& k* r1588786 ALLEGRO_EDITOR OTHER strip_design reports 'Design has been corrupted'/ t8 J$ E# z" p8 c) t! r
1589252 CONCEPT_HDL CORE Search results zoom into the page origin instead of the selected components0 b* x0 O; V6 X! k
1589318 ALLEGRO_EDITOR DRC_CONSTR Via to SMD Fit DRC reported between embedded pin and via which do not share layers
8 {- G! O) X0 y/ H/ q' o" o1589979 ADW FLOW_MGR Design Name change does not reflect in Flow Manager in the same session of a project& D% Z2 D' x, I- u7 u* F
1590538 CONCEPT_HDL DOC Open Archive: Some observations on the random behavior7 R; _ u# {8 P$ T6 t
1590639 CONCEPT_HDL OTHER Importing a design in DE-HDL results in a crash
1 @; {7 v7 O, ]! D9 o6 m v1590651 CONCEPT_HDL INTERFACE_DESIGN DE-HDL: Duplicate NetGroups created in Interface Browser and Constraint Manager
% }/ _7 K9 A7 Y# m8 U1590720 ALLEGRO_EDITOR INTERFACES Exported Text Size Parameter file does not load names into the text table
: F# \$ Z# l: t) h! E1591070 PSPICE PROBE PSpice crashes when using the Trace - Measurements - Evaluate command+ |2 N' z9 L5 t5 O( b
1591223 CONCEPT_HDL CORE Variant information for lower-level schematic not displayed- ?5 k5 \6 n( L& Z! ?% w
1594240 CONCEPT_HDL ARCHIVER Archiver is not able to change the permissions of the cells archived2 `. {# ^. ^9 y1 E+ ^+ \/ a9 Y m
1594416 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when you create a new pad
/ \' N7 a9 `+ h1596615 ADW DBEDITOR Unable to search parts: Component Browser did not launch; Database Editor did not return search results0 j* v. g( _4 [& n; d/ }. E! _
1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save* v- K% ^% l( F; F* {3 |
1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor
& _1 S6 C/ K" `. Y, @1597385 F2B DESIGNVARI Some 16.5 variant DNI parts appear in 16.6 as X-OUT and some without X-OUT or DNI7 v& d! f, c$ y' l+ X6 V* I+ ]4 x
1598629 F2B PACKAGERXL Export Physical crashes after flagging error SPCOPK-1458
+ Z* K/ N5 }* e _( A1599452 ALLEGRO_EDITOR ARTWORK Import Artwork with Mirror option does not import pins or shapes$ y ]* k! Q$ ?7 w, d# E
1599744 ADW FLOW_MGR Flow Manager: Commands associated with some of the buttons not working
# K" x' S, z& U7 q- [0 d! K1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.9 }1 h9 r8 h0 ]2 R" |
1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group5 _6 y" w& R. r) `0 x5 m
1600618 ALLEGRO_EDITOR DRC_CONSTR Casing of property names is affecting results when working with Physical Constraint Set4 D1 \5 z* v: t8 V/ O: Y
1600914 ALLEGRO_EDITOR INTERFACES Exported PDF has unfilled shapes despite enabling the 'Filled Shapes' option2 a. o! H) ^3 f/ L% u* e" {
1601165 ALLEGRO_EDITOR DATABASE Thermal Relief is not added for Rounded Rectangle pad
6 c2 [- W& X9 N6 F1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol
! k# n4 I" }% r f$ _; L& N1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name.0 t9 S$ p4 g+ p
1602514 PCB_LIBRARIAN METADATA References to some primitives missing in block metadata;TDA errors reported for missing parts after joining a project
1 q s: m. D0 T6 U' \) A% T+ t1602823 SIP_LAYOUT WIREBOND SiP crashes when using the Add Wire command
. s/ X, F: Y. _( g4 Z+ V- W1602955 ALLEGRO_EDITOR SHAPE Shape to Route Keepout DRC not reported for attached database
) I4 ?; k$ [5 M1 @1604223 CONCEPT_HDL CORE Tool stops responding after error SPCOCD-553: Connectivity Server Error
5 u/ @" F4 [3 p1604746 ALLEGRO_EDITOR OTHER In 17.2, layer data is getting changed when importing extracta files into other thirty-party extraction tools
7 A+ E) M( K3 F: v/ u1 A2 S' j1605322 ALLEGRO_EDITOR TECHFILE Generating tech file in 17.2 takes much longer as compared to 16.6! i0 }/ O! V; M- e4 }& U( [3 g. b
. F( k% H0 g! `- x. H( a
/ B* |1 J w) ~Fixed CCRs: SPB 17.2 HF002
; Z1 X& A, F' O0 l6 o06-31-2016 i" F& I- k9 i% ^' |
===================================================================================================================================
- I3 w- M: S1 R, {6 `4 [CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 W" t* ~8 I! g===================================================================================================================================5 A4 |& B# F" c" [/ D, c0 R
1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets
4 q. Z& E5 F( ~( C ~: K1469146 ADW LRM Packaging error reported after updating the design using LRM0 M% k" R+ h6 L# H8 w
1481802 ORBITIO ALLEGRO_SIP_IF Import of an OrbitIO file to an existing SiP file offsets the results incorrectly& h/ V- t; p. u) \
1518957 APD SHAPE Shape void result incorrect
7 i/ r. z0 J: ]) @: |1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error
! z3 m: _' q7 p% C9 D1524947 SIG_INTEGRITY SIGNOISE Custom Stimulus is not recognized correctly in Allegro Sigrity SI or PCB SI.
5 P) X f- R- x, X9 I1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.% b+ ~8 E5 m ?* \0 \
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in the attached design.1 ?7 s8 W, g. z" F/ f8 b
1544675 ALLEGRO_EDITOR OTHER Export Libraries corrupts symbols if paths do not include the current directory (.)
! _. y' M3 Q9 l& ~/ o& _( J% F1 `+ c1549097 CONSTRAINT_MGR XNET_DIFFPAIR Show warning message if differential pairs are created for nets with voltage properties
4 c5 g* U+ m! O/ c+ L1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None'$ @* T3 z! B& O. j: _/ D
1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library* R2 r4 x3 i: }& B& J! u
1555009 CONCEPT_HDL INTERFACE_DESIGN Unable to rename a NetGroup.
/ p5 J& g: e- \9 k1 Q, G8 V1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets% Z$ @+ B. G3 ?* R G, ~
1559552 SIP_LAYOUT ORBITIO_IF device offset in oio2sip translation
" d0 Y( K6 b) |. d C1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
; r$ r! [* d, \3 o9 G1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters: a. `$ Y3 a) `+ }5 a
1561501 ORBITIO OTHER OrbitIO stops responding when refreshing a design in SiP Layout
. U8 t3 T5 ]/ ]/ f! i1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC
1 e/ T( G5 y- S ?1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins! L" w! }5 [! |9 z/ e$ {* o
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas
3 ?& m) V/ s9 k( O7 @6 W+ F1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions' l# @/ A C+ B, ^) y) u" j
1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete( u0 ]) }4 {5 [; [8 ~
1566942 ASDA MISCELLANEOUS Several extra files in the /tmp/ folder on Linux% c( {% k ^4 Q7 U- {) |& I
1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.
/ L' L; q P. j1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct1 N* x. K9 Q$ `! f) K3 j7 W h" Q
1569056 CONCEPT_HDL CORE Opening the same drawing in multiple cascading windows view displays non-existent artifacts3 A% m6 @, t) f
1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'
, b! k: F- C& X3 F1569147 CONCEPT_HDL CORE The signal name auto-complete drop-down list is not displayed correctly
8 T$ X( c' a3 M& z1 J, D1569394 ALLEGRO_EDITOR SKILL axlPadSuppressSet( 'on 1 '(via)) not working on SPB17.2- h |& j7 \2 T# f, j' b
1569924 CONCEPT_HDL CHECKPLUS Checking in a large BGA into ADW results in an error related to negative signals
& @6 ]' ]% G% H( z# f+ P( Z1570398 SIP_LAYOUT DATABASE Diestack layers cannot be deleted if there are unplaced symbols in the design
5 u& F8 E3 F& Q3 ~/ R1570419 CONSTRAINT_MGR CONCEPT_HDL Need to add a customized worksheet custom property weblink in Constraint Manager
5 g. A% V! p+ V) K1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short
" |, O! m4 B/ P& c3 u1570678 F2B DESIGNVARI Variant Editor: Error when adding an RSTATE property
; C: A: x) |2 Y) T" q1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only4 W* P) v. D( |1 [2 ?0 b1 A
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display, n2 ~5 z$ A* b; [+ `5 F
1573127 CONCEPT_HDL COPY_PROJECT The CopyProject functionality creates an incorrect 'view_pcb' directive value
' ]. t* P" h9 L; m0 ]+ Y+ v1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)
& x) p5 C3 r2 q! `6 ?/ I1573625 CAPTURE PROJECT_MANAGER Toolbar customization is reset when Capture is re-invoked in SPB 17.2
# a4 P0 I2 J. r; x8 t: V1 {1573755 ALLEGRO_EDITOR CROSS_SECTION Changing a layer's type is also changing its material in Cross Section Editor3 S `5 S2 U7 N3 i
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the project CPM.arch file1 {- T; g& q1 j; p, X
1574381 CONCEPT_HDL OTHER Packager crashes on repackaging a design with RefDes related advanced settings% Q1 Q$ Q9 U+ l0 B4 P) a X: I
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'+ T5 i/ {0 W+ L7 _
1577381 CONCEPT_HDL CORE ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure% ]( x9 H K' P2 L. g
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files. u3 w% Q- F6 S* q
1580891 SCM REPORTS Dsreportgen crashes in different scenarios
; W/ b" G; ~( T6 A7 X# k1581254 SIP_LAYOUT CROSS_SECTION Cross Section Editor crashes when adding a layer
! s2 }5 S5 z; d* F2 `1584957 ADW FLOW_MGR 17.2 Flow Manager, JavaScript - Tool Launch Error
* s; s: N! W3 |9 D% v1588823 ADW FLOW_MGR Flow Manager: In 17.2, using back slashes in the UNC path results in problems in working with the tool
7 X% s; P) q1 M9 i1 x1590064 ADW LRM Allegro EDM Flow Manager - An empty LRM dialog opens on design load in 17.2
$ \$ B5 q% ?% m! T8 q# G7 S/ Y8 U
' {) ]# I% B/ B1 M# E+ p& e
$ s( _2 n- n1 r# i: |$ h1 L0 @Fixed CCRs: SPB 17.2 HF001
5 E# C' j$ ]; E: a8 n |$ |05-06-2016
+ B7 x" P! J: `3 Y& K) _( N/ I& Y===================================================================================================================================0 S# R% u/ a- c+ ]& M0 m8 D8 |" _
CCRID PRODUCT PRODUCTLEVEL2 TITLE
% _5 d* q: B- R+ {9 g8 S1 ?===================================================================================================================================
: o' ^+ k) h4 g- u& t8 U1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output
! `: ]# T3 k# f/ B1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group
- ~5 L) g7 D/ C1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
% x0 ]7 c& w- l, x( h1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail! I- y, G% z# S/ U3 Z* H, f
1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
+ R. B; s( k" K1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
% _( {% v# t4 N* M9 S1506672 ALLEGRO_EDITOR INTERACTIV In the attached board file, when using Replicate Place, some shapes are missing from some layers/ L+ v% p- r" E& m' V
1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager
1 ?5 X! B U0 I. A" T1523532 F2B PACKAGERXL Adding subdesign names in the 'Use subdesign' or 'Force subdesign' sections hangs for more than a minute
$ A1 K3 A' A# R9 o4 y1 \1525783 CONCEPT_HDL CORE '\BASE' scope does not work for SYNONYMed global signals
; `) L: K" i; I; d o1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash in the interactive and batch modes
. ^0 P; c1 W$ f$ Z! T) g& D0 w1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork9 W, G: |1 J; V m( e
1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed, n( \, G0 v1 X- j& k
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.
b+ w' j& S5 N9 \1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
$ A0 A: ^5 k0 q" I1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols
. A0 r8 Z9 @4 u6 }1543410 ADW LRM LRM shows confusing part status; reports that update is needed but clicking update does not work" \) P+ M0 S8 J) L" G+ m
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file$ i& L& Z4 O% f" \" S
1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design' G# w5 R/ x3 T# h0 d. l
1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license; V' k9 V0 y& d$ }) p0 f9 g
1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork) ]/ Z. b" Z1 X! c% F; l f
1546877 CONCEPT_HDL CORE Align Left on wires fails with incorrect error message
! u4 D- | e+ x1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system3 u1 V7 \7 t+ ]' K8 H8 Q R. P0 ^+ U
1547584 SIP_LAYOUT OTHER SiP - Design Variant: Delete embedded layer if not selected" `: R$ F. h' h5 {0 w( x
1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol
8 j( f: n B! s1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file
' S" T3 ]1 Z1 d; f( P6 X `- g8 E* @1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report' b, h1 M, P w, }$ S5 y3 E
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines
" n. }9 x, i u1549662 ALLEGRO_EDITOR OTHER Import Parameters Path fails if parampath does not have the current directory (.) set
! o- b$ p/ [2 G5 V9 P1549836 CONCEPT_HDL CORE Tools - Customize - Keys - Reset does not reset keyboard shortcuts" r3 C' a0 ~. ^! u/ r% q, i, D: U, Y
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems
4 B& K! f; H/ h" q$ y# Q2 S0 {9 q, ^1551713 ALLEGRO_EDITOR DRC_CONSTR Hole to Hole DRC between via and pin not shown5 z( o% r: h, g3 Y9 Q" {
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl(pixel2UserUnits) crashes PCB Editor
* P1 z7 |& q* D9 C/ \1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to NetGroups
0 k0 i3 Z+ ~7 @: ~) m1555092 SIP_LAYOUT DEGASSING Degas offset is not working with hexagons
0 K# I0 @2 X+ i1 c `9 ]% M4 [1556261 ALLEGRO_EDITOR DATABASE DBDoctor crashes with the error 'Illegal database pointer encountered, Exiting DBDOCTOR.'
B) d5 M$ N8 m# M5 M4 V1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted. o- t/ O# F% I; G" `7 z7 @- v
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor - Refresh co-design die! {" j! K1 v% e, b+ u; Y
1560197 CONCEPT_HDL CORE BOM-HDL adds extra characters to subdesign_suffix when generating hierarchical BOM4 w! o7 ?' w) ?1 d2 u0 B" U
1561077 ALLEGRO_EDITOR INTERFACES Beta - IDX User Layer export fails on Linux
( R0 ^: j3 W! g! m3 I1562537 ALLEGRO_EDITOR MENTOR Using mbs2brd in 16.6 gives a fatal error k/ H& |1 w, v4 M- c. j
1564203 ALLEGRO_EDITOR ARTWORK Cannot generate negative artwork' W3 p0 i6 R/ y
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发表于 2019-11-5 13:54
楼主