|
|
Readme for SPB Release version 17.2
7 X, h0 D$ C7 x" ~" q9 c( s8 T9 R
1 [/ u; Z% E0 DCopyright (c) 2019 Cadence Design Systems, Inc.
" Q4 r3 Z$ D7 J& E/ {All rights reserved worldwide.
+ g& a/ @+ ]9 y- v5 n% G% V6 s1 ?0 T
" [* p5 \# k- b0 AFixed CCRs: SPB 17.2 HF060! ~; L3 z C* C# @: |7 r
10-11-20199 c, ~7 c' V, \% H. S1 X
========================================================================================================================================================* `1 r8 `4 z5 L |: m' a
CCRID Product ProductLevel2 Title/ l! ]; n0 q& t* R3 e
========================================================================================================================================================9 L! Q4 M( I, G- d( Y l
2137594 ADW DBADMIN EDM is not allowing to modify step model3 @: ]6 \0 l- E' |( M9 q/ ]
2115805 ADW DBEDITOR 'BOTH' in ALT_SYMBOLS prevents correct generation of part_table.ptf
0 f5 S) m: C6 _! R3 }2135452 ADW DBEDITOR DBEditor poor performance in high latency networks8 M% {$ F, d `( [$ w
2142315 ADW LIBDISTRIBUTI EDM Library Server stops often and adwserver.out file is extremely large, more than 1GB
! ]* t/ ]' a8 ?2 E; b4 I2155396 ALLEGRO_EDITOR DATABASE Netlist error when importing from Capture CIS
* e! I U3 o; t. e$ X {0 w) c% H8 i2118231 ALLEGRO_EDITOR DRC_CONSTR Crash during DRC: DBDoctor exits with error 'Illegal database pointer encountered'4 _, V* E" m0 l+ L4 a. a+ M9 n! i
2150923 ALLEGRO_EDITOR DRC_CONSTR Via at SMD fit DRC not detected with rounded rectangle pads3 l. U7 R/ G- l* U8 w
2140441 ALLEGRO_EDITOR EDIT_ETCH Drill hole to line DRC while sliding but 'Allow DRC' is not selected in the Options tab
4 P+ H$ z- w+ W7 n8 L7 h+ I2141329 ALLEGRO_EDITOR INTERFACE_DES Error message (SPMHSY-49) displayed on running 'Tools' - 'Database Check'
2 H; m9 }* V# ^! J; h: _2126562 ALLEGRO_EDITOR MODULES Create Module File / Place replicate assigns incorrect netname: F0 B) N& }0 v7 j$ a2 [& l+ o9 Z
2150410 ALLEGRO_EDITOR SCHEM_FTB netrev.lst is created in the wrong folder( R0 s2 E0 Q' m) H4 g! y0 s8 P
2136158 ALLEGRO_EDITOR STEP Update STEP Mapping Data Only should be seperate Menu/Command.8 O1 c4 E4 |& S9 i N) a! f
2137801 APD VIA_STRUCTURE High speed via structure instance not adding properly
6 e8 F& Y8 d6 U4 E/ f2145072 CONCEPT_HDL CORE Error on choosing 'Enable Hierarchical Variant'
) B0 ^6 g+ H% @) y5 y& a- m2124843 PCB_LIBRARIAN CORE Prompt displayed for license choice marked to be used as default
8 L7 n% ?* M0 `* U$ J2141656 PCB_LIBRARIAN CORE Part Developer pop-up option 'Edit' for symbols displays an error message$ y% F1 n# [" e/ g, x) v$ h
2125794 PCB_LIBRARIAN SYMBOL_EDITOR Part Developer new Symbol Editor: cannot move inverted pins that contain circle and dot# p: u! _; k) E$ a
2161864 PULSE R2PLM Second publish with CPM-derived item number and cadName set to $NUMBER causes 'an item is not unique' error
% X9 k6 B* f* r2 H/ q1997911 SIP_LAYOUT ORBITIO_IF Support keepout translation between OrbitIO and Allegro layout/physical editors
V& _4 j9 W1 m, ?' E l; j& {
6 D H, I0 n2 s% E6 p1 ]4 S" z
Fixed CCRs: SPB 17.2 HF0590 G) E% s$ k3 K4 A( M
09-13-2019$ F% m6 ]8 a7 ?* |
========================================================================================================================================================% P6 q( \7 H; f6 r1 L" @
CCRID Product ProductLevel2 Title
6 F" N: p1 q! V========================================================================================================================================================
# h- a) X" i- B2112454 ADW DBEDITOR Icons in DBEditor do not start applications after renaming a model
: ]( ]* u3 {5 k# Q% A: _8 P2120548 ADW LIBIMPORT Missing alternate footprints from vault area after library import.
8 a2 b6 E+ X) p2143314 ADW PART_BROWSER Component Browser does not start after installing HotFix 057 of release 17.2-2016/ F! T' `8 S+ V
2122302 ALLEGRO_EDITOR ARTWORK Coverlay details not being output to Artwork data as per the visibility9 T$ ]$ t G- z9 e% `4 e
2135521 ALLEGRO_EDITOR ARTWORK Artwork dimensions do not match Allegro PCB Editor
& N. R, ~# ~- V, ]6 d3 u2054584 ALLEGRO_EDITOR DATABASE Through hole mechanical pin in zone area without Soldermask Top still shows a pad on Soldermask Top
) d, ?) c1 a+ F% c! v, W4 J* G1 ]2111444 ALLEGRO_EDITOR DATABASE No soldermask for mechanical holes within zone$ c9 M; ^4 h/ l9 S, K) ^: Q
2115596 ALLEGRO_EDITOR DATABASE Unused Pad Suppression removes pin connected to shape using Net_short property
0 P2 ?, {0 F: m! _; W2135436 ALLEGRO_EDITOR EDIT_ETCH Allegro PCB Editor crashes when routing with VOID_SAME_NET property on cline0 K8 G; [6 t2 d8 o
1825020 ALLEGRO_EDITOR INTERACTIV GUI ( Quickplace ) not adjusted to current resolution3 y7 `$ e. M1 x3 g( B6 H. x
1949705 ALLEGRO_EDITOR INTERACTIV Quickplace GUI not adjusted to lower resolution! u) i, a0 X, Z+ S- u: W
2023090 ALLEGRO_EDITOR INTERACTIV Dialog boxes do not fit vertically on the screen
t& A' T: w3 x6 l; C' K2109940 ALLEGRO_EDITOR INTERACTIV Quickplace pop-up window does not fit vertically on the screen
# \; T" s6 @/ j3 p4 f2136823 ALLEGRO_EDITOR INTERACTIV Cannot resize or move dialog box to access buttons
. |; r- }; `6 a+ t2116748 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets
. z) G- P- E9 `$ [6 r2138977 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to HotFix 057
) ]' m3 [- v2 f& p2132628 ALLEGRO_EDITOR NC Improve the User Preference description for BACKDRILL_OVERSIZE_OPTION
" F5 |9 k- U4 u6 B. n: N* F2152244 ALLEGRO_EDITOR SCHEM_FTB Netrev.lst is written in the package folder9 n1 s k, x" m! H- R8 X7 _ _
2152493 ALLEGRO_EDITOR SCHEM_FTB netrev.lst is not created in the correct folder - error displayed for neltist import
' [% b- Z. w0 Z2104559 ALLEGRO_EDITOR SHAPE PCB Editor crashes while performing shape operation 'andnot'
7 C9 k1 v# x3 j" d! l( [/ u2108207 ALLEGRO_EDITOR SHAPE No Void Overlap option is not working in AMB) m2 f# P3 @' C7 A# F) a9 c
2125571 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes for a RAVEL rule! h+ |( c0 Y, J4 H" n5 W! t% C
2140707 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes on creating dynamic shape
" { U/ t; N5 O' Y7 C2078434 ALLEGRO_PROD_TOOLB CORE Shield Router - cline end caps treated differently than cline-segment end caps
5 E" c6 _9 s" I1 c- L2101020 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC with multiple net classes: script selects only the last two classes in a group
! ?" j% W4 ?8 X! v) k- X2029279 CAPTURE SCHEMATICS Slow response when selecting parts in schematic
6 g- x& M! h; C2039931 CAPTURE SCHEMATICS Slowness in OrCAD Capture when ITC is enabled
% }6 h- C+ `. l A2106942 CAPTURE SCHEMATICS Inter-tool communication needs to be disabled to resolve the lag issues in Capture
3 q, L; A& `/ c+ v7 c2 q) h2131683 RF_PCB ROUTING PCB Editor stops responding on using RF - Add Connect2 ?' W; w6 m) e# ^* q8 _) x
2126505 SCM OTHER Thevenin Termination dialog displays resistors incorrectly" D1 e* x$ C4 v( U4 S" E% r
2102383 SIP_LAYOUT WLP Advanced WLP Non-standard fillets not working properly: fillets not added
5 ~8 K8 f( F+ \1 e+ Y+ G9 F% v: o" z- ?3 e% s
0 c+ o4 R7 `3 \, d o! H6 }, U: r
Fixed CCRs: SPB 17.2 HF058& Z; L- G) I3 W8 N- |
08-16-20199 `: v; a3 j1 L$ }
========================================================================================================================================================
. E. e3 A# p2 U9 r" g+ o* cCCRID Product ProductLevel2 Title0 P- R5 j! I" b; S( M* _ ]' J
======================================================================================================================================================== P8 }9 Z& O4 @ z% G1 N$ g( m
2113265 ADW LIBDISTRIBUTI Various DB operations take too long, rebooting server seems to fix the problem1 Y% s8 h7 q ]# I) z0 m7 u
2122941 ADW LIBDISTRIBUTI Lib_dist execution taking too long to run, Capture CIS DBC File appears to be taking the most of the time8 u8 V, O0 Z) E9 J( q2 }( ~2 v
2127319 ADW LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250)
; M1 c4 i: \6 V( ]5 O( v2107578 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Canvas shows split layer
) T' ^2 ]* {; I4 Z2099538 ALLEGRO_EDITOR EDIT_ETCH 'Glossing - Via Eliminate' shifts traces to another layer, u* }4 ?- w: s' T
2031883 ALLEGRO_EDITOR INTERACTIV Sub-Drawing: clipboard origin point is not set correctly
4 p) Y; ?7 K; L w2100433 ALLEGRO_EDITOR INTERACTIV Pad Edit displays error for extents (SPMHA1-69) if pads are at 90 or 270 degrees# O, I% ]$ g& k0 _
2127239 ALLEGRO_EDITOR INTERACTIV Exporting a query result changes the working directory: U1 _4 I: ~6 L! z( V, y0 c
2117160 ALLEGRO_EDITOR MCAD_COLLAB Error encountered when importing IDX file into MCAD tool in HotFix 056* i1 o8 w. I0 P: B0 ]( v% o5 J
2117427 ALLEGRO_EDITOR MCAD_COLLAB IDX files exported from HotFix 056 cannot be read in MCAD tool (the same files from HotFix 055 can be read)
! b2 z% \* l' E1 s& {2117839 ALLEGRO_EDITOR MCAD_COLLAB IDX file created from release 17.2-2016 with Hotfix 056 is not readable in MCAD tools/ z r5 D1 O) Z" X5 S2 ^
2118019 ALLEGRO_EDITOR MCAD_COLLAB Export IDX is not working in Hotfix 056 but working in HotFix 055* ]! j- K/ l, N! a" e7 ?
2106425 ALLEGRO_EDITOR NC Disable undersize regular pad and oversize soldermask pad for start layers
& H; S7 c4 z; D; u$ S2126766 ALLEGRO_EDITOR REPORTS Cannot generate reports and export ODB on board1 s$ B6 `& R' R( f$ M
2107849 ALLEGRO_EDITOR SHAPE PCB Editor stops responding on updating shapes `4 p1 R) p9 I. H) L; {4 t
1778109 ALLEGRO_EDITOR UI_GENERAL Constraint Manager exits on doing 'Undo' in PCB Editor
9 v9 b% f9 E& @. ~4 W2064092 ALLEGRO_EDITOR UI_GENERAL Allegro Constraint Manager closes on clicking Undo in the layout editor
" h/ |1 e$ w3 u" n* f( R0 p2093341 ALLEGRO_EDITOR UI_GENERAL Show Element incorrectly displays in report window on a single line if an HTML Report is open when show element runs) t/ o4 b: \+ j; Q3 f" Z
2110909 CONSTRAINT_MGR UI_FORMS Cannot type dot (.) in DFA Table of Package to Package Spacing in DFA of Constraint Manager.0 y- [" @. a$ b8 r+ c4 u
2096846 INSTALLATION ADW Component Browser does not open if adwservice.exe is not added to the Windows firewall exception list
3 W; U5 }% p- ]) |% J" \2 G* p2128118 INSTALLATION ADW Unable to connect to Component Browser.
( o* q0 g: i( q- l) k# y9 Q2116749 PCB_LIBRARIAN OTHER Cannot open Part Developer with a Venture PCB license (PA3810)
; U! M) T4 e+ m2115302 SIP_LAYOUT IMPORT_DATA Performance issues with die text in and pin use codes, function utcle pwrgnd7 x7 r, k7 C5 [; ~
2103784 SIP_LAYOUT MULTI_USER Symphony Server rejects the move void commands on a specific shape instance5 I/ }; k2 C" H/ t! \
2096239 SIP_LAYOUT STREAM_IF Database fails to create stream out file$ K% C' v4 B7 m1 R- O
2117572 SYSTEM_CAPTURE EXPORT_PCB System Capture crashes with multiple Export to PCB Layout
9 X; f8 ~+ K" m. ]. }# \7 X
T/ Q }; k, O& f4 q
) E9 B; K+ |6 \8 F% r4 q& h+ p4 ^3 d$ tFixed CCRs: SPB 17.2 HF057
: |9 T: g' k0 o9 t) J8 |07-19-2019/ ?' _6 u u t( J9 d$ m. U
========================================================================================================================================================) p9 w$ L k6 m: |1 d* o
CCRID Product ProductLevel2 Title
7 `$ n; k2 c# |3 F) V$ S$ \" T========================================================================================================================================================( E- L/ g% ?9 o7 I. r( T
1920958 ADW ADWSERVER Designer server will not start due to corrupt inr file
- h% r& a& w. D" Q5 b+ h! k2039243 ADW LIBIMPORT libimport ignores footprints generated by Library Creator due to changes of attribute names* R/ v# e) N( n* D, J* E
2113226 ADW PART_MANAGER System Capture stops responding while importing DE-HDL sheets
# L' n6 H* m& B4 m o3 S2035942 ALLEGRO_EDITOR ARTWORK 'Create Artwork' is slow when all films are selected/ a* u0 `* b9 I2 q0 ]
2096958 ALLEGRO_EDITOR DFA Cannot launch Constraint Manager after assigning CSet and closing+ R8 q8 O: Q% T7 @3 d* C
2087181 ALLEGRO_EDITOR DFM DFM reporting false positive hole to hole with stacked microvias
( L+ V' k( w1 _, z2099400 ALLEGRO_EDITOR DFM Placing a mechanical pin on a cutout causes PCB Editor to crash
4 G7 L7 `9 P$ D2 |4 X4 ^2067214 ALLEGRO_EDITOR DRC_CONSTR Constraint Manager crashes for design linked board
! {+ l& a: A# |7 ^* q2097464 ALLEGRO_EDITOR MULTI_USER Design data lost if network connection drops in Symphony( s7 |& R9 Z# [- ?3 ^$ o
2108211 ALLEGRO_EDITOR MULTI_USER Error: Update #1 (Perm shape) was rejected by server# v) O9 S: d6 N w1 v
2117154 ALLEGRO_EDITOR MULTI_USER Error message needed for Symphony for client disconnections
1 k1 a. p" ^+ q) X2100149 ALLEGRO_EDITOR REPORTS Error message (SPMHDX-9) for too many field names while generating dangling via report
1 \, j: \$ W% B5 k3 A2101932 ALLEGRO_EDITOR REPORTS PCB Editor internal error (SPMHDX-9) for too many field names when running BOM report
6 w( V: c" S+ p; q2111449 ALLEGRO_EDITOR SYMBOL 'Layout - Renumber' results in error! ~1 g/ Y: B. z; _. A
2102177 ALLEGRO_EDITOR UI_GENERAL axlDMBrowsePath returns incomplete information" r2 G; k4 x* t8 Z8 i$ Z* L
2105342 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding for 'Show Element - Find - Symbol Type' on a particular board3 p% c6 j% P% u9 o3 }
2085443 APD ARTWORK Gerber lacks precision required to void some vias for a design in artwork output: need warning5 }) l. J5 C# Z$ k m% a
2080118 CONCEPT_HDL CORE Getting error after adding offpage to bus and assigning a new value to $sig_name
* ?; Y/ l4 t# h3 M% x* M3 F/ z2099438 CONCEPT_HDL CORE Genview allows dragging group of signals in split symbol distribution form
; ~8 S( K- d' N1 Z8 }2108289 CONCEPT_HDL CORE Variant data is not in sync with the packaged data
5 q, \8 Y* y4 A0 l9 T2087217 CONCEPT_HDL OTHER Variant back annotation will not work if there is a double quote (") in the description field of a part
: ~! T2 w$ w$ g0 V# \, f( C( {" T; Q& i2107430 CONCEPT_HDL PAGE_MGMT Insert page is not working8 Y- a3 n' N3 M6 f( [3 E: J( u- [
2063875 CONSTRAINT_MGR OTHER PCB Editor crashes on deleting match group without closing Constraint Manager
8 G1 ] A" M: g, r# ~2103729 F2B DESIGNVARI Cannot enable hierarchical variants for block
' U, t$ {- v) J2099076 F2B PACKAGERXL Package fails for 'Save Hierarchy', but succeeds for 'Save'
8 W% r2 [( I2 X# k& y2 k8 @/ Q2081132 INSTALLATION SPB Part Information Manager cannot connect to EDM server after upgrading to HotFix 053
: H0 H' u+ a" d/ ?& h1599964 PSPICE ENVIRONMENT Version Info displays 'OrCAD Version Viewer MFC Application has stopped working'
- J% c/ |4 X+ C. ]. s Z9 c2045497 PSPICE SIMULATOR 'Illegal Parameter Value in File' error when loading Monte Carlo parameter file' h* C' D1 x6 B# J2 L
2025997 SCM TABLE Copy-Paste Broken in Physical View9 v/ d2 N+ w+ [2 t) G6 v M
2102652 SCM TABLE Unable to copy the Associated Components Ref Des values to Excel+ D) \) ?" U/ w3 }* H. X5 }9 A& |
2054225 SIG_INTEGRITY SIGNOISE Cross Section Editor bug after changing the impedance value in Analyze - Preferences0 _. ^$ V M: r
2100075 SIP_LAYOUT DIE_ABSTRACT_ Refresh co-design die running slow5 k5 W8 J. Z) n, n0 c e
2106312 SIP_LAYOUT DIE_ABSTRACT_ Die abstract I/F to bring into SiP Layout and OrbitIO power/ground and signals not designated as RDL1 C8 G: O# q) _) a* l" \' @
2106314 SIP_LAYOUT INTERACTIVE Large design causing severe lag in Windows Server machine8 N+ n5 [; |( n' T% b
2101622 SIP_LAYOUT MULTI_USER Symphony Server rejects the slide commands when tapered trace option is on
2 ~$ {+ Q( J1 J6 a5 ]- I3 T2107897 SIP_LAYOUT WIREBOND Design stops responding when running Wire Bond Auto Spread in HotFix 0556 x: ~: N4 M. u/ z+ A
2104885 SIP_LAYOUT WLP Advanced WLP: Metal Density Scan, scan area in report is incorrect
. r. B1 G3 i; b2 F8 w! k% p+ J% ^& A
: _( s) L& n9 n% @% S. Y' Y' T# ~+ g
8 ]: e6 W& w% ]$ FFixed CCRs: SPB 17.2 HF056
/ a7 S. W! y) @) Q5 @06-21-2019
$ K. h! K; C2 [+ p& B7 i" _======================================================================================================================================================== p% M) c' \* B- h8 r/ \% U* q
CCRID Product ProductLevel2 Title
$ u; y- m4 b" n! l1 k========================================================================================================================================================
n# x' z9 q) F8 q: _& \2086463 ADW PART_MANAGER System Capture cannot add components when accessing remote machine via Citrix( C1 d1 E) o2 {2 }6 ?' i. r
2092868 ADW PART_MANAGER Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not to flow from pstchip" k4 o v8 @4 O; j6 m' s( u
2092872 ADW PART_MANAGER Import DE-HDL Sheets stops responding
6 `8 ^. Y2 _5 D2088975 ALLEGRO_EDITOR 3D_CANVAS Bending in 3D Canvas causes PCB Editor to crash
( K# H. X* g5 p) i2088577 ALLEGRO_EDITOR COLOR Export color nets does not write all the nets in param file
; |+ r% U$ l8 Z. ]2028867 ALLEGRO_EDITOR DFM False DFF Trace to Thru via pad spacing DRC
- y, V# s& e4 K' Z" X2037361 ALLEGRO_EDITOR DFM Soldermask features drawn with a line do not DRC to pin, via, or shape soldermask features
# A7 ]7 y3 D: s) Q/ R4 ?2077913 ALLEGRO_EDITOR DRC_CONSTR When running a simple SKILL command, the tool will run for a very long time+ A( {6 w5 ~( W: {
2079642 ALLEGRO_EDITOR DXF Drill symbols are rotated in exported DXF in release 17.2-2016
& E2 |/ B3 q; ?2083493 ALLEGRO_EDITOR MANUFACT Manufacture - Cross section chart is not readable for rigid-flex designs
) ]+ v& J; w8 T" Q& z* ]: q2073607 ALLEGRO_EDITOR MCAD_COLLAB IDX_IN batch program to allow a batch update of an .idx file
3 M: z' V+ v6 Q2095632 ALLEGRO_EDITOR MULTI_USER Design server on Symphony stops responding and cannot be closed or downloaded- d9 B1 s t8 h
2098221 ALLEGRO_EDITOR MULTI_USER Symphony Server Manager allows connection to databases deleted from the project area
: f$ U/ V3 D, t3 J/ e2087315 ALLEGRO_EDITOR NC Backdrill exclusions raised on pins of a component8 x+ o) N& B/ D% |
1947929 ALLEGRO_EDITOR OTHER The 'show measure' function crashes when measuring pin to pin distance" c6 d6 p1 `' N7 l5 t
2091932 ALLEGRO_EDITOR OTHER Unsupported Prototypes command missing for the OrCAD licenses7 B) A! q5 `$ ?0 g! \7 }7 M
2089470 ALLEGRO_EDITOR REPORTS Summary report shows the exclamation character (!) in the middle of numbers and words- h: O! u, d$ l% S- v
2067324 ALLEGRO_EDITOR SHAPE Netin crash during third-party Netlist import
q0 ] {! f. o/ F6 h5 ]2075191 ALLEGRO_EDITOR SHAPE Delete islands in the design: update out of date shapes and Database Check/ |- e6 }# n+ F z4 Z ^: J4 ^
2090604 ALLEGRO_EDITOR UI_FORMS Undo/Redo UI grayed out when invoking Color192
" W$ S" p2 g9 T: |2043825 ALLEGRO_EDITOR UI_GENERAL Custom toolbar settings are not retained upon restart of Allegro PCB Designer
% Q/ D @, r0 h4 F s2090185 ALLEGRO_EDITOR UI_GENERAL UI setting in INI file not retained
. D+ [. S7 w& Z0 t" ?2090517 ALLEGRO_EDITOR UI_GENERAL Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane
$ O' z+ @5 W0 R }/ D5 w; \3 G" C2092436 ALLEGRO_EDITOR UI_GENERAL RefDes length of input string for Modify Design Padstack is limited to 20 characters
" C6 t( c$ u7 E- c$ Q% Y2099070 ALLEGRO_EDITOR UI_GENERAL UI setting not working properly, Icons missing after restart.+ x- T# n- e. L3 T1 o
2088484 APD DATABASE Some objects (Vias and Cline) cannot be modified (edit, delete and slide) in the mcm database
* z% k/ U; y0 f1951623 APD DEGASSING Shape Degassing fails with specific Void to Shape boundary value
8 N) |+ z$ w2 K+ j* t2081363 APD DEGASSING Cannot degas for specific shape% }4 p! z+ a9 d( C6 b( C
2083498 APD WIREBOND Cannot wire bond from a diepad to another diepad on the same component- ]+ Y- J5 D9 {1 C& Q
2086589 CAPTURE NETLIST_ALLEG The generate the CM enabled files from the command line using pstswp.exe.
8 w9 ]0 |7 d3 T3 p' C2098248 CAPTURE NEW_SYM_EDITO Ignore pin is not working for individual pins in Edit pin spreadsheet when edited for all pins
- D# P2 ?3 D! K7 T2 G, J9 i5 S1773047 CIS PART_MANAGER Pin numbers and names for DNI parts will get disappeared in variant view mode if they are relocated in part editor$ L# x# J j% J, r
2003818 CIS PART_MANAGER Pin name and number of 'do not stuff' parts are not visible in the View variant mode
+ a, p; `1 R6 g. o: @2076265 CIS PART_MANAGER Variant view pinnr/pinname disappears( z% M; E- O2 v2 e2 n& v/ a( F
2076282 CIS PART_MANAGER View variant does not show pinnr and pinname
; x" j) `& l6 A* O2 @2083394 CIS PART_MANAGER No pin names and numbers on variant view for specific parts# p. Q+ ~2 _$ `" ~8 d5 S
2090027 CONCEPT_HDL CORE Cut and move of split hierarchical symbol to another page results in error due to lock or write permission issues& D; L7 k( s6 x5 n# R
2071355 ORBITIO ALLEGRO_SIP_I Dummy nets creation in die after performing Merge Updated SiP
0 V Q# v! R, `0 H2 s9 E% c& D6 f' G2067703 PCB_LIBRARIAN OTHER PDV crashes immediately for vector pins if MSB is lower than LSB
; k2 \ C6 W; C$ V: P# _0 v2041348 PCB_LIBRARIAN SYMBOL_EDITOR Grid setting change cannot be saved in new Symbol Editor" v7 V% X6 Y$ L) {; P9 l: x
2041365 PCB_LIBRARIAN SYMBOL_EDITOR Improve copy drawing objects in new Symbol Editor
* u6 U$ K$ j+ p" R+ z/ m0 y2067931 PCB_LIBRARIAN SYMBOL_EDITOR New symbol editor grid issue: documentation grid spacing value changes
0 H1 s1 ?0 D' G" }2093849 PCB_LIBRARIAN SYMBOL_EDITOR Symbol font text and appearance different when placed in Schematics
* V, M+ B. A. z; V1 p0 S. t' B' H1 E1919298 PSPICE FRONTENDPLUGI Capture crashes on archiving project- T8 c/ J9 S/ S% b
1953001 PSPICE FRONTENDPLUGI Archive project causes Capture crash.
) ^: _; r$ ?% r# M4 S2 R2035572 PSPICE FRONTENDPLUGI Crash on archiving project9 y" F6 u$ C9 K$ E9 X/ e1 V
2041286 PSPICE FRONTENDPLUGI Archive project crashes when using lib as global.+ a- b9 Z- r d8 B7 t$ a5 M) Y( }
2081796 PSPICE FRONTENDPLUGI 'Archive Project' crashes Capture in release 17.2-2016, HotFix 053
+ B4 K7 m& ~" r2106017 PSPICE FRONTENDPLUGI Capture crashes when archiving PSpice-enabled project A- [) ~# f6 N! d J E
2051450 PSPICE PWL PWL Sources application: pop-ups and messages when browsing and placing source: Z4 A1 |" e* C5 n: I
2090021 PSPICE PWL Modeling Application - Sources - PWL Sources Dialog is not properly displayed
& D4 j9 ~7 [. {5 u- H2 i2 S3 d2094548 PSPICE SIMULATOR Model undefined error on TL494/ c$ X0 ~1 X; e* K# j& P
2058018 SCM PACKAGER Reference designator mismatch in 'exportsch' schematics and board file
! ]5 q3 n2 W1 ]0 r1955868 SIP_LAYOUT STREAM_IF APD/SiP Layout: Export rounded features as circumscribed and not inscribed polygon in GDS/ G: A% h6 W" V* K, G
2081914 SIP_LAYOUT STREAM_IF Release 17.2-2016: GDSII stream out drops shapes: {4 O: L f+ _; @7 `
2013647 SYSTEM_CAPTURE CANVAS_EDIT Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections+ w% |! i/ I+ m: `. e$ {1 w
# I# z6 b# |) d: Y' s) K
+ ]9 S4 B+ a; k9 Z4 O
Fixed CCRs: SPB 17.2 HF0555 _ W& w- |% Z$ P- ]5 L/ V
05-24-2019+ x0 o( C, n. d: k
========================================================================================================================================================
. B# i `1 ?: C" T& Z; o; d* NCCRID Product ProductLevel2 Title
0 a) {2 i. S- D" V========================================================================================================================================================: j4 p7 M; k: v X
2078057 ADW PART_BROWSER Symbol Graphics preview is not available in the Designer Server5 j+ k0 R3 ^$ X6 g2 ~
2092863 ADW PART_BROWSER Component Browser is not displaying the symbol & footprint preview
7 f3 p5 E# z( W1 \2076339 ALLEGRO_EDITOR 3D_CANVAS Floating parts on bending a board in 3D Canvas with HotFix 053
( I! l: J6 S; @3 f( j2051075 ALLEGRO_EDITOR ARTWORK Incorrect Gerber import in Allegro PCB Editor
7 A0 P0 _; Z0 u2073407 ALLEGRO_EDITOR DATABASE axlDeleteByLayer deletes fixed shapes% i6 v m. u1 |; R2 g
2079117 ALLEGRO_EDITOR DATABASE Release 17.2-2016: Board file saved in HotFix 049 cannot be opened in HotFix 0143 Q) V: u3 D y
2079204 ALLEGRO_EDITOR DFM Enabling option to update analysis mode and run DesignTrue DFM wizard causes PCB Editor to exit
) B' U: w. E9 n9 g1 a$ ~2082394 ALLEGRO_EDITOR DRAFTING Angular dimension not owned by the same parent symbol in the layout are not deleted on moving object& u, G3 W" X) U" J
2067916 ALLEGRO_EDITOR INTERACTIV Place replicate module bounding box does not move with circuit after module is updated
7 |! h$ J+ Y% B0 ?2068449 ALLEGRO_EDITOR MANUFACT Stackup chart and table shift slightly from original location on re-generation in Allegro PCB Editor release 17.2-2016: e1 s+ a+ C; q. {; {/ A+ D
2065820 ALLEGRO_EDITOR MCAD_COLLAB Selected objects deleted from the design on clicking Cancel in IDX Flow Manager Import$ Q. N2 K+ P" i
2080164 ALLEGRO_EDITOR MCAD_COLLAB IDX outputs two sets of masks1 @: `1 {3 r& |$ R8 c, L
2081955 ALLEGRO_EDITOR NC Artwork file error for via size
/ N: F! M& S9 ?& n5 L8 h2045061 ALLEGRO_EDITOR PLACEMENT Setting PSMPATH: axlSetVariableFile() does not update Place Manual but User Preference Editor does8 g/ j' S" o- I# r% E
2049949 ALLEGRO_EDITOR PLACEMENT Get import errors and cannot place some parts if user-defined option is turned on for netlist import
9 ?: u5 q: ?6 t# z2069289 ALLEGRO_EDITOR PLACEMENT Cannot place part because attribute definitions are incompatible for the 'DESCRIPTION' attribute (SPMHDB-154)# g2 Q/ w9 F. [' L9 J( q$ ^, _
2056573 ALLEGRO_EDITOR SCHEM_FTB Import Logic takes a long time when checks are turned on
8 k4 N) {; R: D) L( d. g2076452 ALLEGRO_EDITOR SHAPE Shape Degassing crashes if 'Inside Shape' is selected+ D' C2 Y% N% E3 `
2076873 ALLEGRO_EDITOR SHAPE Symbol Editor stops responding on editing shape with a .dra file
7 z) Y! m. B( v! H# S) ^$ F; Z* x1788703 ALLEGRO_EDITOR SKILL axlPadSuppressSet does not work when 'none' switch is used4 F$ O2 q9 a1 @2 d
1955127 ALLEGRO_EDITOR SKILL axlPadSuppressSet( 'off 'none ) returns a warning message and does not work per the documentation
" k( k2 M& K$ v B( ^2 H, z1 K2031711 ALLEGRO_EDITOR SKILL Syntax error related to allegro.ini shown if allegro.ilinit loads INI on startup) H @5 U d* t: ^5 r
2062527 ALLEGRO_EDITOR SRM RF elements are shown in Symbol Revision Manager
% A. k, Z: a ~2074249 ALLEGRO_EDITOR TESTPREP Testprep re-sequence causes PCB Editor to crash if 'Labels with Net Name' is selected( X& t+ f) I- h0 [9 E" j6 A
2070534 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox bar code generator is creating corrupted shapes in the database
- L: p. t6 F4 k$ Q2046278 ALTM_TRANSLATOR CAPTURE Third-party import fails/ E8 ~: ?) }7 T; i
2052399 ALTM_TRANSLATOR CAPTURE Third-party CAD translation stopped with error message6 o1 l: W9 m! I( B5 y
2005087 ALTM_TRANSLATOR DE_HDL Cannot translate third-party to Allegro Design Entry HDL6 O& l& f" ^7 n1 \8 I' B! e6 Y5 a* i
1922222 ALTM_TRANSLATOR PCB_EDITOR Third-party translation converts to board with unconnected nets! s( f1 [( {/ y2 _& W( W5 i+ X
1987263 ALTM_TRANSLATOR PCB_EDITOR Third-party board file: copper not imported* e8 I. i9 |) j- q( c7 `% R, _" A
2017988 ALTM_TRANSLATOR PCB_EDITOR Third-party to Allegro PCB Editor import issues with routes, constraints, size, and accuracy4 [2 n r+ l; ?, O: e/ q8 {4 `
2021300 ALTM_TRANSLATOR PCB_EDITOR Third-party translator does not show any results on PCB Editor canvas
+ K% k, j% J) G r3 {1890675 APD DIE_EDITOR Mirror Geometry is Mirroring the symbol from TOP to BOTTOM Layer in SIP file; R2 z2 J/ V s
2064219 APD DIE_EDITOR Applying mirror geometry results in mirroring: moved from TOP to BOTTOM layer
& d0 V1 n: O& d+ R& }# l2086574 APD OTHER Duplicate layer text shown on the vias
4 g" |1 O4 i; S7 S/ j: s1948169 CIS CONFIGURATION Auto Symbol Refresh Checking not working for shared folders
$ i& Z$ ? w8 ~8 S6 Z& R2025385 CONCEPT_HDL CORE Hierarchy Viewer expands/collapses randomly after clicking the '+' or '-' symbols+ u+ D$ b& U) n" E; D' t( Y, z
2050010 CONCEPT_HDL CORE Copyproject does not properly copy the variant files; l ?, l9 ^- g$ A& K! B+ o4 F
2063457 CONCEPT_HDL CORE DE-HDL: very slow rendering on some systems# x' N1 _7 ^% g9 ?5 {( w
2076312 CONCEPT_HDL CORE Getting 'Variant out of sync' warning when creating BOM for a design with no variants( O& I, L$ C4 Z! r9 {/ T
2083650 CONCEPT_HDL CORE Lower-level signals are appended with _1, _2, and so on8 @ {# L3 D7 F( e0 V1 [8 J- d
2083651 CONCEPT_HDL CORE The physical net names still do not sync with the assigned signal name8 ^" _, J: U- ~2 ?! s! M
2056736 CONCEPT_HDL GLOBALCHANGE Global Property Delete does not operate on the entire design unless the top-level page 1 is open
. }7 j [9 }! M& l+ D8 D! h1955357 SIG_EXPLORER OTHER Signal explorer invocation with OrCAD PCB Expert Suite license6 ~- K7 V" L1 ?5 ]( ^8 \3 V- c
2079071 SIP_LAYOUT SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die
0 S8 M( u( B5 v( M' N2081884 SYSTEM_CAPTURE CANVAS_EDIT Symbols take a long time to move, and results in DRCs and broken connections
: r; G* o9 ~% K" s1942542 SYSTEM_CAPTURE IMPORT_PCB System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks( |0 l- G* e3 v( W5 a
2071303 SYSTEM_CAPTURE MISCELLANEOUS cds.lib file is picked up from wrong location
( O$ H, y7 h3 t' X2058979 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture prevents a project from opening by putting a single quote at the end of a line in CPM file' h1 o: h: I( q- b+ H
2088210 SYSTEM_CAPTURE OPEN_CLOSE_PR The 'enable pspice' entry in CPM file is occasionally corrupted
( l/ e3 d3 u1 V- z# V- \- \6 w' ~; A+ u* {, Q6 S F
$ G* m3 N! c! B1 b# g+ YFixed CCRs: SPB 17.2 HF054( c1 u1 }) Z0 h: J0 x
04-26-20193 [. c8 q1 g- s( s4 w. T* V! ^3 g5 X
========================================================================================================================================================( Y- I8 X5 |# C) ~
CCRID Product ProductLevel2 Title# U# F, e4 N9 n1 [2 D% A9 T
========================================================================================================================================================' D+ p/ e5 b9 b2 d+ R
2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes9 c# f' m$ \* N) ?, Y( J
2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property
+ m9 g# I; d6 r) P* J) f7 x2 N' x1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser: {: q4 ~' H; Y* q& W: R0 u: E
2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache. q4 O1 ~8 {' \, W) R
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name, x$ V3 q0 M; c3 q& D/ g t: P1 A
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
; z( k; ^; E+ |- m2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object+ Z; k/ B, n2 j3 n7 T; E. D
2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas9 ?: C& |2 {5 Z. r
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation N" U6 l* Z5 ]. D& @* |
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
$ P7 v( B+ z g: P3 e* ?2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off
2 D; c- n! w; p. D, l: k: ]: A2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set8 s7 F9 @( B2 H) P: n" R* B* f
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
{. s: H! F0 u% V C* f( s: H; J2 I2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements$ o! d) O# r) C
2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin
: a0 e2 p* m* ^0 P# Q" [2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element
' N" M1 c/ p" {* u2 o1 I) ?0 e2056497 ALLEGRO_EDITOR DATABASE Place manual is slow, B3 r; Y* T5 e# ?$ H+ _) ]
2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error
, k: b$ a2 L& B1 K& x; C, D2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code
7 e' b- I% r9 o5 O) ^2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016$ y! y7 ?9 v; F6 Q# m
2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
# z+ v* W5 v. g4 s y2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets
l$ [8 g+ s# n2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File." F. ~: t7 O: V* q
2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.
) D9 u" x1 ^6 G" [6 ?2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself' S7 a0 ]2 @) v* m; l4 D
2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations
0 M* V' C ?5 ? {/ J0 a2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
; w y2 o" T/ E9 n- l, _2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill
6 l% O# Y/ R% L: [2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets' q6 f5 C! M' Q- D7 u
2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor
" S0 Q/ w3 s! K) T4 W0 Q2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias# | Z I; s( C1 X) Y
2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor
( j- [, s$ M% L+ p- F9 e) B- r! m2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable3 c7 B/ c" e* z& U& g' u, q6 ?
2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components; V+ S, w( r5 ]3 ~
2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report
3 ]! j# ?. O, z4 r2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL* q4 W. q% J$ t8 f- {0 B; a
2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
' |* ~! g* m3 [! @; t2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
8 a' A; r0 Z. r2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'
3 P" {) Y' E _: }2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
: G# _7 G R5 v0 e/ M8 m2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present+ ~ K7 f9 R3 r5 I
2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes
$ D0 q* r$ `, o: m% r2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'; s2 s4 p i& Z
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.# {$ q- W! v7 l1 ?# W- x8 W- z( q
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
/ ], |/ c* [4 H i2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.
: ~' l3 o& C8 L% D1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)
( k3 e; V& [; q! J4 C# M1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
8 E, p( f5 w3 W6 f" R9 x2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048) }+ ]3 h& |; d# M* n
2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design) J+ ~, b: U+ }) Y5 m; q+ ?; {% v
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas
0 [4 x; y" a5 Z! u2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice2 C! M0 m3 S1 \
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html
0 f1 b! y( b' F. y$ n2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
! M. |2 [& N8 C. y/ I9 k2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.64 R. M- V; J5 |
2050674 APD PARTITION Cannot remove C-Point from a partitioned design4 S, F. K: }6 h
2068814 APD WIREBOND Bond wires cross on auto-separate8 O3 Z% K0 D. _2 F3 T( F
1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open
' S8 k3 D& d) _5 T0 G/ X% L* O1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering3 @9 {' P. h* N0 K
2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL* k3 L; k' h' R- z; z1 w/ V# ^
2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window6 ]& J( ]# x. i2 i5 W& `% @* q) d
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved Q b7 V% E/ K" H+ K( \- _
2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix
. o% ]8 y( l$ @, K& b2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager0 b0 m: f5 l, j) L9 J, o+ W4 r
2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps2 h8 k, n( Z+ ]6 Z [6 o0 d; m
2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM' |: n1 _# X9 m3 ~- q/ H
2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties n! R9 B" @1 J
2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.2 C3 f e2 d) p% i. S+ u; @# G- f
2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses7 r; R* \6 K7 d' X+ ^ a" a1 w
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
% C$ P9 g% R% x# e: D( R2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.. X: J* ?5 t/ M
2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma
8 g& M7 l2 Y- i& R' L; s0 Q0 m2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.
1 H7 K" K* f" s( M+ D2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character+ [! |+ z1 K9 _: A
2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped; |5 w- ]! O8 X9 M6 [
2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties
+ I! x$ a- ] R1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated
5 \! Q, L6 f l% N# G1 s6 R2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated' a" d2 V8 X# H7 c
2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated; {, ?) h" i1 s% L
2038021 PSPICE FRONTENDPLUGI Bias display is not updated5 `& D! z, u% H; R# Z9 g
2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open8 U: e! l" _+ v9 F/ F9 k
2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component
* j# J1 X; t" t7 j2 c3 J# Y; g2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks
$ U7 P. r& l& t% D2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.. S2 U# }$ w9 u& g
2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign, N* v, D5 [# k$ m$ H
2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed* i" e6 G7 x" r5 b' V8 C% e W
2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'; G% @ m0 y, x; b K% ?9 e
2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
) z' M' Y- y& l6 p% _0 _2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode. Q. I7 N' ]0 |: Q
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error# u3 G. G+ C' C& y% q6 A
2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
2 s Y" j/ {1 n1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.9 J8 @8 }3 G8 i% d9 C' ]
1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
+ V) H) ]8 D3 m4 g0 \$ r- _1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
+ p* L$ c6 b5 e9 X- `2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written m7 P( H& F, S, g4 E: H7 U. R
1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping
2 c2 [+ K! k& e+ }: ]7 {4 z T2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor
5 D" z, b) U( B* L$ r6 [! L6 V+ K8 [1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste: \: Y$ u5 J, o; }' _+ D/ e
1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position
. D+ J# R' a/ n7 N1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM
4 E9 n' c2 P! j& o1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range
* C0 e# B0 H% O6 k3 h( r2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.
( ]/ z4 J1 [9 M2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF
c3 H) }, ]: ?0 ?9 }. z1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
+ X6 e' O1 m w5 u5 K* e( Y6 A( k1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number$ `# w5 y \& P3 p
1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project+ s; x/ \- s i+ W8 y6 u7 H
+ E) \" l: q7 L2 c' k4 x
% x. `2 F/ \2 o3 P+ R( b% X4 d& UFixed CCRs: SPB 17.2 HF0534 P2 k3 _8 O: \0 j1 U
03-30-20198 p3 ]0 i3 C5 h2 I7 Q! x
========================================================================================================================================================. z9 Q2 o+ e3 l' M
CCRID Product ProductLevel2 Title
4 G+ z% M. I3 M9 S2 s# D9 {========================================================================================================================================================
! [3 |4 n" x P2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right
3 R/ v' T8 l% C3 Z2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag
4 r1 H+ c- @$ o' @5 K$ Q: `9 u2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
1 U2 |3 Q+ e% c6 k+ r4 g( T8 d% g2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
& m/ L& _+ P. g6 x4 p! h: ?2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error
; N9 |& A. x1 C; ?2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
+ j" s% c |7 c! y8 P; u) Y7 w2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer9 t9 }4 \- c3 F* q a' Y5 c
2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down
. x& k9 R, t- W& a* q2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
& `. A* M3 ^& |3 F# a" B! v2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation, _( b+ D3 t+ j9 S; [& [
2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned
( w, g! _, _+ m$ c) S2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded7 F2 l1 N- O9 P7 a+ U
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone G& |5 Y, W( d0 b0 a' ?
1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.; S# [, N0 m5 w4 A
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization. P! C- B4 W7 a: I# A1 ]; C: l
2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack' ]7 U/ ~0 C. R2 G$ ?
1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols, ?2 T* |6 A1 p e
1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines, {' D8 t, m/ {
1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.) Z; v+ o5 _7 n
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types0 U" u& B5 E' O1 l" P' H- L9 }
2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.
* G O7 Q! Z( e7 T6 Y. D% c2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command) j" W! t& P6 @ }) U( D+ C
2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation# M. M" ?2 Y; l/ w4 i
2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
: x6 T, |4 e; O1 y2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column. e! N" K) X& }" r3 v) @0 v
2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.
9 [' v) d/ ?2 S2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table- \7 e6 X9 A1 g5 _9 Q3 }
2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data1 @+ x, J4 Z% @+ l6 Z1 S
2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value
; O7 x( B) T9 p. u2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added
% R5 ]3 F5 v4 M |2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created8 w4 ?' n9 c7 i. b2 F% K
2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev8 `% T7 L1 B& |) N" @/ Q {
2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point0 O0 B# R0 s2 j# n8 I
2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding
0 u ?8 H( n4 L1 w2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
; d Y: q p, ?* o) X% ^2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.3 ?+ v$ F( t( Q
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present5 a g( ?0 ^7 a
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.
: ~ ?# s, R) K" v/ K$ \: O% _2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash6 }8 L. Q- }+ m& w) a" V8 R' a
1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint1 j5 r/ I0 w% _1 ~0 e$ N" @" x" n
2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
- O$ P; [6 _( u2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash6 A- W$ P2 I- j
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas7 Q3 U0 ~2 D& v( V9 K! B/ `4 x
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden$ N1 l5 O) b$ Q/ F% e
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash
3 c4 g( {+ p; a& P' A% K1699433 APD EDIT_ETCH Field solver runs when not expected; [' R$ j% ]# `
1937159 APD EDIT_ETCH Routing clines takes long time/ q/ O8 e; }1 U+ O
2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region
$ D" g$ \) D) \/ p2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051
. ^1 K& H& M, E- @( K; T2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture
/ Y" ]" J0 l1 N- ~; E j& D0 k2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
D3 V' d. J3 Z" o+ \3 q2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project
! @- ^+ p$ K( s4 q7 `2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification
. `1 T3 n$ X6 o. \2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM, r1 E3 G. q5 `3 B: S a
2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source( K4 o* W% z/ i7 q
2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol8 D! ?5 G- w9 }# r6 H9 M
2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks1 q, M6 H, O$ ?/ ?! l& O0 T" n
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
1 t$ q5 T2 L5 J6 }) I* \2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library
" R( z6 L3 s. A( C, z- h' [( u2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
% [/ g. ? g; `, ^4 d. }$ @1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
) w ~3 w4 h! K# Z. X, N3 M1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled
4 f0 z8 P9 I- E+ j% L1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components
$ S, y* t) P2 c. U7 {7 F1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names
( x- G; O( O5 G2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character7 Y. f7 h6 O9 W4 x, G3 o3 M
1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
) f5 [; G4 Y+ X( Q9 S1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
2 C$ `- R; p( _! l, d! l( o1 j2 o9 V1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped
6 a/ t: T+ G) v1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical
w9 i: t. U4 _- ]& |! G; I( d1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
: m" P5 J" G% M/ G1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas+ G2 L$ ?" L+ e( P9 d' H- W8 g2 }
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
# H* t" }& ^- ^1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast0 J# U8 x% A1 r& A
1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently* s- g- ?3 ?! |! N
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
5 B# n9 W8 K2 M. J1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI5 e6 l5 q+ X& \8 x+ k z
1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created+ s% |# i6 t9 ^, [, L
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
" I' a" S8 L, ]. }1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
' F! X1 Q2 m4 h% H9 x' A, P1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL
! x. P, Z0 [, p# x1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
; `" A+ W' J( C# D1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message" c! J! {) ~% F9 ]+ f" s+ G
1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor, D; W& P: o3 M& {6 k5 I. m
2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder6 L/ ^$ W: [; K) A) @2 g0 f
1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message" c( K( d( J5 [/ n
2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component H+ K: D/ ~- r8 @( M1 `
1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES
) e( H& S+ b3 `+ q* `5 ^( q1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option4 Y5 s) f9 G8 H/ a& n a- d$ U* g" n
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor! A4 s7 i$ a; n" I7 B% A
7 c7 ?3 e5 J6 o& j n; U, _! O0 _
$ l- Y4 \8 j- o3 bFixed CCRs: SPB 17.2 HF052" Q0 d; c9 Y. |" I. [. E B
03-01-2019
: n+ T/ I. D) o6 e1 u2 _8 S1 K========================================================================================================================================================5 N1 i( Z' e9 [2 O
CCRID Product ProductLevel2 Title h9 n8 V% K. \, y- k9 P
========================================================================================================================================================0 m& o' l9 G4 o* U$ X% \# l$ t+ d1 [
2020429 ADW ADWSERVER Incorrect adwservice status on Linux. {5 ~; h- n/ B" L; [
2034815 ADW LIBDISTRIBUTI Cannot mark classification obsolete because it is associated to objects in the database3 ]/ V0 l4 Z& R8 ^2 I4 r- m# {
2015461 ADW PART_BROWSER New Component Browser should read the mapping of symbol and associated package as it results in error PKG-10053 n( Z* Q: S% t5 q' `5 O
2049380 ADW PART_BROWSER System Capture Import HDL not importing complete PTF File data0 {+ }2 b. _% g! E$ a% ~2 o
1948608 ADW TDA CUSTOMVAR directive value in project CPM was not updated by TDA UPDATE command.
8 n& v0 _- I M8 O- g1992662 ADW TDA Custom directive added to the cpm file not updated after check-in# k$ _$ [7 k6 t. Y' z% q9 h1 |" p
1733129 ALLEGRO_EDITOR COLOR 'Display - Highlight', double-click permanently highlights symbol; X4 I' ?8 G0 Y$ B0 C
1861938 ALLEGRO_EDITOR COLOR Changing layer color changes layer visibility% k5 i3 {/ c; P, y; c
2034753 ALLEGRO_EDITOR CROSS_SECTION Allegro PCB Editor crashes when a cross-section technology file is imported in Overwrite mode
9 X' Q; V, _1 u! s# h2036895 ALLEGRO_EDITOR CROSS_SECTION Replay script error during import of tcfx Xsection file
: t. E, N# @3 b# {4 x1929360 ALLEGRO_EDITOR DATABASE Via color is inconsistent on Vias with color assigned- Y9 u4 R: ~0 s
1984203 ALLEGRO_EDITOR DATABASE Drill holes not displayed correctly in the Zone area
5 e. y T7 k8 `, I: P2013596 ALLEGRO_EDITOR DATABASE Assigning net name on Vias does not change the Via Color to that on Net Color automatically- t$ t7 c8 x( g5 b X9 J2 R _* H2 G3 c
2025798 ALLEGRO_EDITOR DATABASE Assign net to via changes color of the via to the default color3 ?4 Q0 Q0 {+ Q9 l" m
2032678 ALLEGRO_EDITOR DATABASE Unable to delete layer on design
3 Q7 a, |0 V7 y. C8 X: H2 P2032725 ALLEGRO_EDITOR DATABASE Dehighlight removes color assignment from color dialog U4 `3 W/ U/ K
2029542 ALLEGRO_EDITOR DFA Interactive Placement with Manufacturing Package to Package spacing' H3 C/ f* X. Y' x) b" O- ?$ j
2020548 ALLEGRO_EDITOR DFM Cadence DFM Customer site cannot Submit Request
' n' `: D' P h# q8 Q# q: ]2020566 ALLEGRO_EDITOR DFM Error when sending Design True DFM Rules Request! ^. w4 q( s; @% g c
2030179 ALLEGRO_EDITOR DFM Allegro PCB Editor .brd file will not save after routing using Automatic Router
, Z; R9 ] G0 J9 S, k4 p; Y* S+ ]* v5 m# g2052907 ALLEGRO_EDITOR DFM The Submit Request button for DesignTrue DFM Rules Request does not work
3 Z! Z [& Q' B2 W1928915 ALLEGRO_EDITOR EDIT_ETCH PCB Editor constraint status bar does not match Constraint Manager data when z-axis delay is turned on.
/ q' F, S! C( K: a8 o1932165 ALLEGRO_EDITOR EDIT_ETCH Arc slide behavior with clines at odd angles: notches on slides
: L4 W/ q+ N6 E% w1943901 ALLEGRO_EDITOR EDIT_ETCH arc segment incorrect on slide.
4 j* f5 u, l1 y5 s& M, `3 Z2031055 ALLEGRO_EDITOR EDIT_ETCH On drawing cline the width on a Layer is larger than defined constraint
# F+ M9 X, O1 N6 `& p1877891 ALLEGRO_EDITOR GRAPHICS Allegro PCB Editor crashes when started from EDM for projects without a board file or empty master.tag file4 e9 O% i! j8 @$ K6 R2 M% x
2040689 ALLEGRO_EDITOR NC The decimal digits of a rotated oval padstack do not match the Drill Chart.
+ S0 B2 v1 e2 P% y, Y2028105 ALLEGRO_EDITOR PLACEMENT Delay in moving a large count pin symbol6 z0 W' i( u* K! p4 f( r* T
2019027 ALLEGRO_EDITOR REPORTS Information shown in the Report Viewer is not correct.2 p8 h* |8 a0 q& B' n( J
2022461 ALLEGRO_EDITOR SHAPE Abnormal termination of thieving function in Allegro PCB Editor
4 ^( }% T) L9 |' u2032048 ALLEGRO_EDITOR SHAPE shape void difference from hotfix 026 to 048: need square corners for full round. S& p/ K6 u2 I3 e1 C8 V; ]9 V
2040138 ALLEGRO_EDITOR SHAPE shape_rki_autoclip affects the overlapping shape boundary. \4 E5 E" n9 Q9 h& S5 {
2040259 ALLEGRO_EDITOR SHAPE Same net shape and cline adds shape void around cline
4 h3 Z, j+ V1 \2031468 ALLEGRO_EDITOR TECHFILE Cross section import (.tcfx) not working correctly.5 O+ k1 i+ E1 b" T
2006425 ALLEGRO_EDITOR UI_FORMS Option to disable 'Create a New Design' window in OrCAD PCB Designer
% l& h. [* P1 n, P- g# X2007451 ALLEGRO_EDITOR UI_FORMS Option to suppress 'Create a New Design" window for File > Open in OrCAD PCB Editor from hotfix 0483 q4 {$ G/ Q0 I0 a: t* H- T
2009314 ALLEGRO_EDITOR UI_FORMS Existing scripts that open OrCAD PCB Editor not working in hotfix 048
# Q7 B& E5 o6 A0 o& V2021476 ALLEGRO_EDITOR UI_FORMS PCB Editor is slow when using the command 'add connect'
7 o% e2 K: P- X2039462 ALLEGRO_EDITOR UI_FORMS Hovering over Default symbol height in Design Parameter Editor does not display a description% w/ O2 ]3 Q) r
1808054 ALLEGRO_EDITOR UI_GENERAL Illegal value in axlFormSetField crashes PCB Editor
. p0 y' g& l9 p; S8 ?. T1822679 ALLEGRO_EDITOR UI_GENERAL 'Symbol pin #' field is truncated on rotating components in the Placement Edit mode4 h9 M+ B: l( W5 ?7 G" K
1856438 ALLEGRO_EDITOR UI_GENERAL Script recording messages not displayed in the PCB Editor task bar when using the script window.! \2 A; n, S5 C: i' J
1879078 ALLEGRO_EDITOR UI_GENERAL Running PCB Editor from command prompt with '-product help' should list all products and options
; ~8 }4 G) z. N; c( @1944225 ALLEGRO_EDITOR UI_GENERAL Cannot close log file window till we close report dialog box
+ N3 L& ~5 _3 r( {' b4 F: W1967708 ALLEGRO_EDITOR UI_GENERAL New Command Window Shows Last Command in UI
. F7 ]( P! z: U/ `$ t& x1968380 ALLEGRO_EDITOR UI_GENERAL Write all open editing sessions in MRU
; b. r; W$ m+ l7 z% y! f1982138 ALLEGRO_EDITOR UI_GENERAL axlFormListDeleteItem(fw field -1) not deleting last item of a list" _5 G0 q/ f" i; S2 T0 t
2003054 ALLEGRO_EDITOR UI_GENERAL Grids not shown when 'nolast_file' is set
* Q0 e9 q4 N! z. M2010760 ALLEGRO_EDITOR UI_GENERAL Pressing tabs is selecting only vias and not selecting clines in PCB Editor in hotfix 048$ h6 K* ^9 G \% B
2019120 ALLEGRO_EDITOR UI_GENERAL Tab key is not working when there are two objects on top of each other0 m' g/ l* z( X. s6 z4 u
2029248 ALLEGRO_EDITOR UI_GENERAL Colorview load is not working when using absolute path2 _8 J1 \2 x, T" O6 r, s1 w
2030985 ALLEGRO_EDITOR UI_GENERAL The view of the PCB is offset after closing and opening the board.
3 |4 s2 T, x; }) F2037968 ALLEGRO_EDITOR UI_GENERAL Tab key will not cycle between cline elements.' f+ j9 ~: P) y) u/ F0 U& m
2015766 ALLEGRO_PROD_TOOLB CORE Advanced Testpoint Check does not work* c7 r, U* A7 n% D: W
2023356 ALLEGRO_PROD_TOOLB CORE Edit new session does not work in quick symbol editor tool box8 a- g5 r! |1 v" y, Z) q' F
2017162 CAPTURE CONSTRAINT_MG Cannot apply ECSets in Constraint Manager-enabled Capture
9 b) o5 Q9 X% b5 X! G% S/ u2026777 CAPTURE CONSTRAINT_MG Cannot apply electrical CSet (ECSet) in Constraint Manager-enabled Design Entry CIS
: M) n9 k% s. r5 ~( A2027545 CAPTURE CONSTRAINT_MG Getting error (ORCAP-40320) while creating ECSet
5 E2 o ^3 \. Q8 Z; B1 I9 t2012967 CAPTURE OTHER Capture license is loaded slowly in hotfix 048
1 M+ v/ W# a9 a! f9 u ?1 k2010093 CONCEPT_HDL ARCHIVER Archive .zip file keeps the whole folder hierarchy and not only the project hierarchy Y. K5 d+ ?5 b; E% q
2040431 CONCEPT_HDL EDIF300 EDIF300, Schematic Writer, crashes in release 17.2-2016
) \& D% E0 Z2 H$ v$ w- N6 q5 d" l2034077 SIP_LAYOUT DFA DRC is not catching all Shape minimum width violations
' N: \8 ~( ?9 B7 X5 i+ V2034094 SIP_LAYOUT DIE_ABSTRACT_ [VSDP-RDL Exchange] some traces are lost in SiP Layout
% x; _9 [& h% ^9 s" g6 N* r2037462 SIP_LAYOUT DIE_ABSTRACT_ Cline Segments are lost on saving and re-opening the design in next session
! X: t# O2 t+ H- {$ g2025321 SIP_LAYOUT IMPORT_DATA compose symbol from geometry defaults need to change due to performance9 M+ r% I0 Q+ w4 @
2017759 SIP_LAYOUT PLACEMENT Placing a die creates extra place bound and puts pin numbers in the wrong place, causing future netlist import failure; _: D- ~! P. ]4 _* f' [# s
2021057 SIP_LAYOUT SHAPE Polybool assert error when adding dynamic shape prevents shape voiding. A" a3 B! D9 L3 C* L, L" R, d
2012381 SIP_LAYOUT SKILL Ability to check if the Dynamic Unused Pads Suppression box is selected using SKILL
5 {2 F: K7 C6 Q8 a4 o& C1990299 SIP_LAYOUT UI_GENERAL Pressing 'Esc' cancels DRC checking when there is no focus on the Allegro PCB Editor canvas
/ F/ B9 ^' [3 T2 t4 K4 d3 M1997317 SIP_LAYOUT WLP Advanced WLP, Metal Density Scan does not correctly calculate scan region count in Y direction% \/ ^! |7 N, R+ a9 [
2029524 SPECCTRA ROUTE SPECCTRA stops responding when executing the quit command, F" v* c; b; x; q7 D g1 g
1670888 SYSTEM_CAPTURE CANVAS_EDIT Rotation error when connected to a power symbol% y1 }3 k' D5 p3 S2 o( V; W
1880809 SYSTEM_CAPTURE CANVAS_EDIT Can modify only one RefDes from canvas for duplicate RefDes; can modify both from the Properties window
' n) M4 f4 Y, ~+ a2 l* n' k. C0 N9 Y1979063 SYSTEM_CAPTURE CANVAS_EDIT System Capture : File > Close is grayed out
6 k7 }0 m1 r4 g( {$ U2034498 SYSTEM_CAPTURE CAPTURE_IMPOR Cannot find parts via Find & Replace after importing Capture design3 s- j, o& a9 ~6 ?
1984561 SYSTEM_CAPTURE CROSSPROBE System Capture: Cross-probing from layout does not work when zoomed into a specific area on canvas
3 t6 w% u0 Y4 j, O1863460 SYSTEM_CAPTURE DARK_THEME thumbnail preview of pages is in light them but dragging the page the previes is dark* P6 O4 V4 v& _
2025876 SYSTEM_CAPTURE EDIT_OPERATIO Route failures when dragging a circuit
* U. p- D' ~" h, M) C2005904 SYSTEM_CAPTURE FORMAT_OBJECT Pin name text is smaller in System Capture than in DE-HDL by about 25%0 Y' q2 A: I$ e9 R+ I4 N
2036782 SYSTEM_CAPTURE IMPORT_BLOCK Unable to import the block from project.3 A( b; q& n n
2025949 SYSTEM_CAPTURE IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not translate in System Capture
" D9 b) Z: @6 b N2025950 SYSTEM_CAPTURE IMPORT_DEHDL_ Broken connectivity on imported ground symbols
0 O6 w) o6 b2 B$ q5 t9 b) i* f) o! Y2040923 SYSTEM_CAPTURE MISCELLANEOUS System Capture - Multiple Symbol Replace, disconnects and changes orientation8 H" R" M9 ]2 D$ F8 W) Z9 Y
2017526 SYSTEM_CAPTURE NAVLINKS Page information missing in NAVLINKS$ P! d, [0 t) q8 Z
2015346 SYSTEM_CAPTURE PAGE_MANAGEME Rename page fails in some cases: n9 a- q) g& v2 ]: b
2038811 SYSTEM_CAPTURE PRINT Black & White PDF showing colors' z3 s* p1 E2 B/ D! [* i
2048493 SYSTEM_CAPTURE SYMBOL_GEN Symbol Editor, Modify outline adds an 'X' in symbol incorrectly* O: V9 q+ Q7 v0 e* }* X! Y; }) k
2031995 SYSTEM_CAPTURE VARIANT_MANAG Variant Editor does not load the design and restarts the machine after sometime.
/ ~; Y3 r/ y* X0 y& G2032005 SYSTEM_CAPTURE VARIANT_MANAG Custom variables not saved for variants
k( F7 c+ u, T T( q: A1968431 SYSTEM_CAPTURE WORKSPACE Unable to reorder the pages (tabs) when opened in the workspace2 |7 N. O8 x6 |- {" X
2040995 XTRACTIM GUI Running XIM from APD enables "skip DC R simulation" by mistake
5 P( P" g7 y6 r4 T" Z# H0 ^5 j) o5 I5 _- I( L
) z# N9 M" H6 y3 w% R7 S4 F
Fixed CCRs: SPB 17.2 HF051
) X: e, g( Q/ W5 e3 i* D01-30-2019/ G' _3 C" M8 n9 `1 F+ I
========================================================================================================================================================
4 p7 A3 Z8 z8 _5 oCCRID Product ProductLevel2 Title
4 k$ Z& ?5 t, ^5 [# X) J========================================================================================================================================================
* O0 O. o1 e, D% v& l, Z1 v$ F" m2015843 ADW LIBDISTRIBUTI Error for library distribution (lib_dist_client) regarding string index out-of-range& z8 y/ T+ l6 D( A
1869914 ADW PART_BROWSER Adding components to System Capture schematic canvas takes long time in Linux clusters5 k9 s% W/ z f3 S% v
2010458 ADW PART_BROWSER RefDes values not appearing on parts
1 D$ Y' W; _) T4 n2022630 ADW PART_MANAGER Unable to successfully import a DE-HDL Design into System Capture
, r3 k5 L+ G8 ?# g J5 _" z2005033 ALLEGRO_EDITOR 3D_CANVAS 3D Flex issues: Error message when opening design with bends in 3D viewer
3 L4 L% n& {, V4 u2023496 ALLEGRO_EDITOR 3D_CANVAS Error for designs with bend in 3D Viewer% k+ N) `! a8 z+ V
2033459 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
+ N& a8 ]9 v# O4 J% T: h9 Y9 @1996431 ALLEGRO_EDITOR ARTWORK Via holes for connection have incorrect coordinates in Gerber- G; n! s% b9 b3 u6 m, V
1995656 ALLEGRO_EDITOR DATABASE Attaching and Detaching a text file created with SKILL writeTable() function corrupts the text file3 F# w+ G& |; Q+ y0 }
2027122 ALLEGRO_EDITOR DATABASE PCB Editor crashes when creating Place Replicate module9 Z. O6 f& H7 b* {+ N- U# V
2023916 ALLEGRO_EDITOR DFM DFF Annular Ring: Thru via pad to Mask violates on via in pad instances.$ c1 }7 q' q) t4 Z
2024523 ALLEGRO_EDITOR DFM PCB Editor crashes in Mask To Trace check of DFF.5 O8 \5 T0 ~2 D
2021318 ALLEGRO_EDITOR IN_DESIGN_ANA Integrated Analysis and Checking: Unable to run simulation with Crosstalk flow3 \: j U* e' z' v- [% Z) j" i! R! m
2014162 ALLEGRO_EDITOR NC Backdrill results using an OrCAD Professional license showing wrong values with hotfix 0481 b- B' u0 i6 Y y4 _. n
2010791 ALLEGRO_EDITOR PLACEMENT Setting dfa_pause_level to 3 and then moving and rotating part places the part with offset
2 g# T5 l( o7 ^5 _/ }, k) }2017112 ALLEGRO_EDITOR PLACEMENT place_boundary shown at wrong location when moved with User pick and footprints rotated3 O9 R2 K$ i. F* h9 ]
2028048 ALLEGRO_EDITOR PLACEMENT Rotate option using pick is rotating the outlines in different axis in view8 n& w u- M1 v7 x8 f- ~
2028314 ALLEGRO_EDITOR PLACEMENT Crash on moving components in Allegro PCB Editor
. r/ x0 A8 k4 ?1 l& p2029235 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when moving more than one component and hovering on IC
, E8 J' Y- v1 c$ _7 |% n' m2022644 ALLEGRO_EDITOR SHAPE dv_fixfullcontact obsolete in release 17.2-20168 U* F5 m! ~+ O4 W' {5 q
2023322 ALLEGRO_EDITOR SHAPE Gloss does not add teardrops on all clines.# r/ \5 P& O# n) M2 ]8 Z6 e6 }
2024235 ALLEGRO_EDITOR SHAPE Copper Pour disappears when area includes parts8 o; m" v* }9 x$ m
2024531 ALLEGRO_EDITOR SHAPE rki_autoclip is not working at a special XY location
# [, C) z3 N. e4 K# D2024599 ALLEGRO_EDITOR SHAPE Cannot create round corner for shape& L# f$ ^- o- `& s
2024707 ALLEGRO_EDITOR SHAPE In-line void control does not work when there is no_shape_connect property attached0 K. {0 a6 s" L8 o# x0 R
2026849 ALLEGRO_EDITOR SHAPE Cannot assign region name using the 'next' operation- @ V6 A) r8 i, @: l" {
2030156 ALLEGRO_EDITOR SHAPE Shape Area report for cross-hatched shape includes hatching and boundary
& ~) [+ H2 M! F2 d1852981 ALLEGRO_EDITOR SKILL Error message while creating Copper Mask layer without a name using SKILL not clear6 ~; G) [2 C' O4 F9 K$ v
1968054 ALLEGRO_EDITOR SKILL Document of axlClearObjectCustomColor should indicate that it can clear color for DBID of Net
+ E Z9 X8 B4 J+ h# c2026429 ALLEGRO_EDITOR UI_FORMS PCB Footprint wizard: horizontal and vertical lead pitch level reversed in the image g( l/ D- `; Y8 {! J) [
1768032 ALLEGRO_EDITOR UI_GENERAL Numeric keypad does not work for file selection shortcut2 {- k. s$ D( G+ @( V
1797376 ALLEGRO_EDITOR UI_GENERAL Release 17.2-2016: Padstack Designer saves padstack to the working directory when script is used" s; b5 d3 W5 n4 W
1798524 ALLEGRO_EDITOR UI_GENERAL Unable to save a padstack using script/ w$ y: d$ a4 v6 k o3 r) r: ~
1823031 ALLEGRO_EDITOR UI_GENERAL Help not working for OrCAD Productivity Toolbox5 o5 `; ^# w3 A8 o
1849921 ALLEGRO_EDITOR UI_GENERAL Analyze menu missing in OrCAD PCB SI% I x4 K( e6 r% Q7 c; O9 s
1951740 ALLEGRO_EDITOR UI_GENERAL Trigger for 'open' does not work when opening a .dra file
( x i- H$ P: T8 f1952163 ALLEGRO_EDITOR UI_GENERAL Analyze menu missing in OrCAD PCB SI
0 m+ m) ]$ ]3 I4 c7 M$ p1 h) ~1982966 ALLEGRO_EDITOR UI_GENERAL SKILL command to access the Option window fields while in Interactive commands.
. T6 ?6 m* P4 [8 a$ j+ J! h1983567 ALLEGRO_EDITOR UI_GENERAL Alias with Ctrl not working with 'command window history' variable enabled; W5 e7 {, w9 R% n5 ]
1989507 ALLEGRO_EDITOR UI_GENERAL Third-party tool causes PCB Editor to stop responding to command
: w" w4 g4 l% F K) Q2003511 ALLEGRO_EDITOR UI_GENERAL Aliases using control (tilde) characters stopped working after upgrading to hotfix 048; m6 y1 V$ F4 K e2 b9 \. W
2010418 ALLEGRO_EDITOR UI_GENERAL New command window breaks funckeys1 g- ~9 H* }' F
2018201 ALLEGRO_EDITOR UI_GENERAL SKILL axlDBControl ('activeLayer /') updates active class/subclass but ministatus form not updated
- v& f1 w* e2 h/ O2023468 ALLEGRO_EDITOR UI_GENERAL axlZoomInOut does not zoom out, always zooms in regardless of zoom factor (positive or negative)
, S' i' }' Z+ |! b7 s2026428 ALLEGRO_EDITOR UI_GENERAL PCB Editor takes several minutes when saving a design
5 j8 a3 E. r! I5 l+ d2032697 ALLEGRO_EDITOR UI_GENERAL Funckeys with Ctrl not working with 'command window history' variable enabled: X) W# Z5 R4 O0 F$ ~! ^ \9 u
2032717 ALLEGRO_EDITOR UI_GENERAL Funckey combinations, such as Ctrl + M, not working4 R0 g. |* M G ^, q+ V
2014211 ALLEGRO_VIEWER OTHER Arrow keys are not panning in Allegro Physical Viewer
W1 n1 ], k' g& r; J1 V! S, E5 ~" _2039081 CAPTURE NETLISTS Netlist not created: netlist fails for numeric pin names with backslash '\'0 q# ^! O8 W$ o# a S+ I' J1 j0 L( l3 @
1993057 CONCEPT_HDL CONSTRAINT_MG Constraints disappear in hierarchical design (Electrical->Net->Routing->Relative Propagation Delay) |/ _) X# O) {
2004641 CONCEPT_HDL CONSTRAINT_MG 'Save Hierarchy' (hier_write) deletes bus object in Constraint Manager
& f, K6 f6 e% t+ N2020901 CONCEPT_HDL CONSTRAINT_MG Incorrect match Groups created in CM (TDO design)
0 n# }/ I9 g/ | @# l8 ]8 _4 X2014979 CONCEPT_HDL CORE The active schematic page randomly changes while editing text
% k% W3 s1 f m) ?2027905 CONSTRAINT_MGR DATABASE Pin Property changes in CM during uprev to release 17.2-2016: L) X) Q6 s/ u* ^
1762263 ORBITIO INTERFACES Add set allegro_orbit_import variable to user preference
1 A, V ~2 Q: O) F$ S; B% w' K4 ~7 Y2005860 PSPICE LIBRARIES Error when simulating design with TL494 part in release 17.2-2016
" ]" w! F9 k! ]+ J. \. Z! _1980072 PSPICE SIMULATOR Noise in the waveform when using DELAYT and DELAYT1 with capacitor2 z3 q& h: |1 k- [9 B- Z% B& _7 N
1977615 RELEASE INTEGRATION Cannot import third-party schematics into OrCAD Capture in release 16.6
1 C7 i4 M4 _5 `: f2027009 RF_PCB SETUP 'RF-PCB' - 'Setup' changes not saved on Apply
( ]$ q- d* }$ h4 N$ S2002040 SIP_LAYOUT MANUFACTURING IPC 356 'ignore die layers' does not work: netlists to die" p* G' r; }( W" ]# ]( \8 }
2024703 SIP_LAYOUT WLP Cannot Add Pin Text: Error on 'Manufacturing' - 'Documentation' - 'Display Pin Text'7 z. {& X) N& M6 k% X
2010045 SYSTEM_CAPTURE CANVAS_EDIT Cannot snap back vertical CAP until moved up and down horizontally4 U/ a: S1 v4 A; L0 u. y
2010443 SYSTEM_CAPTURE CANVAS_EDIT Cannot select the CAP part
% \0 Z6 w0 U5 v& Z+ ?3 ~5 w: X2012843 SYSTEM_CAPTURE PACKAGER Cannot short two grounds in the schematic
8 @' w0 I1 v7 Q9 L2015574 SYSTEM_CAPTURE PACKAGER System Capture is treating quotes in PTF files differently from DE-HDL* v3 ~# n5 j6 K; r
2022653 SYSTEM_CAPTURE VARIANT_MANAG Variant Editor - Allow Alternates where ALT_SYMBOL is a valid match for JEDEC_TYPE3 U4 b9 N3 Z8 D0 @+ ^
2024742 TDA SHAREPOINT Accessing projects is taking time
2 E Y/ L, q* }' J* Y2010531 XTRACTIM OTHER Allegro crash on repaint of command window
4 p7 c2 g, @% l1 W2022351 XTRACTIM OTHER XtractIM is crashing the latest HF S049
& Q1 F# n: {% s& x L' o; o; ~; S: Z3 y/ f& \, A- A
0 m4 p& b( j" R0 x+ |. z. l3 UFixed CCRs: SPB 17.2 HF050
2 a9 S. \4 ?( @& q) s5 U12-23-2018
4 c, r1 Q s0 k0 [5 y+ n/ ^- v- k; b, m2 u========================================================================================================================================================% E( G3 A7 C! d2 @* b; |
CCRID Product ProductLevel2 Title
% A* E6 {6 Q# r4 s8 ^========================================================================================================================================================/ l! F4 P U- ?, E. |
2012119 ADW ADWSERVER Cannot connect Component Browser to server
! _6 E, f1 A, w' N! L8 Z1998856 ADW ADW_UPREV adw_uprev fails and a typo in rule name
5 `, c) V6 }( i b- ?1673333 ADW CONF Configuration Manager stops working and gives Java Timer-1 Error
; F. ~# ^/ o/ D& N1900342 ADW DBEDITOR 'Link To' on a schematic classification attribute does not work with linked attributes containing parenthesis. M% X% @, A& ^+ [# e- f# Q* F1 c
1997516 ADW DBEDITOR DBEditor stops responding on changing attributes
% F9 o$ D0 J) O8 J2 o1986292 ADW LIBDISTRIBUTI Some parts are not updated in the part table in all_noauto and ini_noauto (restricted_sites).3 n" `" V, e: E9 \+ y+ E0 G! z
2010460 ADW PART_BROWSER PKG-1002 error when opening a DE-HDL design2 D' I7 ]- ~) u- o! g
2013430 ADW PART_BROWSER Add component is inactive if WB_SHARED_RESOURCES is not pointing to the installation directory
; k) I0 j; V) a/ N7 E2 S* j7 i' n/ l2022806 ADW PART_BROWSER PKG-10005: Cannot package the following primitive instance in any section of the physical part5 i9 Q9 ]( V% U
2006528 ADW PART_MANAGER Part Manager does not update parts when Key PTF property value changes8 I; R9 F! S3 @2 g: ^+ y b
1980397 ALLEGRO_EDITOR DATABASE Mechanical pins with route keepouts (RKO) not updated
( `/ C& c# N2 a6 x: A) j1988171 ALLEGRO_EDITOR DATABASE Backdrill clearance Keepout is not applied consistently7 Q% t( L* ~' k
1994280 ALLEGRO_EDITOR DFM PCB Editor crashes during Unplace component
9 t1 B* g3 |' d* e a! ~0 ]2012742 ALLEGRO_EDITOR DFM DFT for testpoint to outline not showing DRC" P0 R: J, V# A
2002680 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on choosing Add Connect for two selected nets
9 ~$ z/ m! L1 e/ _6 [2004597 ALLEGRO_EDITOR EDIT_ETCH Illegal BMS Identifier error when copying multiple via structures/ i) S O0 N7 m+ }4 y
2004929 ALLEGRO_EDITOR EDIT_ETCH Net with physical pin pair constraints is using incorrect line width when routed* J# @* y" J% t( A p; c
2008314 ALLEGRO_EDITOR EDIT_ETCH Adding nets in tabbed routing crashes PCB Editor
% Q( _/ _8 T ~: A) A2018710 ALLEGRO_EDITOR GRAPHICS Using the mouse to zoom by scrolling stops working randomly! D! R- U U- P0 ]- X4 ~3 Q
2018841 ALLEGRO_EDITOR GRAPHICS Canvas does not regain mouse focus after working in the Options pane in hotfix 049
0 x3 u+ s+ N$ c8 h8 G/ o2019482 ALLEGRO_EDITOR GRAPHICS Canvas does not regain mouse focus after working with the Options pane in hotfix 049 on Windows 70 U/ U5 _9 M6 x1 L. g. Z1 d
2019864 ALLEGRO_EDITOR GRAPHICS Using the mouse scroll button to scroll the canvas: focus is in the Options pane5 K% N _ [) z' j5 Z5 z
2020750 ALLEGRO_EDITOR GRAPHICS Zoom in/Zoom out scroll does not work+ e2 A6 @' a6 }/ |8 o* O* {+ E6 r
2020847 ALLEGRO_EDITOR GRAPHICS Scroll up/down key focus remains in command screen even when canvas is selected
7 n" x' x$ A( R1908812 ALLEGRO_EDITOR INTERACTIV Tools > Design Compare command does not work on Windows
6 L% w" B8 E4 r' _( ?1995846 ALLEGRO_EDITOR INTERACTIV When there is an embedded component, the result of Metal Usage report is incorrect.2 P( H& {4 x8 X- t& s; s9 D
2011449 ALLEGRO_EDITOR INTERACTIV Command not found error (_impvision) for Impedance and Return Path DRC visions) l/ L4 h2 o7 W* @; B( d
1982867 ALLEGRO_EDITOR INTERFACES DBDoctor displays error for objects outside extent that cannot be fixed because the extents cannot be increased0 C7 I, `, c$ J) r
1983177 ALLEGRO_EDITOR INTERFACES PCB Editor crashes when reading IDX file+ L2 \$ y; M& g) x: }2 T# L2 ]: J% ?
1985623 ALLEGRO_EDITOR INTERFACES STEP model not exported from PCB Editor6 @. k/ Y( r( U! b# @
1994855 ALLEGRO_EDITOR MANUFACT Drill legend with counter-bore: legend size not uniform when database set to inches4 F( m H0 W* [; `" T/ M; Y$ F
2001355 ALLEGRO_EDITOR NC PCB Editor crashes with NC route parameter
6 X" i, C, q# a5 ~( S1753414 ALLEGRO_EDITOR OTHER Ability to add Rigid Flex class in a format symbol( D0 J) w: V+ q
2004786 ALLEGRO_EDITOR OTHER Legacy menu option missing in OrCAD Professional
$ m6 Z% x+ ]9 }3 ?% G- q$ f1949695 ALLEGRO_EDITOR PADS_IN Third-party to PCB Editor translation does not make a clean conversion
* Y' A5 O9 n1 p# _' g) [2 r1949658 ALLEGRO_EDITOR PLACEMENT SKILL module creation issue: subsequent runs rotate module incorrectly
6 x3 C; }3 D. j3 c2001496 ALLEGRO_EDITOR PLACEMENT Constraint Region not replicated as part of the Place replicate apply command, h: Y- d/ N8 {) ?, n
2002989 ALLEGRO_EDITOR PLACEMENT Default rotation point is set to 'User Pick'* Y9 }4 K$ {* q5 k0 u% c* }
2007301 ALLEGRO_EDITOR PLACEMENT DFA boundary is shifted when moving components with User Pick
& L! Y3 S- ~4 r# p2007312 ALLEGRO_EDITOR PLACEMENT DFA boundary is shifted when moving components with User Pick( W- w$ d' d5 F: Z ?
2008098 ALLEGRO_EDITOR PLACEMENT DFA boundary shows a shift if anchor point is set to 'User pick'
8 M! J' r, c! b2009085 ALLEGRO_EDITOR PLACEMENT DFA boundary is shifted when moving components with User Pick, d/ ]9 N# V; ]" c9 G& p
2009090 ALLEGRO_EDITOR PLACEMENT DFA boundary is being offset when moving components with User Pick! f! n, _1 x4 M' w3 A9 e
2009580 ALLEGRO_EDITOR PLACEMENT Component outline offsets during move process
; O- w! Y. Y) h+ w2010726 ALLEGRO_EDITOR PLACEMENT Two images appear when moving component in release 17.2-2016, hotfix 048/ }+ Y; N* w8 W$ y p( e$ P
2010819 ALLEGRO_EDITOR PLACEMENT A separate outline appears when moving components using User Pick
# f+ o: c G( J" K2011454 ALLEGRO_EDITOR PLACEMENT DFA boundary is not centered correctly on moving components
2 t- t) f" p W c l% Z1 P( I: @2011497 ALLEGRO_EDITOR PLACEMENT DFA boundary shifted from the part when moved9 s1 u7 c1 {0 R
2014250 ALLEGRO_EDITOR PLACEMENT Moving a symbol using the 'User Pick' causing an offset image of the symbol outline getting attached to cursor
5 a' x. E+ I4 j1 V0 J N2015676 ALLEGRO_EDITOR PLACEMENT Strange end-to-end DFA checking: offset of DFA from component when in user pick- z0 R2 ^ p9 `
2016421 ALLEGRO_EDITOR PLACEMENT Fail to place symbols because definition is incompatible for attribute 'PW_GENERATED'
/ J* b. g' s) \" j6 x& c" ?) A) v8 l! V2016452 ALLEGRO_EDITOR PLACEMENT Some symbols cannot be placed due to property definition differences7 A# e! Y% i) \9 D4 s
2016527 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes on moving all components on board0 c$ B+ _9 t+ f* p4 A1 z# D0 _
2017364 ALLEGRO_EDITOR PLACEMENT Strange behavior when moving component: DFA or place bound area is centered around the User Pick position
' n5 L" A- U0 j1 `) j& [8 f4 R7 _2018859 ALLEGRO_EDITOR PLACEMENT Moving parts by 'User Pick' or 'Sym Pin #' shows two component placement boundary outlines
. k# K" O1 h9 `/ |. V! O' s2019364 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when moving components
" J v- N! H' h2019478 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when moving more than one component across the design( U( v5 i1 T, o" [! d
2019624 ALLEGRO_EDITOR PLACEMENT DFA Boundary is offset from definition when moving symbols with user pick" a5 o7 l8 \% [3 p7 K/ l
2021625 ALLEGRO_EDITOR PLACEMENT Graphical Issue with Edit - Move and User Pick: additional outline image shown
8 e1 T; n* H5 E( N4 H k& U2022203 ALLEGRO_EDITOR PLACEMENT Place bound outline is shown at the center of the pick when moving a part by User Pick. s* L% G: q) r. V7 y: D
2024655 ALLEGRO_EDITOR PLACEMENT Moving multiple components causes PCB Editor to crash% E5 O: f0 g2 W* k! Q
2025895 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when multiple symbols are moved and on getting too close to another symbol# a! ~9 _, b* d+ J, z/ k
2004497 ALLEGRO_EDITOR SHAPE Automatically deleting antenna shape is not deleting thermal reliefs associated with those shapes4 D- \1 v2 `* G
2007832 ALLEGRO_EDITOR SHAPE Cannot void shape properly after rotating symbol) S, z! B2 y3 ^6 G- q2 R" H) s7 Z1 c' R
2009601 ALLEGRO_EDITOR SHAPE Error for shape created using third-party SKILL utility: X! Z* @$ \8 Q
2010924 ALLEGRO_EDITOR SHAPE Dynamic shape does not void in route keepout areas
; F( O: S* J1 |! @6 f2011176 ALLEGRO_EDITOR SHAPE Nothing happens on choosing 'Shape- - Change Shape Type' in Allegro Sigrity SI
( e" _" X; A3 B- R/ d2015446 ALLEGRO_EDITOR SHAPE Thermal relief connection created for static shape covering pin when inside a void in a dynamic shape.% N8 t- Y$ R$ D" I- y
2017273 ALLEGRO_EDITOR SHAPE Same net spacing does not void properly for shape to hole.9 L2 ]! \2 z) a, v
2012878 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as size differs for customState and customExteded in registry& ]) T; T6 |9 h" P' n; v8 o
2018177 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as size differs for customState and customExteded in registry
1 [" ~# B7 N4 c" ^7 z0 d$ m2019437 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as size differs for customState and customExteded in registry. Z" O. L- W, N3 o- h. a0 }
2020491 ALLEGRO_EDITOR UI_FORMS Cannot load custom toolbars because the customState and customExtended Windows Registry entries are incorrect
5 S s6 A' A% O4 z' O1897843 ALLEGRO_EDITOR UI_GENERAL Function Keys, such as F3, F6, and F7, are not working if tool is idle for some time3 l7 A% A4 ?9 l9 U
2000445 ALLEGRO_EDITOR UI_GENERAL Funckeys not working in hotfix 048 with the new Command Pane as default
* M2 q: o8 w |% b) j: C/ }* ?2001847 ALLEGRO_EDITOR UI_GENERAL Ctrl related funckeys not working in hotfix 048
! q7 e1 q$ T4 O9 s+ M) U5 G2008112 ALLEGRO_EDITOR UI_GENERAL Funckeys using Ctrl and Shift do not work in hotfix 048 (QIR 7)9 V$ ~" C2 o- `. E
2010370 ALLEGRO_EDITOR UI_GENERAL Shift + arrow key does not move component in release 17.2-2016, hotfix 048" N4 r% w+ `- V, O+ {: c5 e- h
2015418 ALLEGRO_EDITOR UI_GENERAL Funckey not working+ k% G2 _# p8 Q* G- r0 r
2015443 ALLEGRO_EDITOR UI_GENERAL Text does not regain focus even on clicking after using a drop-down menu# ]7 d) _/ b5 f7 a+ X6 @
2016899 ALLEGRO_EDITOR UI_GENERAL Dynamic zoom and funckeys are disabled after clicking a combo box in the Options pane
+ r( T( d, H3 G; w2019753 ALLEGRO_EDITOR UI_GENERAL Infinite Cursor disappears regularly in hotfix 049 when infinite_cursor_bug_nt is set
" b# w, Q# A7 ^, _% I2019990 ALLEGRO_EDITOR UI_GENERAL Mouse over does not highlight pin, need to click/ b1 ^$ A/ `' ?, W- {2 d
2020162 ALLEGRO_EDITOR UI_GENERAL Funckeys not working in hotfix 049: pressing F4 not running Show Element! v% ?( Y$ n# f: W
2020168 ALLEGRO_EDITOR UI_GENERAL Data tips not shown on mouse hover
. h7 x% H# A9 Q, }4 t7 e# _& U- p2020840 ALLEGRO_EDITOR UI_GENERAL Page-up/Page-down (remapped to zoom-in/zoom-out) stop working until mouse scroll button is pressed
% g& u2 G7 n0 U1 W5 ~& }3 Y8 c) c' _2021416 ALLEGRO_EDITOR UI_GENERAL New user interface does not shift input focus and zoom in/out does no longer work in layout window- w- B- ]; j: v5 A
2022185 ALLEGRO_EDITOR UI_GENERAL Ctrl related funckeys are not working
- B( {' e/ z$ _- O* \( D8 o* Y F2023402 ALLEGRO_EDITOR UI_GENERAL During Add text, focus does not move from the subclass dropdown to the canvas.9 g; r) o& s% e% u6 \5 s# P
2025806 ALLEGRO_EDITOR UI_GENERAL Function keys and shortcuts not detected# H0 u5 p- f0 {
2027581 ALLEGRO_EDITOR UI_GENERAL Funckey problem: focus lost from canvas on using another window
3 t- A& r2 p2 R2009382 ALLEGRO_EDITOR ZONES When deleting zone by Zones - Manage, the shape in zone is out-of-date3 D& @5 X9 n R9 d$ K! P
1977211 APD DXF_IF APD: die pads shift after export DXF5 P& C. c+ e, V$ ~2 a _! ^
2018483 CAPTURE NETLISTS Error when extracting netlist from schematic (ORNET-1193), r! ^5 O( k* _# {1 f
2022764 CAPTURE NETLISTS Schematic will not generate pstchip.dat file
6 w9 O5 q6 p7 Z1921557 CAPTURE NEW_SYM_EDITO Zoom to region option grayed out4 H9 ]- G: L t) R1 _: n3 K0 s0 T; B
1945203 CAPTURE NEW_SYM_EDITO Symbol Editor: No Zoom to Region and cannot edit Pin Type and User Pin Properties for multiple pins% l' I' r0 n6 f+ @6 t' E+ a
1950178 CAPTURE NEW_SYM_EDITO Ability to remove convert view of a component, V0 _/ B8 @$ y& {$ V+ H
1966792 CAPTURE NEW_SYM_EDITO JavaScript error on trying to edit pin name for GP0' f2 g2 Y' x# \ D' W& p
1969099 CAPTURE NEW_SYM_EDITO Cannot add convert view after creating a part* ]! z* }3 c% O# E1 M
1969834 CAPTURE NEW_SYM_EDITO Shapes not mirrored around center if more than one shape selected in Symbol Editor0 f, i' h' b2 ~) ~ p
1970984 CAPTURE NEW_SYM_EDITO New part is getting Numeric Numbering automatically F: T- X- x7 O6 p0 _: S
1972607 CAPTURE NEW_SYM_EDITO New Symbol Editor: name cannot be edited unless value is entered for a new property1 T6 a$ t$ M& H- ^+ q3 ]
1972635 CAPTURE NEW_SYM_EDITO New Symbol Editor: wrong listing of Symbol Properties in right pane0 q4 h+ ?0 |3 Z9 n* v
1974296 CAPTURE NEW_SYM_EDITO Design Template font settings are not being honored for new library/part creation
& H8 K: [ z# q- _8 E+ {; k1982783 CAPTURE NEW_SYM_EDITO Part Editor is blurry when zoomed out.
5 X/ \* {/ b8 C% j1993361 CAPTURE NEW_SYM_EDITO Cannot change part numbering, set to Numeric by default! s, }& D) M/ @) i
2003749 CAPTURE NEW_SYM_EDITO Cannot save edits to hierarchical blocks in new Symbol Editor in hotfix 048
" K& y- Y* k& G5 _2004395 CAPTURE NEW_SYM_EDITO 'Pin ignore' modifications not saved in new Symbol Editor 'Edit Pins' after hotfix 048
5 \" \, v: X4 U2007747 CAPTURE NEW_SYM_EDITO Cannot add Convert View after creating a part1 h; @0 W& _. F
2011321 CAPTURE NEW_SYM_EDITO 'Place - Picture' is not working for blocks in hotfix 0482 a, ^5 S' I: h$ ]+ `, c7 C
2013146 CAPTURE NEW_SYM_EDITO 'Part Edit' not updating changes in hierarchical block
- o' R- e: k3 N9 K2002904 CAPTURE OTHER Unable to check out Capture license in release 17.2-2016, HotFix 048
2 A" Q B0 r# V0 Z; z2 O2002922 CAPTURE OTHER Unable to check out Capture license in release 17.2-2016, HotFix 048' s7 W1 z: J! Y* y# W5 l5 y8 y9 q
1988812 CAPTURE PART_EDITOR Parts created or edited with hotfix 038 Part editor do not use default font size
" Q' e1 F7 [1 ?( g1 j; d! w2008912 CAPTURE SCHEMATIC_EDI Design Compare shows 'NaN' in the graphical output
; j$ O. I, D+ t1985701 CONCEPT_HDL CHECKPLUS Library symbols are missing from the examples folder
. P$ r( Q' y7 R+ y' u/ W$ ~1933789 CONCEPT_HDL CORE honor_sch_custom_texts
7 C7 U0 ?% E; a& F1933892 CONCEPT_HDL CORE HONOR_SCH_CUSTOM_TEXTS; l% }) [! J! w: _/ G, T/ _" U0 \
2001737 CONCEPT_HDL PDF DE-HDL crashes on choosing File - Publish PDF0 X- D" u' b( F1 |$ k8 X6 A
2010508 CONSTRAINT_MGR CONCEPT_HDL Schematic data corrupted on reading the data from CM database using the CM SKILL APIs) {; n8 E( Z1 U/ ^& l" A
1997461 PSPICE AA_FLOW 'Edit PSpice Model' from 'Assign Tolerance' window does not work
1 }! Y' o! G* w f5 H6 g" J2005948 SIP_LAYOUT DIE_EDITOR CTE expansion tool shifts pins off the die
( h/ V2 X8 }+ }8 u- W4 _1893045 SIP_LAYOUT INTERACTIVE Refreshing bond finger labels causes all the labels to shift location" c3 e- h `4 a, h
2006926 SIP_LAYOUT ORBITIO_IF Bundle translation from OrbitIO is incorrect/ K( P+ i3 k& a, G5 b3 W
2006659 SIP_LAYOUT SHAPE Cannot form fillets inside a shape in hotfix 048# n, n% P$ K- p4 a X' \1 R
1969192 SYSTEM_CAPTURE CANVAS_EDIT Pin Numbers of Discrete Symbols visible& C/ z1 e+ e: [( A* h6 V
1982368 SYSTEM_CAPTURE CANVAS_EDIT System Capture switches to Auto Pan, even if the option is disabled, in the Notes mode0 c' V* x0 d- r( e
1995012 SYSTEM_CAPTURE CANVAS_EDIT Connect lines do not move with components9 t* Y% o- L* [6 U
1907992 SYSTEM_CAPTURE CONNECTIVITY_ Draw stubs is not respecting stub length setting.3 `) |5 j8 G/ u& |
1960100 SYSTEM_CAPTURE CONNECTIVITY_ Moving components after routing failure: connect lines do not move resulting in disconnected route/ N% T6 N$ c% M+ K( ?, F
1988284 SYSTEM_CAPTURE CONSTRAINT_MA Log files and topology files are being stored at the top-level design (CPM) folder level" d$ l; N# O$ m) T8 Y) h* x
1996039 SYSTEM_CAPTURE COPY_PASTE Cut and Paste change the pin numbers for connector after saving design./ p" m* J; S, o9 Z" @( d! O
1951700 SYSTEM_CAPTURE EXPORT_PCB System Capture: Export Physical - Change Directory UI entry block not displaying properly
; O7 d! r6 u8 c4 O5 S& M. C' X1970761 SYSTEM_CAPTURE EXPORT_PCB Cannot import System Capture netlist if PCB Editor is launched with -proj argument. P" L; S5 C! i
1997533 SYSTEM_CAPTURE IMPORT_PCB Pins do not swap in System Capture on backannotation
- _* k) W+ J. J1910962 SYSTEM_CAPTURE MISCELLANEOUS Dragging GND symbol placed on a pin sometimes disconnects the GND symbol
; B0 n% \8 k' `- [% z% ?1962037 SYSTEM_CAPTURE TABLE_OF_CONT Table of content link number not same as page number in the title block6 Q# n. o" O# x0 C
1986317 TDA SHAREPOINT Cannot enable Design Management and SSO session expires
6 D% m8 |# W6 i4 Y3 g* _5 i8 U1 |1 p; G+ z/ t$ f
" M4 u) I- l* W5 C ^) h
Fixed CCRs: SPB 17.2 HF049& q" y9 |% I( O) H0 S
11-16-2018
# b4 y; f! a% o) d- n0 H0 b; A========================================================================================================================================================7 W$ C& }; L, O
CCRID Product ProductLevel2 Title9 H5 Q# P& z+ y3 k" N( H5 g
========================================================================================================================================================8 N% E* ^& f% o6 l) v
2002642 ADW ADWSERVER Exception in adwserver.out with LDAP enabled
: j& X' Z- K* S* I) o+ M9 h" r2007046 ADW ADWSERVER Component Browser is not connecting to server in hotfix 048; j! J l9 A) v4 m4 x
1997678 ADW DBEDITOR Model not deleted due to missing cell model relation
( n+ v/ D7 i/ V# i1985059 ADW FLOW_MGR Flow Manager issues warning about project path that contains a period, removes from catalog file
( m& Q2 D% Q/ [' x1991515 ADW FLOW_MGR Flow Specific Tools: Launch error after upgrading to Hotfix 044 and extending code
" w! t3 K$ F$ [1972762 ADW PART_BROWSER The Schematic Models icon does not match the definition in EDM Component Browser
" J" c# C) w; u/ f( n. Y: Q1830062 ALLEGRO_EDITOR DATABASE Uprevving release 14.0 design with stand-alone DBDoctor in release 17.2-2016 crashes; works in release 16.6
' R, Y6 C$ M w. r0 O1980161 ALLEGRO_EDITOR DATABASE NODRC_ETCH_OUTSIDE_KEEPIN assigned to text in library part is not passed to PCB Editor
/ [% W' [- E* u9 B6 z3 @2 Q% ^2003757 ALLEGRO_EDITOR DATABASE Open circuit not detected by PCB Editor: reports unconnected pin as connected
$ g- _8 k2 M, B: b5 v' |2009748 ALLEGRO_EDITOR DFM PCB Editor crashes on Update DRC
$ D4 N7 P. v2 T, L( b: l: F9 ?1796895 ALLEGRO_EDITOR DRC_CONSTR Increase precision of Inter Layer Spacing check
, ^: I7 ]; E4 V& \+ o1997487 ALLEGRO_EDITOR DRC_CONSTR Cannot add teardrops to some pins$ b4 ^- y$ ~2 h6 A/ `0 V
1857024 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using funckey 'y FORM mini padstack_list -+'
! L# G2 l1 m+ C1 f# E5 H9 f' u1979750 ALLEGRO_EDITOR INTERFACES axlStepSet not working for component definitions
2 e9 D4 \) {! I/ k9 F1988168 ALLEGRO_EDITOR MANUFACT Graphical Compare in productivity toolbox terminates with errors( S1 ]1 j) p9 E9 v9 ]( G: l
1982233 ALLEGRO_EDITOR SCHEM_FTB Netlist files cannot be imported into board as the process is not finishing7 t; |: p5 E1 q0 e( D3 G) z
2000367 ALLEGRO_EDITOR SCHEM_FTB Cross-probing between OrCAD Capture and PCB Editor does not work in HotFix 048) _8 B- {8 q" p" v8 }4 N2 {6 W
2000397 ALLEGRO_EDITOR SCHEM_FTB Cross-probing not working with hotfix 048
/ R; z/ {9 I# Z: m8 O" h2000552 ALLEGRO_EDITOR SCHEM_FTB Cross-probing is not working if we are importing Netlist from PCB Editor n' \0 k9 r) Y0 e
2001165 ALLEGRO_EDITOR SCHEM_FTB Cross-probing between Capture - Allegro PCB Editor fails after hotfix 048' [" S2 q( O7 Q7 C+ V* w
2002635 ALLEGRO_EDITOR SCHEM_FTB Cross-probing issue because of Unique MPS Session in HotFix 048 (QIR7)2 i- R- [2 \; X$ Q( T) c
2004252 ALLEGRO_EDITOR SCHEM_FTB Cannot do cross-probing between Capture and PCB Editor) W' h; @* Z1 l W# c
2004305 ALLEGRO_EDITOR SCHEM_FTB Inter-tool communication is not working properly in PCB Editor release 17.2-2016, hotfix 048- v B& a$ p! `1 V$ T$ ?
1978660 ALLEGRO_EDITOR SHAPE Static shape on dynamic shape issue: thermals not removed when component is moved
: {- f8 s) G1 m" j1 d7 E. X) ]5 F1985035 ALLEGRO_EDITOR SHAPE Thermal reliefs not removed on moving parts( i& b- }* `/ ^8 I/ ~" c. l
1960966 ALLEGRO_EDITOR SKILL Stackup import is not working in release 17.2-2016 via automation
* ~* u7 W* ], d% Q" s2003651 ALLEGRO_EDITOR UI_FORMS Error on starting and loading footprints in hotfix 048: message about customExtended and customState0 K c1 L( S9 W) z z8 j4 t8 |( ], b
2003810 ALLEGRO_EDITOR UI_FORMS OrCAD layout editor font size is too small for almost all UI) |5 E7 D/ D# {% w8 i, s5 v; [
2003832 ALLEGRO_EDITOR UI_FORMS Error on loading footprint in hotfix 048: custom toolbar cannot be loaded due to registry problem, a9 x5 |2 c( ?5 O3 w Y& a% X
2004769 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as the size of customState and customExtended differs in registry
8 ?) K' ?5 q* b2 h6 D2 ]: Q2007669 ALLEGRO_EDITOR UI_FORMS Broken scalability between OrCAD PCB Editor and Allegro PCB Editor
% i2 {9 h- N2 y& D0 p9 Z' O1987164 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding when multiple sessions are accessing third-party tool
' U8 `* {; U$ U/ R( n) m1983512 ALLEGRO_PROD_TOOLB CORE Allegro Productivity toolbox: Advanced Testpoint Check is not working
V# D+ m$ d2 P" `1 F/ O+ g; z1996008 APD 3D_CANVAS New 3D Canvas does not work in APD! {9 F; ], Q+ O' `; b- ^) G. {' t
1993698 APD SHAPE APD stops responding and database is corrupted on moving, deleting, or updating a symbol
& d7 F6 Y( `( ? D" P- h1999446 CAPTURE OTHER Update symbol database in Trial4 z( Q2 f- E' F- S- f: I
1962222 CONCEPT_HDL CORE Nested hierarchy block RefDes transfer issue: suffix added to RefDes6 t- p' k$ S4 h) i6 P
1964260 CONCEPT_HDL CORE RefDes not updated in a hierarchy block on repackaging release 16.6 design
8 m6 g# {6 l3 h$ B- k( T1972243 CONCEPT_HDL CORE Version filter does not work correctly
# Z+ |5 v- T' ?8 t# G4 A1 U/ w( w; _1993448 CONSTRAINT_MGR DATABASE CSet is duplicated with same name when modified in SigXplorer
7 n3 z0 V7 M: D8 q5 a/ H+ \. e1976148 CONSTRAINT_MGR INTERACTIV DRC worksheet in Allegro PCB Editor: 'Go to Source' flickers worksheet and does not switch% G' T T' ]: ~
1948372 CONSTRAINT_MGR UI_FORMS cmDiffUtility fails to compare and gives the message 'Failed to read the configuration file'+ u# i4 Q, a' }3 z% P
1961750 EAGLE_TRANSLATOR PCB_EDITOR Voids and some shapes of third-party board not translated correctly, Z ]( n8 H& J$ R6 L
1984569 FSP DECAP When a pin function is in an interface or custom connector is changed, decaps defined for the part is deleted
2 f9 H/ O! x# _, q8 L O5 _1984588 FSP DECAP FSP crashes when changing pin functions or bank settings for a connector T- Z. V# s' u
1984590 FSP DECAP FSP design fails to load if pins are defined with a pin function that is later changed in custom_connector.crf
9 v6 U; d' z8 @( q* a1985555 PCB_LIBRARIAN IMPORT_EXPORT JavaScript exceptions on opening libraries converted using con2cap; E- y8 C0 L" ^; S, n; e
1961944 PCB_LIBRARIAN SYMBOL_EDITOR Hide symbol outline in new Symbol Editor# J I8 s* v% M, r% c! k) O" l: y
1967532 PCB_LIBRARIAN VERIFICATION libimport fails with ERROR(SPDWPAR-102): Metadata has the ErrorStatus value set.. J2 W4 j- C, h% Q, k
1976965 PSPICE SIMULATOR PSpice 'Tools - Generate Report' not working in release 17.2-20167 Y8 G# D; s4 Q9 M/ A8 D
1982260 RF_PCB FE_IFF_IMPORT Unable to successfully pull in .IFF file created in ADS. c4 p9 B- Y2 [( B! Q3 o9 @, f
1981585 RF_PCB LIBRARY Cannot load RF symbol via2 into PCB Editor0 }' \5 Q: f7 {. o" {
1976845 SIG_EXPLORER OTHER CPW trace models do not solve in SigXplorer after changing some trace parameters
. d9 K0 W& I4 s1986466 SIG_INTEGRITY OTHER Delay in Relative Propagation Delay worksheet is displayed as a negative value
* l- `' B3 }( X; L o7 O1980264 SIP_LAYOUT INTERACTIVE SiP Layout crashes on running 'Manufacture - Documentation - Display Pin Text'
: [ ]( z u6 S1983381 SIP_LAYOUT REPORTS Incomplete Design Summary Report% z6 z0 o& Q' G7 U
2005709 SIP_LAYOUT SHAPE Dynamic shape voiding around same net cline segment: no property attached
- A3 B( }. S/ ^7 v8 `: R2008064 SIP_LAYOUT SHAPE Hotfix 048 (QIR 7): Shape creates void for same net cline, it should be shorted
$ X2 _& Y! V# J6 h9 C# E1980967 SYSTEM_CAPTURE CANVAS_EDIT System Capture does not reflect part symbol changes
. T! J0 }8 E/ r/ j1988928 SYSTEM_CAPTURE CANVAS_EDIT Changing version 2 of the resistor part makes the PART_NUMBER property visible& i% ^1 u; k" Z( M) k2 e: L
1990215 SYSTEM_CAPTURE CANVAS_EDIT Draw Multiple Bits: Bits do not follow mouse smoothly9 i* g, a" e$ V2 U
1972658 SYSTEM_CAPTURE EXPORT_PCB Modified injected properties do not get updated in the pstchip.dat file after running Part Manager and Export Physical
' V+ ?! S, c9 C% p3 Q0 U* T5 B1989421 SYSTEM_CAPTURE EXPORT_PCB Part Manager does not update the PTF values
( F# o2 L( r! A1992407 SYSTEM_CAPTURE PART_MANAGER Part Manager removes part properties and main window and details window updates are inconsistent
' e: q+ U3 J! f8 ^) h6 }; @2 u* F2 |) a) M9 H" l- H. h, L
0 v' ?' P: m7 |3 F$ `# y6 J M
Fixed CCRs: SPB 17.2 HF048
, V9 M5 E' K6 G4 l% o# y* Q9 }10-13-2018+ y, }% ?. u# D( t
========================================================================================================================================================) w( V' e3 _+ F( F+ _1 F: Q
CCRID Product ProductLevel2 Title
" p5 v. @: A9 u8 ]6 h========================================================================================================================================================- e# ~8 c- S' p4 U- J7 I* y) X
1913039 ADW ADWSERVER EDM Library Server exits with error message on starting library server service
+ G$ `: n/ X) A: f( x1709155 ADW COMPONENT_BRO Search query does not search for all the parts in the library
5 Y/ c" t% C, }/ w4 S5 s" L' I1827231 ADW COMPONENT_BRO Clicking the 'a' key in Part Manager launched from DE-HDL crashes DE-HDL ^' i6 g3 T2 y! u" S8 L) e( V
1903818 ADW COMPONENT_BRO Parts that have comment_body do not display version
& T: J }* z& ~( y* ]4 n1917961 ADW COMPONENT_BRO Component Browser PPL column values are truncated when selecting the top '*' filter
; n8 b; q2 M0 T: _/ b1938172 ADW COMPONENT_BRO Symbol version with COMMENT_BODY set to TRUE cannot be instantiated
; E& q* Z7 E/ Y' M u$ \6 E' K1914103 ADW CONF conf creates incorrect path in fetch_dump.ini when MLR is enabled.
. F4 {0 U- H! I5 o: [5 e/ J* Q$ q1911422 ADW DBADMIN RuleP101 - PACK_TYPE check against schematic model not working4 k M/ ~* [. f( I! e* q( ]
1926691 ADW DBEDITOR Adding a new classification and immediately trying to delete it results in errors
" c7 U$ `2 m3 j5 c. N1926694 ADW DBEDITOR Renaming a classification and then renaming it back to the original results in error
# N. k+ Z2 ?" [* L& y0 L9 J1934870 ADW DBEDITOR Adding a new classification and immediately trying to delete it results in errors
) a+ z. b4 D; l6 Y1872387 ADW DSN_MIGRATION Design Migration does not cache all used parts into flatlib/part_table.ptf2 ^3 _ q1 a; ^: k, L) h1 |
1254292 ADW FLOW_MGR Flow Manager Open Last Project should open last project closed
7 M+ d! O/ M& _+ L1281817 ADW FLOW_MGR '-proj' switch in 'pcbdw_fm' does not work; launches Flow Manager without loading any project D6 a6 D, L- K
1727286 ADW FLOW_MGR Product options for PCB SI and Power Integrity are incorrect in the flow and tool launchers
7 |- ?) T# L* e, m( n1875498 ADW FLOW_MGR EDM fails to open or becomes unresponsive.$ e( Y- F! ^; a) M2 K) v& ^9 W
1879386 ADW FLOW_MGR Unable to access COS with the default Firefox version in the 17.2 installation) c- k ~& n w& v. h$ M( l
1922541 ADW FLOW_MGR Warning message for unavailability of Java version appears on opening a project on Linux
& U Q' B# x' E) H1945451 ADW FLOW_MGR Checklist does not work with two-byte characters
8 g6 `9 l1 u8 z. X( B: u1956213 ADW FLOW_MGR Not able to invoke Flow Manager on the remote system
7 c! Z% j! D$ G" `* b1892285 ADW LIBDISTRIBUTI Symbol not consistently available in 16.6 ADW Library. F2 H5 w2 g2 W$ m3 d2 g j1 H
1961731 ADW LIBIMPORT libimport fails to create tar for two Capture models/ F/ D2 N& f$ q! k3 y
1836620 ADW LRM Library Revision Manager crashes on clicking Help1 L3 r- r- C' _& ?/ M( O. c1 L% W
1961845 ADW PART_BROWSER Error regarding environment variable, I( ^7 u8 [' N0 C" L' @
1890782 ADW TDA Launching TDO dashboard connected to PLM returns a license error
# r/ E. b5 ] n. f1980914 ADW TDA Cannot start Design Entry HDL and Component Browser in a TDO design
) f7 U9 L! O. r. r) U: x5 E8 D1833750 ALLEGRO_EDITOR 3D_CANVAS Soldermask Text is not shown in 3D Canvas$ m0 F7 _: T/ L! L* I* J, I
1891230 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas Viewer not bending PCB with proper radius- a6 G: o& T/ p+ A3 j. l& ?6 w6 n
1913338 ALLEGRO_EDITOR 3D_CANVAS STEP models missing from exported .stp file
9 r% R# {, @0 g$ c$ o0 s1927507 ALLEGRO_EDITOR 3D_CANVAS Get Error: All bend operations are disabled due to licensing and/or DLL installation issues on invoking 3D Canvas
- b6 | L5 z9 D5 l1 ]7 ^1931508 ALLEGRO_EDITOR 3D_CANVAS Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas
$ o9 I( ^1 O- f# m7 l1943060 ALLEGRO_EDITOR 3D_CANVAS Placebound bottom is not showing correctly.
: ?# t, M: _# R% K9 d1950099 ALLEGRO_EDITOR 3D_CANVAS Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas: N2 W- H5 z { U
1988307 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation; Z- B6 y, u* x5 b( g/ N! s* a
1923585 ALLEGRO_EDITOR ARTWORK Additional unwanted subclasses appear in film control when a new film definition is added& m! M j5 U+ u. d' ~% } ^/ N: e
1944079 ALLEGRO_EDITOR COLOR Export of Board Parameters (Net Colors) does not contain entries for nets with spaces
# R# p5 |3 u* p( ?. e0 f/ v9 K1856320 ALLEGRO_EDITOR DATABASE Donut pad fails to connect with cross-hatched shape in full contact thermal mode, despite hatch overlap of donut.
7 b2 f- C$ s7 Q1912313 ALLEGRO_EDITOR DATABASE Database corrupted during background process
4 A8 J3 N* G% B( _- r7 @: o1913344 ALLEGRO_EDITOR DATABASE When changing accuracy of design, the thermal relief for donut pad's outer pad connects to inner pad
5 O$ d& m$ @; s& b2 P1914470 ALLEGRO_EDITOR DATABASE Release 17.2-2016: export libraries command does not inherit posi/nega information% V) p8 O6 r0 Z+ i* f
1932086 ALLEGRO_EDITOR DATABASE Unable to resolve DBDoctor error$ s4 r) n) w8 Z, w- e( X& x" P
1963932 ALLEGRO_EDITOR DATABASE DB Doctor is not recognizing placed parts and showing them as unplaced.
. P$ o- U" T, Q. ~1987735 ALLEGRO_EDITOR DATABASE Interior sub-lamination backdrill holes are displayed with Top Soldermask pads where backdrill does not exist
: l4 |5 b2 ]9 G' `: b. M1977622 ALLEGRO_EDITOR DFM Not able to add value '5' or multiples of 5 in in DFF constraints for maximum stacked via count$ }' V1 _5 y1 B# V
1892809 ALLEGRO_EDITOR DRC_CONSTR NODRC_ETCH_OUTSIDE_KEEPIN property is not working on TEXT
$ } K$ [$ l& p5 K) K* ]! S1894765 ALLEGRO_EDITOR DRC_CONSTR DRC for no_drc_component_board_overlap is not created if the place bound is outside Place Keepin, W C$ ?% H: K" |
1896627 ALLEGRO_EDITOR DRC_CONSTR Moving components takes long time while doing placement; N; D4 w8 h' l( u& b
1914591 ALLEGRO_EDITOR DRC_CONSTR Spacing constraints for Mechanical to Hole shows resolved constraints different from the actual air-gap/space) y- M4 N( S) o
1956468 ALLEGRO_EDITOR DRC_CONSTR DRC getting generated while moving the uvia and getting removed after updating DRC.
m) N1 Z! K7 c1884149 ALLEGRO_EDITOR EDIT_ETCH Arced Routing of differential pair creates unexpected arc radii, }, g# [: q' n4 y/ r4 P& t
1891985 ALLEGRO_EDITOR EDIT_ETCH Etch edit does not follow the constraints" J) _+ t0 k3 W; t: C5 a9 X
1860056 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes on right-click after choosing the Move command2 L7 I" b3 d! J1 b7 L* K
1860723 ALLEGRO_EDITOR GRAPHICS APD crashes on right-click when using the Move command7 N1 H8 t9 [! d& I5 ^
1870058 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes when using Place Manual -H command
/ z7 U5 S2 |! O! }; |6 P8 ]. Y1930282 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes on executing axlVisibleDesign(nil) from allegro.ilinit
! _0 u! }8 Y5 S, V' s1882813 ALLEGRO_EDITOR INTERACTIV Unable to set the end point with 'snap pick to' when adding an arc" [+ i) _) y0 l& H7 }6 p, t: E
1884725 ALLEGRO_EDITOR INTERACTIV Edit and Move vertex operation not working as desired
' \4 k; {% m+ n3 ?, [% m4 k9 c1902359 ALLEGRO_EDITOR INTERACTIV Connector boundary remains ON for a layer if visibility toggles in Shape Edit application mode- ?* A& Q w8 F; _; K1 T
1909004 ALLEGRO_EDITOR INTERACTIV Parameter description showing wrong for Padless Holes under Design Parameter Editor
7 f8 T6 y( @) [" r8 e) o- ?1912055 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes on Delete By Query - AutoSilkscreen - Find By Query3 H, y1 i" z2 P0 ?- U" ~
1924503 ALLEGRO_EDITOR INTERACTIV Editing shape causes PCB Editor to crash# @* a2 j. ^& [
1929614 ALLEGRO_EDITOR INTERACTIV Unable to Place Via Array when Staggered ring is selected in Global Ring Parameters.
% P+ |0 r# w7 v- q0 j8 \1938523 ALLEGRO_EDITOR INTERACTIV Change Shape Type message is same for dynamic and static shapes
5 h+ e+ C' }" d0 A1940827 ALLEGRO_EDITOR INTERACTIV Irrelevant/incorrect warning message when doing Edit- Change on Clines+ _, Y3 G, X% Q0 G$ c
1872653 ALLEGRO_EDITOR INTERFACES DXF export shows embedded layers in the layer configuration file
: B" M9 ^4 C4 G! }+ O4 z5 Y) w1873971 ALLEGRO_EDITOR INTERFACES IDX proposal comments are not shown when importing the IDX file into Allegro2 d8 h7 Z( }7 U: K# i- o
1892172 ALLEGRO_EDITOR INTERFACES STEP Package Mapping form needs to be larger% f" B5 g+ U/ C, T7 p+ U% Q
1893311 ALLEGRO_EDITOR INTERFACES A line became two lines after import dxf
1 E" ^0 ]3 `* `" X# f1 ]- c1937816 ALLEGRO_EDITOR INTERFACES Unit as % in Property Definition not supported by SubDrawing
+ [% E- o' p9 i8 f' _1973084 ALLEGRO_EDITOR INTERFACES Physical library not placed if design and IDF database not matched while running- S# U! v k. a( u' v3 J
1987526 ALLEGRO_EDITOR INTERFACES IDX import Fails to recognize SURFACE FINISHES Class/ {2 X2 F, C+ ?3 A9 N: @% t* l
1872856 ALLEGRO_EDITOR IN_DESIGN_ANA Message displayed when creating directed groups needs to be improved# \& F. o7 S, [: @0 {
1900832 ALLEGRO_EDITOR IN_DESIGN_ANA RTP: Return Path DRC does not check circle void correctly
3 E* h" F6 u4 K* j3 f8 o1935641 ALLEGRO_EDITOR IN_DESIGN_ANA Return path DRC crashes PCB Editor
( @$ ^$ Y& b& {. o3 s" x6 b$ i" R1649465 ALLEGRO_EDITOR MANUFACT Manufacturing options are not visible in OrCAD PCB Designer legacy menu
# u5 B6 C& Z& x( K1873417 ALLEGRO_EDITOR MANUFACT Autosilk fails to add line information. Only part of the line is getting copied to the autosilk layer.4 U4 Q+ z7 u0 I0 @' }3 A
1911596 ALLEGRO_EDITOR MANUFACT Documentation Editor drill chart shows two different rows for the same slot.* G6 a3 k, Q; w* S8 J& k+ A$ q& u
1937721 ALLEGRO_EDITOR MANUFACT Drill figure character scaled up in GERBER8 O: A6 O' c" M" V6 E" {- ^4 A
1957768 ALLEGRO_EDITOR MANUFACT Import IPC2581 on cross-section does not import line width and impedance
! }. T% J R# y' _8 Z1969363 ALLEGRO_EDITOR MANUFACT Pressfit connector backdrill depth is considering MNC Layer
& Y& n9 w. L8 c: ]/ g3 E1891102 ALLEGRO_EDITOR MULTI_USER Rejected by server error messages when using Symphony Team Design
! L/ i# t% a6 p. k. G$ s! k% T* ~1928082 ALLEGRO_EDITOR MULTI_USER Unknown SubClass BOUNDARY/MULTI_USER_LOCK automatically added when defining Artwork Output.
7 ]) J6 N" Q; ~9 t7 t7 l3 F1976705 ALLEGRO_EDITOR MULTI_USER Symphony client disconnects from server without any notification - despite ping mechanism5 ]% R, k: h$ l) E# V3 T7 I
1972554 ALLEGRO_EDITOR NC Mill symbol moved from Nclegend-slots-1-2 to Nclegend-1-2 subclass if nc_param.txt not present* l* @+ N4 ~2 W1 S* e6 x: |
1914412 ALLEGRO_EDITOR OTHER Autosilk lines do not clear padstacks that are not rectangular
! e% M/ J6 d% c: K( [/ w1921933 ALLEGRO_EDITOR PAD_EDITOR column clearance cannot reset to 0 in padstack editor8 i& J; j& B1 D4 M% V8 [7 C+ b" |3 T
1922234 ALLEGRO_EDITOR PAD_EDITOR DBDoctor reports 'illegal value for pad' and does not fix when zero corner radius for Rounded Rectangle is defined
, u# T3 u! f U5 z. ~3 l1932183 ALLEGRO_EDITOR PAD_EDITOR Drill Symbol information not exported in Padstack XML if Drill Figure in none# a/ L k4 {0 O. z
1934880 ALLEGRO_EDITOR PAD_EDITOR Shapes with offsets not displaying properly in Padstack Editor views! {% m3 U6 [# f5 J! S3 W( R
1813270 ALLEGRO_EDITOR PLACEMENT When a place replicate module is updated, the vias used in thermal pad are removed# B4 i& K' W# v( g/ e
1840275 ALLEGRO_EDITOR PLACEMENT Placing component with the Mirror option causing display problems# a0 P( K+ J( T# @( [
1854099 ALLEGRO_EDITOR PLACEMENT Align components to zero spacing causing mirrored components to overlap8 `5 G( u# D! Q/ e; C! V p6 u$ a/ a
1854696 ALLEGRO_EDITOR PLACEMENT Pins shown incorrectly when the Alt Symbol and Mirror commands used consecutively
* k" [1 t* C. `1862863 ALLEGRO_EDITOR PLACEMENT Too many messages in the command window when symbol does not support mirroring# e' U/ a2 O6 R; A
1909857 ALLEGRO_EDITOR PLACEMENT Using Mirror with Alt Symbol placement displays incorrect graphics. E2 T" n4 `9 n' k) c% `
1917128 ALLEGRO_EDITOR PLACEMENT Place - Autoplace - Room when all the components of the room are placed on board causing crash+ U, S( c; j( |) e
1925144 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding on using the Autoplace - Room command8 ^. f- l! ?6 Z& P8 n* Z
1961509 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes on choosing Place - Autoplace -Room6 F! I1 E, d- ~6 Y4 [
1930669 ALLEGRO_EDITOR REPORTS Net 'VSS' not included in the Etch Length By Pin Pair Report3 F5 l: @2 ]3 K( |( |+ Z: l* X; d `. `
1982934 ALLEGRO_EDITOR SCRIPTS PCB Editor stops responding if Generate button is used to create script from journal file2 m- k; l0 i/ w; V _' ~( r+ R9 G
1337346 ALLEGRO_EDITOR SHAPE Shape Check is generating problem point errors that seem unnecessary- Z. S& ^- ^+ n( ]2 u7 @
1396692 ALLEGRO_EDITOR SHAPE Zcopy with expansion not following board outline
* t/ c( G, h5 J- d1902001 ALLEGRO_EDITOR SHAPE Shape behaving differently across hotfixes
5 Z5 z3 w: d6 U4 l1921287 ALLEGRO_EDITOR SHAPE 3D canvas is showing some stray objects' W8 C$ U3 c0 L- G' \
1936482 ALLEGRO_EDITOR SHAPE Option for Fillet to not obey NO_SHAPE_CONNECT Property( R# }' r; p( I9 S3 K( J
1943899 ALLEGRO_EDITOR SHAPE Only one Shape to Route Keep In DRC in release 17.2-2016 compared to two in release 16.6
: ^0 Y. q8 S" F- w" h8 m1944041 ALLEGRO_EDITOR SHAPE shape_rki_autoclip makes shape voiding incorrect6 V! _) e5 F, U4 i/ m u6 c
1947675 ALLEGRO_EDITOR SHAPE Shape void error when dv_squarecorners is enabled
; w$ S' J8 h/ g" J+ R. L1949250 ALLEGRO_EDITOR SHAPE Shapes are filled even after raising and lowering priority
- p( ^" W) b! F' v1984526 ALLEGRO_EDITOR SHAPE Same net shape voided is inconsistent with respect to vias0 G; t# k4 |) X
1984955 ALLEGRO_EDITOR SHAPE Dynamic shape creating same net spacing drcs.
9 P1 `% p# {3 t6 X$ t0 v3 ~1839147 ALLEGRO_EDITOR SKILL axlDBGetLength() reports that the segments of a filled rectangle shape are invalid database ID arguments- T B7 l% y! f$ N
1882776 ALLEGRO_EDITOR SKILL SKILL documentation for axlIsBetween() is wrong
, R7 s& G4 z5 y, u: T0 C1882882 ALLEGRO_EDITOR SKILL Example for axlMathConstants needs correction in Allegro SKILL Reference1 R$ X4 f E1 W; o0 ]( p1 R' Q
1902712 ALLEGRO_EDITOR SKILL axlAltSymbolReplace moves symbol to the top of design while replacing
z) { a) V$ W1906329 ALLEGRO_EDITOR SYMBOL Mechanical Pin to Conductor property set on a pin in a symbol does not pass to the board4 F) d3 [8 m6 S6 r8 {! ~& }4 b
1911343 ALLEGRO_EDITOR UI_FORMS Global Visibility not turning all layers off
7 G! U: _# p! g a" m1985584 ALLEGRO_EDITOR UI_FORMS Import logic changes the Current Working Directory' Z3 X1 a! o& ^3 J7 R
1987829 ALLEGRO_EDITOR UI_FORMS Import logic changes the current working directory
7 ^" h0 |0 K, x) A; J+ I7 ]/ r0 V% i1 I! n1992722 ALLEGRO_EDITOR UI_FORMS After netlist import process, the board file is changing its current path. J( Z0 b+ L; H, O% Q7 `8 n
1697506 ALLEGRO_EDITOR UI_GENERAL Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-2016; [5 e8 I: n3 `5 n. j
1702631 ALLEGRO_EDITOR UI_GENERAL Etch Length by Net report does not list correct net name for nets in a bus+ [( Z# I- S( k3 }( ]# S- Y) y% L
1703105 ALLEGRO_EDITOR UI_GENERAL Bus net names are incorrect in reports when using the allegro_html_qt variable+ q4 e7 M8 w& V& g0 D+ U, Z
1770786 ALLEGRO_EDITOR UI_GENERAL Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-2016. {! Q; M: F% U+ }& C- B, T
1784938 ALLEGRO_EDITOR UI_GENERAL Etch Length by Net report does not show net names with angle brackets in release 17.2-20166 L0 g# Q# w0 z/ H& Y- ]) ~ M
1822557 ALLEGRO_EDITOR UI_GENERAL axlUIWCloseAll is not closing text window in release 17.2-2016
; k8 A7 i7 y+ G, h1836400 ALLEGRO_EDITOR UI_GENERAL Net names are truncated in HTML reports
7 p, ?% k' v* h0 o# `: e, b1869879 ALLEGRO_EDITOR UI_GENERAL Links not working in the Net loop report
2 W Q8 o7 S' {6 P1 X f3 `1895878 ALLEGRO_EDITOR UI_GENERAL axlUIWClose()/axlUIWCloseAll() functions do not work when allegro_html_qt setting is enabled.
* s. r+ i9 h8 K3 B; u u1912282 ALLEGRO_EDITOR UI_GENERAL PCB Editor exits with error message on editing objects0 k5 S5 @9 T; k* E8 J3 h
1913962 ALLEGRO_EDITOR UI_GENERAL PCB Editor toolbars change on choosing View - UI Settings - Save Settings and then restarting
" D" i- w1 D) A; ]3 j' i6 {( v1933172 APD UI_GENERAL Cannot paste text into the command prompt without clicking when 'enable_command_window_history' is set, a& z! c( n& R0 I! U
1843712 CAPTURE NETGROUPS Signals shown only for first segment of NetGroup! @, V4 N& R* M u+ j1 ~
1917768 CAPTURE NEW_SYM_EDITO Missing package pin overview in Symbol editor( L6 n6 o3 P' k5 W; e$ w
1920088 CAPTURE NEW_SYM_EDITO Package view missing in the new Symbol Editor5 Y- y; }9 o6 J8 O
1922196 CAPTURE NEW_SYM_EDITO Snap to grid issue in Symbol editor
5 j" W# u) ^ E) K1927268 CAPTURE NEW_SYM_EDITO View Package is grayed out in release 17.2-2016, hotfix 038 and later versions; a" w z9 Q+ I+ d& Q, r! Q
1928012 CAPTURE NEW_SYM_EDITO In new Symbol Editor, View - Package is grayed out
! ?9 ^( }/ ^- j$ j' `! B1930865 CAPTURE NEW_SYM_EDITO View Package missing in hotfix 038
, F% B" O9 r4 i9 F+ r$ c8 H7 D+ z1938507 CAPTURE NEW_SYM_EDITO Issues with new Symbol Editor: Justification and spreadsheet usability
' r9 G. L# G/ R3 n5 _- J+ q1940869 CAPTURE NEW_SYM_EDITO Missing pins in 'Edit Pins of All Section' table view for 4k resolution but not in 2k resolution+ n8 x6 Y, O! {7 j) O+ \$ q! G! f( T
1940888 CAPTURE NEW_SYM_EDITO Copying pins from a part and pasting on different parts not working properly.
% e) L# U- y9 w3 ?5 j5 F6 D9 p, t1942994 CAPTURE NEW_SYM_EDITO Cut / Paste of object in New Part / Symbol editor always pastes on grid4 U5 i6 B3 U$ F0 r) h( _
1944396 CAPTURE NEW_SYM_EDITO JavaScript error while copying from 'Edit Pins of All Sections'
/ v3 q1 |" A V( i( I/ [; I& Z1950224 CAPTURE NEW_SYM_EDITO Cyrillic alphabets are not displayed properly on Schematic.
: |9 f3 }$ C0 m4 ]+ F* e- J1951369 CAPTURE NEW_SYM_EDITO Cancel closes Symbol Editor, c5 Y0 G0 d$ x! y* H
1966785 CAPTURE NEW_SYM_EDITO Edit Part is grayed out
0 v) D. z3 D% Y# ]- ? N ~8 n1973135 CAPTURE NEW_SYM_EDITO Issue with new Symbol Editor: cannot copy-paste pins
" @5 d/ m: I/ _5 T. U2 H1973344 CAPTURE NEW_SYM_EDITO JavaScript error on opening part from design! J% r+ s- k2 q$ x7 t4 I
1974122 CAPTURE NEW_SYM_EDITO Cannot copy-paste all pin list on the new Symbol Editor
2 Q3 H, ]8 x* m+ p( _1983593 CAPTURE NEW_SYM_EDITO Script error on copying and pasting to property sheet4 i5 @" f( P) p$ i# I+ C8 J8 y
1929692 CAPTURE OPTIONS PACK_SHORT issues with Pin Numbers that contain letters/alphabets; r* V! v3 `! ~! B
1876939 CAPTURE OTHER Incorrect Capture renaming error (ORCAP-1310)
6 b, C4 m' U# A" G' @1916090 CAPTURE OTHER Incorrect error message when 'save as' fails due to long directory path, j! }, V t) F" g1 m- p1 B
1921927 CAPTURE OTHER Two functions are mapped to Shift + R in OrCAD Capture in hotfix 038* ]( Y* I* [& t1 P7 o, L
1946453 CAPTURE OTHER Shift+R shortcut is assigned to two functions.( u9 s8 k2 p. r
1965456 CAPTURE OTHER Shortcut Shift + R is not opening the Independent Sources dialog box
$ N3 J0 A, `* _1968757 CAPTURE OTHER Close CIP is grayed when right-clicking on the tab in Capture.
: v0 U0 W* i( S7 B. x1938437 CAPTURE PART_EDITOR OrCAD Capture new Symbol Editor Pin Type missing in table: }3 O* P5 B" W
1906757 CAPTURE SCHEMATICS Intersheet reference is overlapping with the offpage connector name
/ I d3 Z9 J; `! {* l1867016 CAPTURE SCHEMATIC_EDI Part placeholders not being positioned when moved9 m- ?- M( Q& Z* d' a- e* t4 K' l
1932837 CAPTURE SCHEMATIC_EDI Parameters graphics are not correctly positioned- j& i& B: W& e4 S6 X3 I
1949518 CAPTURE SCHEMATIC_EDI Getting error when comparing designs
1 \: @* y- A$ `" x! @1967545 CAPTURE SCHEMATIC_EDI Only section A of heterogeneous part being placed and not sections B, C, or D/ T! D0 a! a! y* U2 Q
1933919 CIS DBC_CFG_WIZAR New CIS Configuration .dbc file created in release 17.2-2016 shows release 16.3
+ i" K. ~6 {% _( K. y! V+ y' Z* o1932550 CIS RELATIONAL_DB VIEW NAME in Relational Database configuration is not working as expected.
1 q3 a9 ?/ S8 c; [( p1832524 CONCEPT_HDL CHECKPLUS Default checkplus rules show body height of 0 (sym_2 of the attached cell). This causes the cell to fail verification." I$ q9 H& P5 R* f5 P3 R% e
1912023 CONCEPT_HDL CHECKPLUS signalWidth predicate does not recognize SIG[1..0] as bus.
. ]. v6 D7 r, G8 _" y1966120 CONCEPT_HDL COPY_PROJECT Copying release 17.2-2016 project results in message stating the project is of an older version
5 e! Q6 U9 F! w% L, S+ S+ F e1 Q1879425 CONCEPT_HDL CORE Adding signals with the right-click menu is not following the defined color scheme H) P1 ^; T- U: }; F/ V% V
1890542 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1911) when running export physical with backannotation
+ |; ]9 ?0 I% q% H" m5 u% n+ w1907684 CONCEPT_HDL CORE Moving symbol makes canvas unresponsive for a long time
- e$ x' }& `* ^1 r1920711 CONCEPT_HDL CORE Pin names changes when mirroring the swapped section.% G7 W" p) ~8 d/ K% P3 [
1931421 CONCEPT_HDL CORE On Linux, 'cpmaccess -read' returns incorrect value
* r4 Q/ _* {6 _, B$ G1931782 CONCEPT_HDL CORE Setting DONT_FORCE_ORIGIN_ONGRID to ON does not work for sig_name
" I% x" E% R6 V) a1 L: W1932433 CONCEPT_HDL CORE _movetogrid causes signal disconnection
! p! ]1 B9 c+ x3 r# A2 d1946993 CONCEPT_HDL CORE DE-HDL Part Manager fails to update parts on schematic if new KEY properties exist in PTF but not in schematic1 z. V' y1 f; V) [
1947029 CONCEPT_HDL CORE Design Entry HDL Font Support not working for signal rename
1 z8 ^8 N5 b( T1962865 CONCEPT_HDL CORE Schematic symbol creation with '-' as pin name not packaging
: \! N+ W- B$ e; Q" e! M$ s1966805 CONCEPT_HDL CORE Issues with packaging design containing cells named with a leading underscore
5 ~2 m y: Z% C& u% D1967760 CONCEPT_HDL CORE DE-HDL crashes on moving Net Group/Port in release 17.2-2016, hotfix 044
2 N3 S" L6 t, K; O1968282 CONCEPT_HDL CORE DE-HDL Part Manager fails to update parts on schematic when new KEY properties exist in PTF and not in schematic* E0 w3 ~) P" e9 {1 P+ m- ~
1972815 CONCEPT_HDL CORE Part Manager not updating missing key attributes from the ptf file by using 'Update instances' option
: Q7 O2 w. c* B5 _! j0 a- {/ N1887790 CONCEPT_HDL CREFER CRefer links not working in selected cpm file
+ [* E. Q) U9 v2 |. @1898535 CONCEPT_HDL INTERFACE_DES Global Navigation window does not reflect removal of a net on page2 that is part of a netgroup on page16 T: w. s6 ]% Y! _5 [1 l
1888048 CONCEPT_HDL PDF Japanese characters are not output correctly to PDF on Linux.) K7 N( P' t% A# i6 v
1937505 CONCEPT_HDL PDF Missing intersection dot in schematic PDF
% O) X2 V; F2 Q( u: \: J3 G: S1942486 CONSTRAINT_MGR CONCEPT_HDL CM crashes when you save after importing a TCF file6 w x8 r% ^9 v j7 a8 y
1983743 CONSTRAINT_MGR CONCEPT_HDL Region Class-Class members are being duplicated in CM in the current session3 M- f+ q1 o/ _# A3 Z# {3 h. X
1906573 CONSTRAINT_MGR ECS_APPLY Database corrupt and DBDoctor reports illegal database pointer error
; {- ]6 w3 E# K$ j C1913805 CONSTRAINT_MGR OTHER Setting environmental variable CM_PARTIAL_DCF in release 17.2-2016 causing crash, ^2 D* D3 M, v0 e0 X
1914813 CONSTRAINT_MGR OTHER C++ Runtime error and non-recoverable crash in class-class worksheet0 a6 F( d% E, B; E0 d" i
1920142 CONSTRAINT_MGR OTHER Xnet names are not consistent in the design
% H3 ~9 b8 v, j5 d4 r4 o ^1898549 CONSTRAINT_MGR SCHEM_FTB Importing netlist causing crash in release 17.2-2016, hotfix 036 R- Z% _8 s% n+ T6 z$ e. Z
1814851 CONSTRAINT_MGR UI_FORMS Field solver /DRC check running forever
! C3 Y5 E( s; [% L( e8 \! M! D1889862 CONSTRAINT_MGR UI_FORMS PCB Editor hangs while assigning net voltages in CM
% N9 C) }" \3 b* c5 [0 f/ F1965470 CONSTRAINT_MGR UI_FORMS Constraint Manager GUI Issue in release 17.2-2016, hotfix 039: Font size small and rows/columns in shrink mode
& o8 o# ?, C' I2 M# I& d0 ^1945406 ECW ADMINISTRATIO Tree view was not refreshed soon after changing the site permission.: ]4 A" D1 w3 J+ w
1826848 ECW METRICS SPDWECW-551 and SPDWECW-553 should be warnings, not errors
; I, p$ x' d( p1933373 ECW PROJECT_MANAG ecwbatch does not accept password and does not ignore invalid users
/ y. K$ g6 W1 Z1921502 F2B PACKAGERXL Errors on running Export Physical:SPCOPK-1138 and SPCOPK-1149& n/ q* A# a0 r+ K
1929846 F2B PACKAGERXL PackagerXL is still creating the pstcmbc.dat file on a release 16.6 design uprevved to release 17.2-2016; ^+ g' s% q) C6 o( k. B" `
1953780 F2B PACKAGERXL Updated subdesign package information not updated on the top-level design in the reuse flow0 M( a, S+ Q6 `! b/ G; F$ p
1971738 F2B PACKAGERXL Deleting blank space from pstxnet.dat file crashing DE-HDL+ j2 w, A: }7 |$ W! t* P' P8 H: c
1891002 INSTALLATION DOWNLOAD_MGR Issue with Download Manager (Change Preferences Option does not Work)
2 @# I0 y0 p, p6 I3 L8 `( _1972890 ORBITIO OTHER OrbitIO-APR failed to run if PCB design included
+ k+ a" `$ | }2 j3 N1954262 PCB_LIBRARIAN CORE Footprint model check in fails with verification checks failed error h$ k5 h N) X3 W# X% u' L6 p
1943656 PCB_LIBRARIAN GRAPHICAL_EDI Symbol Editor is blank if .ascii file is newer than .css file5 U# t) q+ ^! y3 I8 |
1897887 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Inconsistent symbol results when adding vector pins in Part Developer; ]' p! |( M5 Q r, _
1898003 PCB_LIBRARIAN SYMBOL_EDITOR Issue with Page Border Symbol0 p6 Z# B9 n3 W$ {" K0 \. u, {
1842007 PSPICE LIBRARIES Change required in swit_reg.lib
& W; ~0 F/ g* X, B1906922 PSPICE LIBRARIES Mismatch in mapping of IC pins in model and PSpice template for analog device AD8138
5 J i0 M7 a. V9 q3 p3 d1947586 PSPICE LIBRARIES Update the model AD8138/AD in ANLG_DEV.OLB
8 `! N6 }& y4 [1748470 PSPICE MATLAB PSpice displays an error when sending current in co-simulation
( m7 a# s- q: U$ q; H/ \1802455 PSPICE MATLAB Incorrect current direction for pins in SLPS flow) ~! L4 ^3 x7 H
1852811 PSPICE MATLAB ORPSIM-2604 being reported in SLPS simulation
3 t; q {( {9 ^1858716 PSPICE MATLAB Co-Simulation fails if 'RC' is used as reference of resistor
5 N z; ~: R8 ^& D1921641 PSPICE MODELEDITOR Model Editor in Client Server installation slow to invoke% G# w; T+ b3 D/ {! y
1922160 PSPICE MODELING_APPS New Capture Associate Symbol GUI not reading libraries0 ^+ ?5 I& p( J, D# ^7 w, ` C( b' o
1843698 PSPICE PROBE PSpice icons appear very small on a specific computer
8 v) a9 `* [4 ?' A1773841 PSPICE SIMULATOR orSimSetup64 crashes when running the simulation for attached design
" i- H5 @2 P* T4 {1 F8 J1816316 PSPICE SIMULATOR Simulation stuck; however, the status bar is correctly updated during Pseudo Transient Analysis
) U6 ~$ K: X( K6 D5 R* _1887119 SCM IMPORTS Cannot selectively update changes in VDD
; e C1 h2 b; s7 G" B3 Q3 @8 f1889362 SCM IMPORTS Cannot selectively update changes in Visual Design Differences l9 I0 f/ `" q7 I- z& Q; b
1958545 SCM SETUP Auto assign models does not work in SCM same way as in DE-HDL
+ K$ t- E, v; L( m( J {7 D5 K0 y4 D1988841 SIG_EXPLORER INTERACTIV SigXplorer stops responding or crashes in hotfix 047 when a design is saved
2 F- v# W- ]1 c/ ?8 k) h: s' V4 I* a1988943 SIG_EXPLORER INTERACTIV SigXplorer crashes on selecting Update Constraint Manager6 ?9 b/ Y$ j6 A2 V% U7 ?3 P
1991375 SIG_EXPLORER INTERACTIV SigXplorer crashes when clicking Save' t$ k. x7 ^& U# `6 c
1993749 SIG_EXPLORER INTERACTIV SigXplorer crashes on saving topology
! |9 C( c3 @$ L0 A8 _ n1969975 SIG_INTEGRITY GUI Model Browser edits model above the one that is selected
3 w" S! ^$ A. p" z1953184 SIP_LAYOUT IMPORT_DATA Sub Drawing not saving dashed lines2 O% Q4 m3 A) a& a# q- G* |
1913864 SIP_LAYOUT ORBITIO_IF SiP Layout design import results in wrong die rotation
" W5 h* c8 i! }1 K& i$ w1880237 SIP_LAYOUT PADSTACK_EDIT Background Window comes to the forefront when closing the Padstack editor
) }: w! }, ~1 C6 o1972560 SIP_LAYOUT STREAM_IF GDS Export fidelity issue: inverted arcs: [/ k f4 n- ]- M. a5 t3 p1 f
1920317 SIP_LAYOUT THIEVING Thieving pattern does not allow for OOPS operation& y9 k5 E; q5 d7 V8 h2 Z2 [
1909075 SYSTEMSI DOC SystemSI PBA channel and circuit simulations do not respond if bit pattern is 1s or 0s
/ T; h1 @( u7 k. v. n% u4 [9 [1916101 SYSTEMSI DOC Lack of stimulus in file causes Serial Link Analysis to become unresponsive8 m7 \3 V) V( v
1919562 SYSTEMSI ENG_PBA SystemSI generates wrong timing bathtub curves in channel simulations for write and read! P L1 d) o+ N* f% x
1964064 SYSTEMSI GUI_PBA Able to sweep AMI parameters in SSI-PBA
3 {) [, Z9 a8 x$ X. d4 C0 s: F1971266 SYSTEMSI GUI_PBA MCP header shows only 49 ckt nodes instead of 52 for s52p S-parameter file
4 C6 K( V8 ] A# y8 \; B1885625 SYSTEMSI GUI_SLA Manage AMI + DLL from Setup Analysis Window
! ^4 r: }" F( h% r6 `, e4 |! C1924382 SYSTEMSI GUI_SLA Data Rate field in SystemSI Stimulus property form is confusing for PAM4 operation
' l. n% f' O% j7 Z1982341 SYSTEM_CAPTURE CANVAS_EDIT Signal rename does not maintain new signal name value
6 o: o$ u" g: r n# Y4 P8 A1976857 SYSTEM_CAPTURE CONSTRAINT_MA System Capture-CM Match Group Creation is not updating correctly. s/ X7 Y" T# Z" K1 q( o8 ^
1929606 SYSTEM_CAPTURE DESIGN_CORRUP Opening design causes System Capture to crash
7 ?7 {6 |" H& O2 x' b" ^! G1914697 SYSTEM_CAPTURE DRC Overlapping component DRC does not work$ t) U9 E1 K8 @$ h
1973467 SYSTEM_CAPTURE IMPORT_PCB System Capture Import Physical shows many component and physical differences on a design that is synced up
2 _5 b. @ P6 A1962603 SYSTEM_CAPTURE NAVLINKS Ability to not underline hyperlinks for Navigation Link values
* \) g \" U& c( R: B1967639 SYSTEM_CAPTURE PART_MANAGER Part Manager does not open in System Capture for part property value changes even after setting the cpm directive.! \. C) O9 f$ l% W I
1964388 SYSTEM_CAPTURE SMART_PDF Some shapes are not visible in the smart PDF schematics
/ n. @( h# S7 T* k1976832 SYSTEM_CAPTURE TDO Rolling Back local lower-block requires check-out of higher-level packaged & variant views V8 M3 P5 t. Z# b
1976844 SYSTEM_CAPTURE TDO CM - TDO check-out dependencies are broken
2 G5 e" y* y4 j. K, R6 ~0 ?- T& M+ [6 g1976859 SYSTEM_CAPTURE TDO Variant Editor in System Capture -TDO allows to delete a variant without checking out variants view- y+ D/ d) o( X( Y
1839816 TDA CORE All the design objects are locked in the EDM dashboard after a DSFrame error
0 G2 w/ }2 T" G, |7 N) g4 }) t( n1889898 TDA CORE Cannot check in the top level of the project in TDO
3 q7 S; B Y' i( g# ]0 n( N1892411 TDA CORE Unable to undo the block checkout if something fails+ j. W3 J3 M' Y! _2 C- V: k' ~
1877757 TDA DEHDL Refresh Hierarchy does not show latest TDO lock/unlock status in DE-HDL, b5 p7 w( W) v m% j+ i
' J/ r4 Q ~' y( }! z* m
" A0 ]% O2 i* O2 RFixed CCRs: SPB 17.2 HF047: k9 ~0 p1 x- H+ F0 b
09-9-20189 X! \6 w9 S6 q7 l1 b; B
========================================================================================================================================================' ^0 J" I$ I5 W8 j( |- J
CCRID Product ProductLevel2 Title
# e* ?. T$ k! b6 P8 d: ? O7 j t========================================================================================================================================================
7 Z5 g9 C4 Y6 I8 M4 H! X* B; G1969527 ADW LIBIMPORT Getting java.lang.NullPointerException error on bulk import in hotfix 044
7 @' N- q# q- `- |1976219 ALLEGRO_EDITOR DATABASE .SAV file not created although message states it is created
- c! Q& i7 H% j$ Q3 @% e1968270 ALLEGRO_EDITOR DFM PCB Editor crashes when running DRC2 h1 ?' k/ t* T. S% d7 h
1978421 ALLEGRO_EDITOR DRC_CONSTR False DRCs between via and its fillet shown after editing shape boundary9 y0 c% {5 O# M8 y4 [4 Y# R$ `0 P
1966772 ALLEGRO_EDITOR PAD_EDITOR PCB Editor and DBDoctor crash on editing DRA file: Found bad pointer, run dbdoctor
: I) l5 A5 V% E0 @" r+ ?4 |1973866 ALLEGRO_EDITOR SHAPE PCB Editor crashes when deleting a group5 O1 o) C! W- J9 s; A
1818779 ALLEGRO_EDITOR UI_FORMS Dialog box goes behind main window on clicking PCB Editor canvas" O6 l+ L) f' f+ U2 C; D# Z
1880175 ALLEGRO_EDITOR UI_GENERAL Multiple sessions of PCB Editor gets mixed up in Linux in release 17.2-20166 u. z$ r0 [5 Q
1946027 ALLEGRO_EDITOR UI_GENERAL Arrow Keys in Canvas stop responding after changing the view.+ ? N" E& m4 }/ T: A
1967701 ALLEGRO_EDITOR UI_GENERAL Arrow Key panning does not work when third-party SKILL call is active
6 t$ k" D& m6 c1967706 ALLEGRO_EDITOR UI_GENERAL Observe Special Characters when command is run
$ M# P$ O5 ]% [% A0 b# q1971183 ALLEGRO_EDITOR UI_GENERAL Focus is lost from command line when Save icon is used1 U0 e2 F4 B. W
1971186 ALLEGRO_EDITOR UI_GENERAL Focus from Command line is lost when using CTRL + N
8 K) g5 J. i* G1971190 ALLEGRO_EDITOR UI_GENERAL Focus from Command line is lost when using CTRL + Alt
7 ?5 z6 R3 M6 _1971200 ALLEGRO_EDITOR UI_GENERAL Focus is lost in comand line when you save using command save" V! i+ V r8 Q* v0 C
1961833 APD SHAPE Crash when changing dimension of existing via padstack in the design
" h" ^2 k& V2 T5 p1968256 ASDA EXPORT_PCB SDA crashes directly after Export to PCB
0 u0 }0 u0 H" k* \. e/ m6 y6 I1970284 ASDA EXPORT_PCB Placing part crashes SDA
# g: C- ]/ E6 L5 P4 ?4 {2 h" {# p& T
# B) O y ]! o+ P0 \% w1 p" ^9 Z$ e7 r
Fixed CCRs: SPB 17.2 HF046, l% }$ B5 g0 c0 |
08-24-20188 R8 e0 I5 k- N: h
========================================================================================================================================================/ m, J& F: f7 O" ]& {
CCRID Product ProductLevel2 Title0 f x% n" ?. o( F2 ~
========================================================================================================================================================6 T$ H0 I7 `" p8 p! C9 n
1880800 ADW PART_BROWSER Server connection failure on a running SDA session.4 T( i3 E3 N* b& A* D) k' K9 U/ w- G
1880895 ADW PART_BROWSER NCB - components missing from the component browser, X, w5 x+ v" J
1962336 ALLEGRO_EDITOR INTERFACES Smart PDF shows both top and bottom probe layers for a film layer with only a single probe layer (top or bottom)
. Z" X- ?: _/ w; o9 @, Y6 I1955128 ALLEGRO_EDITOR MANUFACT Need to close PCB Editor to delete xsectionChart.log generated on placing a cross-section chart) n# H3 J" t: k) [
1969088 ALLEGRO_EDITOR SHAPE PCB Editor crashes on updating shapes to smooth
1 v6 @. T& D: s2 L" D! g f# c1963828 ASDA DESIGN_EXPLOR Unwired schematic block movement with text is not correct
; Y9 o. g6 w0 c p" P6 q1954426 ASDA OPEN_CLOSE_PR Double-clicking to paste a note crashes SDA) l6 P5 l9 F4 @! _7 l+ T& a% P
1965423 ASDA OPEN_CLOSE_PR Crash when working with notes in SDA- H! h% H9 P4 ^4 F
1960060 ASDA PART_MANAGER Original property differences not displayed in Part Manager on selecting a new part from CB and doing reset: M y! W6 ]9 `( m9 q
1960112 ASDA PART_MANAGER Part Manager incorrectly updating part property values8 C7 C/ g3 B( z0 d+ T) T
1955723 ASDA ROUTING Draw Multiple Bits misses bit 0 when in reverse order.
9 v# T# \" k) i# ~* F0 I# F1952963 CONCEPT_HDL CORE Variant Editor takes a long time to load5 A9 P' f9 C# w( L0 ^" B# j, N: f
1962568 CONCEPT_HDL CORE Directive DEHDL_BROWSER_FILEPATH does not work
# [; @6 w4 B9 r0 @: H% n1939192 PCB_LIBRARIAN SYMBOL_EDITOR pin_text size and location very different between DE-HDL and Symbol Editor resulting in text overlap
/ T$ I6 q) z8 s" k$ a7 g1952967 SCM OTHER Error while copying a release 17.2-2016 design: message says design created in release 16.3 or an earlier version
- m& C6 I" v6 r3 ^+ [1948999 SPIF OTHER Some place_keepout shapes and antipads not exported
' z0 c# m2 s' W6 [- Y
' j2 m: Y" {, e
/ U0 @$ B- z# L8 L3 `Fixed CCRs: SPB 17.2 HF0455 {6 }+ H4 }4 k2 j! d. M
08-10-2018- T) n" Q# N0 _4 Q& o
========================================================================================================================================================
- J: Y+ {7 O( x1 GCCRID Product ProductLevel2 Title" r+ W4 n: U+ \3 P
========================================================================================================================================================
6 x/ \7 d9 C8 T2 R8 ?; e1934956 ADW DBEDITOR Footprint missing from part in release 17.2-2016' [" A# Y0 I; G! A& i/ i5 V
1945005 ADW DSN_MIGRATION Right side of Migration dialog box is cut off
) ^! l1 Z' `" E& L* L1933245 ADW FLOW_MGR 'Open last Project' button should open the last opened project
7 I2 {1 R1 N+ @ b" E* c1953210 ADW LIBDISTRIBUTI Library Distribution is not distributing all symbols. No errors for the missing schematic models.2 N/ w9 @; i2 ?7 F
1953727 ADW LRM LRM missing two symbols when migrating from release 16.6 to 17.2-2016
* q8 U1 o3 ?. u T* i0 h; ~1952923 ALLEGRO_EDITOR DATABASE PCB Editor crashes on trying to delete layer' f1 P$ R9 T0 ~# @: |7 }/ j4 G% r/ i
1957171 ALLEGRO_EDITOR DATABASE Pastemask offset not working when creating a symbol that requires two top-paste masks
; v# n2 c0 B3 C: d. j L8 \' N) s. ^1960059 ALLEGRO_EDITOR DATABASE Stackup definition causes custom script to crash
- I! z# A6 b0 H$ g/ r. w, i1932864 ALLEGRO_EDITOR DFM Exporting DFM Constraints losing the association to design level3 P! ? K* V9 Y' @5 c- {, Z x
1957467 ALLEGRO_EDITOR EDIT_SHAPE Compose Shape copies lines to wrong subclass3 d- O/ g" e/ u
1938536 ALLEGRO_EDITOR GRAPHICS Multiple crashes on different boards after installing hotfix 040- B0 x3 Q) J- h1 h @: ]3 ~( n
1954075 ALLEGRO_EDITOR SHAPE Dynamic Crosshatch shapes should be clipped inside RKI if RKI Autoclip is enabled
" l- P) L( c- A, {% x1957803 ALLEGRO_EDITOR SHAPE Wrong dynamic shape status
2 v. c# D2 _4 _/ e; u1 h. J: {1949923 ALLEGRO_EDITOR UI_GENERAL Focus lost from command window when any command is active
- O+ G$ J/ F7 F0 K7 z, h0 E. e7 i9 n1963245 ALLEGRO_EDITOR UI_GENERAL Alias behaves as Funckey in release 17.2-2016, hotfix 0440 T5 u5 F# s b& @
1892126 ALLEGRO_PROD_TOOLB CORE Clines disappear and then reappear suddenly on using Route - Shield Generator
5 ^& B' N' i* K- C4 t4 l1931127 ALLEGRO_PROD_TOOLB CORE ZDRC not working for Xhatch Shape
/ ^# C) k/ @/ ~9 c' e. [4 y1932563 ALLEGRO_PROD_TOOLB CORE allegro_legacy_board_outline environment variable not set in PCB Design Compare.
0 k, P. M8 m2 D" i1929855 ALLEGRO_PROD_TOOLB OTHERS Outline not exported correctly for PCB design compare if Design_Outline and Cutout exist) T5 g2 L5 k5 j
1956494 APD DATABASE DBDoctor removes pads+ _# Z# O" ~5 e7 _& v) L
1956291 APD INTERACTIVE axlSpreadsheetSetStyleProp should accept 0 and 1 as Boolean values for protection style' A! e: h6 a# ^* D% b( \" D8 b
1960127 ASDA ARCHIVER Using the Tcl command 'archiveproject' crashes SDA
" C1 ?. o( ~: z4 @7 e$ ]$ C4 @* c1953718 ASDA CONSTRAINT_MA SDA Import Pin Delay fails with extra columns, does not explain why
# | W# ^. X& q. D1924498 CAPTURE SCHEMATIC_EDI Cannot place part 'B' for heterogeneous part if 'Preferences - Miscellaneous - Auto References' not set
; h2 x0 H- s0 W1 @5 H1927129 CAPTURE SCHEMATIC_EDI unable to place heterogeneous part section directly from place part window
+ W0 O/ j, {) a5 C. }: r% u' s1928255 CAPTURE SCHEMATIC_EDI Unable to place a specific section from Place Part! h* M- u) h& B3 k% f7 @7 L
1945207 CAPTURE SCHEMATIC_EDI Part selection pull-down reverts to part '1|A' when placing heterogeneous part
X/ O* t$ S; C& V9 ?* i1945661 CAPTURE SCHEMATIC_EDI Section drop-down in Place Part window is not working
& G% [$ e: N0 [1958121 CAPTURE SCHEMATIC_EDI Preview and placement of sections of Heterogeneous parts is not correct in New Symbol Editor7 [' z, T5 v- _) O1 p; v
1956535 CONCEPT_HDL CORE DE-HDL crashes on Import Pin Delay for a CSV file0 ]# D) {- K' o# Q4 q! v5 G# a. B
1960922 CONCEPT_HDL CORE DE-HDL crashes on moving netgroup on Windows 109 `6 K, [9 L+ F
1964016 CONCEPT_HDL CORE In DE-HDL moving around nets connected to Netgroups causes crash on Windows 10
" x( X% h; k ^* V* W% N+ T1907040 F2B PACKAGERXL Export Physical output board file name reverts to old when changing options( z; H, t9 \& w; [- e' Z6 d
1957862 ORBITIO ALLEGRO_SIP_I allegro2orbit failed to translate rounded rectangle padstack+ ~$ \# b0 W/ {! j2 y8 @* f
9 R9 y" F9 k6 h. |( q( O5 q9 ~) J
Fixed CCRs: SPB 17.2 HF044
' I- Y7 H$ n3 y. K/ f+ L% E' @07-27-20180 c% u9 j Q: d- W& G/ F% j" g+ [
========================================================================================================================================================9 w D+ W/ o( R( X: F
CCRID Product ProductLevel2 Title* u P6 A8 A X+ e F+ [8 ]
========================================================================================================================================================
! E% e- a+ V/ S1943727 ADW DBEDITOR EDM DBEditor: Cannot check in/out schematic model symbols with many linked parts1 D9 _( P: h8 U( W" P6 [) t
1800630 ADW FLOW_MGR Support spaces in design directory path on Windows, I0 |" B( J' y2 J
1951052 ADW LRM LRM stops responding on project update and removes parts from design; x) N$ l( `3 l
1891428 ADW PART_MANAGER Resistor turns into a capacitor when placed
$ z2 F2 i. l* o* w1945194 ALLEGRO_EDITOR 3D_CANVAS 3D Viewer crashes when opening from board file.% o4 p v# z, T @0 f m8 e8 x7 Y/ y7 X
1935558 ALLEGRO_EDITOR INTERFACES Exported STEP file missing components when viewed in free STEP viewer
+ B1 s7 W2 i* F& b4 x- M+ B; a. z! u1945640 ALLEGRO_EDITOR MULTI_USER Symphony client disconnects from server without any notification
4 n# P% X8 L0 E$ D \, x2 Q1948454 ALLEGRO_EDITOR MULTI_USER Window DRC stops responding when run in Symphony5 _$ l8 K. i3 r8 |) H+ J# a
1946619 ALLEGRO_EDITOR SHAPE Pin/via with suppressed pad on shape layer and thermal connection type of none should void to drill hole.
) {* O4 F2 d8 ?6 Q! @! L/ l1946708 ALLEGRO_EDITOR SHAPE Same net hole to shape voiding is incorrect./ w: |. w+ R' ?/ k0 Q% N0 ?. f$ ~0 g
1952213 ALLEGRO_EDITOR SHAPE Shape voiding from Thru Via when the via regular pad is not completely drilled out by Backdrill hole is not consistent' d! s& f' z3 F9 d1 ?
1889433 ALLEGRO_EDITOR UI_GENERAL Command window shows result at the end of a command rather than showing dynamic updates* H! [! s1 V# M% `2 [* C
1933503 ALLEGRO_EDITOR UI_GENERAL Extra click required to enable command window: o' Y' F P3 o ^1 @ K: u! f
1943692 ALLEGRO_EDITOR UI_GENERAL Funckey commands are not working
3 O2 W% [' X( b$ R1945914 ALLEGRO_EDITOR UI_GENERAL Mouse focus lost in the command console when doing an 'undo' from the toolbar icon9 l! O+ a9 D7 o3 |- D
1945920 ALLEGRO_EDITOR UI_GENERAL Focus lost from command window when the toolbar is used for any operation: b& F) _2 q# U5 ~) u( k
1949922 ALLEGRO_EDITOR UI_GENERAL Focus lost from command window after save or even autosave. e$ I5 y/ F4 p. N, A) \+ \, _. A
1947551 ALLEGRO_EDITOR WIREBOND PCB Editor crashes in wirebond edit mode
; o0 |0 c, D% w+ t1935722 ALLEGRO_PROD_TOOLB OTHERS Panelization: Cannot place parts after migrating design from release 16.6 to 17.2-2016
7 M5 U* m7 ~! K1951511 APD REPORTS The result of Metal Usage Report is incorrect.
9 [9 X% ?- W+ J4 H0 B0 `: O5 I* H# [1952942 ASDA GRAPHICS Need metric (mm) support in grids in SDA
) G( l& e4 d% e4 ] Z1948122 ASDA TDO If user ID has uppercase characters in teamassignmenttemplate.xml, TDO fails to join a project
% ?* o$ k& w3 i# d! W1 q1931199 CONCEPT_HDL COPY_PROJECT Stop hard coding Copy Project license inside EDM8 l$ c4 G' b3 f6 G$ ^* C; H
1938153 CONCEPT_HDL OTHER Component Browser stops responding on replacing and modifying components
8 z3 W% X* c4 ~) w- N3 J1770601 CONCEPT_HDL PDF Wire Pattern set to two-dot chain line not shown in PDF$ j9 \+ n4 z- Y7 } W% G ?
1791175 PCB_LIBRARIAN CORE Allow baseline of cells with pins at symbol origin: change error to warning
' G5 P) q" y. ?; N8 E1922238 PCB_LIBRARIAN CORE Unable to check in into EDM Server due to con2con error SPLBPD-323 - Origin on pin connection point1 F3 [: A- Q' k# [
1936812 PCB_LIBRARIAN GRAPHICAL_EDI New Symbol Editor: Wrong text being updated when editing text after copy and paste
6 C2 ^2 U$ {1 p% l7 W! {9 B+ q n$ H1804159 PCB_LIBRARIAN SYMBOL_EDITOR Copy and paste of pins in new symbol editor: issues with pin name, rotation, and move
8 s% m$ d& |0 l: W! {, y% l1927422 PCB_LIBRARIAN SYMBOL_EDITOR Symbol outline not updated correctly in the new default graphic editor in Part Developer release 17.2-2016
$ g2 E3 |4 ?' `$ i* o" f6 ~1939272 PCB_LIBRARIAN SYMBOL_EDITOR Symbol Editor changes origin to bottom left, outline to invisible, shows rectangle with center rectangle at new origin9 F4 v" D7 ^8 e3 p
1928076 RF_PCB DISCRETE_LIBX dlibx2iff does not work with managed libraries and library-level PTF1 G; e7 g# o p u2 t3 L8 F" m
1929574 RF_PCB DISCRETE_LIBX Discrete Library to third-party Translator does not populate the Available Parts section correctly
! M( } x A! r4 }8 Q3 R1850360 TDA CORE TDO crashes while changing the root design/ E* h8 e2 f `# _9 i
1934388 TDA SDA SDA TDO crashes on attempting to check in a 'New Block in Shared Area'
( I0 W3 f2 V2 q- P+ e. u3 a5 r0 l
8 n2 O" W3 q, X) ^ Q! \+ `' t( _' C/ ]) }8 j8 q2 e3 o
Fixed CCRs: SPB 17.2 HF043
( e( I/ z) T$ T07-13-20188 q& a2 d# {" c7 P& Z
========================================================================================================================================================
0 M3 H. f- F. |CCRID Product ProductLevel2 Title
6 N7 H: S9 {+ ^. ~========================================================================================================================================================
0 W9 \! [& W% l% P; `1935813 ADW DBEDITOR Auto merging of DE-HDL and Capture Classifications is not working& O+ d7 u- F+ i+ w
1935834 ADW DBEDITOR Some DE-HDL only classifications are removed during the CSV merge process of libimport
: z$ I J0 |* R4 v( o1941570 ALLEGRO_EDITOR DATABASE PCB Editor crashes or stops responding on performing 'Info' or 'edit properties' on select pins4 |6 M! L6 z0 _$ A% {! Y
1942536 ALLEGRO_EDITOR DATABASE Allegro PCB Editor fails to create backdrill plunges in Zone area& f0 Y/ {# D6 b( M/ l9 j
1925899 ALLEGRO_EDITOR DFM PCB Editor crashes when placing components in Hotfix 0395 P5 o& Q1 N1 {$ u
1943113 ALLEGRO_EDITOR DFM Restore normal move/slide via performance when annular ring checking is enabled.9 ]5 J8 W* F2 K$ l; F) N
1940939 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashed on running the Gloss - Line and via cleanup tool
, X( }4 `4 A' ?- M. \+ S. M1 r1937754 ALLEGRO_EDITOR GRAPHICS Text string disappears when selected during 'Edit - Text' if using PCB_CURSOR' F* j) }9 q7 y5 ]
1937056 ALLEGRO_EDITOR INTERFACES Cannot import IDX acceptance of third-party change to PCB Editor
' c, v Y8 U3 N' r# ?6 `( X1940197 ALLEGRO_EDITOR INTERFACES PCB Editor crashes when reading IDX file from third-party* K+ \2 Q9 k2 b& K* c f7 x
1940232 ALLEGRO_EDITOR IN_DESIGN_ANA PCB Editor crashes when running Return path DRC
: R. ]& ]7 H2 e; G; R1916921 ALLEGRO_EDITOR PLACEMENT Property Pin_Global_Fiducial not inherited from symbol into board4 t6 g* M6 g# w7 H$ ? |6 S* }
1862241 ALLEGRO_EDITOR REPORTS In 'Summary Drawing Report', the listed quantity for HDI vias is incorrect under Drilling Statistics
; ~/ L, F) K q6 B1 n1935448 ALLEGRO_EDITOR REPORTS Etch Detailed Length Report lists only one coordinate pair per trace- Y% S" U" m1 F5 x7 \ J# ~, c
1948322 ALLEGRO_EDITOR SHAPE Allegro hangs when axlPolyOperation api is called" G. g2 m, F/ E* ]. V$ G0 R
1795564 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, focus is lost from command window after right-click
7 E& g- u0 Q' o" @/ o+ X1919247 ALLEGRO_EDITOR UI_GENERAL Infinite cursor graphics issues on move: Cursor disappears and symbol image remains at old location till refresh
3 ]% i. `* f& S1919256 ALLEGRO_EDITOR UI_GENERAL Infinite cursor graphics issue: Symbol disappears during rotate' {' q+ M1 a' v: O/ n
1933526 ALLEGRO_EDITOR UI_GENERAL Panning is slow in PCB Editor in Hotfix 038
7 F/ m. H% H$ v$ d. L1933530 ALLEGRO_EDITOR UI_GENERAL Strokes are slower to respond in release 17.2-2016" U* ]5 }1 ?% b! h
1933536 ALLEGRO_EDITOR UI_GENERAL Third-party dialog stops responding on running commands
- E s! o$ Q7 f1 j& S! E% a1782227 APD DIE_GENERATOR Ability to specify rectangular shapes in die text in
. R6 o: {0 S! u8 g& l1933011 ASDA PART_MANAGER Parts changed in library with new pin names are not reported or updated by Part Manager
7 E$ g$ y; r( q0 t# ], X1924529 CAPTURE NEW_SYM_EDITO Global colors for pin name and number and part body not allowed in release 17.2-2016, Hotfix 038/039
6 a4 ?3 }6 b& T/ N+ v" S2 o1925846 CAPTURE NEW_SYM_EDITO Opening library or component with special characters in path throws JavaScript exception: [& j. U6 K. Y. b3 M) I% D" H
1928905 CAPTURE NEW_SYM_EDITO Pin name justification, length, and casing incorrect for generated parts in Hotfix 0387 \8 e* Y" M# o4 O/ ]( T |( l) `
1928965 CAPTURE NEW_SYM_EDITO Cannot move pins in Capture if Pin Name is missing
& T, Z0 }4 g1 X/ Z6 G1932149 CAPTURE NEW_SYM_EDITO JavaScript exception if path to part contains special characters in Hotfix 039/ }& r) I4 D. S+ R- Q
1936301 CAPTURE NEW_SYM_EDITO Cannot edit symbol in new symbol editor: Displays parsing error (SPSMI-1) P5 k; ~! w( Y
1917172 CAPTURE PART_EDITOR Pin name rotating on schematic even when pin name rotate is off in symbol editor
1 W1 Q, [8 c- v/ a1924456 CAPTURE PART_EDITOR Color preferences for pin, pin name, and pin number do not apply in part editor but only in schematic7 S$ L! }6 u7 _- z X
1928872 CAPTURE PART_EDITOR Pin name locations are wrong and each needs to be placed manually
5 m. c4 t) u$ U- z' ?" L# r1929562 CAPTURE PART_EDITOR Changing pin name while adding a pin not intuitive in Symbol Editor* A p& O$ q2 f! \: F! x2 ], O
1932732 CAPTURE PART_EDITOR Part Editor issue: Pin name selection box too long and text not justified in Hotfix 040
& p/ b; j4 i+ f" O8 h0 l1933523 CAPTURE PART_EDITOR Connection box does not appear after changing pin of a placed part in Hotfix 040
* y: [# W* X8 O1936994 CAPTURE PART_EDITOR Error because of illegal characters in pin name and number and net name, Q5 g+ J3 J; z- X' \. n
1943074 CAPTURE PART_EDITOR Pin names rotated in Part Editor not rotated when placed on page2 X5 }# z1 S) ^. u! J/ Z0 E
1943078 CAPTURE PART_EDITOR Pin name rotate not working.
1 x% K$ B( [/ D6 W( F1945055 CAPTURE PART_EDITOR Pin names not rotated in schematic; |. h: ~3 L+ x
1925700 CAPTURE VIEWER Pin numbers and text not shown during Variant View mode anymore.' U& s$ H9 u( c& O" _. ^/ \
1914437 CONSTRAINT_MGR CONCEPT_HDL Constraint Difference Report appears even though there is no difference in constraint.
7 ?( `% @2 n4 M+ c" {1935152 CONSTRAINT_MGR CONCEPT_HDL Match Groups are not formed with the correct pin pairs0 F3 D. ~8 s6 Q# i% H) ?
1940575 SIP_LAYOUT ORBITIO_IF Need new routing flow @0 r0 w; Z6 P& \
1923722 SIP_LAYOUT STREAM_IF Use one symbol for all instances of a Via Structure
7 O: `2 m! {1 U" t9 e t9 f' b, b* q' _; K3 Q7 Z5 X D' u$ c0 s; _
- ]& ]( W% t" |( K, k) w/ P J7 P3 f
Fixed CCRs: SPB 17.2 HF042; G1 T0 }: ` e" U4 |6 Z& A
06-22-2018
, J; \6 d% q! M========================================================================================================================================================
( j Y1 Q6 d* \0 i1 w x5 iCCRID Product ProductLevel2 Title( s8 I. Z4 T4 G
========================================================================================================================================================
7 i' K; F/ U5 z! X1922654 ALLEGRO_EDITOR ARTWORK Difference in board and Gerber display
, T* Y8 M0 }0 `1932714 ALLEGRO_EDITOR COLOR Manufacturing subclass NCDRILL_FIGURE missing from Color Dialog when editing .dra file6 u* a2 F" k( \7 A
1932316 ALLEGRO_EDITOR DFM DFM constraint reporting wrong DRC between backdrill via hole to shape clearance under copper spacing: g' D' ^4 H9 s+ F% y" H8 |$ y
1914334 ALLEGRO_EDITOR INTERFACES Design Compare does not import some netlists created using Export - Netlist with properties from PCB Editor
( \8 Z6 ^$ B. o/ x1910213 ALLEGRO_EDITOR MANUFACT OrCAD PCB Designer shows Backdrill Status in Check - Design Status
. e$ ^, \$ X: r" }6 W5 ~1933049 ALLEGRO_EDITOR MANUFACT NC Route seems to put all routed drills in the same .rou file regardless of what layer they are on.
7 K2 h; p; n! S: g/ v/ p1880576 ALLEGRO_EDITOR PLOTTING Extra lines appearing in plots that are mirrored
, G7 B, X0 S0 v: }; B1881031 ALLEGRO_EDITOR PLOTTING Plot Preview with the Mirror option in the Plot setup creates fancy lines on shapes# }1 `" O: T8 s! R' d
1908005 ALLEGRO_EDITOR PLOTTING Plotting with mirror options set results in strange lines on the plot9 j; O2 g' t- V
1909530 ALLEGRO_EDITOR PLOTTING Use mirror function when plotting lines to design* Y ~3 c6 C2 F( N* v
1919405 ALLEGRO_EDITOR PLOTTING Printing with the mirror option results in arcs in Print Preview
* |7 ^& g3 S E7 t1830419 ALLEGRO_EDITOR SCHEM_FTB Import Logic with 'Overwrite current constraints' deletes attributes from drawing
/ B1 q3 m/ U1 o8 M* o1935253 ALLEGRO_EDITOR SHAPE Compose shape command causes tool to stop responding
2 S+ l2 M; `% N- o, a6 e1571600 ALLEGRO_EDITOR UI_GENERAL File - Capture Canvas Image missing in release 17.2-20166 h3 a( P* ~8 Q+ O$ Q8 B S1 d8 D- a
1650403 ALLEGRO_EDITOR UI_GENERAL Include Capture Canvas Image command in Allegro PCB Editor release 17.2-2016- @- Q; U" _# G$ X6 }8 j
1710310 ALLEGRO_EDITOR UI_GENERAL 'Capture Canvas Image' command is absent from the file menu in PCB Editor in release 17.2-2016
; d& P+ R3 w" b! T, L& w1718407 ALLEGRO_EDITOR UI_GENERAL Reintroduce the Capture Canvas Image command- b+ Y% l1 I9 k! @, H
1729699 ALLEGRO_EDITOR UI_GENERAL Capture Canvas Image is not present in release 17.2-2016, S$ a5 p& M8 i9 T8 ~
1753234 ALLEGRO_EDITOR UI_GENERAL Capture Canvas Image missing from the File menu
3 F& _2 J& W3 J5 `+ ~1754222 ALLEGRO_EDITOR UI_GENERAL Need command to capture view window as image in release 17.2-2016+ ` e, x. o- [. y i
1794348 ALLEGRO_EDITOR UI_GENERAL Reintroduce Capture Canvas Image in PCB Editor in release 17.2-20160 l# p8 c# ]4 `$ R- G# K
1818610 ALLEGRO_EDITOR UI_GENERAL Restore the option to capture canvas image in PCB Editor in release 17.2-2016' D) p. r' T4 D8 w6 b
1844591 ALLEGRO_EDITOR UI_GENERAL Reintroduce 'Capture Canvas Image' in release 17.2-2016
9 r5 q2 x1 ]3 ^. K1 [4 ?1869380 ALLEGRO_EDITOR UI_GENERAL File - Capture Canvas Image missing in release 17.2-2016
[! ^" N+ O/ F5 b9 |1889412 ALLEGRO_EDITOR UI_GENERAL Cross-probing between two boards in release 17.2-2016# s- e0 Y9 s6 i2 V& b+ W
1922329 ALLEGRO_EDITOR UI_GENERAL Add the 'Capture Canvas Image' command in release 17.2-2016; {' A* [1 _6 d; m# R" x) d. p
1932070 ALLEGRO_EDITOR UI_GENERAL File - Capture Canvas Image is missing in release 17.2-2016
3 |9 E' Y e9 ]) d. e0 x7 c1885594 ASDA PACKAGER Export to PCB Layout exits without reporting error when Netrev fails
, ]5 q' R1 T# |; H1931657 ASDA PACKAGER Export to PCB Editor does not work for a project
& k" S; f! Y% F: B& m& P1937757 ECW METRICS SDA metrics not getting collected6 F# R) A8 x+ P( o3 o# X- A3 ^
1934482 EMI SETUP EMControl function flow is not working correctly in release 17.2-20161 _" h4 Z) | _5 _6 }4 ?: W6 y
1931623 SIP_LAYOUT EDIT_ETCH Shapes are not updated and force update does not work" b1 E8 v! D }1 R& z4 t7 u l
( } s' R- j' t# k
4 k3 T- g8 i u }- |Fixed CCRs: SPB 17.2 HF041
# U) `- }( o% {& v& @( O, r06-9-2018: B- `8 p0 p# u/ Z* h% b6 ^
======================================================================================================================================================== I, J) } Z2 ^* f
CCRID Product ProductLevel2 Title
Y4 Z4 f0 J3 v( ]- x7 J7 o========================================================================================================================================================
& F0 A& r) B7 T! G0 J6 w2 r: p1880083 ADW ADWSERVER ALM fails to connect and authenticate LDAP server
; P& {3 |1 g6 J" X4 C, N1922218 ALLEGRO_EDITOR 3D_CANVAS PCB Editor stops responding when 3D Canvas is opened for a symbol, X0 P5 U* Z8 x9 @- m h0 m
1915838 ALLEGRO_EDITOR DFM Outline to non-signal geometry is not working for non-etch layers in design
9 @3 M5 F# T$ L) Z1925263 ALLEGRO_EDITOR DFM False minimum spoke count DRC5 v* D2 ]5 o9 m+ o1 N$ B- _
1895486 ALLEGRO_EDITOR INTERFACES Importing IPF displays error regarding line being outside drawing extents (SPMHMF-409)
" B6 M$ j9 Q/ H ?1927266 ALLEGRO_EDITOR INTERFACES Miniaturization license required when using enterprise licenses
$ H" h. C: W# E1 Q) r1912186 ALLEGRO_EDITOR IN_DESIGN_ANA Coupling analysis on one net takes a long time
1 |/ o/ N0 C9 ?: n" }$ H1916015 ALLEGRO_EDITOR NC Improve the message for reporting unsupported characters in the directory path while generating NC Drill data
! r9 ^6 S1 B6 }/ x1926072 ALLEGRO_EDITOR SHAPE Dynamic shape to route keepout not voiding correctly
0 N$ Z* N- ^3 w. u! |: p! {9 l1903202 ALLEGRO_EDITOR UI_GENERAL HTML report dialog does not handle relative links to files correctly
$ \1 D* A" z0 F1 t1880684 ALTM_TRANSLATOR CAPTURE Importing third-party schematic is not working in Capture
+ P) J6 d; t8 t. v: Y( m* B: H1870218 ALTM_TRANSLATOR DE_HDL Unable to translate a third-party design to DE-HDL
. u6 M$ o4 Z) r: j9 p1 n1 L5 n6 p1881208 ALTM_TRANSLATOR DE_HDL Third-party to DE-HDL translation: schematic symbols missing all pins" _ J3 R; n# F/ W( v& i3 |) p
1889909 ALTM_TRANSLATOR DE_HDL Third-party to DE-HDL and OrCAD Capture translator fails with error message or crash1 s' f' j5 {: h @
1924375 ASDA NEW_PROJECT SDA new project path truncated at ellipses/ H4 @. Y# @, ~9 K
1900957 ASI_SI OTHER axlLicDefaultVersion() in SKILL console crashes PCB Editor in release 17.2-2016 and works in release 16.6
* [; n* |# t+ S1 Y" [8 S1918499 CAPTURE NEW_SYM_EDITO Text in new Part Editor is always left-justified and justification cannot be changed* d2 N u; A9 R# |4 @; r3 l
1921505 CAPTURE NEW_SYM_EDITO Error if property name starts with the less than character '<'8 B6 t' C$ J$ Z% T# I( C
1924273 CAPTURE NEW_SYM_EDITO Error if property name starts with the less than character '<', v% _, a% f& X$ n2 N) e$ g5 |
1924332 CAPTURE NEW_SYM_EDITO Capture reports an error when editing pin numbers where names contain the less than character '<'
' F( k& U, o1 d1934655 CAPTURE NEW_SYM_EDITO Properties populated in older release show up blank in new Symbol Editor8 M# H/ p {! R% g8 A! E j. O
1855851 CAPTURE OTHER Crystal Reports not working in release 17.2-2016 _* x. _. t' \" y
1918048 CAPTURE PART_EDITOR Unable to modify pin type and shapes for multiple pins simultaneously in new Part Editor3 M2 @: Q2 n- |6 w6 p
1919459 CAPTURE PART_EDITOR Part Editor background display color is not consistent when zoomed out/in; d# {3 n4 p1 F; J# K& l8 O
1920078 CAPTURE PART_EDITOR Option needed for updating pin type of multiple pins in the 'Edit all pins' menu- I9 F; R* @" h$ M. Y; d7 ?
1922785 CAPTURE PART_EDITOR Cannot place pin array with zero in the suffix in Symbol Editor
, M4 E7 N. g; O5 ^1922831 CAPTURE PART_EDITOR Symbol Editor redraws when scrolling with non-default background and when zoomed out
. O% t( R5 u& V0 Y8 S1923772 CAPTURE PART_EDITOR Placing pin arrays results in error g( ]( s5 | S7 l+ M
1888897 CAPTURE SCHEMATICS Capture slowly redraws schematic page
- f" }! a; _/ P1 E# d1910087 CONCEPT_HDL CORE DE-HDL crashes when adding Current Probe to a design/ p+ E& z3 W: a9 p# E
1930364 CONCEPT_HDL CORE SIGNAL_MODEL properties not deleted on importing release 16.6 DML design into release 17.2-2016 non-DML design
- b) y- l# _* s% e/ {1920716 CONSTRAINT_MGR CONCEPT_HDL Issue with the passing of physical and spacing CSets between Design Entry HDL and PCB Editor0 O7 e4 Y/ R$ D3 r' |/ x
1902591 ECW OTHER Flow Manager reports a digital certificate error when launched with Pulse
/ q* P) ]3 A" R2 B1926029 PCB_LIBRARIAN GRAPHICAL_EDI PDV Symbol Editor opens to a blank page in release 17.2-2016
& a2 E' |" X1 R1884694 PSPICE ENCRYPTION User-defined library encryption is not working as expected
) o1 a0 T; k* D$ S1927537 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes when running manufacturing checks on specific designs
1 ^# c9 Y3 \ d7 F0 ~ Q1878733 SIP_LAYOUT CROSS_SECTION Layer Function and Manufacture fields in Cross-section Editor are grayed out for soldermask layers in SiP Layout% v: ^: z. k; U+ w
1900628 SIP_LAYOUT CROSS_SECTION Board thickness in Cross-section Editor does not change even after soldermask layers are added
' J4 L. i8 o2 n6 P* {) `2 G
" g& H1 W) Y! \( @4 B; B
- N5 H9 ]+ |& w2 A0 qFixed CCRs: SPB 17.2 HF0402 I. G# {: R& R# L2 ^3 d
05-27-2018
# c# P% P' F5 [1 h9 @/ o9 i========================================================================================================================================================
# a! ]7 y* w( nCCRID Product ProductLevel2 Title, D: C, T+ B `" n* E( _. Y/ a
========================================================================================================================================================
, ^- J+ h; o7 H4 H1 u1924541 ADW CONF Designer Server configuration cannot be completed: \3 f- w* a9 J7 w. P: A
1906973 ADW DBEDITOR Rename attribute fails to preserve values in affected parts
w/ C7 m1 j, S6 e0 E a1718524 ADW FLOW_MGR FM: Find Projects does not find any projects when Project Path contains a period, p4 y. G1 ]; R" X# Z3 y
1803310 ADW FLOW_MGR EDM Find Project no longer supports dot in the project path0 E0 v8 t4 E; n7 `7 _" g$ n+ ^6 O1 s
1916898 ADW FLOW_MGR Flow Manager does not recognize projects with a dot in the path6 s% p; p9 K4 Y3 k2 m; V$ S/ E1 X
1887669 ADW LIBDISTRIBUTI ptfgen displaying Java errors
( K1 s, n3 Q6 w( E# ]2 A5 K1897991 ADW LIBDISTRIBUTI ptfgen fails with error LIBDIST-1062 in library distribution.$ C. V! `$ k3 Q" t" N" R" S" p: o% m. X
1915319 ADW LIBDISTRIBUTI ptfgen should rerun with the -rewrite2db option automatically
# @+ a# i7 s% h9 B8 R) p+ ?7 ~* f1920309 ADW LIBDISTRIBUTI Java exceptions in the ptfgen log file
t1 [1 ^, q1 z7 J+ S1914706 ALLEGRO_EDITOR DFM False Mask to trace DRCs! l! @& L1 D0 D. s
1912290 ALLEGRO_EDITOR GRAPHICS Infinite PCB cursor: symbol move results in symbol trail and disappearance of cursor and symbol S( \; C% s9 Z3 Z+ e8 n( ^
1927425 ALLEGRO_EDITOR GRAPHICS Infinite PCB Cursor disappear while moving objects on layout7 L# T2 ]; y1 q# ]- p
1908867 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes in release 17.2-2016, Hotfix 036 and 037
" A/ _3 |+ j3 ?3 L; z1906116 ALLEGRO_EDITOR IN_DESIGN_ANA Allegro Integrated Analysis and Checking: Coupling vision shows the influence of voltage net
( K1 w Y( y& C+ d1918161 ALLEGRO_EDITOR MULTI_USER Symphony crashing and clients disconnecting from server cannot leave session, error applying DBupdate
# F' b# A# T; I7 y1919467 ALLEGRO_EDITOR MULTI_USER Random crashes while routing design in Symphony+ k" Y" x5 K7 m) \- a$ n
1918702 ALLEGRO_EDITOR SHAPE Differential Pair vias not voided in a split plane
) \( N2 q; X% P" p6 ~1905109 ALLEGRO_EDITOR UI_GENERAL PCB Editor randomly stops responding in release 17.2-2016 in Linux4 {$ w7 p$ x8 f8 d$ S! {8 U' @
1882365 ASDA CANVAS_EDIT SDA - body changes but not properties when changing version of a symbol; c# d1 v# J- L+ G; Z1 m
1900370 ASDA CANVAS_EDIT Version command in SDA should use placeholders from selected version$ m5 `" i' F% S {; I$ `. k
1901120 ASDA CANVAS_EDIT Choosing a different version of a placed component does not use the property placeholders as per the new symbol
5 H# ?1 ~- C9 Z# K# t) ]1907497 ASDA GRAPHICS DNI Cross Mark much larger than Components8 y7 P2 y+ Q# J& I) `
1895135 ASDA MISCELLANEOUS Design created in SDA has the cds.lib containing a pointer to worklib+ v; k: U+ f9 e" j' ~* k( L
1895139 ASDA MISCELLANEOUS Irrelevant warning related to worklib when running checkplus on SDA design
2 N2 k2 [5 f* E1920753 CAPTURE LIBRARY JavaScript exception reported on opening part with name containing '\' in hotfix 0380 x: M) h% K/ a* ?8 u3 `! A7 o
1925848 CAPTURE LIBRARY New (QIR6) Symbol Editor has Script error / SR 600037969
" U; M0 r! }" Z' Z$ ^8 T! b1916991 CAPTURE NEW_SYM_EDITO New part/symbol editor ignores grid color set in Preferences( y% X; W; _5 F* j3 D1 `7 J0 r- e9 p
1917090 CAPTURE NEW_SYM_EDITO New symbol editor goes into permanent pan mode on clicking the middle mouse button
* c( ?; m( [2 k1918041 CAPTURE NEW_SYM_EDITO Saves As for symbol in library from new symbol editor saving 0 byte files, ^* M( R$ P4 p& v# _6 i) Z( @
1918497 CAPTURE NEW_SYM_EDITO Moving multiple items using the arrow keys results in error in new part editor& K" V7 ?: c4 u! ]' Z5 r
1918711 CAPTURE NEW_SYM_EDITO Unable to do a Save As from a Library part to change the name
9 R& m: i1 q+ K0 y1920889 CAPTURE NEW_SYM_EDITO Unable to edit symbol with name containing '/'9 [' J' k ?, z" `) {
1922123 CAPTURE NEW_SYM_EDITO Save As for symbol in library from new symbol editor saving 0 byte files
7 u) D, C1 @. Z$ y1922276 CAPTURE NEW_SYM_EDITO Space between pin name and pin for names having bar v( @; e3 A0 H4 T+ M' c
1922282 CAPTURE NEW_SYM_EDITO JavaScript exception on closing new part editor window using keyboard shortcuts
7 Y! d6 u) K3 ?# I' f1923526 CAPTURE NEW_SYM_EDITO Unable to "Save As" in new symbol editor./ [/ v! ]. M8 Y; q$ B0 q
1927262 CAPTURE NEW_SYM_EDITO The File > Save As command in version 17.2-s038 differs from earlier versions% t' p: Q% p" U
1919322 CAPTURE PART_EDITOR JavaScript exception on opening parts and creating new part using right-click+ D) P) Q! Q& J i
1914183 CONSTRAINT_MGR XNET_DIFFPAIR ECSet fails to map in PCB Editor but maps fine in DE-HDL
6 Q& y6 g1 P. K% f2 Z. }: s6 w& x1908102 ECW DASHBOARD Some lines in Design Dashboard in Pulse are grayed out
1 s U" N5 K' J( f- s1914812 F2B PACKAGERXL Hierarchical variable not evaluated
6 L' C) w n/ `7 ]9 ?" z- ?1639231 PSPICE ENVIRONMENT Remember last location in simulation settings
2 u' o/ J* i: |8 a$ g1804391 PSPICE ENVIRONMENT Libraries with uppercase extension (.LIB) not retained if added using 'Add to Profile'. ^# c4 ]0 ]6 h* B, J# E1 c
1879915 PSPICE ENVIRONMENT Check points cannot be loaded from a directory with space in its name5 q" c" `, k7 [1 i/ ]2 O4 C
1695306 SIP_LAYOUT STREAM_IF SiP Layout - Stream out issue: Embedded or stacked components using pad reference in more than one layer% T& B3 t( |6 t0 {) O
! K. P) h0 k" Q: h& R3 c' {; o7 g$ S, t# a* J( I: w
Fixed CCRs: SPB 17.2 HF039
* p d3 C+ N- M7 ]3 Z: ?05-11-20188 _) {- T6 e- |% o
========================================================================================================================================================3 W: y* @0 _/ W: ?. V
CCRID Product ProductLevel2 Title. P2 o5 G4 V3 }% D5 u& E' X
========================================================================================================================================================( W/ r" S$ ^: L: D$ f) p; q
1915149 ADV_PKG_ROUTER OTHER Auto-connect fails to initialize when rats are selected, but works with bundle9 X& ]$ A S0 t2 x4 Y) i5 b( ^
1870109 ADW ADW_UPREV Most mandatory properties turned into optional properties following database uprev
9 z7 Y ~. ?6 @6 F3 O9 r1758396 ADW CONF Server Memory setting in setting.ini is lost if server is re-configured using Conf
1 _8 t7 q# m- |7 V% v0 O/ z) O1911591 ADW FLOW_MGR Flow Manager does not start on high latency (> 25ms) networks: displays Java Content Disabled dialog( P6 I( x9 [: z( P
1887861 ADW LIBIMPORT Library Consolidation reports front2back issues but does not provide information about the issues.4 a+ ~8 @) T1 J; S# }8 r1 K8 F
1778977 ADW REPORT_GENERA reportgen memory setting too high in release 17.2-2016 resulting in launch failure7 I! Q c! h0 ?' _+ |5 _
1900422 ADW REPORT_GENERA Save in reportgen does not save Preferred Part List entry into .rep file) ~# `+ o/ q. _; n0 R% ]& u
1903888 ADW REPORT_GENERA Report generator not outputting values as expected for PPL field. E1 `; L- A1 k/ G! t
1916903 ADW REPORT_GENERA Reportgen -gui is not producing the expected result K* Q% M( z$ X, b$ z: F3 H. ^3 U
1902184 ALLEGRO_EDITOR DATABASE Add connect in package symbol crashes PCB Editor when using the 'clearance_view' variable2 K- @! q2 [' I' ]0 c; z9 s
1914793 ALLEGRO_EDITOR DATABASE Updating shape crashes Allegro PCB Editor7 p" {' z# Y9 U1 @1 x& @. a
1905138 ALLEGRO_EDITOR DRC_CONSTR Max Via count DRC disappears on running DRC update7 x6 F, j. C: ^' ]; H/ v* ]4 X
1848015 ALLEGRO_EDITOR MANUFACT Export Creo View cannot find the webpage on the PTC site2 p& H. C, }) d2 p
1850553 ALLEGRO_EDITOR MANUFACT 'File - Export - Creo View' is not working/ s; L) x+ Q9 {) W' }1 q. J
1853960 ALLEGRO_EDITOR MANUFACT PTC Creo Interface link is broken. R5 i# I. y0 _- ]
1862305 ALLEGRO_EDITOR MANUFACT PTC Creo interface link is not working
3 r( G- R! o6 o" j1878682 ALLEGRO_EDITOR MULTI_USER Delay in Symphony server session when server is started from Allegro PCB Editor
) H6 g; z9 y0 }, I; v1890108 ALLEGRO_EDITOR MULTI_USER Database rejections in Symphony# y7 L5 `+ F: g2 W; l& l
1887331 ALLEGRO_EDITOR NC Milling (NC route) in Gerber tools is not the same as what it is in the board./ T! n# `7 j0 Y3 N3 I2 U
1898179 ALLEGRO_EDITOR RAVEL_CHECKS PCB High-Speed option required for high-speed rules when Venture license is selected
% ^% N: Y6 i$ @2 o1461142 ALLEGRO_EDITOR SHAPE Pin with nearly-tangent via fails to generate void in dynamic shape, results in short.
# s7 I9 H" f, J, @; K1 n1863467 ASDA CROSSPROBE Highlighting all parts in PCB Editor does not highlight all parts in SDA
# [3 ]9 O8 g' s0 t1910974 ASDA CROSSPROBE Cross-probing between SDA and PCB Editor does not work
8 M# s, Q/ \- b* G# r& K) K1904440 CONCEPT_HDL CORE SPCOCD-577 error on migrating from release 16.6 to release 17.2-20167 |1 y+ Q( z$ U, g; l: {8 H
1909611 CONCEPT_HDL CORE DE-HDL stops responding on running '_movetogrid' and clicking 'No'
4 { ]7 I# j0 R1808743 CONCEPT_HDL PDF Inconsistent display of Publish PDF hyperlinks
) G( ?- z! E6 |4 K- [. u* s. X& D" L1894868 CONCEPT_HDL PDF XREFs getting clipped in the Published PDF$ X: s3 o$ W$ \1 L2 B
1911676 CONSTRAINT_MGR CONCEPT_HDL DE-HDL Constraint Manager crashes on selecting ECSet and then creating pin-pair option
- n) ~1 j# a4 R% Y0 h- F9 m1913968 CONSTRAINT_MGR CONCEPT_HDL Match Group pin-pairs are not created on applying ECSet to differential pair, Q4 L; N* D J$ p8 i2 g, o+ p
1899638 CONSTRAINT_MGR XNET_DIFFPAIR Differential pair buffer models are extracted differently in release 17.2-2016 and release 16.6! @' j ^' `: i& h- j; B7 {
1914116 ORBITIO ALLEGRO_SIP_I Unable to import OrbitIO file to SiP Layout
7 t! @1 y( E1 I1896487 PCB_LIBRARIAN GRAPHICAL_EDI Use lower-case characters for notes and pin text in New Symbol Editor
/ y9 W3 b( m( `, k1898008 PCB_LIBRARIAN SYMBOL_EDITOR Styling is not available for custom shape and pins.
T' l, s) u$ z+ N( C, p' X- o7 c# k1644787 PSPICE FRONTENDPLUGI PSpice Model Search window does not show complete library path+ r; ]5 `7 X- G. V
1785939 PSPICE FRONTENDPLUGI PSpice Part Search library browser should display path of the library directories
- M1 ?* f8 S: J0 b1855867 PSPICE FRONTENDPLUGI PSpice Model Search window does not show complete library path) O( u6 X, O0 S' R U
1887016 PSPICE SIMULATOR Pseudotran should always be invoked first time in case autoconvergence is ON
. J* k, Y j$ _1895752 SIG_INTEGRITY OTHER Layout Cross Section: Wrong Differential Impedance calculation (0 ohms) in RHEL Linux 7.1 or later versions
1 w3 M/ [& ^# g; k4 d! `( u1895759 SIG_INTEGRITY OTHER Cross Section does not calculate correct differential pair impedance in Linux CENTOS 7 and gives 0 value
& N" p6 {/ |# |1 `4 v1909257 SIP_LAYOUT INTERACTIVE Error 'E- (SPMHGE-639): Copying component with bond wire is not allowed' when copying SMD symbols
8 B) Q/ Z& ^7 x( N4 D f1900970 SIP_LAYOUT SHAPE Shape does not void around SMD Pins and Vias inside pad
6 D5 L" }( {# Z; T$ U) R s# p# E1885496 SIP_LAYOUT SYMB_EDIT_APP Pin Numbering: different results for release 16.6 and 17.2-2016 for the same case.- ~/ ?0 @$ ~( K) W
1907796 SIP_LAYOUT SYMB_EDIT_APP SKILL commands fail to change pin number in SiP Layout
& T, a5 A8 Y$ {1 ]% b7 d1887703 SIP_LAYOUT WIREBOND On trying to add wire bond to a die, SiP Layout crashes displaying a restart message# A5 t+ ?6 T% ~# g4 p% L
1903081 SPECCTRA LICENSING PCB Router is failing in Linux 7.1 in release 17.2-2016
& _# D1 f. f" |$ d5 W1721606 SPECCTRA ROUTE PCB Router stops responding on exit if opened in the stand-alone mode
/ Q) u$ o0 C ~4 W1844366 SPECCTRA ROUTE Allegro PCB Router will not exit
8 e8 ? F3 L* c! ^) b1 N1873716 SPECCTRA ROUTE PCB Router does not close if opened from Allegro PCB Editor or in the stand-alone mode
6 @" B9 {: S! o" Z. g1907703 SPIF OTHER PCB Editor crashes on choosing 'File - Export - Router' in release 17.2-20162 Q0 Q7 H+ c b$ m) f7 S/ l7 K2 ?
1889059 VSDP DIEEXPORT Incorrect pin location if bump cell origin is not at lower left for rotation other than R0) z9 U! m1 c4 w' ^2 k, t9 C
9 r# ]9 }$ u2 R+ M; U4 N. R( j/ m/ F
5 W' y9 n: e z: c1 e
Fixed CCRs: SPB 17.2 HF038) Y; N* a7 ]0 q/ Y; q/ r1 y
04-27-2018) z, }( L* M! z o. g: g! I
========================================================================================================================================================) Z) E- n W* q, {$ e! Q! v
CCRID Product ProductLevel2 Title
7 y% [1 j+ z2 L- }+ ^- |- h i========================================================================================================================================================5 h2 I$ P9 f" {- ~
1861616 ADW TDO-SHAREPOIN Team Design Option requires Allegro_ECAD_Collab_Workbench license feature& S6 {3 `; |2 C# S. ]7 U' _2 [
1784170 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Canvas does not show the flex zone thickness correctly
, M6 F" k- F7 |1801053 ALLEGRO_EDITOR 3D_CANVAS Moving component in 3D Canvas does not move the pads
0 o) a1 Q* V. ~& a$ ^1805038 ALLEGRO_EDITOR 3D_CANVAS Soldermask and drill not refreshed when component is moved in 3D Canvas, or on the board with Canvas open
6 {2 e* H8 w3 u+ M; E, ?3 C1808579 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas displays annular ring incorrectly
1 h9 ~/ V" b* [ D% }1816732 ALLEGRO_EDITOR 3D_CANVAS Mismatch in shape width between board and 3D Canvas
+ J: O8 C/ ?1 M& c- e3 h1822778 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas does not display nets when selection is done through click drag
6 W- e* i4 b0 o; y! [8 N P1838129 ALLEGRO_EDITOR 3D_CANVAS User is not able to create a pastemask layer that is visible in 3D Canvas
v) s- d) @0 P D# I* w1842911 ALLEGRO_EDITOR 3D_CANVAS Etch shapes not visible in the 3D Canvas when invoked from a symbol drawing6 S1 d7 Q- ]$ j6 C, }( B
1849380 ALLEGRO_EDITOR 3D_CANVAS Mirrored components placed in flex zones are not displayed in the 3D Canvas. {" z! j; z4 {* f' J A" y
1851898 ALLEGRO_EDITOR 3D_CANVAS STL export from 3D Viewer scales it up by 100$ Y9 e0 P+ @1 a$ ]
1853378 ALLEGRO_EDITOR 3D_CANVAS The new interactive 3D Canvas has a display issue with the off-centered drills.
6 V/ y! u) C; Z% Y5 r5 X1859713 ALLEGRO_EDITOR 3D_CANVAS PLACE_BOUND shape with package_height_max and package_height_min set displayed incorrectly in 3D Canvas
3 ~3 v F) W0 t) C3 l" q5 P6 y4 Q1880073 ALLEGRO_EDITOR 3D_CANVAS Design Outline is not displayed correctly in 3D Canvas* N1 V% X$ u2 }0 K5 u
1880338 ALLEGRO_EDITOR 3D_CANVAS Step Model missing in interactive 3D canvas.+ p9 _( A4 t% D' H3 [' X/ ]
1881889 ALLEGRO_EDITOR 3D_CANVAS Changing the color of STEP model in STEP Mapping Window does not display this color in 3D Canvas.$ a$ O. q, \5 T& b6 M" Q
1889861 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas swaps padstack from Bottom to Top* B# a9 a; {1 p( s
1830749 ALLEGRO_EDITOR ARTWORK Gerber 4x and 6x output do not fill the shape# X, g1 Z% h+ o( ~
1848514 ALLEGRO_EDITOR COLOR axlVisibleDesign does not interact with wirebonds- c, I& Q: O/ @
1837388 ALLEGRO_EDITOR CROSS_SECTION Cannot add solder mask to the site layer mask file
- J1 R9 w0 p! V* R1 m1859797 ALLEGRO_EDITOR CROSS_SECTION The Report only option does not work when choosing Setup - Cross-section - Import - IPC25817 A' ]# G. q8 x5 `; t& S, F! i* C
1877858 ALLEGRO_EDITOR CROSS_SECTION Dynamic Pads Suppression option is not working correctly
' L$ x- M" i6 k! B& m- a7 s& y- f1880093 ALLEGRO_EDITOR CROSS_SECTION Unused Pad Suppression options are not working correctly and are reset on opening cross-section1 o0 T3 D3 c3 W+ O) W5 u
1886283 ALLEGRO_EDITOR CROSS_SECTION Unable to turn on 'Dynamic Unused Pads Suppression'
7 {7 [% ]! I0 H8 f8 g; c% F* Y1890959 ALLEGRO_EDITOR CROSS_SECTION Dynamic Pads Suppression option is not working correctly
) x& y( @1 H0 u1900397 ALLEGRO_EDITOR CROSS_SECTION Dynamic Unused Pad Suppression option in Cross-section not working at one go./ e6 U8 o7 E) r+ y8 j1 V; |
1905315 ALLEGRO_EDITOR CROSS_SECTION 'Dynamic Unused Pad Suppression' cannot be turned on.* Z8 w5 Q7 Z. z6 F
1861406 ALLEGRO_EDITOR DATABASE Refresh symbol for flex zone not mapping padstack layers correctly5 ? o, M: | n0 \
1877132 ALLEGRO_EDITOR DATABASE Fail to open #Taaaaed17598.tmp file and save database# _/ ?% ]! G/ `% o2 b
1883747 ALLEGRO_EDITOR DATABASE PCB Editor crashes on stackup modification# t W, r. K3 w7 p2 T+ R( I% o
1860238 ALLEGRO_EDITOR DFM Applying a DFF constraint set closes PCB Editor instantly
' z1 Z3 H: r1 o7 ^1872780 ALLEGRO_EDITOR DFM DFF false pin to via DRCs: Copper Spacing, SMD pin Pad to Thru Via pad& Q$ k: \$ h5 L. D* w. m7 R: ^
1823912 ALLEGRO_EDITOR DRC_CONSTR Thru pin to Thru pin DRC between Symbol Pin to Mechanical Hole (with NO regular pad) l/ _, V& l; f, q
1828168 ALLEGRO_EDITOR DRC_CONSTR Upgrading from release 16.3 to 17.2-2016: Differences in spacing constraints- o$ x8 N/ f" p% d2 s
1844780 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to Shape Air Gap value is reduced when updating shape$ P+ \( L/ u& f, L% E
1845011 ALLEGRO_EDITOR DRC_CONSTR When upgrading from 16.6 to 17.2, Spacing constraints for shape to mechanical pin not being resolved properly
0 S* M3 B9 {" O/ d# N# K5 m+ g( b9 r1861548 ALLEGRO_EDITOR DRC_CONSTR Inconsistent Micro via to Micro via drill to drill overlap DRCs
) k! w: T* a4 R1 Z& \9 `1 n" F1862281 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin/hole to Shape spacing too small
8 ?7 T) h6 D& V1887145 ALLEGRO_EDITOR DRC_CONSTR Mechanical pin to conductor spacing setting is overriding constraint region in release 17.2-2016
* Z5 [ [; A* V1893012 ALLEGRO_EDITOR DRC_CONSTR Shape voiding not taking the shape to hole spacing rules for NPTH
' Z6 B( ]- R, c# Z. b i5 C0 G1906840 ALLEGRO_EDITOR GRAPHICS Context menu stays when PCB Editor is minimized.
) i# a3 x- v9 E$ X- [; E. v! u1738624 ALLEGRO_EDITOR INTERACTIV 'Invalid Sector' error when saving psm file for symbol that has die pads, which are copied0 @" e& j9 K" a3 f. e! ]1 ~
1800741 ALLEGRO_EDITOR INTERACTIV Search in User Preferences Editor is giving incorrect results
+ ^8 c3 t5 h/ k' V7 M* d1812530 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes when opening a file that is in an unsupported format: D0 }# k+ ?6 f# F
1812570 ALLEGRO_EDITOR INTERACTIV PCB Editor hangs when an invalid pin number value is specified as the rotation point in the symbol preselect mode" y+ ?) |7 Y3 ?$ A; l8 h/ Q
1826819 ALLEGRO_EDITOR INTERACTIV 'Route - Resize/Respace - Align Vias' menu is not available
* r9 i+ U3 I" T' V, z1842645 ALLEGRO_EDITOR INTERACTIV Via align command is missing from the menu path
5 q. b! m; g; G1845748 ALLEGRO_EDITOR INTERACTIV With 'Shape - Change Shape Type' enabled, changing visibility reverts the Shape Fill selection to dynamic copper., D& o$ G( S* h! a2 g1 E
1849700 ALLEGRO_EDITOR INTERACTIV Add the reason for generating DBFIX_PAD, to the dbdoctor.log.
/ `! n2 T# J$ X: }: W$ [: I: i1860934 ALLEGRO_EDITOR INTERACTIV Auto-Paste environment variable is not working as it should3 A0 d! N( l, ~( p* M0 x
1861928 ALLEGRO_EDITOR INTERACTIV Provide a Persistent snap pick option for Display - Measure
: E: O9 y7 x3 O& } x7 j. g1 M; r8 N1864238 ALLEGRO_EDITOR INTERACTIV Shape place rectangle issue: Dimension of placed rectangle changes on cancelling action
( B, J( f# v, d3 U {% s& p1877026 ALLEGRO_EDITOR INTERACTIV Filled rectangles on ETCH/TOP and ETCH/BOTTOM are not getting copied
7 Y; ]) V% b: Y8 k/ _2 n0 G5 E0 h1881637 ALLEGRO_EDITOR INTERACTIV Radius of Shape changes when trying to place circle using Place Circle mode.( u- ?5 T" p, {1 B/ @/ M
1883032 ALLEGRO_EDITOR INTERACTIV Find by Query does not find all padstacks in a symbol drawing% L* W _( u- L { o( J' j( }- _6 p
1855248 ALLEGRO_EDITOR INTERFACES The Technology Dependent Footprint command returns an error
N* z7 q8 D; L( W/ w, t) ?1885716 ALLEGRO_EDITOR INTERFACES Increase supported STEP model size to enable the use of models larger then 500MB- |) U" _' b$ s' n& m P
1860835 ALLEGRO_EDITOR MANUFACT Display a message when backdrill_max_pth_stub is defined for vias or pins only8 S+ X3 A8 A0 L3 K, ]
1869528 ALLEGRO_EDITOR MANUFACT Backdrill out of date when deleting Teardrop and Sliding cline with Teardrop
/ I' z5 L& A6 B) C1885672 ALLEGRO_EDITOR NC NC drill is creating false backdrills when repeat code is turned on in release 17.2-2016
, T: X4 x- S4 T( b3 {1895084 ALLEGRO_EDITOR NC Padstacks with backdrill data trigger backdrill out-of-date even if the board is not set up for backdrilling6 [2 Y7 Q4 g! d3 J
1837514 ALLEGRO_EDITOR PAD_EDITOR Offset is not consistent for keepout and mask layers in padstack editor.
" J6 r7 t9 N! a; Z7 [1842902 ALLEGRO_EDITOR PAD_EDITOR Scrolling through the .pad files in the Library Padstack Browser displays Error(SPMHA1-161), e8 L# _) ?% h! S o. z& O
1846504 ALLEGRO_EDITOR PAD_EDITOR COVERLAY_TOP definition lost while opening and saving a 16.6 pad in 17.2 padstack editor
' Y1 G$ W8 v. ?+ D$ h: I1879453 ALLEGRO_EDITOR PAD_EDITOR The 'Y' tolerance in the Padstack Editor does not update when changing the units of the padstack.
" h) O+ }. y# R& Y/ G( J9 x1805202 ALLEGRO_EDITOR PLACEMENT Place via array adds via on differential pairs incorrectly
9 k; v8 r# @9 z2 M! U5 W1806675 ALLEGRO_EDITOR PLACEMENT Place - Manually - Quickview displays the Assembly Top details only5 a/ O3 x: y+ t4 J; m8 D
1835177 ALLEGRO_EDITOR PLACEMENT Can place symbol even after cancelling copy by choosing 'Oops' from pop-up
. n6 r* t( W0 Y3 S/ U- T7 Z: l$ e1846892 ALLEGRO_EDITOR PLOTTING PCB Editor Export PDF does not show lines correct for certain component
, _+ d! J( ^4 G7 [" [ v# {3 L1006328 ALLEGRO_EDITOR SHAPE Static shapes should void around corners as dynamic shapes do
" u5 x. u; U: o ]1033326 ALLEGRO_EDITOR SHAPE Cannot compose lines to shape, y5 S# L3 D! u N& Q$ h2 @5 X6 q
1045089 ALLEGRO_EDITOR SHAPE Dynamic shape voiding is inconsistent for solid and xhatch shape fill type; z8 I/ m! P- F% s4 Y3 t
1069959 ALLEGRO_EDITOR SHAPE Compose shape crashes PCB Editor
9 B: e# ?' H: h1085907 ALLEGRO_EDITOR SHAPE Pad does not get thermal connections to shape if outside of the shape outline by more than DRC spacing.
5 i" s, a5 A. ?! s% X1143563 ALLEGRO_EDITOR SHAPE The pin void inline clearance does not seem to dynamically update the shape and requires a 'force update'.
& A1 ?. \' K c9 F6 M1243688 ALLEGRO_EDITOR SHAPE shape_rki_autoclip fails to clip shape to route keepin% e/ e, Y; X: C
1269069 ALLEGRO_EDITOR SHAPE Shape void not working properly in release 16.5 hotfix 054
$ ]2 m: e2 X2 U2 V7 C1327755 ALLEGRO_EDITOR SHAPE Need the ability to nest dynamic shapes on different nets partially or entirely N* \0 m. _& Z/ o# n3 B& n
1417394 ALLEGRO_EDITOR SHAPE Shape not updating correctly
) t4 S* M k0 }- o; x/ z1430742 ALLEGRO_EDITOR SHAPE When adding fillet to an irregular pad, the fillet might not be added or be strangely shaped7 b- \: t" u, i
1750760 ALLEGRO_EDITOR SHAPE Shape to Route Keepout DRC for a void that meets route keepout- I5 J8 s" y. N6 W/ J, z1 E& I; d; O9 ~& Q
1793898 ALLEGRO_EDITOR SHAPE Add teardrops fails to add anything with different settings
- C5 i& K. K% K/ Q) h1811662 ALLEGRO_EDITOR SHAPE 'show measure' gives incorrect air gap value between two pins
/ t$ E; ]5 V1 U2 K4 ~4 v ~1820901 ALLEGRO_EDITOR SHAPE The pins on adjacent layers are voided as Rounded Rectangle instead of Rectangular as defined in padstacks% f; L7 [2 D7 y* v+ o
1829570 ALLEGRO_EDITOR SHAPE Display measure airgap value is very large
7 b" |- P& y' h5 s7 u4 z! K1858696 ALLEGRO_EDITOR SHAPE The via to the edge of the board is not connecting to shape even with the PAD_SHAPE_TOUCH_CONNECTION property added, f- z0 \8 x% `
1873384 ALLEGRO_EDITOR SHAPE Boolean AND operation returning nil, L0 f, a8 f. i/ t
1873860 ALLEGRO_EDITOR SHAPE Copper shape does not respect route keepout) j N% |) m, A+ p' O
1889312 ALLEGRO_EDITOR SHAPE Shape voided for net vias on adding 'PAD_SHAPE_TOUCH_CONNECTIONS' when enabling via suppression$ e3 N2 b4 \" {. B2 K/ u
1890702 ALLEGRO_EDITOR SHAPE Not able to add teardrop in release 17.2-2016
' @# d r- [& {3 E) ]" B" a1 i# \1892692 ALLEGRO_EDITOR SHAPE Thermal relief connections being added to static shapes present in the void inside Dynamic Shapes7 |2 q7 I) X! v9 D% J; ]& O
1893492 ALLEGRO_EDITOR SHAPE 'merge shapes' results in moved void4 H' r6 w5 Y4 p# |4 ]# b! I
1896543 ALLEGRO_EDITOR SHAPE Same net pin will not add thermal connection to shape if it is a rotated slot in the symdef
$ k: `8 Q- B- S5 {; S" o1897645 ALLEGRO_EDITOR SKILL axlCNSGetSpacing() returns nil if active class is non-etch.
, p5 s7 R# r) s J' O, {, j1822364 ALLEGRO_EDITOR UI_FORMS Design Parameters dialog disappears if prmed is called while show measure is active; Y- `9 O! \! C* h Z4 c- P' r! u
1834395 ALLEGRO_EDITOR UI_FORMS Setup menu of OrCAD PCB Editor is missing the Anchor 3D View command
; H! X |& b9 ?4 u1838941 ALLEGRO_EDITOR UI_FORMS Anchor 3D View command is not available in OrCAD PCB Editor Setup menu
) L4 T. w1 \& j6 K2 F! Q1716433 ALLEGRO_EDITOR UI_GENERAL Alias keys do not work until mouse scroll key is activated M& X; a$ _& r a
1721761 ALLEGRO_EDITOR UI_GENERAL During manual placement of symbols, hovering over symbols does not highlight them
0 ^* v% l5 F% {1 W- h+ l0 W1732915 ALLEGRO_EDITOR UI_GENERAL Alias does not work in release 17.2-2016 when switching windows
$ }* u. @ h% |% C% q! v1770723 ALLEGRO_EDITOR UI_GENERAL Funckey does not work if focus is not on canvas in release 17.2-20166 `" R! c/ y' X, Y. R7 _0 {2 P
1793839 ALLEGRO_EDITOR UI_GENERAL Function Key does not work if a form is opened by a previous command6 J s7 M5 g ]& V7 T9 s: Y
1813961 ALLEGRO_EDITOR UI_GENERAL Inconsistent file formats available when saving reports
9 r4 } j6 u1 R# D8 Y1816716 ALLEGRO_EDITOR UI_GENERAL Shortcut not working when using working layer with 'add connect'
( S: h. @3 }7 g1 v0 y& Y1864321 ALLEGRO_EDITOR UI_GENERAL Funckeys not being registered after focus has moved to other window and back again in PCB Editor
1 Y" g6 c* `7 i5 h( f1865010 ALLEGRO_EDITOR UI_GENERAL PCB Editor does not get focus when clicking shortcut after switching from any other program or application
- [0 [! d# {6 k5 I: U7 A* f1868708 ALLEGRO_EDITOR UI_GENERAL Allegro PCB Editor, funckeys stop working intermittently in release 17.2-2016, hotfix 032
( L) N4 h3 P1 S Y1869745 ALLEGRO_EDITOR UI_GENERAL Allegro 3D Canvas window becomes active on pointing at minimized icon on taskbar
5 G7 S" @, z% [4 o1 i4 Z- R1869860 ALLEGRO_EDITOR UI_GENERAL Hotkeys no longer functional on switching from PCB Editor to another application and then back again
2 @4 Q A7 t$ \# w) q7 y! g1870744 ALLEGRO_EDITOR UI_GENERAL Need html extension added to Save pull down menu.* K, M: [4 O9 a5 N" m
1870996 ALLEGRO_EDITOR UI_GENERAL If you switch from one active window to other, hotkeys stop working& G }& Z' C" F: }7 s8 [# y
1883507 ALLEGRO_EDITOR UI_GENERAL Hotkeys stop working after Allegro PCB Editor UI window is opened) G+ q9 P+ B$ w; \7 ^# E; g, W
1886981 ALLEGRO_EDITOR UI_GENERAL Focus lost from layout when switching between PCB Editor and Capture; x6 _6 x1 e6 c# j6 `5 R3 x6 |
1887519 ALLEGRO_EDITOR UI_GENERAL Release 17.2-2016, hotfix 034: Shortcuts defined using funckeys not working correctly
+ b1 b7 a1 F5 G' A" Y$ W% I1 U1887660 ALLEGRO_EDITOR UI_GENERAL Alias does not work in release 17.2-2016 when switching windows.
) ~/ b3 j- g1 R9 l8 _& l9 k" P1891204 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes if SKILL form is closed using the Close icon ('X')
1 g# C( t1 u! a* ^5 X1898059 ALLEGRO_EDITOR UI_GENERAL Funckey commands are not working consistently in release 17.2-2016, R) f: _5 ^. Y
1902322 ALLEGRO_EDITOR UI_GENERAL Cannot use funckey commands when cross-probing
8 E0 i. ~9 b! j- T( | S6 }1905906 ALLEGRO_EDITOR UI_GENERAL Issue with keys and focus when navigating between windows0 y' @: Q+ m& V7 H& g
1913768 ALLEGRO_EDITOR UI_GENERAL Uppercase funckey shortcuts do not work/ U7 n+ X* g* E5 g
1751586 APD OTHER axlGetMetalUsageForLayer() for etch returns value including pins and vias) }. | E7 ?% t, T8 M' b
1863241 APD SHAPE Fillet is left on the T-Point without Cline(center) connection., G$ q3 W, v& J: }
1894438 APD STREAM_IF APD/SiP Layout: Export rounded features as circumscribed and not inscribed polygon in GDS& X# M1 o }# |6 Y& \% X
1812699 ASDA AUTOMATION Enhance the performance when extracting data from SDA, using TCL functions- d1 l6 @) C+ G' }
1863436 ASDA CANVAS_EDIT alignment guides are not displayed when placing or copy a part, only when moving. They are most needed during placement
; e; N4 e0 k2 Y! A+ C" z: T2 ^/ z1863445 ASDA CANVAS_EDIT Dark theme blue text in docked CM needs to be of a different color: difficult to read
5 r! j1 {2 q& r! q& O1802111 ASDA DARK_THEME Dark theme in SDA should also change the border line color and text color of grid references: they are still black8 N. X7 ]/ ^: q0 @, r; ^5 S* ~- L" Y# x
1869951 ASDA EXPORT_PCB File browser button in Export to PCB Layout flashes graphics of the window behind the form
3 f; {0 s; ~, o0 m9 k) t0 D& n% d% `1845831 ASDA FORMAT_OBJECT Width of the twisted pair of wire should automatically be set to 6, otherwise it is not drawn correctly' z) l( N# Q9 B% y' { w: D# |
1879914 ASDA INTERNATIONAL Using French Keyboard cannot use the . (point) delimiter to set VOLTAGE property value2 e& J" L) n% h$ s+ V
1865753 ASDA MISCELLANEOUS Inconsistent and non-ideal behavior in SDA product choice dialog, small box, hard to check unlike the bottom box* V" Q r+ q5 f. x S$ u" a: v% m
1863457 ASDA PACKAGER Unset all user-assigned references globally
$ z0 U$ X5 U: s' g; O1889301 ASDA TDO SDA TDO Crashes when switching to/from Offline mode
) L- H6 H y$ M6 t# D6 d1823203 ASDA VARIANT_MANAG Variant setting part to not present does not do anything
/ r* W) Q* ~: d+ v1823992 ASDA VARIANT_MANAG Variant Editor fails to read netlist if a net is named NC
( U+ q$ a4 W# T+ N% N1863451 ASDA VARIANT_MANAG variant mode can select multiple parts to add to variant but can't select multiple parts to hit reset+ c8 y$ E ^& ?1 z. M5 c
1863455 ASDA VARIANT_MANAG Cannot resize any panels in the Variant mode
4 y# n, Q5 U" O5 z* \, `1874952 ASDA VARIANT_MANAG Letter I in the alternate part icons in variant spreadsheet should be white for readability
6 I9 ?) s% V% K/ S2 z. K6 h1878401 ASDA VARIANT_MANAG SDA Variant Display - DNI marker color switches between black and red
# i2 ] L t" C1877239 ASDA WORKSPACE SDA DRC window is hidden if undocked and minimized
. n- |/ w5 l0 N1 a9 I1809605 CAPTURE LIBRARY Part has pins in the incorrect order in the Connectors library
8 y: k6 K3 n! Z1 ^1638693 CAPTURE OTHER Capture Footprint Viewer not showing footprint., T2 ]; U M" X R1 z8 K/ M
1873612 CONCEPT_HDL COPY_PROJECT Copy project causes nets to be added to net groups and ports - fails to package due to mismatch
- k0 Z4 S& D$ n1779289 CONCEPT_HDL CORE Adding a component and wire and saving the design results in a 'Connectivity save failed' error
3 z1 S, s& b0 Y, M5 p+ ]- A1878719 CONCEPT_HDL CORE Cannot enable or apply block variants at the top-level in a hierarchical design.
! b/ G. c% g" K- K F1865480 CONCEPT_HDL OTHER 'partmgr -ptfMode shoppingCart' cannot output cell name with project ptf file into shoppingCart.xml- }; m8 T1 H2 d1 H9 `- S- K
1829966 CONSTRAINT_MGR CONCEPT_HDL DML independent flow: Export Physical audits missing signal models in release 17.2, m% m1 d& J# u3 ^7 S* E; E
1904458 CONSTRAINT_MGR ECS_APPLY 'Audit - ECSets' crashes DE-HDL in release 17.2-2016, Hotfix 037. f+ |( p S% T, G3 m s) n5 W8 c
1798269 CONSTRAINT_MGR OTHER Script changes '-' in layer name to '_'; f8 o- W: b4 H5 O; c
1835520 CONSTRAINT_MGR OTHER Cannot add members to netclass name with parenthesis' }2 U1 \* m5 j; Q4 p
1896638 CONSTRAINT_MGR OTHER Constraint Manager worksheets jump abruptly0 a8 i8 w! [0 j& i3 b
1801938 CONSTRAINT_MGR UI_FORMS Add To Netclass window: Focus not on ClassSelection
. J, h9 @& C" o) G% ]5 U" O9 J; I7 l1854060 CONSTRAINT_MGR UI_FORMS Using the tab key in the Manufacturing workbook jumps a cell* ], T9 h" s% {. o' T0 E
1881832 ECW ROLES_PERMISS Adding Users in SSO environment using PS is error prone
5 D& r) L3 K7 d# v e; v/ ?4 s- L& g4 u* x1864870 F2B BOM Incomplete BOM report generated
5 p$ E8 U1 z% L. x, x1846578 PCB_LIBRARIAN GRAPHICAL_EDI radio buttons and clickable buttons are hidden in the UI for verify rules
& f5 L4 `; }/ @% Y' I* ^8 T3 N1854080 PCB_LIBRARIAN METADATA con2con needs to support special characters in Primitive Name; x; |4 t/ A* q7 d9 S/ t4 P0 B7 r6 W
1796377 PCB_LIBRARIAN SYMBOL_EDITOR Unable to move pins using arrows when symbol is opened in Symbol Editor$ X# i5 q. ^$ F! J/ m* y5 A/ U) c
1839692 PCB_LIBRARIAN SYMBOL_EDITOR Properties tab grayed out in Symbol preview window
# Y% ~5 q" @, P' V: m( O8 g) Y. M1865657 PCB_LIBRARIAN SYMBOL_EDITOR Cannot change symbol properties using the General tab" d8 V& j& ` y! W/ s9 B1 g
1906888 PCB_LIBRARIAN SYMBOL_EDITOR Properties button in Symbol Pins tab of the Symbols section is inactive.) _; A- y9 b: e p9 z- p
1891248 PCB_LIBRARIAN SYMBOL_EDITOR Copy and mirror arc drawing object in the new Symbol Editor results in wrong arc on opening symbol in DE-HDL; {+ L- j; O/ g0 y7 U& ~, ^; `( R
1908381 PDN_ANALYSIS PCB_STATICIRD Allegro PCB PDN Analysis crashes after performing analysis and saving result in release 17.2-2016
$ b3 f% ]! G& ]. Q1825087 PSPICE AA_OPT Graph view menu does not appear when we use 'Curve Fit' in Optimizer.
1 P& H o# g! m& n- j1808091 PSPICE ENVIRONMENT 'orSimSetup' crashes when 'Restart Simulation' is selected% t! @3 p [( K5 ?/ L3 {
1811782 PSPICE ENVIRONMENT Setup Simulation Profile no longer enables Advanced Markers when appropriate
/ ]9 U, e- N1 |* G1834147 PSPICE ENVIRONMENT PSpice Part Search library icons not displayed if product is installed in the Program Files folder in release 17.2-2016! n+ X" ^1 q7 h+ O f" ?+ Q
1841992 PSPICE FRONTENDPLUGI Getting a blank Error dialog while adding a marker5 x: B+ K7 `$ ?! K+ R3 H
1858574 PSPICE NETLISTER PSpice simulation: Some models cannot be used after upgrading to release 17.2-20167 r! G3 t+ G5 {$ [' k* F( o
1865022 PSPICE NETLISTER The division operator is not recognized by PSpice in DEV expressions in release 17.2-2016
( o8 T; @8 E0 y) }" v1677119 PSPICE PROBE PSpice crashes when plotting simulation message summary
. l8 U# L4 s7 N! @, c4 n ?1837046 PSPICE PROBE On Windows 10, PSpice crashes on clicking Yes to see message
: y0 P+ c6 K2 z3 C1879387 PSPICE PROBE PSpice crashes when we choose to plot simulation message summary# P2 y5 | x9 A2 n% I
1842231 PSPICE SIMULATOR Wrong results in PSpice Advanced Analysis for DC Sweep Analysis
7 _' V4 M5 M# t6 M X5 z1843446 PSPICE SIMULATOR Distribution type is not showing under Assign Tolerance window for transistor
% n7 l7 S0 L7 J5 k' B# S1872630 RF_PCB ROUTING Transition taper length does not work in route- Add RF trace* a$ |8 u# @; F! S+ j
1872636 RF_PCB ROUTING Inherit Width parameter in Route -RF trace only uses width of one side
& M/ H \( R: ]' q1872644 RF_PCB ROUTING Regression RF trace: change in trace width not retained while routing4 c8 X; p6 H8 |0 |$ |
1901201 SIP_LAYOUT EXTRACT extracta is not retaining custom layer names4 V; j3 U7 B+ F$ U6 B; a
1813380 SIP_LAYOUT OTHER Layer Compare is not adding the required shapes
8 q/ ~4 u* l7 y0 `* N1852762 SIP_LAYOUT OTHER Error generated in Package Design Integrity Check when adding soldermask to my design
1 [7 S& n, r- T; q+ {1886847 SIP_LAYOUT REPORTS Incorrect metal area in metal usage report
' Z( O4 L# b8 J1491315 SIP_LAYOUT SHAPE Dynamic shape filling exceeds the shape boundary on running 'create bounding shape' command
: r# K% Q, V/ D+ ~# t1853989 SIP_LAYOUT SHAPE 'Shape - Select' and then' Move' from pop-up with ix 500 iy 0 moves shape diagonally; d/ u2 E! L1 n4 x9 f
1868509 SPECCTRA PARSER Autorouter takes long time to invoke
% v' N5 T% ~, L7 P1 ], i0 t+ K0 }" k1869317 SYSTEMSI ENG_PBA SystemSI PBA does not align correlation waveforms correctly on Linux platform
9 v ]" i" |7 Y) ?' b4 g
+ H5 p% z! [! T$ X
& J5 B/ Z8 Y% f+ J! z$ yFixed CCRs: SPB 17.2 HF0374 ], D! f; A# [
03-30-2018! m/ c3 p- n) x. V1 B# ~2 [
========================================================================================================================================================
8 R! J O, i; a9 H- `1 U* ]4 \CCRID Product ProductLevel2 Title
8 h! A% p: s' E% Y========================================================================================================================================================5 O: a1 Z2 j* k
1886573 ALLEGRO_EDITOR IN_DESIGN_ANA Fail to launch Sigrity executable from release 17.2-20168 h+ i+ t# e/ d; e5 ^
1891113 ALLEGRO_EDITOR NC Clubbing total backdrill layerwise data
) F; X8 Q. @* F/ \1886085 ALLEGRO_EDITOR SHAPE Line to Thru Via DRC is not displayed automatically
( T6 p, a" I3 S$ f8 Z% @1850888 ALLEGRO_PROD_TOOLB CORE Design Compare crashes immediately after execution7 n/ r% X1 v, |, D) W( w
1639079 ALTM_TRANSLATOR CAPTURE Title block issues with third-party design
% |# y5 c7 P- Y2 B9 V1722577 ALTM_TRANSLATOR CAPTURE Third-party translator does not work in Capture in release 17.2-2016 if CDSROOT is not defined U/ Q9 q6 w1 g5 W
1744697 ALTM_TRANSLATOR CAPTURE Third-party translator crashes
1 S) g# ? Y; T/ M6 D m, B1820160 ALTM_TRANSLATOR CAPTURE Title block does not show ghost image when selecting it for placement4 D& J8 H0 a. R3 i" \! Z
1628560 ALTM_TRANSLATOR PCB_EDITOR Third-party translation to PCB Editor not working properly
2 f- P* V* q7 p5 @$ p' r1836750 ALTM_TRANSLATOR PCB_EDITOR Third-party translator fails to translate a complete design
' @3 U8 ?1 l$ c) v* B1844423 ALTM_TRANSLATOR PCB_EDITOR Third-party translation takes a long time in release 17.2-2016
$ `9 ^0 z: r; e1849338 ALTM_TRANSLATOR PCB_EDITOR Third-party translated board not correct( p3 ?% W$ ^. H0 o+ S
1894607 CONCEPT_HDL CORE Closing CM during 'Save Hierarchy' crashes DE-HDL6 b; S: A5 A T" V9 w
1703351 CONSTRAINT_MGR CONCEPT_HDL SigXplorer shows invalid models instead of default models in extracted topology
% j# [; C* d' b! f' A- I. H* w7 }1868687 CONSTRAINT_MGR CONCEPT_HDL DML-independent flow: some pin-pairs missing for Differential Pair XNets when migrating 16.6 design to 17.2
; n8 I. Q' H2 E* u* x1868747 CONSTRAINT_MGR CONCEPT_HDL Additional pin-pairs created on migrating design to release 17.2-2016 DML-Independent flow% p4 B! i* o n0 K: t! ^; K d
1887794 CONSTRAINT_MGR OTHER Ability to disable cross-section changes in F2B flow6 {8 v" M h5 \/ g
1859193 MODEL_EDITOR TRANSLATION DML provided by Model Integrity has a parsing error: curve must start at time zero4 E9 h1 E3 w0 h3 s9 I
& H4 Q& a) \1 K3 n A. ?* |! c4 o8 T2 g4 [+ q
Fixed CCRs: SPB 17.2 HF036" S/ o0 ~# w# N
03-16-2018
2 u+ w. t- @! P- ^/ L========================================================================================================================================================
: {3 C1 T& ^2 Y2 c/ w) X- tCCRID Product ProductLevel2 Title
z* Q1 H3 D6 q' V+ b========================================================================================================================================================
9 o( j, b0 _1 U% j1880209 ADW DBEDITOR DBEditor quick search is resetting the check boxes in the Attributes tab( \" T, h, t( N, @6 F
1880376 ADW DBEDITOR Allegro EDM Database Editor wildcard search functionality broken after installing hotfix 034.
5 z2 M+ j( G& r1855444 ALLEGRO_EDITOR DATABASE PCB Editor crashes on creating MDD files after deleting subclasses
/ v$ y5 n2 X3 O+ M' @: J* f1863478 ALLEGRO_EDITOR DATABASE PCB Editor crashes on a specific machine when loading any .mdd file
& _# h5 |$ d9 l4 [- w$ ]4 I: r1875544 ALLEGRO_EDITOR SCHEM_FTB Constraints are getting removed1 u! p$ z( A, \' W
1719683 ALLEGRO_EDITOR UI_GENERAL Incorrect display when using infinite cursor.7 e5 y; y, l/ h
1765989 ALLEGRO_EDITOR UI_GENERAL Selection window does not work correctly with infinite cursor option checked8 s( I3 Y1 k9 O1 H6 l$ c& L- D
1885667 ALLEGRO_EDITOR UI_GENERAL Infinite cursor is not working correctly
, Y7 `' ~) ~# q& K- B1873954 ASDA IMPORT_DEHDL_ SDA: Inconsistent pin number positions on part in an imported DE-HDL project* y! i$ g1 K; I8 Y
1873883 ASDA NEW_PROJECT SDA: New project from DE-HDL creates blank Page 1
/ L/ u3 m |+ O" P9 Y. {" x1 o1852036 ASDA VARIANT_MANAG Design with variant cannot generate a variant BOM3 e0 r2 p$ t* [' V5 K3 |
1875549 CONCEPT_HDL CORE Incorrect PART_NUMBER/VALUE properties on schematic5 D: I- ?. [( j, p0 I
1881848 CONCEPT_HDL OTHER License issue: Cannot open Allegro Design Authoring and unable to choose options and features' x. o2 S0 z. t4 w7 w$ [
1872189 CONSTRAINT_MGR CONCEPT_HDL Pin-pairs are created for incorrect members of differential pair after ECSet is applied/ T7 B. }6 y& [* A1 q. _! U4 D6 X
1880235 CONSTRAINT_MGR UI_FORMS Ability to lock auto-generated Constraint Set in UI3 N5 x* v2 c: z
1868711 CONSTRAINT_MGR XNET_DIFFPAIR Nets are dropped from XNets on the BRD file in the front-to-back flow
& _1 _6 E1 _& J" n8 o1879296 ECW PROJECT_MANAG Mode to remove Uprev Lock from locked webs in admin keys* h$ S( H$ B4 ^ D
1881632 PSPICE SLPS PSpice creates 'psp_input.log' during co-simulation flow
4 Q5 w7 R9 @5 P3 b4 g& q3 w1879302 SCM OTHER SCM crashes when global nets are changed in the Block Packaging Options dialog box
9 N) e' k2 J) T g5 A Y& L1879580 TDA SHAREPOINT GetData error when opening a project in Design Data Management2 E3 i' z! t9 c& n; t
' r- m& v( ~: G
6 L" D( G/ m8 Q0 {8 _8 uFixed CCRs: SPB 17.2 HF035
z+ Z/ g; L3 \03-02-2018! ^) }1 k, X; q) U: t# X1 y+ Z( c
========================================================================================================================================================
, y- W' b# \ L M( ]CCRID Product ProductLevel2 Title( x, M& E, V0 x0 S6 ]
========================================================================================================================================================) n0 Z* C7 { A8 o
1873547 ADW ADW_UPREV adw_uprev resulted in incomplete footprint XML7 s# U7 g/ v3 k
1643895 ADW DBEDITOR Create Footprint model name is not working properly if footprint exists in local flatlib! m7 e- L: R6 O& ~4 ]
1846400 ADW DBEDITOR 'Copy As' and 'Rename' STEP model options do not work' Y9 A5 \( ~# f: V& S; L
1868299 ADW FLOW_MGR Copy Project fails and makes Flow Manager unresponsive
9 n$ m$ M) K. [5 m1872796 ADW PART_BROWSER Part/Model Details Attributes are all empty when connected to the EDM DB- a" `9 j$ \+ q+ Z4 _
1877199 ALLEGRO_EDITOR DATABASE Purging backdrill adds bottom filmmask to vias when it is not defined in the padstack
6 {+ ^( N3 m% b# C% o3 j1877219 ALLEGRO_EDITOR DRC_CONSTR PCB Editor crashes on updating DRC
: M8 E! n# a; A- Y2 p3 e# }/ F1875528 ALLEGRO_EDITOR GRAPHICS Subclasses disappear in partition
+ E8 N8 ~0 L9 U' `! N: @: \& W3 V% y0 H1868364 ALLEGRO_EDITOR OTHER Translator for Layout to PCB Editor fails in release 17.2-2016 but works in 16.64 Q9 o8 e! F0 L: w2 c
1822989 ALLEGRO_EDITOR UI_GENERAL PCB Editor very slow when using infinite cursor
5 T* I( Y4 `' h* a/ c0 _1855275 ALLEGRO_EDITOR UI_GENERAL PCB Editor becomes slow if OpenGL is disabled
; [- l& S" D* ]2 d% e* l% h1868803 ALLEGRO_EDITOR UI_GENERAL Infinite cursor not working as expected
" O2 a8 D0 Z: f# ~* {. T1869523 ALLEGRO_EDITOR UI_GENERAL PCB Editor hangs inconsistently on axlOpenDesign
% Z2 g- R. u. k- D; H1 O. d1871409 ALLEGRO_EDITOR UI_GENERAL ESC key does not function with Enable_command_window_history set
I3 U0 ^. C" l. s! z8 @7 L1812306 ALLEGRO_PROD_TOOLB CORE Incorrect DIFF result of PCB Design Compare4 l+ X p( Y8 E, p3 H2 U' G
1872772 ASDA MISCELLANEOUS SDA pulls a license for 'Allegro_performance'
! {# } L- p+ S3 s) M3 N$ k1877070 CAPTURE OTHER Capture redraws icons5 r6 M, @& J e4 B: z# O- t: c
1863624 CONCEPT_HDL CONSTRAINT_MG XNet names are changed in the designs migrated to release 17.2-2016
8 e- q; o% h! c7 Z Q. t1 a! ~1866290 CONCEPT_HDL CORE variant editor/DE-DHL crashed when changing a component property( ^1 P8 f, \; G6 l
1858139 CONCEPT_HDL OTHER Slow graphic response in Windows10: Icons redraw
5 Y1 S8 ^ o X. V+ Z1 S1872703 CONCEPT_HDL OTHER Icon and toolbar in DE-HDL keeps on refreshing for every command
6 H; j' D" p& p- k. p1873949 CONCEPT_HDL OTHER DE-HDL user interface refreshes frequently: k0 T+ q8 e7 R
1871542 CONSTRAINT_MGR INTERACTIV Extracting object with 'Referenced ECSet' does not inherit T-points from the applied ECSet
( U: ]6 l0 I& ~1868812 CONSTRAINT_MGR UI_FORMS Cannot Save Log File from CM ECSet Audit.) \5 K" Y% L* v6 ~/ t3 A
1878574 ECW PROJECT_MANAG Duplicate entries are created in SharePoint users list while creating project on SSO setup3 X8 E' H4 p5 `$ m" w D
1878619 ECW PROJECT_MANAG Too many mails generated on doing create project% \ ~& [- M/ o- f
1862772 ECW TDO-SHAREPOIN Logical BOM file name not displayed in Changed Files of Pulse Activity Log.
( ^: u4 H( X1 [8 Y1860641 INSTALLATION DOWNLOAD_MGR Download Manager remembers credential settings6 n8 x$ e$ b% B. L" y) I
1867195 INSTALLATION DOWNLOAD_MGR Download manager crash
8 X7 i% ]- J0 G- Z' E6 K ?1872187 SIP_LAYOUT DRC_CONSTRAIN Sliding a cline removes DRC markers but updating DRC shows more DRC markers
0 K P& v# h. X ?/ x3 a$ o8 ~5 O) u: m
/ H& {( M( i4 G/ i; Y- gFixed CCRs: SPB 17.2 HF034
C& @5 |: R: Q$ P, J* f! ]9 l3 v02-11-2018/ b/ ~ E* r. s
========================================================================================================================================================
; h: P; A. s' H7 f6 p8 H( ~CCRID Product ProductLevel2 Title
% h; k& ?9 h- P! K========================================================================================================================================================) q1 g. b6 R$ t ~' S
1863981 ADW ADW_UPREV adw_uprev is taking a long time after installing hotfix 0312 L' {' J. y. J. E7 B
1868186 ADW DBEDITOR Configured LDAP authentication giving error on launching DBeditor after ISR31 installation! R3 P \! a, p! k2 a
1861524 ADW LIBDISTRIBUTI Library distribution is checking for obsolete classifications every time it is run hence taking more time
+ ?+ P4 s; E1 f1 {" }" y& c1842998 ADW LIB_FLOW Footprint model check-in fails with verification checks failed error
* a' K- U: S+ @1863047 ALLEGRO_EDITOR DATABASE The layer added above the TOP layer in SiP Layout cannot be deleted from database.( Q$ l& Z2 ]8 j4 ^' \3 P
1852799 ALLEGRO_EDITOR DFM Refresh symbols crashing inside constraint re-enablement code
6 Y+ H0 v% e8 |: w/ p9 I; N1865732 ALLEGRO_EDITOR DFM The Thru via hole to Pad check in Annular Ring should check only the Finished hole size instead of backdrill diameter! `) u$ U8 {" S; g
1862977 ALLEGRO_EDITOR DRC_CONSTR Differential pair phase tolerance DRCs introduced in release 17.2-2016 DML-independent flow, F( f8 G8 S) t' w8 r. H) k) L; r
1864460 ALLEGRO_EDITOR EXTRACT Running Extracta from outside using command window writes layer name for top/bottom layers incorrectly for SiP designs4 d o" j; L- ~9 @& T! k
1859208 ALLEGRO_EDITOR GRAPHICS Pop-up menu remains on desktop when PCB Editor is minimized* y7 z! _6 q1 n
1866422 ALLEGRO_EDITOR MANUFACT Backdrill update taking a long time* x* n% a* _* o1 B
1867148 ALLEGRO_EDITOR MANUFACT Backdrill update taking longer time to process.% Y- F! |7 J9 ?0 X5 a
1872127 ALLEGRO_EDITOR MANUFACT Backdrill performance issues - Additional fixes required for S0349 I, Z; H0 z+ r' j4 R& `
1866577 ALLEGRO_EDITOR SHAPE Board becomes unresponsive on Shape Update or Slide Trace! ^$ ~) P) x% z5 r
1867590 ALLEGRO_EDITOR SHAPE The Shape to Pad clearance on multi drill oblong padstacks is not working correctly
9 \3 x" R' |( f) i+ T0 \1871902 ALLEGRO_EDITOR SHAPE Void issue during rotation of symbol with multi-drill padstack from hotfix S0325 N, M" k0 k1 m6 N( k
1866778 ALLEGRO_EDITOR UI_GENERAL Unsupported prototype 'Enable_command_window_history' is not allowing text edits using arrow keys% m7 H' W3 \1 r& U5 Y
1865757 ASDA DESIGN_CORRUP SDA hangs when trying to save design or copy page or circuitry
, |% q# Z. `- Y. x# k1 U' @1865872 ASDA DESIGN_CORRUP Corrupt design crashes on editing.
2 @3 }$ W" O7 Y* A1867039 ASDA DESIGN_CORRUP Design corruption issues
& F1 ^+ y. v6 f1831263 CAPTURE OTHER Toolbar refresh is very slow on windows 10 after installing latest windows patch
* T) t+ q8 o' |! l- O4 X1 H, v( J/ X1843595 CAPTURE OTHER Icon refresh is very slow on Windows 10 Professional after installing Hotfix 029
+ H+ I5 e! j* J1845003 CAPTURE OTHER Application slow to respond after running for a long time8 a& y8 E9 R6 b3 E* ]$ R' k! w9 N
1847062 CAPTURE OTHER Starting OrCAD Capture redraws the toolbar icons many times.1 J4 {6 K1 c. ^* B
1850816 CAPTURE OTHER Capture redraws toolbar very slowly and repeatedly, j4 D5 r: t, f# E) Y6 ]# d
1851346 CAPTURE OTHER Capture CIS redraws toolbars repeatedly' g: P3 K" e6 @3 O( o' [, v
1851354 CAPTURE OTHER Capture slows down in Hotfix 30 as tools icons are repeatedly redrawn very slowly
- H; j. K! K+ k- s* l, o% b1851883 CAPTURE OTHER Toolbar content refresh is very slow
) e+ k/ p7 @* h8 D+ ~& D$ I; T4 Q1852819 CAPTURE OTHER Capture refreshes toolbar again and again! S' Y; l- H7 ~: ?6 J$ u
1853395 CAPTURE OTHER Release 17.2-2016: Capture is refreshing toolbar icons many times at startup with latest hotfix6 v( D: R5 V, M# s) y
1853972 CAPTURE OTHER Capture starts and redraws toolbar very slowly; X( |4 i; R+ L
1854735 CAPTURE OTHER Capture toolbar reloads multiple times1 y. e6 f8 V, O7 c
1855850 CAPTURE OTHER Toolbar content refresh is very slow
! ?& N3 X! ?, V$ I& A1857523 CAPTURE OTHER Toolbar icons refresh multiple times and very slowly in release 17.2-20168 w6 D5 z% f1 n, K5 ?: y5 o6 I; ^
1859219 CAPTURE OTHER Toolbar is refreshed multiple times while starting Capture CIS- m' w* G, n3 [* c6 i7 M, |
1859626 CAPTURE OTHER OrCAD Capture does not work with the latest Windows 10 update
3 V8 ]# H) I/ \/ g8 m1863341 CAPTURE OTHER Toolbar icon refresh is very slow' ] _+ j5 k; b9 ^& q% d% [' i6 @
1865661 CAPTURE OTHER Release 17.2-2016, hotfix 032: Capture extremely slow on Windows 10
8 o+ e8 S" S6 L! o# B" B1867009 CAPTURE OTHER Slow graphics with Design Entry CIS on Windows 10.
3 w: U8 `4 a$ q8 X% b) K1869160 CAPTURE OTHER OrCAD Capture poor performance (toolbar related)
; C' Z7 u7 J. t) _* ?1869692 CAPTURE OTHER Redrawing of toolbars on Windows 10
, A; X% S1 f! u) x1 x+ O% C7 d1870310 CAPTURE OTHER Allegro Design Entry CIS redraw issue
5 O) }7 i- }5 k1870367 CAPTURE OTHER OrCAD Capture Slow Redraw
2 c: v6 N( ~% Z) x$ [1871382 CAPTURE OTHER Schematic will not open and toolbars refreshed repeatedly
" z: r# Q* ]/ b% Y3 [+ g( t8 r1872427 CAPTURE OTHER OrCAD Capture freeze on Windows 10
0 H# o3 v! t9 v, n1862679 CONCEPT_HDL COMP_BROWSER Unable to input property value to search in Part Information Manager; y/ L ~# C: c% H9 O+ r% @* J
1865039 CONCEPT_HDL CORE 'Save Hierarchy' of a release 16.6 design opened in release 17.2-2016 results in unexpected part changes
9 z% n6 [! y" ?; n5 g9 O6 M! _' ?/ N& b1866544 CONCEPT_HDL CORE XNET_PINS added to migrate Design as DML Independentflow does not get saved in the CSA files4 t* F" {' @" V
1849363 SIG_INTEGRITY SIMULATION Differential impedance calculation shows ZERO when changing dielectric constant
; J0 J- s0 x' B# ]% T) Y1854195 SIP_LAYOUT UI_GENERAL After setting 'enable_command_window_history' in QIR5/Hotfix 031, Edit - Text no longer functions
. G8 G( W; f9 f5 b, b3 W, c
* t# d/ T& _6 F
' W& R/ y, M3 a9 ?$ Y) t% nFixed CCRs: SPB 17.2 HF033+ N) N6 L* N* r% U, Z
01-25-2018
1 @5 F) K4 d& b! H9 t========================================================================================================================================================
; [5 v: H2 x) KCCRID Product ProductLevel2 Title, a# e; Q: O( E4 t3 f* r) p
========================================================================================================================================================
$ U/ L! r# e1 R4 X, }6 b! U( o0 N' s1828672 ADW ADWSERVER LDAP connection error while trying to log in to DBeditor
9 u/ i& v. e+ d) v( e; [" h1840699 ADW DBEDITOR Unable to release footprint model due to older version being linked to a DE-HDL Block Model7 [9 z0 g4 B( m7 C* n! V
1852402 ALLEGRO_EDITOR DATABASE Cutouts are not converted correctly when opening release 16.6 board in release 17.2-2016
0 n2 D6 x; b2 { j6 `1855223 ALLEGRO_EDITOR DATABASE Release 16.6. BoardOutline not fully converted to release 17.2-2016 Cutout Layer
$ X& j/ Y9 D: t) T) s( t2 @1855252 ALLEGRO_EDITOR DATABASE Unable to open a previously saved release 17.2-2016 database& y+ ^3 Q; _( \4 }. ^) Q
1863025 ALLEGRO_EDITOR DRC_CONSTR Shape voiding to Via pad with backdrill keepout is oversizing the Dynamic shape void by the backdrill keepout" F3 O/ }" u+ D' E3 k6 {
1854087 ALLEGRO_EDITOR EDIT_ETCH Sliding arc crashes PCB Editor" c! p- O9 U# N0 G
1840667 ALLEGRO_EDITOR INTERACTIV Choosing 'Change Text block to' from pop-up displays message 'E- (SPMHGE-150): Text font is not defined'
$ T5 @3 h$ X- h# Q1 a1849133 ALLEGRO_EDITOR INTERACTIV On choosing 'Change Text block to' on text , 'Text font is not defined' message appears! h9 K# |8 a3 o6 q
1854695 ALLEGRO_EDITOR MANUFACT PCB Editor crashes while performing nc_route
/ N3 Y& J* v6 B( G" W1854634 ALLEGRO_EDITOR NC NC Drill file is generated with half the number of Drill Holes on enabling 'Optimize drill head travel'( O f) f2 c- n
1856773 ALLEGRO_EDITOR NC Issue with Optimize Drill head travel in hotfix 031: Missing drill holes
+ t3 D4 e" q4 ^0 r' y4 g. L: d1860876 ALLEGRO_EDITOR NC NC route critical difference between hotfix 031 and 022: No slots found warning, V+ I0 Z! |/ u% Q5 W
1758671 ALLEGRO_EDITOR OTHER Export parameters takes long time to export and some times the process hangs4 ?! B8 e2 y/ y
1040989 ALLEGRO_EDITOR SHAPE PCB Editor crashes while editing board outline
1 n( I, _& y4 E( t1328385 ALLEGRO_EDITOR SHAPE Check for missing thermal reliefs when shapes overlap8 `5 N |1 P- l* L0 @
1366376 ALLEGRO_EDITOR SHAPE Thermal created for Xhatch shape overlapping another shape, but not created when solid shapes overlap$ _2 ~, Z( i* s% ~4 ?
1716436 ALLEGRO_EDITOR SHAPE Acute angle trim should not violate DRC.
' r0 z/ \9 w: D5 m1 k9 w1822377 ALLEGRO_EDITOR SHAPE Setting shape parameter Acute angle trim control to Full round produces unwanted shape to keepout DRCs
* J9 j! d' u8 W: ?2 B4 W1826436 ALLEGRO_EDITOR SHAPE Same net shape to hole spacing not voiding shape for cline of different net moved close to vias of same net shapes
+ y y- U x7 J/ D+ A' N1834510 ALLEGRO_EDITOR SHAPE Same Net Shape to Via Spacing does not always clear correctly7 g/ P& R9 C3 w8 K; n& h3 Q" ^# I9 s
1850716 ALLEGRO_EDITOR SHAPE 'DiffPair combined void for vias added with Return Path option' does not work with fillet and pad suppression, x8 f6 e/ ^; `/ _
1852814 ALLEGRO_EDITOR SHAPE Thermal reliefs are not created after placing modules.
- {( b/ m( ] h0 I+ `+ I2 J1853453 ALLEGRO_EDITOR SHAPE Route keepout clipping of cross-hatched shapes needs to be corrected! L% F+ l# `0 c) D( z0 [
1859391 ALLEGRO_EDITOR SHAPE Shapes are not using 'minimum aperture for gap width' for voiding after back drill update.
! g8 @( k* q/ ^1859410 ALLEGRO_EDITOR SHAPE Shape to Teardrop is not using same net spacing rules
; l% h2 V9 h; d1825397 ALLEGRO_EDITOR UI_FORMS Option panel disappears in release 17.2-2016- o6 j; k4 a, L# V0 B# c! ?
1854070 ALLEGRO_EDITOR UI_GENERAL enable_command_window_history prevents many aliases and commands from working correctly
' x9 ?1 w) X0 X# ?+ L1855180 ALLEGRO_EDITOR UI_GENERAL Comma and dot do not work in funckey if 'enable_command_window_history' is set
+ S3 Y7 u4 F" V+ _+ J1860003 ALLEGRO_EDITOR UI_GENERAL Icons and features missing or behaving differently in release 17.2-2016, Hotfix 031, q& i! |8 k7 N. f/ j) @% R. a- A9 v7 S
1861278 ALLEGRO_EDITOR UI_GENERAL Icons and menus missing in PCB Editor in release 17.2-2016, Hotfix 031* b5 U2 n7 u/ z {& w# K0 |3 R) _
1862292 ALLEGRO_EDITOR UI_GENERAL Layout Pins icon missing in toolbar in Symbol Editor since Hotfix 031
* ~! }: q6 O. C& B% {1793284 ALLEGRO_PROD_TOOLB CORE Limit View (V1R, V2R, COM) for OUTLINE layer.
1 O! i/ X J, x0 j' W- F- n1712701 ALTM_TRANSLATOR CAPTURE Third-party translator shows error for missing operand; G( }5 F" R# b. {
1802182 ALTM_TRANSLATOR CAPTURE Imported schematic has connectivity loss' C( N7 c4 e7 m$ }2 c
1802462 ALTM_TRANSLATOR CAPTURE Hierarchical ports placed incorrectly for imported third-party design8 G* k5 h- `/ ?
1823935 ALTM_TRANSLATOR CAPTURE Translating third-party schematics with hierarchical pages from Design Entry CIS4 h0 Y) d5 F4 a D G+ j
1830570 ALTM_TRANSLATOR CAPTURE Third-party to Capture translation is translating only one page out of 32) g: A; k1 g% Y# G1 C
1839627 ALTM_TRANSLATOR CAPTURE Third-party translator is not importing complete schematic
, y" w: E' T. q, |- F; u3 x( Q1846965 ALTM_TRANSLATOR CAPTURE Cannot translate third-party schematic. U" m# I7 X) v7 G
1816767 ALTM_TRANSLATOR DE_HDL Error when translating third-party schematic to DE-HDL, J8 r+ E8 Y9 n- Q
1845601 ALTM_TRANSLATOR PCB_EDITOR Cannot operate third-party PCB translation in release 17.2-2016 Allegro Venture PCB Designer license
7 J6 K: I4 L' ]1841060 APD DIE_GENERATOR Cannot 'die text out' from SiP Layout or Allegro Package Designer/ o- y/ @4 Z2 G1 G$ ?% u
1793232 APD SHAPE When fillet/taper not connected to a pin, voiding process incorrectly applies shape clearance values1 \: N+ `; U. w/ {1 O
1846541 APD SHAPE shape degassing does not obey void to shape boundary3 m$ C9 h' O* R, z* B/ x; I
1863446 ASDA CONSTRAINT_MA A space in the name of a spacing or physical constraint results in the incorrect constraint set name( e5 ^2 k8 ~; }$ J3 @ @
1859678 ASDA VARIANT_MANAG SDA - When hovering over all three buttons, under Preferred Parts in the Variant info it says (Do not install). @4 v9 {; O0 P/ S
1815839 CONCEPT_HDL CORE Allegro Design Entry HDL crashes when entering Location data manually
& X" a2 y, m4 {$ K! K1841857 CONCEPT_HDL CORE Unable to modify Components in non-windows mode
* A" v5 U* q9 p+ F9 V! X1852096 CONCEPT_HDL CORE Creating a block using top-down approach does not generate the CSB file
" ~: B* S, `4 N3 @* Q g# [, y* }1857390 CONCEPT_HDL CORE DE-HDL crashes on moving symbol
1 L! k% Q) r O/ g1 v0 g/ b1789070 CONCEPT_HDL OTHER Having folder 'allegro' in cpm root directory gives error while launching layout editor from Project Manager4 S& s' n l0 }# x' Z- h: q! x
1862484 CONSTRAINT_MGR CONCEPT_HDL Extracting an ECSet in SigXP is missing a t-point
) o* u- w: g& |' E5 J( K6 Y; x1863045 CONSTRAINT_MGR CONCEPT_HDL Pin pairs deleted for a few differential pairs after upreving the design to release 17.2-2016
7 e; l0 [! y ]! X1863054 CONSTRAINT_MGR CONCEPT_HDL Differential Pairs are treated as invalid objects on upreved design
1 i- a6 A' o8 A0 b/ f2 e1863094 CONSTRAINT_MGR CONCEPT_HDL Pin-Pairs are shown duplicated in the topology for the extracted object (Diff Pair)
- t0 N6 P/ m$ l1831998 CONSTRAINT_MGR OTHER 'Tools - Options' settings not saved on closing Constraint Manager
E5 I3 ~* r: H2 D1855324 CONSTRAINT_MGR OTHER Enable the option 'Expand Hierarchy' in 'Find and Replace' dialog, by default
( [+ c+ ^9 E6 J1 f/ q1860847 CONSTRAINT_MGR OTHER 'Include Routed interconnect' option once enabled, should remain enabled for that board file) `8 g( }. U- x6 k
1843359 EAGLE_TRANSLATOR PCB_EDITOR While importing third-party PCB, many footprints do not convert, even though the log file says footprint created: f4 f! D7 x( [$ U6 o/ j. J" B
1839978 SCM REPORTS dsreportgen unable to output reference designator from a lower-level hierarchical block if it has a single component
& o) `' M9 u6 J( L* n2 R r1850013 SIP_LAYOUT OTHER Environment variable 'icp_disable_cte_auto_update' needs grammatical change
+ d m& s: b- ^& a! b1833742 SIP_LAYOUT PADSTACK_EDIT When creating Die to Die Via using Generate Padstacks, resultant pad stack has wrong Layers
) g6 x8 V0 ~" o* T; U$ @$ q2 ~1619098 SIP_LAYOUT SHAPE Acute angle of shape in design
9 l; i) F* T, R0 R, @; Q6 `6 `1728628 SIP_LAYOUT SHAPE Auto-void in dynamic shape does not disappear if object is removed- |! t+ w: C! c' L: ]
1854592 SIP_LAYOUT VIA_STRUCTURE Create via structure returns an error
! W1 f J% K9 q# ]9 |$ ]
, P# c; ^( r/ Y# A9 [8 }/ r2 w% { O" O( I7 f: u2 K
Fixed CCRs: SPB 17.2 HF032& }! W! f; [7 b* v2 x. T+ N+ }
01-13-2018+ c( Q: G# z# l9 U( G$ J
========================================================================================================================================================# z1 p9 U) V. ~1 Y1 p" M; g! V
CCRID Product ProductLevel2 Title' F$ z$ b* E' g* Z. V
========================================================================================================================================================* p) B) ?, X3 N
1846603 ADW FLOW_MGR Copy project GUI not displaying correct design name after changing the project folder name. C/ S% ~% L+ x5 @" |$ U: b: g9 `
1831152 ALLEGRO_EDITOR 3D_CANVAS New 3D viewer canvas is blank: T' a8 r: y6 M/ g8 S
1805870 ALLEGRO_EDITOR COLOR Color file with dot (.) in the filename is not recognized for setting color from the Visibility tab
6 ~( |6 P2 ^2 u% n# t8 ?) C1843126 ALLEGRO_EDITOR DATABASE DBDoctor UI is taking very long# ]( P% ~0 s5 q% N# B! t! ]; r
1857588 ALLEGRO_EDITOR DFM Design for Fabrication - Aspect Ratio is not taking correct drill hole size
. @# z# `$ O! ~$ Z& ]2 \( k1844313 ALLEGRO_EDITOR INTERFACES STEP output viewed in third-party tool has parts sunken into the secondary side
9 @1 j% n! a% d6 V8 q1801301 ALLEGRO_EDITOR MANUFACT Export IPC 2581 fails if VOLTAGE property is attached to the nets on each side of a RF component% s* A; ]! T2 s' _. h3 _
1850078 ALLEGRO_EDITOR MANUFACT Choosing 'Manufacture - Artwork' crashes tool4 g9 B& E: ~8 l% F+ E! c5 m: k/ l3 l
1844049 ALLEGRO_EDITOR MODULES Module deletion not removing related component information.$ ]: u" w# I- N5 K0 d. }
1849665 ALLEGRO_EDITOR MULTI_USER Shape rejected by muserver
+ `: v) E- V" C& x) I1782831 ALLEGRO_EDITOR RAVEL_CHECKS RAVEL file does not load when it is located on a network with a UNC path specified/ m. W, t- a' q) w4 k
1830442 ALLEGRO_EDITOR SCHEM_FTB Fail to import technology file with message for failure to read the configuration file
! z, a" a' ?6 b7 g3 b1837391 ALLEGRO_EDITOR SCHEM_FTB Capture Property cannot rewrite or update constraints in PCB Editor4 K% g! v' @) {6 l5 m
1840643 ALLEGRO_EDITOR SCHEM_FTB Export physical does not work after modifying PCB cross section2 x1 M* ?* k! e& f( ~
1718165 ALLEGRO_EDITOR SHAPE Drill hole cannot be voided by shape5 V: B" D( r/ e; r4 G
1753245 ALLEGRO_EDITOR SHAPE Update Shape retracts more than the shape to shape spacing9 g2 H5 V8 y) }& ~, O
1827366 ALLEGRO_EDITOR SHAPE out of date shape is not flagged as out of date
, {9 M. O. r' D1 \( f" S( ~8 |) Z+ t" r1828208 ALLEGRO_EDITOR SHAPE Shape remains out of date, but status shows otherwise
9 ^% w" R, N! `4 h# u3 j1832098 ALLEGRO_EDITOR SHAPE Skip via shorts to plane at few places even after the necessary keep-outs are assigned to the via pad-stack.6 ~9 I0 I. O& x
1834281 ALLEGRO_EDITOR SHAPE DBDoctor creates a large number of DRCs0 P8 h# [* L: Q) z& j% u
1842121 ALLEGRO_EDITOR SHAPE Unable to clear the Drill Hole to Shape Spacing DRC as Pin is not able void to the shape correctly.7 L& b8 z- P; Y0 I, \* A
1846010 ALLEGRO_EDITOR SHAPE Changing MCAD hole to copper spacing in Analysis Modes - Design does not make shapes out-of-date1 k) O" z! b) j
1839119 ALLEGRO_EDITOR UI_GENERAL On some machines, PCB Editor hangs when launched with a script that uses SKILL to open a design
$ s6 P: s. ~5 W% T( `$ d% ~' f1828794 APD SHAPE Setting Shape Fill Xhatch Cells option to HIGH, crashes the application( s8 y3 ~! |% I+ m* s% G5 k4 l
1840748 CAPTURE PROJECT_MANAG Capture crashes on opening or creating designs( u6 A* |* l: b L
1785298 CONCEPT_HDL CORE Incorrect object access during variant load
3 I4 a: ]- d' g: @, I# \1832119 CONCEPT_HDL CORE Save Hierarchy shows ERROR(SPCOCN-2010) messages but design packages without error# Z6 D9 P3 C6 H/ b2 Z+ y( w5 w
1833036 CONCEPT_HDL CORE nconcepthdl crashes with a core dump when running an external script. P5 U" m( V/ U3 V f
1841545 CONCEPT_HDL CORE NO_XNET_CONNECTION properties added to two-pin filters after upreving to release 17.2-2016
- L) ]* x( m& H; A1 {# {1842289 CONCEPT_HDL CORE Opening a schematic in release 17.2-2016 causes the .dcf file to be overwritten. e6 f( i- q4 ^1 \$ i" V6 t l
1841543 CONCEPT_HDL OTHER DE-HDL crashes when changing a net name/page name/bit bus after installing release 17.2-2016, Hotfix 029
9 F, t& g7 A; j# I; B2 |1843791 CONCEPT_HDL OTHER Table of contents listing does not update for some hierarchy blocks at the top level `+ d0 a3 i# M K9 R$ [
1850709 CONCEPT_HDL OTHER DE-HDL crashes on editing text on canvas in release 17.2-2016, Hotfix 0305 g% r4 r& v: z2 t; t( m, y
1853377 CONCEPT_HDL OTHER DE-HDL crashes on trying to edit bus tap value on Windows 10.
0 T5 U" p3 z3 V5 ~( j1857213 CONCEPT_HDL OTHER DE-HDL crashes when changing Power Property
) x* |; U' I# n; y0 L; {1 p, P' ~1857214 CONCEPT_HDL OTHER In release 17.2-2016, DE-HDL crashes on using 'Change' for a $LOCATION text value on Windows 10
) h& d. v( \% F% I- E$ N1821982 CONCEPT_HDL PDF Pin number shown in PDF published from DE-HDL
1 m9 N4 E F! j: v% @: S1848615 CONCEPT_HDL PDF PDF Publisher shows incorrect pin text values for parts
! Z& p! ~/ k+ `6 }, ~1845996 CONSTRAINT_MGR CONCEPT_HDL Confusing error message regarding 'Auto XNets Off Mode' vs 'DML Enabled'
9 b1 i# c% ?) n1854190 CONSTRAINT_MGR CONCEPT_HDL 'Audit - Electrical CSets' hangs Constraint Manager after the design is upreved to release 17.2-2016/ j' a: k! i, X, b
1854868 CONSTRAINT_MGR CONCEPT_HDL Match Group getting deleted after upreving the design to 17.2 and removing the signal_models
2 z, b4 {, }8 l: i- k+ ~1854872 CONSTRAINT_MGR CONCEPT_HDL Additional Pin-Pairs getting created on the DiffPair after upreving to 17.2# r7 J; W! q8 b
1822624 CONSTRAINT_MGR ECS_APPLY Cannot copy PCB net schedule from a net to other nets
; {6 m: Y9 B1 W8 m! [1854883 CONSTRAINT_MGR ECS_APPLY Match group showing 0 length for pin pairs in design upreved from release 16.6 to 17.2-2016
; l' z9 o: d5 J# R- s1855893 CONSTRAINT_MGR OTHER SigXplorer extraction crashes PCB Editor
; V: ~5 s3 @1 a% \3 ?9 Q1855917 CONSTRAINT_MGR OTHER SigXplorer extraction does not extract constraints unless the worksheet is opened once in CM" E. N9 v. X6 C+ t" R
1855350 CONSTRAINT_MGR UI_FORMS Constraint Manager significantly slower in release 17.2-2016, Hotfix 031
1 P, a1 ?, L8 ~, P1855860 EAGLE_TRANSLATOR PCB_EDITOR Cannot invoke a CAD translator in PCB Editor
: S, o" S. K; E5 i7 q1857745 EAGLE_TRANSLATOR PCB_EDITOR A CAD translator does not invoke in PCB Editor+ [/ n. v8 z) d& `/ M. q9 W
1859005 EAGLE_TRANSLATOR PCB_EDITOR Eagle translator is not invoking at all
/ ]% g, k" i' W& h" ?& Y1843091 F2B DESIGNVARI Variant Editor allows mismatched JEDEC_TYPEs in release 17.2-2016
1 y' K5 {" @3 a. |% \% u7 {1719059 FSP DE-HDL_SCHEMA Termination resistors on buses not being drawn efficiently
9 V( B. A. y+ `9 `1823419 FSP GUI Net Name Template not visible in Change Net Name in Windows 10
0 b$ `; E3 w- y+ w1 x1480035 ORBITIO ALLEGRO_SIP_I Die symbols are mirrored when imported back to SiP Layout5 g5 h+ V) N3 F( h5 l! _3 D; }5 V
1853331 PCB_LIBRARIAN SETUP CPM file not updated from PCB Librarian setup6 f) u+ j( c0 f6 S5 \% O+ r
1841308 PCB_LIBRARIAN SYMBOL_EDITOR Symbol not updated in Library View
$ \6 z3 T" g* B5 I' j1831269 SCM OTHER Blank properties of associated components are being filled with NULL$ d4 z4 S$ S1 ~5 I3 ]+ w
1719057 SCM SCHGEN Pins off grid for voltage nets3 g; B( ]% e& G. U: R7 D' y0 Q
1719060 SCM SCHGEN Pull-ups and pull-downs showing upside down in view% M5 y: H! ^( C
1732687 SCM SCHGEN Schematic generation deletes IO ports; says it's placing them on last page, but never places them. k* N+ [+ S+ q& B: S: D+ l
1855932 SIG_EXPLORER OTHER For non-DML designs, SigXplorer defaulting to mils when PCB Editor design units and CM constraints are in mm
/ J# F; \ X! J4 D1824035 SIP_LAYOUT WLP SiP Layout DRC GUI not reading Tcl blocks in PVS DRC rule deck+ y H& j# n o' W, o% R' ?
5 f( \4 ~( j, P- x" f$ m" F
: ?" ?. }# b1 `Fixed CCRs: SPB 17.2 HF031" }# _3 m/ e c8 |
12-8-2017
% g8 `1 k, z, c$ r, k========================================================================================================================================================
4 K% g; s k6 m B l LCCRID Product ProductLevel2 Title4 a5 p; X, q* }1 r. Z0 }5 f: ^
========================================================================================================================================================
% d6 l9 y; P X6 Y& S8 O- f1746108 ADW DBADMIN Adding and then saving a custom rule set in rule manager results in corrupt rules.xml1 k" E. h/ U# j/ t7 M1 b7 _" l6 `
1609983 ADW DBEDITOR dbeditor should automatically change mechanical kit names to uppercase
( l$ x* o l5 X. ^: h$ X) [/ o1807139 ADW DBEDITOR Cannot add new properties, though the new properties were shown in dbeditor& O8 j+ J! O8 J$ c, S$ }
1807410 ADW LIB_FLOW Checked-in parts not available in database
) q1 }0 B# [; A( n7 m/ q/ z* P1797408 ADW TDA TDO crashes without displaying exception during check-in) k1 D+ ~. Z" C9 U7 F+ F: N! r& t
1804500 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas fails to show all placebounds of a .dra* R J- ~& m3 I- s4 U) \6 }
1810758 ALLEGRO_EDITOR 3D_CANVAS 3D Viewer represents symbol incorrectly in hotfix 025 but as expected in hotfix 024* B$ F* I b' y7 ` V/ m% p
1795567 ALLEGRO_EDITOR EDIT_ETCH Route menu has same hot key for 'Connect' and 'Convert Fanout'. U' b2 x% e. d' a2 ] o1 y6 }
1796525 ALLEGRO_EDITOR EDIT_ETCH AiPT is not pushing dynamic shape to add bumps to resolve dynamic phase DRC9 W b/ L6 W1 F7 I3 [5 m8 c
1818170 ALLEGRO_EDITOR EDIT_ETCH Fanout with Outward Via direction is shorting few pins
( z- Z6 C. v9 g4 ?7 ^* _1712658 ALLEGRO_EDITOR INTERACTIV Add connect: Pin remains highlighted even after choosing 'Done'
0 Y- a1 j7 i& q. y: D% E/ I1727193 ALLEGRO_EDITOR INTERACTIV Logic - Part List truncates device names to 64 characters though database allows longer names
, d( b0 P2 E$ J3 q0 G! D1775484 ALLEGRO_EDITOR INTERACTIV Choosing Next with persistent snap in Show Measure disables persistent snap; U! Y- C" F' C; Z
1711860 ALLEGRO_EDITOR MULTI_USER Multi-user lock cannot be cancelled% Y0 [0 t" ]# q, W
1812448 ALLEGRO_EDITOR NC Crash when canceling NC Parameters dialog
% s2 S! i N: T d) z3 E6 l1792987 ALLEGRO_EDITOR PAD_EDITOR Pad Designer does not recognize flash names longer than 31 characters! }& R8 X* q1 O! i! c
1810958 ALLEGRO_EDITOR PAD_EDITOR Padstacks with offset holes
+ Z B5 K/ ?8 l9 }7 S( A. e787024 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in regions
/ a4 I( s" z- o% I" H: {( y793232 ALLEGRO_EDITOR SHAPE Line to Shape spacing rule outside region affects shape void in region
8 n' T4 x1 |1 @% ]; q' T/ N797245 ALLEGRO_EDITOR SHAPE Line to Shape Spacing with Region not followed
8 a; S+ p) o. L) A865822 ALLEGRO_EDITOR SHAPE The autovoid functionality should use the true line-to-shape spacing value
1 Y, t4 N. J' m& `$ F/ u) g912051 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in regions
' T* p% A/ R6 X, A, ~% E965714 ALLEGRO_EDITOR SHAPE Region constraints are not working correctly on dynamic shapes- q d# Q) Q+ L3 ~3 ]) \# v/ V
968342 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region is taking conservative value and not the actual spacing value
; s' c9 K; n- J7 N/ l974734 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value+ `; a3 r+ W2 m% J9 w6 _/ g, F
1073908 ALLEGRO_EDITOR SHAPE Allow line to shape spacing in Region
D3 h5 W' h+ O. w! C! J1154787 ALLEGRO_EDITOR SHAPE Region constraints not applied correctly to dynamic shapes8 \) Q) V* c7 ]: W
1171283 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value& D; R; b! h0 w
1181767 ALLEGRO_EDITOR SHAPE Allow override on line to shape spacing in Constraint Region, k4 V- K9 e- W& ]
1183792 ALLEGRO_EDITOR SHAPE Allow override on line to shape spacing in Constraint Region
5 |/ c5 O- q3 L: u) B2 |1 ?: K1186210 ALLEGRO_EDITOR SHAPE Line to shape spacing constraint does not follow the Constraint Region value
) a; S2 \. {# ]1 ^1192312 ALLEGRO_EDITOR SHAPE Region constraints are not working correctly.
; V1 o2 j @. P; }- _6 d1387021 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in Regions
" \# a7 {% x" u/ F1447891 ALLEGRO_EDITOR SHAPE Resolved constraint and actual air gap differ
9 `! {5 u2 F4 ~0 V1 a1465383 ALLEGRO_EDITOR SHAPE Line to shape spacing constraint does not follow the Constraint Region8 F/ P* B0 [- u& y$ B9 ?3 n9 u# W
1583144 ALLEGRO_EDITOR SHAPE Line to shape spacing inside the constraint region does not follow region rules
9 }6 o$ l- N; a1591320 ALLEGRO_EDITOR SHAPE Resolve shape to pin constraint in constraint region
% H- x. H$ e) ?2 c% j4 T4 l% Q1627305 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value+ Q! U2 Y3 n6 X4 Y' _$ F5 ~' _/ v
1694552 ALLEGRO_EDITOR SHAPE Constraint region not working correctly" v' {$ k4 _; W
1764474 ALLEGRO_EDITOR SHAPE Line to Shape Spacing for Region should be used inside region instead of conservative value
) e" _' |. r2 F4 @6 n1775119 ALLEGRO_EDITOR SHAPE Shape voiding is not following constraint rules for dynamic shapes in a constraint region
. ^& ]0 }( |3 X$ ~1784916 ALLEGRO_EDITOR SHAPE Shapes are not voiding to other shapes against DRC settings, creating random DRCs.3 ^/ c! z w; x1 K1 x
1793179 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
/ E8 O: O- o/ F: }( N; b1803365 ALLEGRO_EDITOR SHAPE Region shape to shape constraints take precedence when shapes have multiple constraints
8 g8 z& h: ~: @6 c6 l1800530 ALLEGRO_EDITOR UI_FORMS 3D Anchor menu missing when using new style OrCAD PCB Editor menu2 t2 r% U: J* O; B- L h
1813604 ALLEGRO_EDITOR UI_FORMS 3D Anchor View is not available on OrCAD PCB Editor menu.1 s0 O& E/ B% k- Z# X& k
1784710 ALLEGRO_EDITOR UI_GENERAL During Place Replicate and saving file with same name, the warning pop-up window does not show on top8 ^0 @) @8 b$ q
1784728 ALLEGRO_EDITOR UI_GENERAL During Place Replicate and saving file with same name, the warning pop-up window does not show on top- Z+ I1 Y; u' c1 K, [/ S
1721853 ASDA CANVAS_EDIT Movement of components results in shorts and inconsistent routing
: O" z- b( g) i) ], x1802120 ASDA CONTEXT_MENUS Ports are selected though filter is set to Components6 T/ S7 M. k7 u6 _$ K, Y6 t
1803832 ASDA MISCELLANEOUS Browse and select new libraries without editing cds.lib4 Y" }- l( P3 u/ R) J, `. x# `1 _
1804643 ASDA TABLE Exception when pasting table data from third-party tool in SDA
0 \6 Q4 A! E' D; v1 ^1794004 CAPTURE LIBRARY Diode pin numbers different in Capture in release 16.6 and 17.2-2016; z: M. b1 D- q$ U2 W2 R' h* F
1735506 CAPTURE OTHER File menu is missing in Capture- y7 G M5 T5 D( m& }( @( F
1766663 CAPTURE SCHEMATICS Capture crashes during part placement
. ~# J% I2 A9 W( C1762181 CAPTURE SCHEMATIC_EDI Crash on 'Push Occ. Prop into Instance'* ^( C0 o. F1 t3 P8 Q
1786762 CAPTURE SCHEMATIC_EDI 'Remove Occurrence Properties' and 'Push Occ. Prop into Instance' corrupt database. d. L% B3 j$ S% s' Z7 O
1759424 CIS PART_MANAGER Unable to save the link database part from part manager
2 [+ ]/ E1 }* T3 Z1802670 CONCEPT_HDL CORE Variant commands take 6 to 10 hours to run on a block
! K9 }0 ^& ~) m: n/ v! y0 F1816798 CONSTRAINT_MGR CONCEPT_HDL CM API ACNS_DESIGN returns the design name in mixed case
) x1 a8 U: Y6 E/ N$ _ r8 i0 P1812656 CONSTRAINT_MGR DATABASE Constraint Value specified at the DEFAULT PCSet/SCSet is not shown in bold blue& @, e( F, S+ u; Y7 X3 H% J& m: i
1635766 CONSTRAINT_MGR UI_FORMS Worksheet views are not changed as per input
( P- y$ l- H8 m8 u! l1700505 ECW PART_LIST_MAN Shopping Cart Quantity is not read or not displayed in Pulse4 w% Q9 F% I2 B1 F( e4 S% r
1797371 ECW PROJECT_MANAG Clicking on another project sometimes takes you to the default project instead of the project you click on
8 t$ R" [: T4 i2 t1 _1843526 INSTALLATION TRIAL Trial installer should not check disk space in update licensing mode
: [9 L* x8 ?! x1762148 PCB_LIBRARIAN SETUP Part Developer: Text not readable in Setup form) ?' P! w+ ~3 u' C5 R2 {4 z! I% o
1770760 PCB_LIBRARIAN SYMBOL_EDITOR Symbol Editor does not remember the last size of the window
0 J Q0 A* \) B* \1773604 PCB_LIBRARIAN SYMBOL_EDITOR Option to switch between the new and legacy Symbol Editors' @ Y4 b ~3 {3 s8 }* e
1800354 PCB_LIBRARIAN SYMBOL_EDITOR Resistor has too many lines and looks wrong in new symbol editor
& X6 _4 W* t4 W1813346 PCB_LIBRARIAN SYMBOL_EDITOR Resistor looks different with multiple diagonal lines in new Symbol Editor but looks normal in DE-HDL* h4 T* J* o/ s
1815279 PCB_LIBRARIAN SYMBOL_EDITOR Unable to change Grid Settings from Lines to Dots6 |7 D2 D: n) \" u
1738603 PSPICE DIG_SIMULATOR Release 17.2-2016 PSpice digital model: Delay defined by PINDLY is not taken into account
; {! g$ t [" t2 z1802905 PSPICE ENCRYPTION Incorrect option shown in PSpiceENC syntax in usage detail7 X2 I3 ]# ? R2 B
1765345 PSPICE ENVIRONMENT Custom distributions are not added to the dropdown) k" d8 |5 `: t( L
1784856 PSPICE ENVIRONMENT PSpice ignoring directory changes for Save check point in simulation setup session
9 ?( B* W7 d3 ^2 d$ ?/ L7 g1817805 PSPICE ENVIRONMENT Incorrect result for PSpice 'Start saving data after'$ ]4 \, {5 S2 O! V" f
1784507 PSPICE FRONTENDPLUGI Spelling of 'Definition' in PSpice Part Search is not correct
6 m' I+ x# X- n) H* f# v1801790 PSPICE LIBRARIES SAC model giving errors
2 d9 {5 H L! Y' b# B1738776 PSPICE SIMULATOR PSpice simulation stops before TSTOP
; r+ h) B! Q: \; M: V1795950 PSPICE SIMULATOR Simulation cannot be completed in release 17.2-2016 but is completed in release 16.6* x+ R' s, c! y9 U' @# y
1803407 PSPICE SIMULATOR Getting convergence error on a model: s `3 y8 ]; L
1814759 PSPICE SLPS .INC file is not working with SLPS
. L1 w- |9 v5 b# N% ]9 {1715859 SIP_LAYOUT ETCH_BACK Etchback mask not overlapping each other; creating floating metal
% B7 {( g* u' a; c: J* I# C, j( U3 I/ N1729523 SIP_LAYOUT INTERACTIVE When creating a bond finger solder mask the results do not match the required settings
' U9 h8 x X/ |1 m# d$ y1800069 SIP_LAYOUT INTERACTIVE Corrupt dra/psm symbol, but the reason is unclear
# U& d8 O9 Y3 d6 i8 u1756620 SIP_LAYOUT SHAPE Performance issue when moving vias.; o0 |+ D1 l5 Y: w& `' E
1782928 SIP_LAYOUT SHAPE Shape merging (logical operation) shows error though measuring shows elements are correctly spaced; R! \$ G' q( _8 z. u5 ^; O
1816454 SIP_LAYOUT THIEVING Thieving: need thieving as a specific data type in CM to better control the filling pattern6 P/ ?( D, J" f4 Y- P& L
1728026 TDA CORE Check-in should not require all child objects to be checked in specially if they are not checked-out) S) F7 V5 G8 T5 B4 X
1823976 TDA SHAREPOINT Connection to server terminates when joining a project
' Z' b( z: |% O0 {3 x x
$ K& K; \6 b! z( \1 }7 T# T1 P/ h* v* j- J, t
Fixed CCRs: SPB 17.2 HF030
( ~) D7 z4 D8 i# o, f8 A11-17-20170 G5 d) i% D, Z1 c) @* B; `; i9 Y
========================================================================================================================================================
; [7 @- ~* k" x7 H* x2 Y! i/ OCCRID Product ProductLevel2 Title1 n) A8 `' R$ ^+ P' E$ t. L
========================================================================================================================================================* D1 f0 H' q+ M5 s4 T9 V7 a& d0 l
1821774 ADW DBEDITOR MPN is tagged Pending Purge after deletion and lib_dist
0 E# b8 O8 Z0 N. L1 x5 ^1829549 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase DRC marker displayed at the design origin
$ P( J! S/ c% o- a- y% F1690998 ALLEGRO_EDITOR INTERFACES Runtime error when running PDF Publisher
8 i3 \/ ~9 i6 ]* U y8 i! I3 A1805203 ALLEGRO_EDITOR INTERFACES Runtime error when exporting smart PDF on a large board with all film layers selected. @' Q( r; C; w
1811698 ALLEGRO_EDITOR INTERFACES Runtime error while exporting PDF
! `# _) A1 |4 M+ J( S1823818 ALLEGRO_EDITOR INTERFACES Cannot map some step models; ~% l$ f. e4 A& ?1 w1 D& m) U0 s
1750654 ALLEGRO_EDITOR MANUFACT Cut marks cannot be generated on cut outline.; ]$ n8 z7 X/ u6 F4 u' T) V
1828293 ALLEGRO_EDITOR NC Incorrect status returned for backdrill
. g* y( `8 p0 u6 W1 p& \1825401 ALLEGRO_EDITOR PADS_IN In PADS library translation, pads_lib_in fails to create Placebound_Top as a shape& b) k; T, H" |2 u
1825427 ALLEGRO_EDITOR PADS_IN Symbol drawing files (.dra) created after PADS Library translation are not getting renamed to their decals
8 l+ v6 Z9 H; k2 w% E' N$ ?1825460 ALLEGRO_EDITOR PADS_IN Pins are moved from their correct locations during PADS Library Translation
! W/ o. K" S! _. [- l! Z1831200 ALLEGRO_EDITOR PLOTTING Incorrect PDF output for traces
/ w6 V5 D( l/ M/ m1321314 ALLEGRO_EDITOR SHAPE Force update of dynamic shape generates thermal tie that causes net to short
! ~. d3 O, u; ~* X8 `1647585 ALLEGRO_EDITOR SHAPE Void around holes is not circular but of the shape of the bounding box
7 s' ?9 f5 b- c( @* T1830676 ALLEGRO_EDITOR SHAPE XHatch Shape not voiding properly) j7 @/ `8 }% C( S3 C- L
1821286 ALLEGRO_EDITOR SKILL Using axlSetParam to set static shape clearance parameter crashes PCB Editor, U k3 @8 O: g- C7 t& w: E% |4 r
1804662 ASDA DARK_THEME Dark Theme: Change color of selected cells in Rename signals dialog so user can see they are selected; J" @7 M, U+ w- r/ I2 p8 q* `5 c3 }' h
1817486 ASDA NEW_PROJECT Need to save a project with a new name, 'copyprojectas' does not seem to work+ n3 A+ D6 L+ y9 ^
1826023 ASDA NEW_PROJECT SDA requires user to go into project settings window twice to add a library) n3 ^/ j: P: m' X9 b
1830632 ASDA SCRIPTING SDA crashes when you type 'find -types' in the Tcl command window! }. v0 m; y- \! N' q8 r
1798864 ASDA VARIANT_MANAG Retain default part visibility when substituting preferred part for variant( [# S1 r+ _* a& m. V( j- ?
1798865 ASDA VARIANT_MANAG Value attribute of variant is off while printing though on for default and view
" V' A! ~9 \& V/ a: d1798866 ASDA VARIANT_MANAG Variant Printing: Pin numbers printed though set to off on default part
1 V6 S" `6 Q; `* `1831836 ASDA VARIANT_MANAG Cannot delete existing variants in design/ i; n2 ~+ n, g: _* ^
1821120 CONCEPT_HDL CORE SIGNAL_MODEL attached to a component is not displayed on the canvas in the Attributes form
$ u4 k' c/ e% G \4 M/ }' ?1824714 CONCEPT_HDL CORE Display issue: Page border disappears when running the command _movetogrid, m+ O# `# A, b. N: u( k8 Z" V" C0 B
1822587 CONCEPT_HDL CREFER CRefer crashes on a hierarchical design using split blocks4 y- J8 P# Q& [3 \$ U4 K8 k
1825461 CONSTRAINT_MGR CONCEPT_HDL Uprevving to release 17.2-2016 adds NO_XNET_CONNECTIONS on components having custom models
, y& l- O( c: @8 m1 h1 u n1825968 CONSTRAINT_MGR DATABASE cmxlGetObjects returns all the aliased nets and the physical net that goes to the netlist; P' k: d7 l* L: `" s" _
1819622 CONSTRAINT_MGR XNET_DIFFPAIR Discrete with NO_XNET_CONNECTION removed from topology when extracted with Routed Interconnect
" e, A) ^6 ~! j' k1829762 ECW PROJECT_MANAG Pulse log in: Multiple processes triggered, generating many zip file packets and corrupting many of the packets' u! C" l$ Q- F7 |/ y9 a4 T
1810296 F2B BOM BOM includes status column, nothing should ever be forced on a users BOM output* s! G! q: x6 x. ~
1824593 F2B PACKAGERXL PXL crashes and removes the pxl.log file from the Packaged directory/ A0 y- Q( P, H6 {9 ~4 E9 ^+ n
1832005 F2B PACKAGERXL Message stating 'PXL has stopped working' when packaging design& ~/ c% Q% a0 X' o" K N( s" y6 [
1822912 RF_PCB AUTO_PLACE rf_autoplace fails for RF component containing variable
' \" Y) X' T4 f1803731 SIP_LAYOUT DXF_IF DXF export from 'Component Geometry/Pin_Number' subclass not working in release 17.2-2016
0 l; q" e: J& Q) o1825478 SIP_LAYOUT SHAPE When running the Shape Islands report it is listing all the Fillets as Islands
n$ M6 H7 Z9 g1 \2 F I
# H) e5 k1 m" [" M/ D- O' O. {% o6 i+ {0 c" T% ~9 w
Fixed CCRs: SPB 17.2 HF029
7 k' O* N2 I8 c6 F# t! W! m11-3-2017: l6 G" E& T N1 H3 w8 x
========================================================================================================================================================( B- z9 j7 c/ @
CCRID Product ProductLevel2 Title1 Z: ?& m; x+ j8 Q' z
========================================================================================================================================================3 I4 ?% x: B2 O$ J$ f
1814597 ADW DBEDITOR Associate part classification is very slow in release 17.2-2016 of Allegro EDM
0 J, l2 j2 I/ G0 V1733482 ADW FLOW_MGR After installing QIR3, Flow Manager prompts with Java Help question2 y, }- N9 z0 B$ v9 D
1814789 ADW PART_BROWSER PTF shows data in old component browser but not new component browser# f1 W# n4 |; ]4 h2 G4 T
1808620 ALLEGRO_EDITOR DFM Missing graphics in new drc browser.
/ k( U( i2 C: @6 I9 k1814558 ALLEGRO_EDITOR DFM Silkscreen checks do not work if silkscreen is defined as mask in cross section
2 h3 O- ^4 K7 G9 P' ]3 R- v4 p1807996 ALLEGRO_EDITOR EDIT_ETCH Route Clearance View is not using the correct spacing constraint when nets are partially routed in a region
, g) b8 W9 W" y1747929 ALLEGRO_EDITOR INTERFACES Cannot import logo/bmp on a .dra file( h$ O7 R% v# {4 n7 C o
1820142 ALLEGRO_EDITOR INTERFACES pdf_out command not supporting UNC paths for the output pdf file% u# @% o. @4 Q3 r4 @6 }
1671865 ALLEGRO_EDITOR MANUFACT Exceeding 20 characters in Artwork Control Form - General Parameters - Prefix displays 'Illegal Character(s)' error6 |) E/ V$ T9 z' B; d3 D
1710032 ALLEGRO_EDITOR MANUFACT Adding Artwork prefix gives error for illegal characters
+ z2 I2 ~% h+ W6 r+ D9 P1714911 ALLEGRO_EDITOR MANUFACT ERROR: 'illegal character(s) present in name or value' while adding prefix in Artwork Control Form
" Q0 e5 u4 T- W1813950 ALLEGRO_EDITOR MANUFACT In the drill chart, the titles 'tolerance_drill' and 'tolerance_travel' seem to be reversed# X3 Y5 N- K& L8 k1 I
1820970 ALLEGRO_EDITOR MANUFACT IDX_EXCLUDE and BOM_IGNORE excluding objects from IDX export
. H/ g0 f9 f* g, K: @# V2 L! F! R. `1822045 ALLEGRO_EDITOR PARTITION Shape fillet becomes static shape and loses fillet attribute after importing partition3 y$ R& a+ w" b6 {5 r
1776181 ALLEGRO_EDITOR SHAPE Placing via arrays around a differential pair places vias only for one net
7 \0 f/ h" N( j) `$ s' n! Y1817283 ALLEGRO_EDITOR SHAPE Allegro PCB Editor Show Measure Air Gap shows a very large number3 ~' q4 M3 u) i1 X
1815595 APD DRC_CONSTRAIN Differential pair spacing constraint not propagating to physical cset nets* r9 Q, e7 I7 ~! w% J7 A* g- z
1785116 APD SHAPE Big size die performance issue2 D# R6 U# q7 n, o$ J( i: }: T% T
1811134 APD STREAM_IF GDS stream out with 2000 precision has sharp edges along shapes.
8 Y! J) O8 r' k9 V w7 y1811882 APD VIA_STRUCTURE High-speed via structure refresh fails
. Y8 S$ |7 g2 p1814878 ASDA DARK_THEME Part Manager: Difficult to read black text on black background0 }4 N; O: \5 h2 T8 |$ Y
1814889 ASDA DARK_THEME Change 'updating route in progress' message color: a bright orange bar in dark theme is difficult to read
# E9 Z8 X0 w% I1817355 ASDA PAGE_MANAGEME Double-clicking a library in project preferences library does not move the library but changes appearance
/ ~1 i: Z E' Z- `5 v1817964 ASDA SHORTCUTS User Preferences shortcut misspelled
0 T. ^) v' k. q7 J; A2 J6 Q1820247 CONCEPT_HDL CORE DE-HDL crashes while saving a design
" F* E, U4 Q, P1823187 CONCEPT_HDL CORE DEHDL allows editing of the locked component's refdes using change text editor
: J' ^2 u3 E8 {9 K1824052 CONCEPT_HDL CORE Trying to edit on a group containing a LOCK component, deletes the packaging data on the schematic
- U* |" z+ z3 l% d1 g1 S' B4 y1813987 CONSTRAINT_MGR OTHER PCB Editor crashes when Constraint Manager is closed" p V+ p. g4 ~" O3 q7 e! U
1821129 CONSTRAINT_MGR XNET_DIFFPAIR Uprev to release 17.2-2016 adds unwanted NO_XNET_CONNECTION property to discrete symbols
7 G; y$ M3 g U! E4 J. a1814725 PSPICE PROBE PSpice Measurements crashes PSpice for a digital simulation# N5 ^ {* f5 _ F' o, Q" Z
1808672 SIP_LAYOUT INTERACTIVE create bounding shape command options: 'Min Area' and 'Sync with shape layer'
' J7 L0 j2 \. }5 B2 q- e1817458 SIP_LAYOUT MANUFACTURING Error in DXF conversion after updating SiP Layout from Hotfix 066 to 082 in release 16.6
$ C& G: j/ ^. C: D# W A- I! Y0 k5 X' Z6 j' |
1 W$ I4 C. x0 BFixed CCRs: SPB 17.2 HF028- _( o7 @/ |% X3 n D, c$ H
10-14-2017* \( b3 I$ f9 U6 ]
========================================================================================================================================================7 Q" T! G+ D; h2 |7 D2 v R: h: q
CCRID Product ProductLevel2 Title
0 n# z0 ] W Q0 d" s( h========================================================================================================================================================# o; Q; y% ]9 @; ~
1773530 ADW FLOW_MGR DE-HDL hangs on importing components from another design or copying and pasting components within a design T# p2 F- P. a# @
1790584 ADW FLOW_MGR SKILL code for comparing two PCB Editor .brd files does not work in EDM in release 17.2-2016
; |9 F4 E( W0 i f- w1794116 ADW FLOW_MGR LRM fails to run on project k a; [/ V' H# \
1811532 ADW FLOW_MGR The message for missing tools.jar should not appear in adwcopyproject.log/ ?, N8 @' k5 M- a
1812109 ADW LRM Library revision manager displays errors while re-importing updated sub-blocks x6 p, b, r7 Z
1771851 ADW PCBCACHE Problem in packaging upreved imported block
3 y8 r# F' e4 O# [+ z8 M1814785 ALLEGRO_EDITOR 3D_CANVAS PCB Editor crashes when a bend is created and then viewed in 3D Viewer+ a1 V1 @4 o; J0 j, j
1800131 ALLEGRO_EDITOR DATABASE allegro_downrev_library utility fails on Windows 10# M+ p( k3 q% ]; \) u$ ?1 W
1814607 ALLEGRO_EDITOR DFM DFM check for soldermask does not include Package Geometry/ Soldermask if the soldermask is part of stackup
3 L5 E' A! Q7 R# c" c1813996 ALLEGRO_EDITOR EDIT_ETCH Add Connect crashes PCB Editor if clearance view is set to channel
$ B$ k2 c. s- b$ P4 g: R1810832 ALLEGRO_EDITOR SCHEM_FTB Error while doing Export Physical from DE-HDL to PCB Editor
. m3 j# L2 J2 A" N5 X H i- z) U1811785 ALLEGRO_EDITOR SCHEM_FTB Import > Logic > Import Directory does not resolve the relative path to the packaged folder
* s' G5 B4 \& c e' j1 l: |, I1814166 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version of database
! S# a" S+ d7 A) u' y T1 i) A1817891 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version6 i' u# N1 a& ]7 ^+ Q/ L& C
1818954 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version of database$ q0 j! n$ O2 S; W! N
1812808 ALLEGRO_EDITOR SHAPE Artwork is different from PCB board, @" K# V8 i8 Q ~! U0 h: {* {, F
1814836 ALLEGRO_EDITOR SKILL Doing zcopy Xhatch pattern crashes PCB Editor in release 17.2-2016
' V* c% H. L" x5 b+ W1772218 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding on Show Element1 V: B0 y3 U, K2 ?5 D- `# n; z
1778353 ALLEGRO_EDITOR UI_GENERAL Intermittent PCB Editor crashes on loading IDX in release 17.2-2016 Hotfix 020
; I2 Z: Y% Q! |# M' w! G1818077 ALLEGRO_EDITOR UI_GENERAL axlViewFileCreate disappears behind window or is blank
- y% E# h# @9 g( l' x2 i3 k1807423 ASDA NEW_PROJECT SDA CPM file has erroneous date
' |* m+ ~& w9 J1 V1809597 CONCEPT_HDL CORE Problem auditing SI model in Allegro Design Entry HDL from Hotfix 025 onward, no problem in Hotfix 024; o0 u' N& {$ }0 f4 X
1810322 CONCEPT_HDL CORE Unable to package design if OK_NET_ONE_PIN property is set
. H9 k/ H2 h: S6 x4 ^1813436 CONCEPT_HDL CORE Read-only block import issue in same session: displays error message SPCOCD-553 l+ Y; ]. V$ I0 z5 @1 a0 I% M
1813912 CONCEPT_HDL CORE The response in DE-HDL is sometimes extremely slow
# N7 k& \6 G1 Y% g2 K& ?2 P# E1812506 CONCEPT_HDL INTERFACE_DES Error messages during packaging followed by a success message though there are errors in design
+ R- F7 X: S' u' ]0 G) m8 ]+ Q+ H2 Z1808677 CONSTRAINT_MGR CONCEPT_HDL Auto-generation of differential pair finds several instances of the same net, G: b6 w8 Q4 W6 M$ I
1808898 CONSTRAINT_MGR CONCEPT_HDL Unable to resolve the ECSet mapping errors if the topology has pin of PINUSE POWER & GROUND. ^* c8 O6 h. O( c
1810320 CONSTRAINT_MGR CONCEPT_HDL DE-HDL - Constraint Manager: Cannot add group to net class if a net in group is a member of the net class$ l# _* U# l' B' a" H
1812459 CONSTRAINT_MGR CONCEPT_HDL Auto-generation of differential pairs has issues) h3 {' p5 g3 F0 i
1796234 CONSTRAINT_MGR OTHER PCB Editor crashes on query (ALLOW_ON_ETCH_SUBCLASS) without data type defined$ D4 _; E9 ~& \
1811692 CONSTRAINT_MGR OTHER Constraint Manager: Set Topology Constraints - Rel Prop Delay - Pins is empty in release 17.2-2016 Hotfix 026
& v$ `$ _& v7 u! ~ d1816311 CONSTRAINT_MGR XNET_DIFFPAIR Extracting a differential pair into SigXplorer crashes DE-HDL, H1 I% X7 g( ^) Z. g7 y
1807593 ORBITIO ALLEGRO_SIP_I Die symbol shifts when importing die from OrbitIO to SiP Layout
1 m' G9 S# t/ b2 q& K1800763 PSPICE SLPS Error while running co-simulation in MATLAB for PSpice-SLPS demo designs- A4 x1 ]) M' G/ U7 |2 W7 U" Z
- h9 p* |) m0 i8 Y
* r/ v) f: U$ \7 T1 A3 h2 v0 P
Fixed CCRs: SPB 17.2 HF027' }4 p" W* R. e- D
09-29-2017& K& l5 f2 c6 A, W& M
========================================================================================================================================================
0 p4 O6 ?: o# U& D3 ?CCRID Product ProductLevel2 Title
! S& i" g1 @9 [========================================================================================================================================================
% L) k, ]! J- p/ H1795353 ADW FLOW_MGR Tool unable to find project in windows_project.txt
2 ~ C* z0 Y" E9 S1810386 ADW FLOW_MGR Error regarding not finding project in 'windows_project.txt'
9 ?. o8 _& ~! q) e) R' b' D# b+ l1743732 ADW LIBDISTRIBUTI adwserver -install does not give error if it cannot connect to server.7 C% J6 }4 }3 z4 t% ~( j) r
1804378 ALLEGRO_EDITOR 3D_CANVAS Bend area issues in 3D Viewer
\0 Z4 S3 J' H. [1795312 ALLEGRO_EDITOR DATABASE Cannot unlock symbols as status is changed to View on opening design
# q1 d( I% |* e# G3 V9 b1803262 ALLEGRO_EDITOR DATABASE Donut pad With DYN_THERMAL_CON set to FULL_CONTACT has connectivity issues/ j" A6 W7 ]+ L# r) H& N& {" O4 \' R9 c6 F
1802183 ALLEGRO_EDITOR DFM Using mouse wheel to scroll error information in DRC Browser changes font size
! j3 S0 z' L! {0 K1797222 ALLEGRO_EDITOR DRC_CONSTR Updating DRC results in error 'SPMHDB-403'- B; G) {4 l* e0 D" L
1792163 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on moving components
. V0 v- i) u6 z. Q, g# \: U1806640 ALLEGRO_EDITOR INTERFACES Step Mapping not working in release 17.2-2016 Hotfix 025
! q! Z2 i6 |* O$ C0 k% k4 N1807278 ALLEGRO_EDITOR INTERFACES Running 'step_export_product_asm.exe' displays 'vcruntime140.dll' missing error
+ P) L% E, L' w2 t1807286 ALLEGRO_EDITOR INTERFACES The facet file (.xml) for the STEP model 'modelname.step' cannot be found.( ~5 _ j0 ?5 F7 F% \! g5 [: w1 T
1808006 ALLEGRO_EDITOR INTERFACES Facet file for step model cannot be found: X s( ? h& f" ~0 Q5 J
1704335 ALLEGRO_EDITOR MANUFACT Documentation Editor shows an error about backdrill while no backdrill was used in the design# d. I5 J, P+ r a# y, x. K
1800115 ALLEGRO_EDITOR MANUFACT IPC2581 Export giving error that backdrill is out of date even though no backdrill is defined in the design9 H' g- j% _0 L% E. v, b
1799444 ALLEGRO_EDITOR PLACEMENT Via Array - Boundary placement fails with error- R* a$ W" v: s/ L
1725242 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
a! O% f0 k1 t3 j1804129 ALLEGRO_EDITOR SHAPE XHatch Shape not voiding properly6 e" V8 E8 f& @% K: u, x6 e
1805238 ALLEGRO_EDITOR SHAPE PCB Editor crashes while importing netlist% C J$ c$ h* N
1803542 ALLEGRO_EDITOR SKILL Using axlPadstackEdit to change drill size causes via net to change in release 17.2-2016 Hotfix 025
9 O; u' ]" N' d" T3 x1800774 APD STREAM_IF Only one pad in GDSII when running 'stream out' with the Flatten Geometry option2 m: \/ j! N6 z" _( [
1804196 APD STREAM_IF Component is mirrored by X-axis instead of Y-axis on enabling mirror geometry( r4 d. K, M% _) h
1803375 ASDA IMPORT_BLOCK Import HDL Block fails with message regarding Xnet states and DML independence
! ` y. k5 Y7 o) [6 N1807423 ASDA NEW_PROJECT SDA CPM file has erroneous date
! }8 l1 P1 M4 i ]/ g5 F1789400 CAPTURE SCHEMATIC_EDI Capture schematic opens unannotated pages on search% k) `) R6 U# s
1801573 CONCEPT_HDL CONSTRAINT_MG Upreving release 16.6 design to 17.2-2016 adds NO_XNET_CONNECTION to some components: }. ^: Z+ E2 [
1810586 CONCEPT_HDL CONSTRAINT_MG DE-HDL crashes when transferring XNET properties to similar components in a read-only block; L& j \6 y& S
1794169 CONCEPT_HDL CORE _automodel command crashes DE-HDL if PACK_IGNORE is set
& \% @# b0 e) a9 ], u1798672 CONCEPT_HDL CORE Dashes in design name creates an extra design folder in worklib after upreving to release 17.2-20162 E( Z& o9 b3 K, y5 u
1802258 CONCEPT_HDL CORE Locking unlocked components results in a warning (SPCOCN-3403)/ X4 d# s0 E7 y7 K, U
1803019 CONCEPT_HDL CORE DE-HDL crashes on backannotation, z, c# ]5 }4 q+ G, `) D
1803615 CONCEPT_HDL CORE After running 'Mark for Variant', the block cannot be changed to blue
9 G4 I1 W7 N3 U) \- N1804029 CONCEPT_HDL CORE Visibility issues when using the LOCK functionality9 G2 j. }; {- R: k
1806352 CONCEPT_HDL CORE Group Mirror is causing design corruption.9 \; q( K p- f0 ^
1806978 CONCEPT_HDL CORE Cannot mirror a group of objects
/ h4 b2 }- [3 D- d1810387 CONCEPT_HDL CORE Mirroring groups causes erratic display and may corrupt database if project is saved
+ M& A2 U- E% D2 D1812811 CONCEPT_HDL CORE Schematic group mirror not working
6 W: H e; { s- W9 {1810401 CONCEPT_HDL INFRA Add Signal Name: Cannot select suggested net name4 N% w3 Z! J/ d' a
1787409 CONCEPT_HDL PDF Minus character at the end of netname causes unexpected string concatenation during PDF Publish5 f b" a+ ^" m' l+ q* |
1800931 CONSTRAINT_MGR OTHER Even after removing NO_XNET_CONNECTION on parallel termination, topology extracted has duplicate capacitors- j" j: x- F& K/ h6 Q# G( Z! X8 @0 C
1790106 CONSTRAINT_MGR SCM Cannot find the constraints file (0) in the schematic project/ _4 h( v& W# B2 p3 T
1787117 CONSTRAINT_MGR UI_FORMS Creating bundle in Constraint Manager crashes PCB Editor+ v; W) ]( k) m% \5 R
1797384 ECW METRICS Pop-up metrics value tool tip is translucent, making values hard/impossible to read
2 ~0 g6 u) U# J- s% x6 J& V1803226 ECW METRICS Pop-up metrics value tool tip is translucent, making values hard/impossible to read
. o: W* I9 E! f1664059 ORBITIO ALLEGRO_SIP_I Incorrect connectivity after .brd import& K3 K- G" H8 D. u: [6 b
1799338 SIP_LAYOUT DRC_CONSTRAIN Multi-threaded DRC fails with internal memory error even after setting shape_cache_size" q4 V2 [8 p4 J( A
1799499 SIP_LAYOUT DRC_CONSTRAIN Multi-thread DRC fails7 }% X7 j: I3 I+ G- F2 j6 N" l& c
1806585 SIP_LAYOUT DRC_CONSTRAIN Multi-threaded DRC update aborted: internal memory resource depleted
1 r7 v! k1 Z2 L4 _7 u1809804 SIP_LAYOUT DRC_CONSTRAIN Error message while updating DRCs in release 17.2-2016 Hotfix 026 regarding shape_cache_size. I9 N- l8 E4 a8 P6 D! n
1788770 XTRACTIM ENG Translated bump / ball conductivity is wrong (PowerDC and XtractIM)
- a# r2 S3 U" F! k$ ? g L) C/ v
" g6 J9 m( v5 d4 }4 J4 U5 {5 i; E4 M" \* n, K$ z
Fixed CCRs: SPB 17.2 HF026, c" O" K4 J7 v0 |; z
09-15-2017" x, W8 E; l% N
========================================================================================================================================================' m, P0 n- G8 p [& ^9 t
CCRID Product ProductLevel2 Title( |* a6 J8 {6 t
========================================================================================================================================================: { ?3 z/ a: }) ?) p' i5 M+ [
1765398 ADW DATAEXCHANGE Duplicate MPNs are created when updating MPN classification properties with data exchange
' |: G7 i' d' N# g" G5 ]9 Z1780147 ADW DBEDITOR 'Associate Footprint from Tree' does not log the information8 L6 x# S$ B6 P# j3 `: L+ R' x
1790134 ALLEGRO_EDITOR DATABASE Correct spelling in Layer Function definition
$ U4 f) u/ u, u2 \- o4 V1792345 ALLEGRO_EDITOR DATABASE Pastemask is added to bottom layer on backdrilled pins
* R; z; l! k0 f! k! p1792930 ALLEGRO_EDITOR DATABASE Uprev required for all libraries and padstacks to use release 16.6 DRA in release 17.2-2016+ m6 g8 M1 S! U2 u! `. Q6 z
1781203 ALLEGRO_EDITOR DFA DFA Spreadsheet Editor not starting from Windows Start menu
Y" K; Y b. j$ @0 p/ C& |1797422 ALLEGRO_EDITOR DFA DFA Spreadsheet Editor not starting from Windows Start menu4 x) V V( X) M" Z) L' K
1770694 ALLEGRO_EDITOR INTERFACES Incremental IDX does not place unplaced components, E: Z6 x2 R. Y6 T9 A1 \
1776791 ALLEGRO_EDITOR INTERFACES STEP file not displayed in PCB Editor for mapping. y" S% z- y& a$ f9 |
1783515 ALLEGRO_EDITOR INTERFACES PCB Editor reading step model incorrectly% |. q9 t4 i% {. e
1781485 ALLEGRO_EDITOR MANUFACT Setting ipc2581attrpath results in error 'E- ipc2581attrpath: Variable not defined'
) r, M7 ?& l+ g+ U9 U1 B4 M1772713 ALLEGRO_EDITOR MULTI_USER Allegro Symphony Server rejects group moves8 T' @- R/ l: a9 E2 M' z( W! E7 m
1789853 ALLEGRO_EDITOR MULTI_USER Symphony Server rejects updates and hangs frequently/ i1 ^0 l" G& R' \0 f' f3 d/ ]
1725591 ALLEGRO_EDITOR OTHER File - Export PDF crashes on the design attached% J- U" r0 e+ [, w' |) M: W
1736324 ALLEGRO_EDITOR OTHER Export - PDF fails to export PDF' p& \+ B2 @2 h% ]. g! U5 l x' ^- K
1794071 ALLEGRO_EDITOR PLACEMENT The placement of component is very slow and takes around 3 to 5 minutes per component.
`& N( Z ~. C! I1496199 ALLEGRO_EDITOR SHAPE Overlapping route keepouts result in a broken shape.
. k$ A0 X5 H o; N* E1760146 ALLEGRO_EDITOR SHAPE Void offset in Artwork but not in board for a particular instance only Z8 ~* N: R: P S$ x4 w+ e
1770372 ALLEGRO_EDITOR SHAPE Overlapping shapes merged in artwork shifts void causing a manufacturing short
P' Z* ^4 u P. \ c1793419 ALLEGRO_EDITOR SHAPE Unexpected shape void in artwork in release 16.6( g1 @0 @+ X* E( j* u3 N/ n. v
1796666 ALLEGRO_EDITOR SHAPE DRCs for out-of-date shape while placing single via
* l o s& f2 T1786386 APD EXPORT_DATA Exported dra and pad files do not have right stackup
) E) Q5 S' [" K8 Q T) ?5 t; o1765673 APD SHAPE Shape in Cu1 and Cu3 cannot void correctly
0 ]" A% z1 k2 C/ I+ N" Z9 e- d, y3 D1782418 APD SHAPE Artwork is showing unnecessary horizontal lines
* }9 B$ @: G7 r1 D: t) y* V5 T1778366 CONCEPT_HDL CHECKPLUS CheckPlus not printing logic design name, K6 {& ?* s- B' \* S5 n& N
1723855 CONCEPT_HDL CORE Cannot use Rename Signal for unnamed wire segment if the wire has a branch to the same instance2 _5 C. B- J# r0 ~- D
1755174 CONCEPT_HDL CORE Unable to create XNETs on the read-only blocks
: o3 o( a' J* `( S1765533 CONCEPT_HDL CORE Strokes are slow to respond in release 17.2-2016! v. F2 h+ s& O7 |8 \3 d/ S
1780253 CONCEPT_HDL CORE In Windows mode, with copy command still active and symbol on cursor, DE-HDL stops responding on pressing Delete key
7 [4 v0 ?) }# y; ~1785069 CONCEPT_HDL CORE Warning box for SPCOCN-2251 needs to be resized and the text formatted correctly
9 B. K# u; A$ R1786030 CONCEPT_HDL CORE Packager fails in release 16.6 but runs successfully in release 17.2-2016: U9 V7 c3 k; f- U8 u* x
1788077 CONCEPT_HDL CORE Creating new window (new tab) in DE-HDL resets view of original window& c' i) z1 p0 W& j5 J* P
1788591 CONCEPT_HDL CORE Wrong pin number displayed after running packager
/ N+ Y$ b6 z( K0 y; o1776774 CONCEPT_HDL CREFER CRefer crashes without error entry in log file
t6 ~6 i2 a% ~# B2 t( @" A, J1328320 CONCEPT_HDL PDF Cannot select/search sig_name in published PDF
4 P* ]: t* B6 O1787409 CONCEPT_HDL PDF Minus character at the end of netname causes unexpected string concatenation during PDF Publish* W5 f: J, P* b4 Z6 |$ l$ O
1758122 CONSTRAINT_MGR ANALYSIS Extracted topology for a differential pair is missing a pin-to-pin connection in the top file# a @& E7 m. t) H
1786161 CONSTRAINT_MGR CONCEPT_HDL Random crashes in release 17.2-2016 while working on the schematic editor along with Constraint Manager
& Y# P- D; Z3 C5 b6 D# g1788877 CONSTRAINT_MGR DATABASE Constraint Manager API cmxlImportFile looks for sub-string during replace mode and not explicit names* I" N h/ H! w8 L% j
1800263 CONSTRAINT_MGR OTHER DE-HDL and CM crash when deleting regions
! W t6 B& N' {1 E1792000 CONSTRAINT_MGR UI_FORMS Data type of constraint not shown in GUI
# b* U# k1 I# E. R" s% k3 E1744828 FSP CAPTURE_SCHEM Button appears during 'Generate OrCAD Schematics'
" q* G3 I4 S2 }3 ~4 g# O7 U1747568 ORBITIO OTHER Import of .oio file in SiP Layout takes a long time$ ]; `5 r5 D# v2 i; O r( W
1765229 PSPICE AA_FLOW Not able to run PSpice MC after setting Assign Tolerance
# @+ S! L/ ~$ o, Z- R R8 p/ n1770174 PSPICE MISC Issues with DMI Template Code Generator7 P m" H L9 ]8 X0 P
2 T8 F4 G7 Z. n
4 `! B% H6 k8 L$ {Fixed CCRs: SPB 17.2 HF0256 L5 f: r8 A% y0 I1 @7 |5 u
08-25-2017! H5 `" j, z9 I
========================================================================================================================================================
. N, G/ E# ?% Y3 x! I' y4 r% rCCRID Product ProductLevel2 Title
5 o6 Z8 y$ ]3 I. h2 l" O9 q1 ]4 y, H% ]========================================================================================================================================================; ~# Y \+ I; G+ Y$ I5 T
1258913 ADW ADWSERVER Copy project message: Unable to locate tools.jar$ D* i; _8 H" ?& ]+ O4 t
1760866 ADW ADWSERVER Metrics dashboard in Allegro EDM Configuration Manager does not show updated SPB 17.2 hotfix8 N. f/ \ [: ~- Z
1055946 ADW ADW_UPREV Set PTF_SUBTYPE SEARCHABLE to false and default value to exclamation mark
# s I% t# G- H( `% o* Z- c- i1508163 ADW COMPONENT_BRO Manufacturers Part tab disappears on clicking anything other than the part number in the left tree6 _% R" P* G* V( k
1774164 ADW COMPONENT_BRO In release 17.2-2016 Hotfix 22, DE-HDL crashes on using Generate View
: @* i M/ f2 s( a0 R1345018 ADW DBEDITOR Database Editor does not catch empty mandatory properties if no changes are made to the part
. z3 z0 _9 i+ T& M- G% G1586858 ADW DBEDITOR 'Access Denied' Error while opening Datasheet Model using Launch Viewer in Database Editor
& y) b; G0 _8 A3 K4 u1754185 ADW DBEDITOR Max Height value in DBEditor is different from PCB Editor: w/ r8 o& [2 M5 y7 D8 m
1719260 ADW FLOW_MGR Configuration error on a fresh install of EDM in release 17.2-2016 Hotfix 014/ m! t) R/ c9 D$ G/ F
1743730 ADW LIBDISTRIBUTI .lis file error in install_model while using MLR.
3 y. t7 ?0 H" a1757178 ADW LIBIMPORT back-end libimport failed, crash and existing flashmodel not found' V6 I7 ~. x5 {% g% y9 A9 T# e( c
1648609 ADW SRM PCB Editor stops responding when launched with -s option in release 16.6-2015 Hotfix 078
2 O7 d" K: H- \1731152 ADW TDA TDO coredumps after a new object has been checked in as minor and deleted.
/ ]5 T$ @- w% B1766998 ADW TDA TDO-ASA: Cannot enable the project for team design until a component is added to the new ASA/SCM design
3 s$ |& b, s3 J2 u" E1695240 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D View of a package symbol not showing the correct mapped STEP file attached to the package symbol2 C, j# d6 {, N
1698148 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Viewer crashes on Windows 10
# Q: x% g" P3 [+ C$ Z& Y" p3 g% i1738655 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas crashes on Windows 10
3 d8 G l" E4 A! {* }" n# w4 y( @1750001 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D Canvas crashes on selecting in symbol view1 D/ e9 \: E! m O: G
1751796 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas shows component placed at wrong layer for Embedded components
: N! ~' M& i! N2 Z6 s5 |: M; u1768775 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D canvas closes when Update Symbol is done and cannot be re-invoked# P3 w9 V: q4 ?2 J" ?
1695025 ALLEGRO_EDITOR ARTWORK Artwork film show shorts.% ?6 n, O0 x0 h8 }% [
1708674 ALLEGRO_EDITOR COLOR Dehighlight all should disable the check boxes in the color dialog/nets
- ?* p. l6 A- V' F0 N1735522 ALLEGRO_EDITOR COLOR In release 17.2-2016, PCB Editor crashes when not being able to write the CVSettings.xml file.
, f- v: F8 Q3 l$ a0 c1 _) J! _1764475 ALLEGRO_EDITOR COLOR Allegro PCB Editor hangs when selecting OK on the Color Dialog form) O0 {7 }* Q+ R4 ^) L
1718438 ALLEGRO_EDITOR CROSS_SECTION User interface is inconsistent for the Mask Layer Subclass site file editor.1 N& M" I/ J9 e6 ?
1765387 ALLEGRO_EDITOR CROSS_SECTION Cross Section Editor does not retain or remove layers added/removed from Setup-->Subclasses
# ]( J8 U) c. M! e3 ]) |) M% @. g& D1714910 ALLEGRO_EDITOR DATABASE PCB Editor crashes with blank allegro.jrl file when a release 16.6 board is opened in release 17.2-2016 Hotfix 013
# |3 H2 G( e, S& b; w3 [1769534 ALLEGRO_EDITOR DATABASE DBDoctor unable to delete invalid subclass, B g! `$ [+ g9 g+ R/ {2 A" r
1775705 ALLEGRO_EDITOR DATABASE Updating stackup in PCB Editor does not change backdrill status to 'Out-of-Date backdrills'
9 w" K5 W* J% E1778608 ALLEGRO_EDITOR DATABASE Rigid Flex design: Components with pads defined on the TOP and BOTTOM layers are not placed on the correct layer( }2 o/ m& N( Y' @4 b
1778644 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes while trying to place dimensions6 {2 B! O% _4 G) [! W3 z
1698695 ALLEGRO_EDITOR DRC_CONSTR Line to Mech-Pin DRC not displayed! l9 }8 u. e3 W2 T3 g3 k+ R
1705214 ALLEGRO_EDITOR DRC_CONSTR Shape to drill DRCs not getting void and 'cns_show' does not report constraint value
7 Y& B5 L( J! }1 I7 ~* V1722841 ALLEGRO_EDITOR DRC_CONSTR Inconsistent soldermask to soldermask DRCs on vias as compared to board geometry/soldermask
8 X+ [9 G3 N1 I# d& D! k8 k1736116 ALLEGRO_EDITOR DRC_CONSTR Shape Voiding and DRC error on layer with no hole or pad definition+ K7 n3 D( M. b2 \1 u
1744248 ALLEGRO_EDITOR DRC_CONSTR Release 16.6 to 17.2-2016 DML Independent Flow does not resolve differential pair pin pairs Correctly: @0 x4 e2 z S7 y9 ?
1776848 ALLEGRO_EDITOR DRC_CONSTR Negative plane island DRC reported in release 17.2-2016 Hotfix 23
6 W$ P4 d. A9 |4 i9 r1730806 ALLEGRO_EDITOR EDIT_ETCH Element 'vias_allowed' is not valid for content model adding high speed via structures) H7 c6 A, q1 F6 Q3 _/ } @
1745332 ALLEGRO_EDITOR EDIT_ETCH In release 17.2-2016, PCB Editor crashes when starting Add ZigZag Pattern
) n$ r1 n9 j i- G, d: Q1765555 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes during contour routing9 k# o- [3 @, k) Q
1644401 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes on running the z-copy command
b2 H& P! k, Q8 g: n1657621 ALLEGRO_EDITOR INTERACTIV Copy cline and via cause redundant vias: t3 m* O1 O8 o8 m
1688556 ALLEGRO_EDITOR INTERACTIV Limitations with editpad boundary' o- e- F8 h' W5 D+ V
1704901 ALLEGRO_EDITOR INTERACTIV Changes cannot be done when 'Design outline' is selected
" j% W2 y4 {2 l. L: u' s1710731 ALLEGRO_EDITOR INTERACTIV The Edit > Change command does not select or change the text on a block" l2 p4 l( {4 k( l* Z" q
1714855 ALLEGRO_EDITOR INTERACTIV Placing two objects on the Design_Outline subclass causes PCB Editor to crash- l- _- W( Y* a9 l i
1725736 ALLEGRO_EDITOR INTERACTIV Edit>Change cannot change silkscreen line to a different class, but works in preselect mode) Q- e7 g8 ` z/ d# l
1728004 ALLEGRO_EDITOR INTERACTIV Text cannot be edited if the Design_Outline subclass is in the selection box
$ @6 H! }3 @% r/ l' a' L1 C1728794 ALLEGRO_EDITOR INTERACTIV The Oops command and the Esc key do not work when moving components in the Temp Group mode, K$ I$ L) s% s/ F
1738070 ALLEGRO_EDITOR INTERACTIV Copying shape after Shape Operations results in error 'E- (SPMHDB-72): Current active shape must be filled first'; f' y3 w* G& z' k3 ?" k0 V
1750696 ALLEGRO_EDITOR INTERACTIV Add notch angle option fails to update if changed while add notch command is active./ w& b a w4 b8 i
1755240 ALLEGRO_EDITOR INTERACTIV Copy via does not work
/ l- g! Z# E- C4 l) A. D0 u1777416 ALLEGRO_EDITOR INTERACTIV Running shape operations results in database corruption5 l$ a! a P0 Q
1715835 ALLEGRO_EDITOR INTERFACES When IDX is imported in PCB Editor, all the shapes are created on package keepout on all subclasses* P+ C* o! I* m4 W
1744111 ALLEGRO_EDITOR INTERFACES Pads rotating 90 degree when exporting DXF file from Allegro PCB Editor' Y, p" ~9 g X( F @$ \3 t" i0 s
1736045 ALLEGRO_EDITOR MENTOR Third-party import crashes PCB Editor with error stating that .SAV file will be created. \! _4 R# [& x$ i; ~' C/ {
1751914 ALLEGRO_EDITOR MULTI_USER Find Filter options get disabled while creating symbols
3 N0 q2 b) L& J& r$ e4 N! E7 B1770811 ALLEGRO_EDITOR MULTI_USER In release 17.2-2016, axlTriggerSet('exit 'routine) causes a crash while exiting: E; p* N; _+ ?" L
1736545 ALLEGRO_EDITOR OTHER Spelling mistake in description of no_dynamic_zoom variable in user preferences Editor
- ]& D& Y& {, i& K2 |5 V& \/ x1761610 ALLEGRO_EDITOR OTHER Dynamic shape is not voiding as expected.
9 d( r$ u/ ?0 J! q; u1 Z* D1702535 ALLEGRO_EDITOR PAD_EDITOR After modifying a padstack in Pad_Editor, the Update to Design function fails to update the dra file7 x9 I0 ?4 E8 |8 Y' f# l- K
1713461 ALLEGRO_EDITOR PAD_EDITOR Padstack editor default geometry not working when cell is preselected
) J6 n8 h: }7 }1715702 ALLEGRO_EDITOR PAD_EDITOR Donut shape is lost on cutting the pad shape of the donut pad
4 x+ a. Z/ ^9 |, z& W2 m# p O3 V/ K1720300 ALLEGRO_EDITOR PAD_EDITOR Multi-drill staggered pattern: Different hole placement for first and second rows for releases 16.6 and 17.2-2016- M! w8 \' R# R( A; J
1724896 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor shows flash symbol for regular pad on selecting 'Shape Symbol'
4 o7 u+ g) l# `- S1 {1714839 ALLEGRO_EDITOR PLACEMENT Selecting an alternate symbol (alt_symbol) in a group, in the Placement Edit mode, removes the symbol from the group; a/ J0 k3 l9 e4 M
1781502 ALLEGRO_EDITOR PLACEMENT Quickplace by room crashes Allegro PCB Editor
- k" c3 l9 Z- M( B, U; }1699690 ALLEGRO_EDITOR SCHEM_FTB 'view_pcb directive' no longer working as expected
; s/ c+ @% M5 k1758796 ALLEGRO_EDITOR SCHEM_FTB PCB Editor launched from Project Manager does not read the relative paths specified in the view_pcb directive3 \# H0 ~2 }! G2 G1 P
1761101 ALLEGRO_EDITOR SCHEM_FTB On saving a board after import logic in PCB Editor, the file is saved in the cpm location and not in the physical folder
9 R: f1 f* D+ F1761394 ALLEGRO_EDITOR SCHEM_FTB Working directory for PCB Editor changes after import logic. H, h9 L. z+ `) x7 j
1714922 ALLEGRO_EDITOR SCRIPTS Running script in the non-graphic mode runs the tool graphically
" R+ ^' q1 j) u+ I5 q1 B! \2 A1726550 ALLEGRO_EDITOR SHAPE Shape failed to connect to pin( @' j( h9 B& r9 S. h4 a
1754945 ALLEGRO_EDITOR SHAPE In release 17.2-2016, Delete islands fails to add DYN_DELETED_ISLAND to voids on Windows 10 systems
. }* a! m' Y) _& J5 `% N1766280 ALLEGRO_EDITOR SHAPE SPMHGE-300 Polygon operation failed because of an internal error
% B& O- q. n3 r9 ~1768307 ALLEGRO_EDITOR TECHFILE Properties defined in the technology files are not being imported in a new design
9 O; ]) x& z' [# |; [9 K5 R1771584 ALLEGRO_EDITOR TECHFILE The tech file import command does not update user-defined property immediately
% {! C- ^. k$ D# N# z6 z" o7 t1730104 ALLEGRO_EDITOR UI_FORMS Change description of Title bar option variables in User Preferences0 O* K; Z: a8 @% o
1749272 ALLEGRO_EDITOR UI_FORMS etchlen_ignore_pinvia variable needs to be updated
& n+ ^# B& B8 l4 L$ K+ r1649254 ALLEGRO_EDITOR UI_GENERAL Using wildcard to open padstack file generates error SPMHA1-161 in Padstack Editor in release 17.2-2016/ Q& b5 ]3 ?) g6 n: {: d/ ~0 b Y
1685985 ALLEGRO_EDITOR UI_GENERAL Funckey not working for Display - Measure) r' K! e$ v2 `# b# |* n
1687073 ALLEGRO_EDITOR UI_GENERAL Show Measure command shifts focus to Search field in result window after selecting first element- K2 p. S' M' {* ^0 K9 C
1699272 ALLEGRO_EDITOR UI_GENERAL File Viewer not displaying HTML files correctly when 'allegro_html_qt' is enabled
- Y& |) Z) f. u8 Y% w% _1711321 ALLEGRO_EDITOR UI_GENERAL Database settings do not change on changing color settings using the SKILL function axlDBDisplayControl()8 ]5 X( u2 E _7 B8 L: N2 K5 S% [
1728468 ALLEGRO_EDITOR UI_GENERAL The Show Element window takes the focus away from the PCB Editor window) t8 `. o% `6 Q- |- ^5 |
1733690 ALLEGRO_EDITOR UI_GENERAL Performance issues in Visibility dialog if called repeatedly in release 17.2-2016, Hotfix 0179 q6 B; t3 r9 C4 c* \
1734176 ALLEGRO_EDITOR UI_GENERAL Unable to sort padstacks to open in the padstack editor using wildcards: q1 ^, W* `% P% s1 A
1735733 ALLEGRO_EDITOR UI_GENERAL RAVEL checks slower in release 17.2-2016, Hotfix 0175 `: @3 H& F9 m' X5 C4 A
1737545 ALLEGRO_EDITOR UI_GENERAL axlVisibleSet is slower in release 17.2-20162 N' t/ u; g+ N Z; A5 w
1744655 ALLEGRO_EDITOR UI_GENERAL SKILL code with axlVisibleSet slower in release 17.2-2016 compared to 16.6! h# {/ d: q% s a w8 f- ^5 c
1759380 ALLEGRO_EDITOR UI_GENERAL axlLayerPriority API changes layer visibility and colors
( o+ f0 R6 \" i0 X9 Z1775071 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, dialog boxes are not displayed in the right order on using SKILL( I7 k" x# m, Y+ S1 `
1708554 APD GRAPHICS MCM shape lines are almost short and different with DXF and Gerber files
( g% S: \) u, S: L1678824 APD SHAPE Updating dynamic shape fails to void all elements on layer L2.$ d: r$ G, X" @' U# }9 O
1742335 ASDA COMPONENT_BRO Libraries missing from new Component Browser
# c; s3 u6 z6 j, Z7 Z& J1779777 ASDA CONNECTIVITY_ SDA: Net name and physical net name are different# @+ J& @) Z7 U/ |
1721919 ASDA CROSSPROBE Cross-probing a net from the .brd file highlights the entire bus in the schematic: I3 O5 y8 @2 }
1714313 ASDA EDIT_OPERATIO Filter does not work correctly in the Change RefDes form4 q, O( B' K' ^: p5 S1 J- o* ?5 ~2 `
1730809 ASDA FORMAT_OBJECT Image transparency slider does not update the number in the combo box correctly
) S; n) v) b0 p7 u7 Z+ K, x1747397 ASDA GRAPHICS Pop-up DRC descriptions are too small and cannot be read! _6 g/ \; F2 E1 n+ _9 f
1640061 ASDA HIERARCHY Incorrect message received when invalid characters are specified for subdesign suffix# q* V8 e( i' `9 K$ e! {) Z
1723535 ASDA MISCELLANEOUS Clicking in the Command window should place the cursor at the last line to avoid editing previously run commands. S/ w9 O' i4 x6 W( i- h
1699936 ASDA PAGE_MANAGEME Page gaps created while moving pages
+ J5 Y; l3 Q5 y" z" ]* A! [% _1 e9 U# I1737180 ASDA VARIANT_MANAG Deleted variants are removed from the variant.lst file but displayed in SDA
* ?: c5 Y5 V5 I C: ~) L2 e1763247 ASDA VARIANT_MANAG Changes in Variant Editor are not reflected on the schematic page.1 {" |: I8 k- F: K
1733971 CAPTURE CONNECTIVITY Auto connect to bus not working in the attached design
" A$ r1 w( X9 S' m0 N. y# `) n1236010 CAPTURE DATABASE Capture is very slow in processing designs.
" j! n: ~( @) o% H" Y1518560 CAPTURE DATABASE Large schematics are slow to respond
! w3 [. @* V( s8 a$ m, ^( q1705592 CAPTURE DATABASE Capture hangs when switching between schematics that contain nested netgroups8 ^: j9 M6 L3 ^! I! N( e
1770687 CAPTURE GENERAL In release 17.2-2016 Hotfix 021 and 022, selecting Help - Learning PSpice throws Java Script error, F6 t' n4 Q/ J6 q; k; _" G, r9 C2 J; x
1692435 CAPTURE HELP Version Info Window is empty* l( m4 y/ I; b# O& ]. L: U
1767374 CAPTURE NETLIST_ALLEG Capture crashes on canceling the netlisting process$ [2 V9 K2 ?4 C3 F& w
1719613 CAPTURE OTHER Moving a wire in OrCAD Capture CIS or Allegro Design Entry CIS results in design crash9 ^( x, Z3 D" r/ F
1746663 CAPTURE OTHER Capture slows down significantly in release 17.2-2016 Hotfix 017 and 0180 k% |# ?$ c3 W" N8 s A# L
1709179 CAPTURE PROPERTY_EDIT Unable to delete unwanted properties associated with Ground and VCC nets.
* o9 A k& z0 S1714121 CAPTURE SCHEMATIC_EDI Mirroring and moving a symbol resets the position of a newly added pin property$ N/ d. l y7 A# Z
1729861 CIS OTHER The 'Refresh Part Types' icon is alternated with 'Refresh Symbols From Libs' icon6 u* G7 x3 A' ?9 P9 K% F
1333600 CONCEPT_HDL COMP_BROWSER Sort the sections numerically in Part Information Manager* _* Q& ^) V, q, U
1758761 CONCEPT_HDL COMP_BROWSER Incorrect Version showing in Component Browser in 17.2
2 z1 }" k2 j4 s- K$ o+ n1769591 CONCEPT_HDL COMP_BROWSER Modify Component / Project Information Manager (PIM), parts take longer to load in EDM
# O% x$ g) p$ E' U; O1479711 CONCEPT_HDL CORE Mirroring symbols causes alignment issues
, q& c; Y5 G9 j" n Q1696208 CONCEPT_HDL CORE Display issue with the grid visibility after a save hierarchy* X" I. y2 Z9 s, U
1698802 CONCEPT_HDL CORE Pin number overlap with the pin stub when the component is mirrored.
2 n, t; t7 k3 |1708917 CONCEPT_HDL CORE nconcepthdl crashes on a design with a core dump& I* L3 H; E- m H( T1 K
1744815 CONCEPT_HDL CORE Deleting a page crashes DE-HDL
* \2 h& P, r, h8 `% @( J1751863 CONCEPT_HDL CORE 'Move' does not move body but only properties of selected part! ?6 E/ J5 m! X+ }: M0 W, i- C% f5 J
1763556 CONCEPT_HDL CORE Component Alignment and other graphical feature not working in Windows 10
( u) `) ?: n; U; a# A# G3 M' b; C5 A1725121 CONSTRAINT_MGR CONCEPT_HDL Audit report of ECSets reflects some gaps in certain columns5 Z5 F, c' O5 L
1758740 CONSTRAINT_MGR CONCEPT_HDL Extracted topology does not populate the gather control used in the ECSet
% I8 Y; |) r& d8 T6 w1759580 CONSTRAINT_MGR CONCEPT_HDL Class to Class assignments are incorrectly displayed in the 'CSet Assignment Matrix'
9 i$ h7 b8 A4 p7 b% L# m1 h1759590 CONSTRAINT_MGR CONCEPT_HDL Unable to create bookmarks in Constraint Manager0 ?4 R5 _; i% p
1764597 CONSTRAINT_MGR CONCEPT_HDL Copying constraints from a SKILL-defined CSet copies the automation flag/attribute ('A' in UI), as well.
+ w5 F* B9 l4 o8 u9 N0 V2 v: y6 u8 M1771427 CONSTRAINT_MGR CONCEPT_HDL Decimal units specified in the precision settings are not applied correctly! n# O! R9 O5 } K$ a: s0 G# \, @4 }8 W
1700402 CONSTRAINT_MGR DATABASE Parallelism violation DRC not reported until cline is moved
; j- N- w, x+ I" Y' K. n1 o, U1700370 CONSTRAINT_MGR OTHER Constraint Manager: Expanded nodes collapse on restart0 `) L4 ~) d4 j: v1 T
1735636 CONSTRAINT_MGR OTHER Inductors are extracted as resistors in the topology# @! T! E& s) }" p- h
1776917 CONSTRAINT_MGR OTHER Creating advanced formula causes the tool to crash
$ c; A; h: o1 b( b* Y1762979 CONSTRAINT_MGR TECHFILE Constraint Manager does not retain values after importing tech file
. Q5 D7 }; K* Y! U1 i& n1699275 CONSTRAINT_MGR UI_FORMS Constraint Manager: Dialog boxes opened from the File – Import menu show files and folders in incorrect order+ ^* _) p. ?. Z2 v w4 g2 G& x
1699312 CONSTRAINT_MGR UI_FORMS Typing *.* in the File name field does not display all the files in the Import Constraints dialog box
) |8 c/ t+ g/ F5 z2 q! A1742134 CONSTRAINT_MGR UI_FORMS Editing a cell from any of the constraint set in Constraint manager is filling other cells that should not be selected. Z, G0 A8 }* u: b5 M- ?
1755576 CONSTRAINT_MGR UI_FORMS Constraint Manager: Physical CSet filter not working correctly
) Z h; S. j; V* h4 I( p: k1775333 ECW DASHBOARD Activity Log is not accessible to ECAD_Integrators if they are not part of the project team
9 H: z7 i: K: J, K- G3 _1749220 ECW OTHER Remove 'Role' column from Users web parts
" h! {" H) P! D4 t1 h! X1716527 ECW TDO-SHAREPOIN Allegro Pulse: Mismatch between metrics with components on schematic and components in layout
2 ?2 P. u4 {0 q6 }! W1724195 FSP SYMBOL_EDITOR Device pins are not correctly aligned after being moved in Schematic Symbol Editor
! y9 Z, v# o4 S0 U; g8 }' _8 f# X6 P7 U1725479 INSTALLATION DOWNLOAD_MGR Download Manager error prompts user to close downloadmanager.exe
" R- x1 i6 `+ k* t5 n7 o, f1738952 PCB_LIBRARIAN SYMBOL_EDITOR Pin table must allow for Copy/Paste of Rows
0 E O- j0 l$ Q1638740 PSPICE FRONTENDPLUGI Set minimum height for the search field in PSpice Part Search
: C0 Z' A. g5 ~1699822 PSPICE FRONTENDPLUGI Set minimum height for the search field in PSpice Part Search# {6 ?! M" z* @% \0 N; a. m
1652265 PSPICE MODELING_APPS Cannot place PWL source from PSpice Modeling App
5 O& d* j6 F7 l8 x" O- s6 I! @1685967 PSPICE MODELING_APPS Getting error when trying to place PWL source from PSpice Modeling App" k5 Y+ K8 I0 e) F# `
1716313 PSPICE MODELING_APPS PSpice PWL Sources not working correctly in release 17.2-2016 Hotfix 014
, ^. [7 e3 `) L4 m1738747 PSPICE MODELING_APPS Inconsistent file type for PWL part in modeling application and source library k2 g2 X8 b* |0 p; l- a
1762202 PSPICE MODELING_APPS PSpice modelling app Tcl issues
Y% ?% _# @0 q% k2 O1736605 PSPICE SIMMODELS BSIM4.6 model parameters incorrectly handled by simulator
1 X- I0 a" Q6 E+ M3 q1442623 PSPICE SIMULATOR Bias points are nor correct in attached circuit$ h" S1 E. v6 K5 O
1618815 PSPICE SIMULATOR Bias Point calculation appears incomplete) a) |/ `( t. l5 q6 l( j
1723039 PSPICE SIMULATOR PSpice crashes when curly braces are specified for the ETABLE parts
7 K# n3 q6 y1 O9 q& o1782353 SIG_INTEGRITY SIGWAVE SigWave crashes when opening .sww file in release 17.2-2016 Hotfix 023
4 P7 ?( L- C, ?1745940 SIP_LAYOUT DATABASE Cutting a part of a tapered cline does not remove the connectivity on the dangling cline
5 R& m0 o' O' Y" H# ?1780072 SIP_LAYOUT DIE_ABSTRACT_ Export->Die Abstract File causes a crash
! w/ q. Z+ w0 p$ F: x% g9 G1736396 SIP_LAYOUT SYMB_EDIT_APP 'No such child' error message when deleting pins in symed& b0 t( E# `! N- b Q6 p8 I
1769728 TDA CORE Default policy file needs to be fixed
& d* I* Z# k, X' h" Q ]1735682 XTRACTIM GUI XtractIM translation is incorrect: adds anti-pads% m' P5 m' C U. E2 G9 n4 `
- _% f* G& z+ X* Q2 C1 j- C
! T Y6 k7 I. B: oFixed CCRs: SPB 17.2 HF024
- Q3 Y8 ?) P9 _07-28-20172 A! B. t ~: L$ w/ f+ ~0 G
========================================================================================================================================================2 P6 p9 ?. y4 R6 k7 H+ u* @
CCRID Product ProductLevel2 Title
2 b/ R4 C4 R6 t ]========================================================================================================================================================
2 G$ b7 @5 V% _1762143 ADW COMPONENT_BRO Part placed using the 'Add' button does not populate 'PART_NAME' property: o' D, _* Z- ^; L) K
1765790 ADW PART_BROWSER Fail to extract component part number and footprint information5 ~9 e9 D; ^5 n d4 m5 {8 p% v7 T
1757719 ADW TDA TDO and Windchilll Work Group Manager out of sync at times2 J2 d' _9 [, K2 j
1760607 ALLEGRO_EDITOR DATABASE Value for number of decimal places changes in Pad Designer in release 17.2-2016
+ u7 t, g8 \( C, A1 O1775160 ALLEGRO_EDITOR DFA Loading DFA spreadsheet crashes PCB Editor in release 17.2-2016( e; A$ V0 }$ t7 l- Q2 F
1765984 ALLEGRO_EDITOR OTHER Cannot view System Info
$ O3 B6 ?+ G9 ^/ U3 ?# ?1729350 ALLEGRO_EDITOR REPORTS Net loop is not listed in report
( e+ q3 g, p3 K) G; V; {0 M1725242 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
; |3 ^7 k! f+ b O) O: J1754402 ALLEGRO_EDITOR SHAPE Illegal arc radius error (SPMHA1-85)
( X. f0 Y: q7 y1762888 ALLEGRO_EDITOR SHAPE Border line missing for some crosshatch (xhatch) shape voids5 F/ c" K+ ]! F n
1769188 ALLEGRO_EDITOR SHOW_ELEM 'Show Element' with the 'Groups' option used on certain modules crashes PCB Editor
0 B4 D0 l) ?! f! j1767690 ALLEGRO_EDITOR TESTPREP PCB Editor crashes when running automatic Testprep. f" @6 E' H* B5 x3 B' b" v4 v h, u
1737337 ALLEGRO_EDITOR UI_FORMS Pinned Show Element window closes when opening new design in release 17.2-2016
' X3 d0 n( f8 y; |1736642 ALLEGRO_PROD_TOOLB INTEGRATION Cannot change accuracy to 4 for 'Change Width' in Productivity Toolbox5 T9 H! v0 M- v+ x# n
1685216 ALTM_TRANSLATOR CAPTURE Third-party translator placing symbols off grid+ p- `, J1 h+ K! n, n2 U0 R
1738679 ALTM_TRANSLATOR CAPTURE Connectivity loss in imported schematic
5 [9 N" R6 f" Q9 ~' D2 p2 X1738705 ALTM_TRANSLATOR CAPTURE Connectivity loss in imported schematic1 X7 N9 Q& N- _) m( i9 ?% K
1748583 ALTM_TRANSLATOR CAPTURE Crash on importing design using third-party translator+ ~) N& C( z) F% V5 I
1679310 ALTM_TRANSLATOR PCB_EDITOR Third-party translator should fix off-centered connections/ u3 A* x0 f& K2 } p
1686845 ALTM_TRANSLATOR PCB_EDITOR Third-party translator does not place parts after successful translation
3 _% k% J3 x8 o- r! [1723141 ALTM_TRANSLATOR PCB_EDITOR Placement outlines are rotated in third-party translator; E+ \5 M7 Z' w9 m' R) P9 c2 Z: M
1723164 ALTM_TRANSLATOR PCB_EDITOR Third-party translator creates board with missing data: vias, traces, and so on
: {& U; U( q" b% V1723190 ALTM_TRANSLATOR PCB_EDITOR Third-party translator changes design origin: {+ N: O& n0 U6 J
1750496 ALTM_TRANSLATOR PCB_EDITOR Third-party board with arc tracks not correctly converted to arc clines* l" n9 i( h, r& q7 J9 N( N1 }
1769624 APD DATABASE Attempted symbol delete crashes APD! f* G" U4 m1 h* ]& i
1727206 APD SHAPE Merging two shapes results in an incorrect shape
- n! P& g7 e! H9 s, `; d- v1707756 ASDA VARIANT_MANAG Scrolling in Create Variant closes tool$ ~! l/ }$ T8 J" t1 f3 x
1753699 CM RELEASE installDebugger() does not work in release 17.2-2016 as SKILL kit is not installed
2 F1 B3 M: }" U5 n! }2 i1741534 CONCEPT_HDL CORE DE-HDL freezes when selecting a net that contains many connections8 K+ N, Q1 {8 Z) S3 P: R
1752687 CONCEPT_HDL CORE The move command changes the connectivity of the schematic
3 W+ _9 E( D5 `, R1 u3 u1763525 CONCEPT_HDL CORE Genview crashes when generating split symbols
6 g% k$ ]6 Y; s8 j* p) Y1766797 CONCEPT_HDL CORE Schematic not refreshed after using the clear xnet overrides feature# q. v, |% M8 V0 _' y C! F
1770852 F2B PACKAGERXL ERROR(SPCOPK-1138): A hard location was found on instances of different physical part types
; m- e3 x# E; N0 F! T1 u5 k1754473 FSP DE-HDL_SCHEMA Provide an option to generate symbols with custom attributes
2 p. I" u5 T5 W% P5 E! p1748106 FSP OTHER Create protocol from existing protocol error message needs clarity
) Y, I5 T: ^" i. t+ M1724201 FSP SYMBOL_EDITOR Unable to change 'Pin Direction' in symbol editor1 a+ x6 \% ^7 a( P* d; e
1772429 ORBITIO ALLEGRO_SIP_I Import - OrbitIO: Translator cannot create bundle in PCB Editor
4 k0 r6 S x$ A. Q4 I& o1725759 SIG_INTEGRITY OTHER PCB shape/plane capacitance" |$ |/ d9 X8 H3 m* }
1760924 SIP_LAYOUT DIE_STACK_EDI Package height of die .dra file reset to 110um when placed
8 i' S2 m9 y* F1764385 SIP_LAYOUT MODULES Embedded components are unplaced in created modules (.mdd)
& C3 s' l. y; t$ {7 F1733679 SIP_LAYOUT OTHER 'metal density scan' does not use select window
) h/ }" s5 M; j W' ~2 V1763707 SIP_LAYOUT OTHER SiP Layout exits with error message in release 17.2-2016
7 B0 T4 v& n1 k4 o1763515 SIP_RF DIEEXPORT Virtuoso writes incorrect width for 45 degree path segments in XDA file
* E* @0 Z+ I; U$ A! O' g1772397 TDA DEHDL DE-HDL crashes if license is not available for team design
, b- T/ S" ^/ ~2 m* P6 [
& N3 P* ]/ C7 G. N* C) ^/ H! f2 `, K# F' C
Fixed CCRs: SPB 17.2 HF023, i- J: g* S" C- ] a
07-7-2017
9 w1 C0 ]4 y; b) X' E========================================================================================================================================================% i3 L" O- [) E8 s, w5 }
CCRID Product ProductLevel2 Title& O* U. `4 r Q( i* \7 F
========================================================================================================================================================
- w' Q% N9 b! n( J/ d1703281 ADW ADW_UPREV Design_init needs to support the -cb command3 b& |$ i, }$ s
1762238 ADW COMPONENT_BRO DEHDL crashes without reason
* T2 X: f0 u% g* M j ]3 z1759467 ADW DBEDITOR DBEditor does not recognize that 1.10 is a higher version than 1.9# D4 b0 P4 m% D
1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager
$ j5 _- L1 N- u o, `2 y6 z/ D! H1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager5 g: F& @5 M% a4 g' M" i
1757443 ADW LIBDISTRIBUTI Blank PHYS_DES_PREFIX in PTF file
6 {. A. O3 k/ C: I: y d1752126 ADW LRM cache not getting updated with std models when moving from 16.6 to 17.22 Y$ u& O* U/ Z7 a) v; I1 Y
1754444 ADW LRM Update Standard library in LRM causes an error, "Cannot proceed with update as don't have permission to delete."$ L$ G$ F R& @' i5 `- X# B! `: T
1715861 ADW SRM symbolrevchk.par has incorrect variable name for SRM to ignore the tool version
- O8 c, [& j0 E: i" F1628403 ADW TDO-SHAREPOIN Objects remain checked-out after multiple failed 'check in hierarchy' attempts5 G& s% n, m2 h, h; O- o4 C4 O* f4 ?. ^
1759250 ALLEGRO_EDITOR DATABASE Flex-rigid placement does not move bottom pads to nearest layer' ^9 \/ c' |$ H1 ^8 M9 X
1762782 ALLEGRO_EDITOR DATABASE PCB Editor crashes when creating artwork
( ~0 t6 I. N e, w1 S1746665 ALLEGRO_EDITOR DFA Cannot scroll in DFA Constraints Dialog if the DFA constraint file is read only) n/ ^. D- V, k1 `7 r2 b9 M+ A
1750084 ALLEGRO_EDITOR DFA DFA spreadsheet disappears from the DFA library if hyphen is present in the name6 ~# M! a& ^# H
1697155 ALLEGRO_EDITOR GRAPHICS Position and size of Show Element and Measurement windows not saved in PCB Editor
+ o E5 ~" F1 D7 `7 u( Q1734282 ALLEGRO_EDITOR GRAPHICS Placement of reports and pop-ups not retained in PCB Editor8 w4 O' ?' ?& _7 O
1740863 ALLEGRO_EDITOR GRAPHICS Show Element and Measure windows do not retain position
. X3 y+ p6 F* t$ b: D1749687 ALLEGRO_EDITOR GRAPHICS Position and size of Show Element and Measure windows are not saved in PCB Editor in release 17.2-20166 S4 t8 V0 h& x" _6 O
1764124 ALLEGRO_EDITOR SCRIPTS Replaying recorded script file crashes PCB Editor
9 D' f: p+ Y8 [. [2 z* Z0 h" \: w8 {1762888 ALLEGRO_EDITOR SHAPE Border line missing for some crosshatch (xhatch) shape voids% X# I: ?! N+ N+ n* s2 I/ l: N, A
1763619 ALLEGRO_EDITOR SKILL Incorrect text block name when extracting text parameters using SKILL
( P/ U& c8 q; n; H/ t1685826 ALLEGRO_EDITOR UI_GENERAL Reports when opened from Status Form disappear behind PCB Editor canvas when clicking on canvas
+ e* z& v' G. ^( ?% Y1733552 ALLEGRO_EDITOR UI_GENERAL Although F1 is defined as an alias for another command, pressing F1 opens help# k; t0 f1 {+ s
1735098 ALLEGRO_EDITOR UI_GENERAL axlUIYesNo displays garbled text when customized for Chinese in release 17.2-2016
7 l w5 Y; W, P1753430 ALLEGRO_EDITOR UI_GENERAL 'Tools - Quick Reports' opens only one report at a time
/ k6 o8 k2 h' p) i6 ?1754283 ALLEGRO_EDITOR UI_GENERAL Call multiple reports from a function key2 B3 v& x5 a% f) ^+ j
1742822 APD STREAM_IF Component pins are not mirrored properly when mirror geometry option is checked and component is mirrored at 90/270
7 n& O& s$ X3 d, \. J# \1762284 ASDA COPY_PASTE Copying testpoint crashes tool and eventually the operating system
8 t+ _9 i1 r: s% ?1655057 CONCEPT_HDL COMP_BROWSER ADW Part Manager and Component Modify hangs
( R, F8 u1 R* ~/ `, ~4 S6 M3 T1689740 CONCEPT_HDL COMP_BROWSER Bad response time using Dehdl component browser
. ^5 y4 B2 u- _# Q3 I4 c% ]: K* V1735332 CONCEPT_HDL COMP_BROWSER Sort in mathematical order Symbol list in Component Browser1 p# e) w* W9 ^. v7 F1 x
1739197 CONCEPT_HDL COMP_BROWSER Part Information Manager can`t sorted symbol version4 M: s/ \2 R5 A+ m
1764605 CONCEPT_HDL CORE Signal added from the console should be 'Left Aligned' instead of 'Center Aligned'8 o y/ g; g$ p1 c" ^- \* x3 S5 y
1761706 CONSTRAINT_MGR CONCEPT_HDL cmDiffUtility has a typo in the usage statement2 n3 m/ C8 G' Z# V# c- v4 P
1758426 ECW DASHBOARD Behavior of 'Apply Label' for Dynamic and Status labels should be same in TDO and DE Webpart
8 G& Z- N# R0 u* G1 F8 y1764096 ECW PROJECT_MANAG Renaming project using the ETD window randomly hangs the edit window, refreshing bring backs the page" i( |# l; _! H& M- @5 Q% W% k$ p
1764070 ECW TDO-SHAREPOIN Join Project: Multiple entries shown for workspace/project with multi-hierarchical structure* s! i! F) i* T+ I& n
1754473 FSP DE-HDL_SCHEMA Provide an option to generate symbols with custom attributes' `1 m9 i4 r8 p; Y2 J( F, l
1724124 FSP DESIGN_EXPLOR Provide Tcl command to filter data in Design Connectivity Window
( }6 l0 l8 E: t* q. \2 u1726548 FSP OTHER Unable to open FPGA system planner if username/log file path has Cyrillic letters
( _6 j h9 Z$ K8 g& @1719133 SCM SCHGEN Voltage symbol not getting placed for some of the voltage nets
1 I& y; [7 o$ U9 J2 S& z' i1680989 SIP_LAYOUT ARTWORK Artwork film set-up: Match Display including invisible layer& @$ n# t& ~) Y8 k" h
1732218 SIP_LAYOUT DEGASSING Shape will not degas as needed - not all voids degassed
- c1 ?* W% Y4 U' O1763280 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout does not recognize width of segment when importing .xda, c$ s) W: u9 t4 t) h. y
1762992 SIP_LAYOUT OTHER Saving a design after adding a solder mask layer in the cross-section crashes tool
# n! S' ~( y( Q# H" F& E3 G: d7 O8 \% k
8 R) Y; ]$ R/ ]3 [/ A) b N
Fixed CCRs: SPB 17.2 HF022
# w+ [: d. t6 ?$ z" @7 v7 o& o06-16-2017
% @9 S0 r) y# Y( x! @========================================================================================================================================================/ k @! J/ a% g
CCRID Product ProductLevel2 Title- x. l2 \# v$ ]) |5 Y0 h
========================================================================================================================================================
5 p* u3 j+ l, f9 r; k6 H1755789 ADW DBEDITOR Checking in HSS Block returns 'Failed to create archive'4 d4 B/ ~4 r) B4 z H
1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager
# ~& Q! P, l x0 `- c5 h4 U1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager
2 Z, l; G- S. D. J1744081 ADW FLOW_MGR Error regarding configuration file when trying to open Workflow Manager2 g( Y3 _; |( ]. X/ l
1756727 ADW LIBIMPORT EDM Library Import fails with java exceptions when merging classifications
' N" {" A& w# X1743763 ADW SRM Find filter is grayed out when Allegro PCB Editor is opened from EDM Flow Manager
8 d; n+ i2 M7 E8 S5 i1748399 ALLEGRO_EDITOR DATABASE In release 17.2-2016, end caps not visible for certain clines in PCB Editor$ g/ s" L2 p8 Z) v3 S/ u5 e; j) d
1748522 ALLEGRO_EDITOR INTERACTIV A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it0 T& w$ n5 P5 _. X, m8 A8 E
1734983 ALLEGRO_EDITOR INTERFACES Secondary step model does not stay mapped after drawing is reopened
3 R. C6 q; D, e1753704 ALLEGRO_EDITOR REFRESH Refreshing symbols crashes PCB Editor' w0 @- i! U1 |5 j$ b2 H2 [" w _
1493721 ALLEGRO_EDITOR SHAPE Voids on negative planes are not adhering to constraints
5 [% q5 R2 f0 Y- E/ Q3 G- v1711242 ALLEGRO_EDITOR SHAPE Route keep out leads to partly unfilled shapes with gaps
6 t5 T' o/ K3 l1726865 ALLEGRO_EDITOR UI_GENERAL Pop-up Mirror command does not mirror at cursor position! [, Y6 u* M: C0 g l9 H
1752987 ALLEGRO_EDITOR UI_GENERAL axlUIViewFileCreate zoom to xy location not working while in user created form.% `( E1 [" L5 U" q' u9 `
1755638 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run5 w) z% ~! X/ m, d8 ?# O
1719792 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC hangs or crashes PCB Editor$ I+ S% P; i6 t9 M. B& A
1624869 ALTM_TRANSLATOR CAPTURE A structure file is required to translate a third-party schematic to OrCAD Capture
' ~3 R' {2 o0 I4 _# ]! g1707416 ALTM_TRANSLATOR CAPTURE Missing components and pins in the OrCAD Capture schematic translated from a third-party tool4 {& r5 {) E1 e- w5 Z& j3 ?
1708825 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate the schematic2 E* }4 x( }- s# l
1719200 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate all the pages of a schematic8 O# m* x9 A: d/ H
1546070 ALTM_TRANSLATOR CORE Third-party to DE-HDL schematic translation fails5 ~1 |% y7 R- J2 o( P! q. w
1700508 ALTM_TRANSLATOR CORE Third-party PCB translator does not work in release 17.2-2016
$ E. P) p" |* T' \$ M6 |. [3 F b- y1699340 ALTM_TRANSLATOR DE_HDL Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor
R/ d/ [' W0 X( V% s1630379 ALTM_TRANSLATOR PCB_EDITOR Third-party translator is not importing clines and vias
' o5 W8 y* M8 m& G- t! s. s+ Y4 { w1708615 ALTM_TRANSLATOR PCB_EDITOR All items of third-party PCB not imported in release 17.2-2016. M, [% l- d" B
1758296 APD DXF_IF DXF OUT: Rounded rectangle pads mirrored incorrectly
3 p! ?/ N/ y ?: V1756040 APD IMPORT_DATA The 'die text in' command ignores values after the decimal point6 |! w, q& X5 s4 o; ^( w3 N# N, o$ I
1727206 APD SHAPE Merging two shapes results in an incorrect shape
4 b& w% q7 }/ l& K2 r1753682 CONCEPT_HDL CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL
4 E0 c! g, F' \4 o- K: Y1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic
+ V! O1 \+ e' R/ K* Q5 `+ l6 P2 o1747559 CONCEPT_HDL CORE Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)
$ j6 W; k, S9 r* K* R) n2 d/ }1749644 CONCEPT_HDL CORE In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes
" c) {4 }) f W+ K1746910 CONCEPT_HDL GLOBALCHANGE Global Component Change unable to identify part data when using schematic pick option
2 l9 w& Q: F. v8 G! Y5 {+ n1 N' T1743572 FLOWS PROJMGR Project Manager displays incorrect values in Project Setting
9 {9 I( L) V5 S q2 Q, ?! V' s1724124 FSP DESIGN_EXPLOR Provide TCL command to filter design connectivity window9 U2 ?. S7 ~1 [' e: n
1719105 FSP GUI Tabular sorting not working in FPGA System Planner1 k/ `" w, o% L# K- K6 ?+ E) T
1755750 PCB_LIBRARIAN GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor$ n$ U8 U7 ?1 l# J
1722993 PCB_LIBRARIAN IMPORT_CSV Part Developer crashes while importing part information stored in a .csv file* G! n/ i0 o( V0 e1 c0 p" b
1758856 SIP_LAYOUT 3D_VIEWER Correct the spelling error in the 3D Viewer Design Configuration window
, J7 t" C+ b( a6 z# \1755179 SIP_LAYOUT ARTWORK PCB Editor crashes when creating Gerber files( H/ b- y) K% E
1743511 SIP_LAYOUT MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check
- I0 Y6 I6 c7 T/ e& E( d
2 u) L7 V2 D: k1 ? o. S9 s2 C7 d$ G! k, d3 B- k( q& N
Fixed CCRs: SPB 17.2 HF0214 X! s# _9 s, R' K4 Y& X: O
06-3-2017- h P4 f$ k1 d& l' v
========================================================================================================================================================
d2 q7 T6 G8 x$ {1 ^9 M; f: B, VCCRID Product ProductLevel2 Title1 U# I1 E- }) A5 k
========================================================================================================================================================
) s/ f2 W: ]" s* {& Z# r4 Q/ L0 _$ s! d1401318 ADW DBEDITOR Bulk Edit - Previously modified cells do not turn blue when selected' d/ j$ l$ h/ n
1621446 ADW DBEDITOR Bulk Edit - sorting highlights incorrect cells to mark them as changed/ Y g9 L% l: l. M( Z+ r& R R
1743997 ADW LIB_FLOW Match file for standard models is incorrect
* n: |& z! q. u* L# o6 q0 q* E1746052 ALLEGRO_EDITOR DATABASE PCB Editor crashes when applying no drc property
& F+ H' R9 a( } c9 o1736067 ALLEGRO_EDITOR DRC_CONSTR Interlayer checks not reporting DRCs between cline and mask layer0 M7 R ]9 m7 q7 @/ O4 i% @
1738587 ALLEGRO_EDITOR EDIT_ETCH Line width changing on slide for ETCH - Conductor (Not on a NET)4 L: J* U! @3 Y/ i) V2 P7 O
1745277 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using the slide command* z( E* w' D% O0 o6 R3 z
1747942 ALLEGRO_EDITOR EXTRACT Fabmaster Out does not export arc in pad_shape7 t! R0 V" ] Z
1737202 ALLEGRO_EDITOR GRAPHICS Setting the variable display_raster_ops0 C# q' ~$ J) W/ }8 r
1744042 ALLEGRO_EDITOR GRAPHICS Unused pad suppression is not working on few nets
4 W5 S7 X) h/ x! x0 ]1703848 ALLEGRO_EDITOR INTERFACES IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty( Y0 a: b) n6 S, _) d/ s0 g! o/ L
1743899 ALLEGRO_EDITOR MANUFACT Glossing dangling vias crashes PCB Editor
1 g! E" l' _2 F8 r! _1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor
$ Q% c) V7 m- _2 w8 M! v7 _1748520 ALLEGRO_EDITOR OTHER TDP fails to load on an empty database
9 [4 v3 t7 ^) \+ Y/ M4 z1748581 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when changing default pad geometry6 Z" q+ c7 l* ^
1751469 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes/freezes when browsing for a shape symbol
- H! ~7 W4 J* b! j; l1725948 ALLEGRO_EDITOR SHAPE Shape differences after conversion from release 16.6 to release 17.2-2016
1 Z2 W: p0 e8 k2 g1729306 ALLEGRO_EDITOR SHAPE Seting shape_rki_autoclip variable causes no void to be generated. X I# O, q, M7 I: p* v
1698876 ALLEGRO_EDITOR UI_GENERAL Tabs are large and text is compressed in release 17.2-2016
! h( Z* b1 G9 q+ E1698883 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors* C8 X: u* |3 _/ l
1707933 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not locating menu as per x_location
/ u q# u' h" M( C- p1741460 ALLEGRO_EDITOR UI_GENERAL Right-click, context menu options grayed in some cases after choosing Edit - Copy: f( t' h( n4 z4 D! b
1747588 ALLEGRO_EDITOR UI_GENERAL Interacting with PCB Editor by sending messages is not working* K1 z: u. A! o" b% A4 l
1747488 APD EDIT_ETCH Route connect is improperly affecting existing routes in locked high speed via structures- x8 d! S% Z- X5 ?
1750182 APD STREAM_IF The stream out settings are not saved+ n/ v% y3 t* O5 n
1752067 ASI_SI GUI Links to differential waveforms do not work in Sigrity SI report9 U5 z! R1 c' {; \5 D
1752131 CONCEPT_HDL COMP_BROWSER Symbol view in part manager doesn't match the symbol version
" t2 d" L/ D. k9 J1 e! _; U) Q# ]1754116 CONCEPT_HDL COMP_BROWSER Default Symbol selected is n°2 instead of n°1 in component Browser
5 B. n0 x0 i% R4 s2 [0 l( G1754949 CONCEPT_HDL COMP_BROWSER Part Information Manager displays preview window with the wrong symbol and missing footprint* e: Z' I( B. p. G/ M1 D
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic. j, W/ y( L0 K. d# o
1750916 CONCEPT_HDL CORE DE-HDL crashes when trying to uprev a project in release 17.2-2016
E% Y* `& D4 K' P1711487 CONCEPT_HDL INFRA Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design
, V/ }9 P2 [, |+ S, g& \1746915 CONSTRAINT_MGR CONCEPT_HDL Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow
, d! A: X4 D) o3 }1 v1743523 CONSTRAINT_MGR DATABASE Suppress warning pop-ups from the constraint automation script: H2 y( [ Y% o! k8 m" @$ ^9 Q
1746941 CONSTRAINT_MGR UI_FORMS 'Go to Source' from DRC tab is not working in release 17.2-20161 e2 B" K. f( w' K; t
1753010 ECW METRICS Metrics not getting collected due to old license in use& B( O i8 K5 B# O
1713052 FSP GUI Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance
3 F. h' J8 |) V1 f0 M$ u3 Z1 {1719099 FSP GUI Net naming wrong after building block
U& d: ?1 m4 s, }8 e1719105 FSP GUI Tabular sorting not working in FPGA System Planner- g" Q9 v. L/ ]& L0 X
1720479 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems
3 }8 J P9 b$ {1723411 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems9 B ?: D! I" Q9 X
1746628 PSPICE ENVIRONMENT PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016
8 S/ K9 N2 Q9 y, S. f1745976 SIG_INTEGRITY GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing% f) a& T4 T8 d9 m0 I7 V/ P
1690820 SIP_LAYOUT PLATING_BAR Cannot add fillets to pads with plating bars in release 17.2-2016: p* V y1 Y! j s
1725042 SIP_LAYOUT PLATING_BAR Creating a plating bar removes dynamic fillets: f+ _! q; `. }9 A: I5 d2 G
1747534 SIP_LAYOUT SHAPE Moving fiducial crashes SiP Layout0 O! `! @$ J' h% d) f" [
; M8 Y+ z5 M0 M' c X# m; _6 A$ e1 x; v/ m. G( F
Fixed CCRs: SPB 17.2 HF020& D2 Z$ y$ N1 S% u/ Y$ [3 R
05-21-2017. Z: R" h# _3 W1 ^& A
========================================================================================================================================================
& m! s3 c; R! n+ iCCRID Product ProductLevel2 Title3 G0 n q0 _! n6 q9 n
========================================================================================================================================================
; W3 k0 c3 L: P0 a7 D3 D8 _1737443 ADW DBEDITOR Revising the schematic model classification for one category causes all parts in the library to be revised
; y. E$ H ]4 G L- o) P1734123 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas crashes Allegro PCB Designer in 17.2 S016
: |0 K/ f$ G# @& {* d& c1742084 ALLEGRO_EDITOR DATABASE Running DB Doctor on DRA files with custom pad shapes resets some of the custom padstack shapes in release 17.2
7 |. A. p3 D/ O' B' o" u1739397 ALLEGRO_EDITOR INTERACTIV In release 17.2, running the SKILL function axlImportXmlDBRecords causes Allegro PCB Editor to crash1 K9 M6 C B9 ^5 _! n5 o. j
1724588 ALLEGRO_EDITOR MANUFACT Backdrill Route keepout suppressing existing Route Keepouts8 G( T% P! c+ e
1740036 ALLEGRO_EDITOR MANUFACT Generating the cross-section chart does not provide information about the overall board thickness2 Y3 t4 ~4 x4 y
1743726 ALLEGRO_EDITOR OTHER IDF file export: In release 17.2, only one design outline is exported as against multiple board outlines in release 16.6
7 B9 A; C- c* x+ l1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor
4 e# x; y ]& y9 a3 [- }& t1729350 ALLEGRO_EDITOR REPORTS Net loop report is not working.! N! w) y+ g& x! P. X& S, [! O
1713014 ALLEGRO_EDITOR SHAPE Incorrect behavior of donut shaped pads at certain rotations) Q* H' ]: ^2 E7 s# _% J
1739870 ALLEGRO_EDITOR SHAPE The artwork is different from the PCB in release 17.2 Hotfix 17
' Q T% | S. q1698869 ALLEGRO_EDITOR SKILL PCB Editor crashes when trying to open another .brd file after running SRM on first .brd file$ g9 o+ T% D, b7 d7 v6 r: e
1739307 ALLEGRO_EDITOR SKILL axlCNSDFAExport fails after first run. @% Z7 I# a: u9 p
1743385 ALLEGRO_EDITOR SKILL SKILL APIs for STEP model mapping are not available in release 17.2 Hotfix 17 or 18
! Y, l* m1 l1 K9 l6 N1 V1685826 ALLEGRO_EDITOR UI_GENERAL Reports when opened from Status Form disappear behind PCB Editor canvas when clicking on canvas" D' X( U6 ~; o; e g( E4 F
1687797 ALLEGRO_EDITOR UI_GENERAL Cannot open two HTML windows, one after the other, while using SKILL function
3 Z6 Z. x/ O. @' r) o% h, {: [; m* {1696229 ALLEGRO_EDITOR UI_GENERAL Setting the 'allegro_html' environment variable in User Preferences Editor overwrites existing popup text windows
# M0 @7 U1 }5 X9 I1708636 ALLEGRO_EDITOR UI_GENERAL In SPB 17.2 release, keyboard focus automatically shifts to the newly opened dialog box
/ F0 A) o* o3 @" q d; _1 n/ @6 _1711367 ALLEGRO_EDITOR UI_GENERAL Launching two report windows using SKILL is not working in 17.2
0 m& q6 H% Z/ W: ^) e9 @3 [1742856 ALLEGRO_EDITOR UI_GENERAL Allegro PCB Editor crashes if Project Manager is open for a design in release 17.2 Hotfix 18
- _8 A' q% f' e& Y+ f1729519 APD SHAPE shape degassing does not generate all voids to cover entire shape
3 F; s9 A# l: v4 h) \" ` y" M4 P1711375 CONCEPT_HDL CORE Copy-paste of schematic between two instances of DE-HDL is not working as expected0 Z6 t; S# Y/ O9 [" [
1737230 CONCEPT_HDL CORE On the Linux platform, copying of schematic objects does not work between designs of releases 16.6 and 17.23 k7 I2 U, B: c0 u! X! Q
1741375 CONCEPT_HDL CORE Inconsistent behavior of the Move command when moving a symbol3 B: F" W# N4 h0 o: K/ w
1743992 CONCEPT_HDL CORE Inconsistent behavior of the Move command when moving a symbol
N' a) ]: V, \& C. U1736093 CONSTRAINT_MGR CONCEPT_HDL Incorrect topology extraction and mapping errors related to MUX parts
% K# u: i2 a" u- F6 O3 n' j7 s, F1743518 CONSTRAINT_MGR CONCEPT_HDL Lag observed in expanding and collapsing the net classes in Constraint Manager4 H. X# v/ Y, W' e/ X, O
1730159 FSP ALLEGRO_INTEG FSP diff engine does not read PF Thevenin connections in FSP" `( J2 o- H6 k- K2 h
1664070 ORBITIO ALLEGRO_SIP_I Display pads of SMD components on correct layer
4 H' ]6 J9 N; c+ R/ S1709319 ORBITIO USABILITY OrbitIO issues an error about Device template while importing brd with Bundles- v3 c% B: O' m' N s
1741150 PSPICE ENVIRONMENT Need a way to prevent the 'pspSimSetting.js' file from being overwritten by a hotfix installation in 17.28 w# \" w, L/ D( n6 I2 H2 B {
1735354 PSPICE SIMULATOR Access to custom nom.lib is not working as expected
1 s9 B5 c/ K- _) {1716523 SIP_LAYOUT COLOR Tool crashes on using the PageUp, PageDown, and Tab keys in the Color dialog box.
' G; N% y5 b. e3 [$ r; T# y3 T& E- k) w4 Y
! a t" n. M& X
Fixed CCRs: SPB 17.2 HF0196 p& ^3 r4 a& a! s7 ^: d
05-6-2017
5 X5 w B. R/ U' V& L========================================================================================================================================================' C" j( h8 `7 P/ T
CCRID Product ProductLevel2 Title
9 k' L/ {+ A, X* s9 o( ~" u========================================================================================================================================================+ P' u' j; ]! j! }! c
1701785 ADW ADWSERVER Getting 'Unable to locate tools.jar' error while using 'Copy Projects'" t' h2 O( _1 ?+ s; p
1706782 ADW ADW_UPREV Design uprev failed with error 'ERROR (FM-107): Failed to run adw_uprev'2 L) |. I( M( @! `# D: `
1508159 ADW FLOW_MGR Flow Manager 'Open Last Project' option points to a deleted project
9 R( B. N ^+ @/ e u' J1690903 ADW FLOW_MGR Flow Manager library project list empty after 'Remove From List'
/ M" r" P# D6 a$ H1705224 ADW LIBDISTRIBUTI Cannot migrate Library Footprint Models having subdirectory to release 17.2-2016( V6 [5 x) p2 B0 q
1672037 ALLEGRO_EDITOR EDIT_ETCH Add ZigZag Pattern crashes PCB Editor
/ K7 g, ]: p6 t2 d# x$ n8 e6 T" h1695711 ALLEGRO_EDITOR EDIT_ETCH In release 17.2-2016, Fiber Weave Effect - Add ZigZag Pattern crashes in Windows 10' h7 m& t% ]1 Q. k4 p
1706522 ALLEGRO_EDITOR INTERFACES DFX import displays error message '*Error* eval: undefined function - cloneID' but imports outline
7 N2 \9 f8 B% m- J% t. N& K1716336 ALLEGRO_EDITOR INTERFACES DXF file is not correctly imported into PCB Editor
, f. O5 E) }4 `1 u& L1720290 ALLEGRO_EDITOR INTERFACES Incorrect rotation of padstack after dxf import8 U& D" o, K$ j6 o
1724683 ALLEGRO_EDITOR INTERFACES DXF OUT: incorrect Rounded/Chamfered rectangle pad rotation
. P6 W5 s2 A1 S X2 B1732587 ALLEGRO_EDITOR INTERFACES Format/content of ipc356 files exported in release 17.2-2016 different from release 16.6* t( S) X+ x* _# k
1737516 ALLEGRO_EDITOR INTERFACES IDX Import works differently for placed and unplaced parts
. P9 l+ J! M6 J8 P+ s& q1715152 ALLEGRO_EDITOR SCRIPTS Clicking Layout in Project Manager fails to load PCB Editor and gives message 'Word too long'- K* O) p) E6 F# T. |* B- r
940699 ALLEGRO_EDITOR SHAPE Update shape to smooth fails to void a few clines.
! Y7 g. S3 l1 q, z9 @+ S1706581 ALLEGRO_EDITOR SHAPE Dynamic shape void clearance errors with vias1 I1 H3 H5 z. W B% X$ H- |
1638300 ALLEGRO_EDITOR UI_GENERAL Version information set in $cdsversion truncated on title bar for some tools
7 @, r6 y" d1 c3 G4 a9 P6 Q" h* P1697732 CONCEPT_HDL CORE Pasting a signal name results in warning (SPCOCN-922) if the wire is too close to the edge of the page border
: |. N4 a2 M3 A& T( a% P: W1729510 CONCEPT_HDL CORE Changing the name of a split block adds pages that are part of the page gaps
% ^5 {& J% `$ ^& Q# L0 e5 W5 u- |, F1721065 CONSTRAINT_MGR CONCEPT_HDL Physical import errors on changing plane to conductor in stack-up6 r+ Z2 K: d0 o2 b, ]3 f
1734875 CONSTRAINT_MGR OTHER 'Create Spacing CSet' crashes tool from existing CSet context and grayed out in design context) Y/ M! H, |1 Y# o+ V0 W
1473104 ECW PART_LIST_MAN Pulse does not filter capacitor values correctly
* s. p4 k$ ]9 M/ h" P1736580 PCB_LIBRARIAN SYMBOL_EDITOR Grids are not displayed correctly in Symbol Editor
2 `6 H! K/ M2 {, n1738955 PCB_LIBRARIAN SYMBOL_EDITOR Need ability to edit Symbol Properties: [, M8 A1 j& m7 z8 p( @0 C
1735215 PSPICE FRONTENDPLUGI PSpice part search customization CDN_PSPICE_ODBC_SRC environment variable is not working( \: I+ Z6 i5 G
1733198 PSPICE PROBE Probe crashes when exporting trace expressions with multiple plots to CSV files
1 t7 A, A. D+ X: Y/ [* r ]3 v5 ^1737060 SIG_INTEGRITY SIGNOISE signoise fails for the AllegroSigrity_HS_Base_Suite option in release 17.2-2016 and release 16.6-2015
$ m, B2 m/ ^1 k1 F5 V1707443 SIP_LAYOUT WIREBOND Moving bondfingers violates spacing constraint
$ \2 O2 u6 C2 {9 g( p. C' X- [$ |5 }: K V I$ T/ d& G+ O) C
' t: t+ h: r+ Q3 i
Fixed CCRs: SPB 17.2 HF018
9 z. C: F* L& d' V, c04-23-2017" Z& N0 Y; x4 t. T
========================================================================================================================================================
. @' i/ i% j: F" O5 F( VCCRID Product ProductLevel2 Title
: P7 a- y! {$ H2 R# j9 R========================================================================================================================================================6 r( l: y4 E9 K- K% Z i
1721773 ADW ADW_UPREV adw_uprev updates all versions in history log to the new version. Should only insert note about uprev.
8 s% Q" d8 y7 A. T+ `1684346 ADW LIBDISTRIBUTI lib_dist_client fails for new release 17.2-2016 design server9 H* M/ j9 O! o+ N) G k; I
1696632 ADW LIBDISTRIBUTI lib_dist_client fails on release 17.2 Designer Server having release 16.6 Master Server
: N2 y9 J$ N c) F1705224 ADW LIBDISTRIBUTI Cannot migrate Library Footprint Models having subdirectory to release 17.2-2016, R( Z, Y# i7 @ v7 m
1721017 ADW LIBDISTRIBUTI adwserver -install fails intermittently during Master Library Server or MLR distribution
# k6 g% Z" ]% B1 H! ~1 n1 H$ C1711373 ALLEGRO_EDITOR COLOR Cannot interact with Allegro PCB Editor when Color dialog is open
" U& x, B) W6 |1710772 ALLEGRO_EDITOR DATABASE Mirror command not working on zones
3 E; f) a9 r: ]+ O" ~0 J1725621 ALLEGRO_EDITOR DATABASE PCB Editor crashes when moving a group of components or clines ^' k; P! B/ ]! B4 |% \8 a
1699796 ALLEGRO_EDITOR EDIT_ETCH AiDT fails and reports there are no timing constraints even when propagation delay is set
9 a$ W- U; m- P1726483 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashing when converting corners to arcs
4 n' a9 ?3 {( s" N( t1726678 ALLEGRO_EDITOR INTERFACES IDX copper layer export does not export all pin pads
8 }, D+ i: I4 A' v4 {' ^1 H' Q1691036 ALLEGRO_EDITOR MANUFACT Fillet not centered on trace
+ e! R* \' Y" [/ U1 u- ~: d1732304 ALLEGRO_EDITOR MANUFACT Countersink does not have drill figure on NCCOUNTERDRILL-1 subclass
$ t! z, w) y! {1719564 ALLEGRO_EDITOR OTHER Cannot open PDF published in release 17.2-2016 in third-party software" M$ c+ q- a; n3 u
1723065 ALLEGRO_EDITOR OTHER PDF out does not print the outline correctly
! Q# E- m( J+ ]$ X G$ G1729247 ALLEGRO_EDITOR OTHER Cannot delete shape on Route Keepout layer; p- s+ N" m! d) o% p( C
1722747 ALLEGRO_EDITOR PAD_EDITOR Option to enable 'Connect by Touch' in Pad Editor) k* @4 L" W. c+ p5 Y
1731643 ALLEGRO_EDITOR PAD_EDITOR Changes to secondary drill are not saved on padstack update
8 T' x8 O; ]& I. E1727303 ALLEGRO_EDITOR REPORTS The 'Shape Dynamic State' report has changed to 'Shape Dynamic Status' in release 17.2-2016
: C+ X$ l& V3 ^+ b+ K6 a1695879 ALLEGRO_EDITOR SHAPE Dynamic shape priority error creates shorts.
3 h0 e2 u* B5 y) L1713014 ALLEGRO_EDITOR SHAPE Incorrect behavior of donut shaped pads at certain rotations
: o1 Z0 s. \ S5 L2 a* j/ Q1588769 ALLEGRO_EDITOR UI_GENERAL Alt+key shortcuts are not available in release 17.2$ I4 b0 U* ]8 \' s! [
1602563 ALLEGRO_EDITOR UI_GENERAL Shortcuts to menu items not working in release 17.2- j* ]$ c& ]$ X2 v! ]
1603776 ALLEGRO_EDITOR UI_GENERAL Alt key not working with menu commands
( H N, m* S- N5 c. q% `1 K/ Q1611516 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts have no response0 i$ e" a9 N# G, ?5 Y( g
1647271 ALLEGRO_EDITOR UI_GENERAL Preselection is not working for docked Find window
t+ t" F) t/ n' v: ]1650044 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts are not working properly in release 17.2
4 q0 i* P8 p) L8 E) y1651912 ALLEGRO_EDITOR UI_GENERAL Inconsistent response when using the Alt key) Q1 u; Q0 ]; J+ \0 E
1679964 ALLEGRO_EDITOR UI_GENERAL Many dialog boxes are blurred in Allegro PCB Editor' ?) d! [- W7 Y; q* n q% Y
1692416 ALLEGRO_EDITOR UI_GENERAL Underscores in menu commands denoting shortcuts are missing in release 17.2
. o$ R. Q) l. E9 n& \1 r1693055 ALLEGRO_EDITOR UI_GENERAL Reports with html links end with an extra > at the end7 q" K2 c$ H0 ]
1693968 ALLEGRO_EDITOR UI_GENERAL Batch process that uses SKILL is taking too long to process files and generate reports7 g1 {1 Y+ M3 p9 v s( I
1698840 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016 Waive DRC report, selected coordinates of a Waived DRC remain blue6 T6 n% t& w# s! V! R4 t" U6 k
1703065 ALLEGRO_EDITOR UI_GENERAL Menu shortcuts do not work as expected
" {# B6 J" @& z1707547 ALLEGRO_EDITOR UI_GENERAL Release 17.2: The Alt key function is not working in PCB Editor
5 @ x3 m$ Y. F8 ~, B0 }" j- G1709280 ALLEGRO_EDITOR UI_GENERAL Alt+Function key not working in release 17.2.
1 F. Q- ~' Q1 i8 b! Q6 {( A1711203 ALLEGRO_EDITOR UI_GENERAL Color does not change for selected coordinates in reports and Show Element2 Z2 F+ h4 j m) I
1711724 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, custom interactive menus stop responding when invoking another custom command! L2 u3 K, O! U0 Z3 o0 U' q
1715613 ALLEGRO_EDITOR UI_GENERAL With undocked Options window there is a mix up of entered text and funckey0 H% z1 }! F- T0 g2 u) R
1719301 ALLEGRO_EDITOR UI_GENERAL Selected coordinates do not change color in reports and Show Element* c3 N2 [) u) Q8 J8 k) c3 Z
1724197 ALLEGRO_EDITOR UI_GENERAL Short cuts and hot keys not working in PCB Editor in release 17.2-2016
) Z0 z/ }: u$ P1728724 ALLEGRO_EDITOR UI_GENERAL Funckey is not working in release 17.2-2016
2 ^* W4 P2 w& N% W1 ]1673703 ALLEGRO_PROD_TOOLB OTHERS Design compare not reporting the Top and Bottom layer differences, Y. D9 t3 E" s, P q. y
1704474 ALLEGRO_PROD_TOOLB OTHERS When using Productivity Toolkit - PCB Design Compare, 'Override undefined width' is incorrectly applied7 D7 U, a0 |8 C! z8 o" ^
1571035 ALTM_TRANSLATOR CAPTURE Circles in third-party schematics not getting translated into Capture' O9 N2 r. y4 i4 |6 {4 V
1588911 ALTM_TRANSLATOR CAPTURE Capture crashes when translating, project and libraries are empty% E8 d# y+ p9 R: }- \
1589394 ALTM_TRANSLATOR CAPTURE Schematic getting shifted off the page after translation* @/ `3 g/ C+ Q$ {* N' }1 w
1631294 ALTM_TRANSLATOR CAPTURE Errors while translating third-party design when original design is in metric units3 B; q* K) v- c( R
1663176 ALTM_TRANSLATOR CAPTURE Only first sheet of design getting translated from third-party schematic into Capture7 U9 H' G$ h# G# \: k, U
1694363 ALTM_TRANSLATOR CAPTURE Capture is unable to translate third-party designs! k$ ]# ]& b4 s7 |( `2 S
1539739 ALTM_TRANSLATOR CORE Capture crashes on importing a third-party project
' {& u3 B2 K" ~2 V* o1542860 ALTM_TRANSLATOR CORE Capture crashes on clicking Translate after selecting a third-party design5 A1 c/ _9 {5 Y
1551642 ALTM_TRANSLATOR CORE Unable to import third-party schematics into Capture
( j5 l; W$ B, H4 |8 T& V1572929 ALTM_TRANSLATOR CORE Footprint names getting altered during translation
* H/ n O+ a$ S) h% E a2 F% K, g9 N1568436 ALTM_TRANSLATOR PCB_EDITOR Unable to translate third-party layout data into PCB Editor
! r% Y. M9 \. D: k& a6 Q& I1629256 ALTM_TRANSLATOR PCB_EDITOR Getting empty symbol and devices folders when importing into PCB Editor
( k# ?9 ~$ u) T$ w3 |1664120 ALTM_TRANSLATOR PCB_EDITOR Import from third-party to PCB Editor is not translating data correctly
, R0 I+ O$ _! t+ P+ x1701537 ALTM_TRANSLATOR PCB_EDITOR Import does not complete and reports errors. p: K9 T% u" [3 Y& j6 F
1698706 APD DIE_GENERATOR When using Compose Symbol from Geometry, circle from DXF cannot generate to pin; [6 Q$ c# _1 ]/ _0 o' f; R
1714528 APD DIE_GENERATOR Getting 'illegal pad pointer' warning when creating die from geometry1 T: D0 v, J, P; }* a0 X2 X* Y/ @2 g
1714532 APD DIE_GENERATOR Compose Die from Geometry creates incorrect pad shapes, M' k) t/ G- ~: z8 }* x2 l( j! h
1734310 APD MULTI_USER Symphony server mode malfunctions when die layer present.
# z/ U: y' v5 L; z+ q1 x2 \5 ]1725506 APD SHAPE In release 17.2-2016 Hotfix 015, void is not generated in Artwork for BC7 layer causing short0 K: r9 I- i e) k# t: Q* s- j
1724395 APD WIREBOND Running axlBondWireDelete returns error message
: k" q/ i! ~8 |! s( M6 A, E1726609 ASDA CANVAS_EDIT Paste should not be allowed in the Current Refdes column of the Change Refdes form
' |& ~2 T" z- a+ B: ?6 |, z1719754 CONCEPT_HDL ARCHIVER Path stored in the compressed file starts from /home instead of the current working directory
7 e& n5 i$ E* I" w! @8 a0 Y1726570 CONCEPT_HDL CHECKPLUS Checkplus crashes on Windows 10
% K- C" v& H) T/ g1697977 CONCEPT_HDL CONSTRAINT_MG Differential pair disappears when it is packaged5 K; E- _% @/ i. E, a7 X
1679575 CONCEPT_HDL CORE Page numbers are duplicated in Hierarchy Viewer when editing page names
& y( G: a3 |6 ]1697732 CONCEPT_HDL CORE Pasting a signal name results in warning (SPCOCN-922) if the wire is too close to the edge of the page border
. g w2 v+ V0 X0 f1711564 CONCEPT_HDL CREFER CRefer crashes while processing a hierarchical design containing subdesigns6 ]4 I' y/ E' a
1730736 CONCEPT_HDL OTHER Crash on generating BOM from design1 _0 C. G# e( R ]; ~2 Z
1608350 CONSTRAINT_MGR CONCEPT_HDL Name of buffer model is not passed from Constraint Manager of DE-HDL to SigXplorer
# q* R0 N, H3 f7 m# z. C; E' ?1715803 CONSTRAINT_MGR CONCEPT_HDL Extract a net from constraint manager to SigXplorer, the models assigned are not displayed in SigXplorer" B& P1 s) e3 f" _
1718073 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors on an upreved design in release 17.2: Pins in XNet and CSet do not match
1 d# E" q( B2 ^3 d6 a9 t, {) a2 f* q1720886 CONSTRAINT_MGR CONCEPT_HDL SigXplorer does not extract assigned model from the schematic
4 M8 s2 z6 S6 Q6 E7 {( {2 r0 W7 @* M; n1718514 CONSTRAINT_MGR ECS_APPLY Extracted topology does not use the PINUSE overrides specified on the canvas. C. O9 s: y, {4 V# E" x E
1722306 GRE CORE Boards with Total Etch Length constraint only should not include z-axis when budgeting pin pairs
8 a# L3 S: z6 y2 b1710049 PSPICE SIMULATOR Functions are not taking parameters in correct order
5 I' \/ z# s1 Z' ]8 J/ x1693021 SIG_INTEGRITY OTHER PINUSE is not updated correctly at model assignment with specific steps d/ X6 o5 \8 C. N" _
1730854 SIP_LAYOUT SYMB_EDIT_APP Cannot delete all the die pin from a symbol using the Symbol Edit application mode
. K. j \3 c1 n) b" G/ b* P2 k' m' ~% J+ {8 ]: a( |' H0 _7 Z
* z- |4 K6 m$ a$ o! v, uFixed CCRs: SPB 17.2 HF017
: C7 U' g0 C4 h8 Z04-13-2017
8 y4 O% u" k+ ]) \' t5 l# S========================================================================================================================================================% |/ a0 w* q. A! x* ]
CCRID Product ProductLevel2 Title
6 J3 Y6 P% U5 j d0 M========================================================================================================================================================! L7 w Y7 d% U6 r
1732877 ALLEGRO_EDITOR SKILL The 'axlXSectionGet' function fails in release 17.2 Hotfix 016
+ D b4 @2 G% a# u; w( f% {; Y0 ~( J) U8 g1 i4 r
2 K+ V" f3 q8 f. K# x2 SFixed CCRs: SPB 17.2 HF016
: Z( `% G9 n" r( {; [04-6-2017
# a4 j9 y g3 J# v% J! ^========================================================================================================================================================
: L; p" N4 ?7 [8 j7 |# p1 dCCRID Product ProductLevel2 Title2 W5 `( l% N5 B7 @; A, e8 E$ J- g2 l
========================================================================================================================================================
0 V7 `! d/ }; E* G+ G& q1673128 ADW COMPONENT_BRO Directive is saved in project CPM
1 G4 S- |* L: i* a* G1673510 ADW COMPONENT_BRO Lifecycle status color column is not sorted correctly in Component Browser search results, ?9 T5 }+ e; O
1604734 ADW DATABASE Parts displaying non-key properties and values in the Component Browser in ADW
2 N' E6 s* I1 q5 k8 g1142957 ADW DSN_FLOW No Help available for schematic design verification
" ]3 \# N/ h9 s. i' p. G B1609186 ADW DSN_MIGRATION ADW Design Migration utility should handle ADW board reference projects and manage atdm.ini
* P3 A" P" P) Y4 }1 S& T1591757 ADW GENERIC_UI Running 'Create Test Schematic' in ADW Flow Manager results in Error SPCOCN-1736% L3 b) G& i, }+ q. {1 @; |8 W
1588111 ADW LIBIMPORT Library Import fails with Java errors while processing .csv files
- {% i" _8 \% Q+ Y# k7 d1 {1642367 ALLEGRO_EDITOR 3D_CANVAS Component height is not correct in new 3D Viewer" _8 Z8 h: Q- q1 p: r l
1642668 ALLEGRO_EDITOR 3D_CANVAS The new 3D canvas does not show STEP model of the drawing (.dra)( l3 m. T2 j) D( \5 b, ^7 [
1653247 ALLEGRO_EDITOR 3D_CANVAS New interactive 3D Viewer shows wrong placement6 @; z$ S2 m" L
1658275 ALLEGRO_EDITOR 3D_CANVAS Components on the bottom side are shifted in the new 3D view/ x" b" O- B9 `1 `; P
1639244 ALLEGRO_EDITOR ARTWORK When importing an artwork, a sub-folder is created with the value of the ads_sdart environment variable4 m1 v6 u, o( B6 ~+ W2 s! R( X! H
1658173 ALLEGRO_EDITOR ARTWORK ARTWORK: Value of Scale factor for output.3 @9 D6 H/ b/ K( l
1661760 ALLEGRO_EDITOR ARTWORK Import artwork to Design Outline layer does not give error in Allegro prompt.2 p% e8 r! Y$ C6 r7 F
1667778 ALLEGRO_EDITOR COLOR Add option to set FORM mini dehl_retain_color to NO) x- j5 X/ \" ~5 R |2 _0 u7 j
1669462 ALLEGRO_EDITOR COLOR Changes made to the Visibility tab are not reflected in the Color Dialog window. y7 A3 L7 D B& t0 U- l
1641265 ALLEGRO_EDITOR CROSS_SECTION The differential impedance value for a layer is not getting updated
5 @2 z) m( |; z" r7 v& S6 P1648149 ALLEGRO_EDITOR CROSS_SECTION Getting warning when calculating impedance in mixed stackup
$ S0 l" r3 k+ Q1 v3 v, ^; D: Z1671441 ALLEGRO_EDITOR CROSS_SECTION Enhancement request for cross section dialog box
1 X; o% W3 v5 y8 `+ ~& r7 g1673320 ALLEGRO_EDITOR CROSS_SECTION Diff impedance calculation fails
# f5 T; }1 k# B% ^8 L# z1690021 ALLEGRO_EDITOR CROSS_SECTION How to keep settings of expanded/compressed columns in the Xsection2 o; A" P+ Z" y$ E2 {
1703831 ALLEGRO_EDITOR CROSS_SECTION Calculation of Diff Z0 fails in flex designs- `& k7 C. w+ f6 q/ m9 B
1711484 ALLEGRO_EDITOR CROSS_SECTION ShowAll Column does not retain its status
0 C- B7 b! z3 k( N7 r1672841 ALLEGRO_EDITOR DATABASE ERROR(SPMHDB-153): Table corrupt; current/maximum mismatch& B) K4 D, d) p
1673613 ALLEGRO_EDITOR DATABASE COVERLAY_TOP not present in the Non-conductor section of Color Dialog window
T. G' u3 x; Y6 X% [1688123 ALLEGRO_EDITOR DATABASE Drill Plating Issue$ m! d2 Z/ {3 @/ i) l d3 D/ Q
1701995 ALLEGRO_EDITOR DATABASE When upreving a 16.6 brd to release 17.2, lines drawn on OUTLINE are translated to CUTOUT and not DESIGN_OUTLINE
" e0 u/ R: K8 m: S1710772 ALLEGRO_EDITOR DATABASE Mirror command not working on zones
% L# [$ V0 j7 t. }, y; j' y: u& v1713335 ALLEGRO_EDITOR DATABASE Defining Adjacent_layer_keepout_above and/or Adjacent_layer_keepout_below and then saving the .dra file giving error: B$ f" A7 `1 V y4 R6 Q
1693289 ALLEGRO_EDITOR DFA File - Save As script does not save the DFA file' ]! Q: W8 v- c/ v' \5 t# J
1644004 ALLEGRO_EDITOR DRC_CONSTR Unreported DRCs from dynamic copper to line and dynamic copper to SMT pin
7 N" t7 w% W; ?4 B& w1651425 ALLEGRO_EDITOR DRC_CONSTR The .brd file crashes when moving text controlled with minimum metal to metal constraints3 x0 V. V) Y3 q. C b
1663494 ALLEGRO_EDITOR DRC_CONSTR Reported Mechanical Pin to conductor spacing DRC constraint value is incorrect leading to false DRCs% t( G: s" M5 j
1687049 ALLEGRO_EDITOR EDIT_ETCH Create a Via Structure disconnects nets
* D$ B3 X1 P4 F1704296 ALLEGRO_EDITOR EDIT_ETCH Asymmetrical fanout created for BGA Quadrant style
9 f; W7 A4 M6 R& |' u1686873 ALLEGRO_EDITOR EDIT_SHAPE Merge static shapes deletes both the shapes selected.
* j$ [! N! \! C# r1 l" S" e. |1629925 ALLEGRO_EDITOR GRAPHICS Errors reported and no layout data drawn in PCB Editor in release 17.2 Hotfix 003 on Ubuntu 14.047 C" E) B/ z+ o _8 W# w7 L
1628895 ALLEGRO_EDITOR INTERACTIV Shape Edit mode: An error message is required when attempting to edit a Shape with the FIXED property2 u) \& `" @: k, z* g0 C
1666379 ALLEGRO_EDITOR INTERACTIV Place replicate is not working on the attached test case3 u4 H9 d( }. e# d) n
1668282 ALLEGRO_EDITOR INTERACTIV Grid display incorrect for repeated grids
) N% T: E& Y+ S( J9 s1675531 ALLEGRO_EDITOR INTERACTIV Design Entry CIS: Cross Probing with PCB Editor and Constraint Manager is not working4 ?+ S, J9 l1 u4 }
1694470 ALLEGRO_EDITOR INTERACTIV Update description of variable padstack_nowarning_display
& H- F. j8 A3 |$ M: P. K8 Y) k1696855 ALLEGRO_EDITOR INTERACTIV Mixed grid setting is not displayed correctly on Define Grid screen.
; t5 c2 _% C( E$ ], o9 y- Z1698192 ALLEGRO_EDITOR INTERACTIV Deleting and replacing a component causing database corruption in Hotfix 009- B) @6 Z" B3 R ~; y/ q0 b! {
1703671 ALLEGRO_EDITOR INTERACTIV An error occurs when defining grids with zero increment value; T# m# v1 `0 a/ H" s
1703812 ALLEGRO_EDITOR INTERACTIV Crash during move when using the 'snap pick to' option set to symbol origin
W6 R4 _* t2 [4 I1719276 ALLEGRO_EDITOR INTERACTIV Setting variable grid for 'All Etch' displays an error in the Define Grid form" f1 c8 C! h& S* S7 s, B
1663422 ALLEGRO_EDITOR INTERFACES Shape loses group membership after importing through sub-drawing* u* ]; s5 j( u! C; K- _2 N
1637959 ALLEGRO_EDITOR MANUFACT Thieving uses different clearance values around the route keepin.9 T n0 ]- w+ Q5 L& V6 Z( }
1716431 ALLEGRO_EDITOR MANUFACT Test points generation stops due to an error& Z2 @: o* p) q
1641994 ALLEGRO_EDITOR OTHER DB Doctor: Incorrect spelling of 'eliminated' in the log file messages
5 W6 ^* e& i0 Z# a# ?1660496 ALLEGRO_EDITOR OTHER SiP Layout crashes when trying to generate abstract level view by using export chips and connectivity. z" T. I) P; k
1685464 ALLEGRO_EDITOR OTHER The 'alias ~S save' command is not recognized when set in the local env file
: K! {, {5 C7 x- o6 }1696486 ALLEGRO_EDITOR OTHER STEP export results vary between releases 16.6 and 17.25 @: L0 I1 r, i+ X; N( O
1706623 ALLEGRO_EDITOR OTHER axlBackdrillGet crashes for invalid argument! x, \" p. i5 a$ h2 [* h- X
1586957 ALLEGRO_EDITOR PAD_EDITOR In Pad Editor, selecting a pad geometry is not showing up in the Design Layers tab
' ~/ U0 I$ m8 Z* g. J H1610984 ALLEGRO_EDITOR PAD_EDITOR Geometry set in tabs not read, only initial value set in Start page is used3 K* H6 S; ~ ]: d6 e* ]. C8 j
1614015 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor in release 17.2 does not auto fill geometry in design layers; r8 k$ t' |6 j6 U# x0 f* F; T
1636012 ALLEGRO_EDITOR PAD_EDITOR Keepout should not be allowed if antipad is not defined for outer layers
5 D w6 d+ M$ ~$ y1641973 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor: Path to the previously opened .pad file is not seeded in the File - Open dialog on a fresh launch3 Z+ a9 T$ V/ x! X# U
1642789 ALLEGRO_EDITOR PAD_EDITOR In release 17.2, 'Units' and 'Decimal Places' in Padstack Editor are not updated as per the .pad file9 I/ }1 l( Y# g7 K& L9 }- I
1646914 ALLEGRO_EDITOR PAD_EDITOR The 'Save' button is grayed out in Padstack Editor
3 o/ u# L* e E0 n1657553 ALLEGRO_EDITOR PAD_EDITOR No possibility to specify Padstack Editor default library path at invocation6 ~7 w4 V0 x, r: Q) t7 e7 y+ L" a
1657609 ALLEGRO_EDITOR PAD_EDITOR Changing Tolerance field in Padstack Editor does not activate the Save button
/ j: w8 Z/ x* Q7 W8 F1662225 ALLEGRO_EDITOR PAD_EDITOR Padstack editor dialog message doesn't match available options
. L4 u$ }* [6 C- [+ j1667062 ALLEGRO_EDITOR PAD_EDITOR Padstack editor does not retain the decimal places from the previous session5 ^, U2 x6 Z, z5 ^& u- y+ P
1672774 ALLEGRO_EDITOR PAD_EDITOR Pad Editor graphics appear to show offset incorrectly. ]* w7 Y" U* b6 {
1674157 ALLEGRO_EDITOR PAD_EDITOR Update Symbols does not update Pad Type Information
- D+ y# h2 T: X1 l- I& T1675438 ALLEGRO_EDITOR PAD_EDITOR Drill hole size warning for the SMD pad
8 D8 L* c3 J1 Y2 ]; K5 X1684376 ALLEGRO_EDITOR PAD_EDITOR Pad Editor issues with settings, such as decimal places, layers, and so on
' Z' d: f# y' P. c1690376 ALLEGRO_EDITOR PAD_EDITOR Variable padstack_nowarning_display fails to suppress warnings2 M- i( _8 T. g2 F$ U/ ?% e; ~" Z
1694649 ALLEGRO_EDITOR PAD_EDITOR Change Cancel button to No in warning generated when updating padstacks in design layout: }3 R2 p$ W6 R" [+ w/ Z+ y$ ?
939242 ALLEGRO_EDITOR PLACEMENT Cross probing between Capture and PCB Editor is inconsistent
+ | E% y) t" P1 r- d% {0 t1103945 ALLEGRO_EDITOR PLACEMENT Place Replicate Create does not include the etch connected to pin6 I! t$ K7 w7 S- ~3 h
1233019 ALLEGRO_EDITOR PLACEMENT Allow cross probe object selection apart from highlighting during place replicate
' F! _; p6 h4 u9 N1643078 ALLEGRO_EDITOR PLACEMENT PCB Editor flags an error message when a module is placed at a specific angle9 K8 X. Q! X; x; p r' Z% ^6 G- k
1696932 ALLEGRO_EDITOR PLACEMENT Inconsistency with Snap pick to when selecting Segment Midpoint
1 b+ R4 X+ @+ j! u, Y; X0 U, a1654500 ALLEGRO_EDITOR REPORTS In release 17.2 Hotfix 006, display of Netin (back anno.) report fails when variable ads_sdreport is set2 m8 F, A4 L, e' g
1643992 ALLEGRO_EDITOR SCHEM_FTB Export Physical fails with the 'netrev.exe has stopped working' error0 x; d7 ]& `# D' T4 z
1653400 ALLEGRO_EDITOR SHAPE Dynamic shape does not void a via.
# q) b3 L; c. R0 E6 ]1668262 ALLEGRO_EDITOR SHAPE dynamic shape does not void custom route keepout with arc* Z% o8 b' `6 L/ f% D5 a+ m3 {
1682569 ALLEGRO_EDITOR SHAPE Variable 'dv_squarecorners' not working correctly.3 e- H& ?6 J& X% T# {
1696240 ALLEGRO_EDITOR SHAPE SKILL error when merging polygons
$ w9 T, ?$ a- d0 g/ }* X$ v1709968 ALLEGRO_EDITOR SHAPE In release 17.2, DB Doctor reports error in shape when no error was reported in release 16.6 for the same shape
) o/ d/ K b. E& c" M/ C9 B- t3 y1632505 ALLEGRO_EDITOR SKILL In release 17.2 Hotfix 004, PCB Editor crashes after SRM update and save6 Y* d4 Y# T, h; `
1651701 ALLEGRO_EDITOR SKILL Cannot set the etch factor value in the cross-section using the axlXSectionModify() SKILL command
0 b4 B5 Y0 z1 l& ~6 K1658419 ALLEGRO_EDITOR SKILL PCB Editor crashes after running SRM* P) H& @( o9 l9 `
1658948 ALLEGRO_EDITOR SKILL axlIsLayerNegative() is not working in release 17.2* m9 [) C3 b( `
1670956 ALLEGRO_EDITOR SKILL axlIsLayerNegative() always returns nil# y: ]9 ?: o9 O7 h% K" S
1687239 ALLEGRO_EDITOR SKILL Problem with SKILL function axlCNSGetPhysical - incorrect parse string
' s) p- n: M5 G# t9 \/ _1692345 ALLEGRO_EDITOR SKILL The axlGetParm documentation example for deleting an artwork record is incorrect.3 O6 ^* I5 y: e, g/ J" S l6 h+ {
1707878 ALLEGRO_EDITOR SKILL Object rat_t does not work with axlDBPinPairLength.
# Z" L4 m0 q e1 s9 J- V1 k2 c1598061 ALLEGRO_EDITOR UI_GENERAL Adjust menus to allow side by side view
- g4 t) F6 |- J! F1 V6 j6 X, Q1599901 ALLEGRO_EDITOR UI_GENERAL Color Dialog box is not updating according to visibility tab.5 T) P7 I2 H$ i% w; U- z: ~
1602563 ALLEGRO_EDITOR UI_GENERAL Shortcuts to menu items not working in release 17.2
. p& U$ C8 [3 _; K" ~! h- J1603776 ALLEGRO_EDITOR UI_GENERAL Alt key not working with menu commands* Z) x/ M) V( l$ [ r) L- r
1611516 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts have no response5 W6 K$ X* Z @6 g1 k
1614763 ALLEGRO_EDITOR UI_GENERAL Cannot scroll to the bottom of an undocked command window in PCB Editor* I1 I+ L" S% y
1619873 ALLEGRO_EDITOR UI_GENERAL Command Window scrollbar does not reach its end+ U" f( h7 [1 U* p2 x8 Q
1624617 ALLEGRO_EDITOR UI_GENERAL Dialog box title under Setup > Outlines > Design Outline... Design is misspelled as "Desgin"
5 H5 r1 Y8 S1 b# L: j1631646 ALLEGRO_EDITOR UI_GENERAL Visibility pane not retaining the correct layer view3 V- I8 A9 T! W C9 h7 {8 K
1637062 ALLEGRO_EDITOR UI_GENERAL The last line of the floating command window in release 17.2 is hidden behind the command window frame
' r, b( C8 Q m; H5 y( |% L _: t1642645 ALLEGRO_EDITOR UI_GENERAL Cannot scroll to the bottom of an undocked command window in PCB Editor
9 m' t) Z# d/ e+ F9 ?1645335 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes in Hotfixes 004 and 005 if ODE and Allegro Manufacturing options are installed: {0 ~* x6 q1 x" P. j
1647520 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes after installing release 17.2 Hotfix 005# `) ?2 B7 a3 U$ L
1647541 ALLEGRO_EDITOR UI_GENERAL Release 17.2 Hotfix 005: PCB Editor crashes immediately after launch9 m, W9 u" v* |
1650044 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts are not working properly in release 17.2! r( d- Z7 O9 ]& D
1651912 ALLEGRO_EDITOR UI_GENERAL Inconsistent response when using the Alt key
, ]! {7 o( S6 \! r" k1652423 ALLEGRO_EDITOR UI_GENERAL Using the F1 key does not display the help document
8 _! {+ U" I) O% K! e; }1654600 ALLEGRO_EDITOR UI_GENERAL Spelling Mistake in "Design Outline" dialog box, Setup->Outlines->Design Outline, misspelled as "Desgin"
: J9 @2 X. ~# \- |& V5 c W [1654777 ALLEGRO_EDITOR UI_GENERAL Reports UI does not work properly when writing a report file.7 j9 Q, f5 K8 N* O& a# F2 X
1655500 ALLEGRO_EDITOR UI_GENERAL Visibility selection ignored after color change
' ~, _4 r# U- F+ O% Y1 Y& N9 [1655514 ALLEGRO_EDITOR UI_GENERAL Artwork Film is available in the View section only after you restart PCB Editor
8 g7 [1 U% A( \+ H. c. r; n/ l1663819 ALLEGRO_EDITOR UI_GENERAL In release 17.2, SKILL function, axlOpenDesign(), does not work as expected' R& p; j1 r5 @& W) Y' x2 n: w( x
1671334 ALLEGRO_EDITOR UI_GENERAL Design outline is not shown in 'World View' window% T5 V2 A; X6 ^: } {
1672148 ALLEGRO_EDITOR UI_GENERAL Add option in release 17.2 to change the placement of the Find, Visibility, and Options tabs similar to earlier release
, V! ?9 c$ f3 E! Z2 R1679418 ALLEGRO_EDITOR UI_GENERAL On choosing Edit - Move, the 'Symbol pin #' box is obfuscated
5 g' j* l& t+ z4 [- q1679761 ALLEGRO_EDITOR UI_GENERAL Choosing Edit - Spin hides 'Symbol pin #' partially* S" A2 M) h( ~( J1 }! G( w
1686887 ALLEGRO_EDITOR UI_GENERAL Hyper Text no longer selects coordinates for easy copy8 ~7 W# \- }$ \0 ` p$ P8 P
1687286 ALLEGRO_EDITOR UI_GENERAL In 17.2 Hotfix 009, the Static Phase meter shows up in the middle of the screen instead of the lower-right corner$ z! H4 _' L# M; y* N8 I8 H
1692416 ALLEGRO_EDITOR UI_GENERAL Underscores in menu commands denoting shortcuts are missing in release 17.2
8 S6 l' f) _5 U% ~ `: J7 P1693968 ALLEGRO_EDITOR UI_GENERAL Batch process that uses SKILL is taking too long to process files and generate reports
! @0 X4 A1 p) K1702420 ALLEGRO_EDITOR UI_GENERAL Unable to maximize reports viewer in 17.2
; i1 r) {, g7 r! S: _+ P1703065 ALLEGRO_EDITOR UI_GENERAL Menu shortcuts do not work as expected
: J: |$ m% R- B: A8 f0 t* G. O1703107 ALLEGRO_EDITOR UI_GENERAL Scripting using regional settings for decimal separator
; o! R$ A/ r& ?1707547 ALLEGRO_EDITOR UI_GENERAL Release 17.2: The Alt key function is not working in PCB Editor
) B$ R- b+ `. h1 z1709280 ALLEGRO_EDITOR UI_GENERAL Alt+Function key not working in release 17.2.
. m2 Y$ Z) y* `) a, f: K1639896 ALLEGRO_PROD_TOOLB CORE MFG collector does not move files to subdirectories( Z9 v4 l6 }- g, f0 ^2 ]) t% s* \
1608804 ALTM_TRANSLATOR DE_HDL Translation issues in symbols with multiple physical pins mapping to a single logical function
: ^0 o# [; c& O1658525 ALTM_TRANSLATOR DE_HDL Invalid characters in pin names
6 F+ f2 q9 _: m3 O% M. Q1658536 ALTM_TRANSLATOR DE_HDL All cell names should be generated in lowercase letters3 F* y+ ?0 |/ _/ s: G
1609962 ALTM_TRANSLATOR PCB_EDITOR Errors reported during design translation
4 e: q8 d, J* C1 t7 r1661562 APD DRC_CONSTRAIN The wrong space calculation on finger to trace. u# f( |* l, z1 q) T
1682398 APD SHAPE Deleting islands causes out of date shapes, S" e y# l& r( s# M( V0 K: Z
1638112 ASDA CANVAS_EDIT Unable to rename multiple selected buses using the 'Assign Name' command
p7 J% c) ?4 p1 a, T/ Z# n& w5 ^1645571 ASDA CANVAS_EDIT Various routing inconsistencies with synonym bodies on the canvas
2 X7 Y3 d0 D h4 z* r: G' x1656336 ASDA CANVAS_EDIT Presence of illegal characters in the net name removes the entire net name" x% L& {+ T- n! q! y
1667176 ASDA CANVAS_EDIT Unable to add the port symbol in a specific scenario: U$ @9 o C8 K0 M# n- c
1641473 ASDA CONSTRAINT_MA Importing a tech file into SDA makes the tool unresponsive
, K# B$ r" ]4 u; K. E% Q1661350 ASDA CONSTRAINT_MA Unable to create physical & spacing class from the docked CM! h- u" l7 x8 F. K( X8 U
1645557 ASDA IMPORT_DEHDL_ Importing a DE-HDL design into SDA adds the COMMENT_BODY attribute to nets
& W$ J2 F! `/ T: f/ f: |1652753 ASDA MISCELLANEOUS Tcl command window should display correct casing for autocompleted command5 |$ D9 ^( r$ I4 S* I
1654973 ASDA MISCELLANEOUS If there is a casing mismatch in the Tcl command name, correct command is not picked from the list
$ d$ c& H( \+ V. y5 t: I7 z0 z1652718 ASDA PAGE_MANAGEME Page numbering on the page border does not update correctly when pages are moved, added, deleted
2 u- q8 ?+ S% Q S8 [/ f+ v% w1699454 ASDA TABLE In the table object, cursor skips a cell on the first use of the TAB key
: \+ w) [0 Y1 e9 q1702702 ASDA TABLE Copy-pasting table objects to a new page fills the headers and rows in black
* |9 b6 s3 j, Z5 ~: I7 e1 g1668877 CAPTURE ANNOTATE Using Ctrl+drag does not preserve the reference designator value
, b* u8 R+ i+ c; K; Q; \3 V1665454 CAPTURE NETGROUPS Incremental copy for alias does not work anymore.) P% l, ?* a9 Y% g2 S
1634598 CAPTURE OTHER The ‘OrCAD_Capture_CIS_option’ license not released even after selecting another product option+ ~) |3 A# r8 f( J
1636090 CAPTURE OTHER Capture crashes after switching from release 17.2 Hotfix 003 to 004 due to some Tcl files9 q9 v* X! [6 L6 c: _
1650029 CAPTURE OTHER Crash while archiving a newly created PSpice project without adding simulation profile5 d: Q0 G2 S- A, X; {
1659602 CAPTURE OTHER Saving CIS BOM via TCL command window
! g! w! U& J3 f6 ]9 y/ d. |1678715 CAPTURE OTHER Capture.ini [WebResourcesMenu] is not working in release 17.2; V$ i, m) w5 e5 o' P8 X
1619449 CAPTURE PROJECT_MANAG Search not working in a PSpice project$ _- S( J4 `# Z' A" F% D( Z
1670133 CAPTURE PROJECT_MANAG Start Page showing wrong Software Version( `5 ~* F9 O% U4 W1 ?
1670766 CAPTURE PROJECT_MANAG autoreference does not work properly
7 `) `1 K. `2 E0 s1676095 CAPTURE PROJECT_MANAG (SID:22758) OrCAD Capture Start Page reporting wrong hotfix installed1 C3 h8 c: |2 Z& A: G( b( j
1658315 CAPTURE TCL_INTERFACE Inserting text with double quotes is not working as expected in PDF created from Capture
/ S8 W+ T4 V5 |) Q$ m* w! i1642601 CIS OTHER Design Entry CIS: SQL server password is required each time the tool is launched
4 o/ A3 `4 t: {% u" S j/ P% P: h1712279 CONCEPT_HDL CONSTRAINT_MG Differential pairs are dropped from Net Classes when upreved to release 17.2-2016
+ l& `/ e8 \: M1665449 CONCEPT_HDL COPY_PROJECT Copy project fails with error COPYPROJ-774 d2 Q( A% q4 \3 X3 S5 Y
1661778 CONCEPT_HDL CORE Advanced Find will not find pins with the SIG_NAME property attached
! W4 |* Z T% k4 r6 I* E) h1666084 CONCEPT_HDL CORE All user-defined properties are not listed in the Customize columns in Variant Editor
+ b0 A0 J$ d0 y" K0 j1667043 CONCEPT_HDL CORE Incorrect information in cpm.log file7 F* S3 s9 U- q# b# M3 n. p, k
1670659 CONCEPT_HDL CORE SIGNAME text off grid when pasting copy using ctrl+v.
6 m; Q) Q8 A2 e* ?# q) i1697732 CONCEPT_HDL CORE Warning (SPCOCN-922): The object is being placed towards the left edge of the schematic. Ensure that the objects are pla6 L$ X$ v, o" j1 _2 ~ [
1697955 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net
% t8 J& N5 @; { c* v3 i, O \1 ~4 J" |1711635 CONCEPT_HDL CORE The arrow keys do not work as expected in Windows mode1 u* K" B; ?. l8 |$ E. K) j
1713091 CONCEPT_HDL CORE Difference in the behavior of 'Add Signal Name' in DE-HDL between releases 16.6 and 17.2
3 d8 \4 w$ C, T/ h; a1708820 CONCEPT_HDL OTHER In a board cache flow, component bodies are missing when importing another board cached flow project. r N9 w u0 T4 x/ ~
1639928 CONSTRAINT_MGR CONCEPT_HDL The '-filterFile' argument is not recognized when cmDiffUtility is run as a command line operation
- q( X8 b0 X: u- p1657048 CONSTRAINT_MGR CONCEPT_HDL Unable to navigate through the search results in the CM Reports% x$ R2 o0 i- Q
1718073 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors on an upreved design in release 17.2: Pins in XNet and CSet do not match
7 C+ ?7 e9 R( \# `$ S! w0 |) Z1717336 CONSTRAINT_MGR DATABASE Netclass members change during logic import; it's a toggle switch
9 ^* H. a% X0 A( [: Y! P1718514 CONSTRAINT_MGR ECS_APPLY Extracted topology does not use the PINUSE overrides specified on the canvas
5 n3 N M; P# d1682885 CONSTRAINT_MGR INTERACTIV Constraint Manager worksheet switching does not work correctly in Linux% b) d/ C& M, J5 _ j# C
1669523 CONSTRAINT_MGR OTHER Select is disabled in Constraint Manager when a command is active in PCB Editor3 l, I0 H& [! e% U/ X) T
1670802 CONSTRAINT_MGR OTHER Selecting a list of nets using the shift key does not work in Spacing and Physical domain1 I4 |. y, N4 W1 n, j; E0 r# C, i
1670922 CONSTRAINT_MGR OTHER Title of the Layer Remove window is Constraint Manager4 {/ V. d0 R1 d, @2 A T
1678235 CONSTRAINT_MGR OTHER Select option grayed out in Constraint Manager if a command is active in PCB Editor
5 g& g- s( V. d H. E0 n' k1680917 CONSTRAINT_MGR OTHER In release 17.2, nets cannot be selected in Constraint Manager when a PCB Editor command is active. f2 R( _) _+ W3 H4 V" C+ Y
1691125 CONSTRAINT_MGR OTHER Highlight command no longer selects the net in CM, i' g l; K6 M; x
1703791 CONSTRAINT_MGR OTHER Cross highlighting and assigning color to nets between PCB Editor and CM does not work
: L' J% {; [( v, O" `1649603 CONSTRAINT_MGR UI_FORMS Expand and Collapse commands do not work when multiple objects are selected$ J, @: ]) c6 b) y8 M
1654931 CONSTRAINT_MGR UI_FORMS Expand, collapse only works on one of the multiple selected objects.
. A, ?, W) T" H* z1668794 CONSTRAINT_MGR UI_FORMS Incorrect via name shown when filtering via list9 X! \8 V0 r% ~8 a' y1 U
1678305 CONSTRAINT_MGR UI_FORMS Unable to use the CM worksheet customization (wcfx) from the CDS_SITE area0 y# y, J5 k; k* t& q
1679909 CONSTRAINT_MGR UI_FORMS Incorrect layer order getting saved when defining BB vias in Constraint Manager PCSet0 R: t5 J6 j) `" h( D) o
1691906 CONSTRAINT_MGR UI_FORMS Display Issue: When you use the filters, the horizontal scroll bars are duplicated* c9 a3 Q: \& q6 g1 }4 e/ u
1677893 ECW INTEGRATION Integrations list update is not working as per scheduled time" B% N1 T& k4 W
1652707 ECW METRICS Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart! M) T- `6 E' ^2 }
1654512 ECW METRICS Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart' \. I) ^$ t! g- V5 C6 I
1668953 ECW METRICS IE11 Swedish only: Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart& v$ Y* m! ]. R; V
1677443 ECW METRICS Queued up metric packets on Pulse server are not processed if there are any packets related to a deleted project
3 e/ c. E! F3 p/ X' |& j1663676 F2B PACKAGERXL Physical net name (PNN) errors in the log file
$ Z/ F: Q, p+ r) p: T1669583 GRE DETAIL AiDT always fails push when there is a connect shape attached to the cline being tuned
# R. Q3 V4 d# {$ V! n D! d1686350 INSTALLATION SPB InstallDiagnose fails to repair some errors
; v8 K/ E* ^: D$ [( j) N/ K1672369 PCB_LIBRARIAN EXPLORER Cannot create a New library build in Library Explorer.
0 O; t& B- m% D( R6 ]: J9 d1631034 PSPICE ENVIRONMENT When simulating the design in release 17.2, Capture crashes but works with release 16.61 Y% s Z& J+ i$ b
1648284 PSPICE ENVIRONMENT PSpice project crashes when a design is opened in release 17.26 G: D. e" m; G: ?, t7 i1 Z
1663336 PSPICE MODELEDITOR Ibis translation not supporting paths with spaces
/ J& q; ^/ h8 Z8 l. _! P+ {; d1679376 SIG_EXPLORER OTHER Topology created in OrCAD PCB SI license cannot be reopened with the same license
2 i% I0 \& E: Y. S1666484 SIP_LAYOUT CROSS_SECTION On converting a design from release 16.6 to release 17.2, a Dielectric thickness of ‘0.2032’ is added to another layer.
; j- w# ?: H$ `1687988 SIP_LAYOUT DIE_GENERATOR 'compose die from geometry' does not retain the user-defined padstack name- K2 R' O1 R! R; G3 O! t3 K
1715016 SIP_LAYOUT DIE_GENERATOR Using Die Text-In wizard to replace a die reconnects wire bonds to the wrong die in stack-up# N: u* V- h) i& X; V7 a/ ?/ l% h
1620601 SIP_LAYOUT MANUFACTURING Need the ability to create LINES with round end caps in the same way as the LINES appear in the database% q. k. k2 U& N8 t" t
1705963 SIP_LAYOUT PADSTACK_EDIT Pad Designer: "None" changing spontaneously into "Circle 0.000" in a pad stack definition and unable to save* i' y) D/ X1 e& J4 M7 K
1713767 SIP_LAYOUT REPORTS Reports in release 17.2 for the Verilog Port Name are adding incorrect data that was not found in release 16.6; N- ]! v1 s; I/ G3 y
1696218 SIP_LAYOUT SKILL SiP Layout crashes on reassigning nets
, w6 j$ `/ H, _0 |( q1 Z4 N1695885 SIP_LAYOUT UI_GENERAL Visibility Tab check box: unchecked "All" disables access to "Shp" check box0 S6 J# e: _' m" X0 `9 g' L
1639838 SIP_RF DIEEXPORT Enhance the error message, SIP-1507, to include that overlapping pins within tolerance are included during die export& n% [1 k) l$ s2 l7 w
1653894 SIP_RF DIEEXPORT Redundant error message for die export, when view name is other than "layout"
8 R- E( R/ B2 [3 _1681332 SIP_RF OTHER Running die export causes Virtuoso to crash
3 S P( h5 j1 n1679336 SPECCTRA LICENSING Min/Max Propagation Delay cannot be routed by PCB Router using OrCAD PCB Designer Professional
: `, T/ B% O. b+ ]- t9 `
9 W4 b" b' i, T( f" W1 ?/ ^3 A8 Y5 M7 w. }/ d
Fixed CCRs: SPB 17.2 HF015. Y. }7 j0 Z5 s: z6 D) Y
03-16-2017
. @% \; t0 ~4 H8 u* r========================================================================================================================================================. M( W% n. y- t* p) S
CCRID Product ProductLevel2 Title- u0 x+ ^3 k$ P2 m! X) E# [
========================================================================================================================================================6 X- X8 z' Q7 n3 t' L% K( P8 Z
1653366 ALLEGRO_EDITOR INTERFACES Unable to attach step model to symbol
8 P, |- W* o! [7 Y B1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model! o3 k2 H$ H7 {$ F
1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function
8 F" _, V9 g7 T& ?) }9 m" @1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file
; H& H6 u* h2 S5 Z1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting Padstack Editor results in incorrectly scaled forms2 L, F c5 H: f D
1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design8 s v& L( p! @. p) x
1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees
( E( R8 A% ]& a+ Y# Z/ s# R" L3 `1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.& [' [' B" x: c" A" \
1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
* z6 K- a' \9 S$ r6 Q4 l- S* _1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor7 s' P7 c; v' J2 e* J* j
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not' R% ?- @4 H( n* r' }1 s& U9 A8 w
1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used& ] X* m0 c2 ~" K! S1 j
1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places
) l7 V% c; I$ E+ @. [1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value
3 T( g1 N! {5 Y7 e$ o: d. W+ X0 m; Q1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
8 |5 t4 `) b! l8 k) G6 h6 j& g1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad1 N9 P$ _; _4 c* V& H/ p/ S
1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout P. W9 Y, [3 }6 X% ?
1698697 CONCEPT_HDL COPY_PROJECT Copy project corrupts the .dcf file7 D! r S2 v5 d% j
1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084* M- l6 F* a- @) I0 u- x) l7 v6 m# w
1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position# L5 w' c6 H8 d d. I# P
1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net. h( R0 _, Z' k: H
1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer( t7 [2 u) r) ?2 B3 Y* {: c! w
1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation2 J+ p9 c8 @/ [- T; K
1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
: ?! |$ {& j3 a9 r1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode4 n- O; A) Y A" ?( ?1 s2 n3 ?& ]
' P9 |. O! k# N6 s0 h! z) X9 z1 O+ w" e/ i
Fixed CCRs: SPB 17.2 HF0149 e5 s/ h) X9 w0 I# q$ V) P2 ]7 [
03-4-2017
& s0 W. C& F! M========================================================================================================================================================
3 h3 k7 K. N! ]7 ZCCRID Product ProductLevel2 Title& L! o- Y! @! f* g
========================================================================================================================================================8 A i* g* E8 `0 F
1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships8 B. T4 R# O6 X6 e
1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity
9 ?% n/ X4 s6 P( y1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-2684 c9 P* {' c; u5 F% A8 e
1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data
- I7 s9 `& I6 I" @+ _! \$ [# g8 r4 E1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data q( `' ?2 _% d( I$ D; E
1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors+ a- I v- g8 F2 ~6 Z
1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.8 X, L m$ s) ^; Y j" H; B
1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted
8 d5 M6 \ w. |" G/ l9 ?. m0 ]1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location5 h% r' H5 q1 Z( j" ^0 [
1685995 ALLEGRO_EDITOR SKILL All film sequence numbers are returned as 0 when using the SKILL function axlGetParam
4 O9 k% k: N. C7 p1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately$ E, c% w' x c& q
1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6/ i$ O1 i& L8 l% \: l3 }$ a
1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one6 M w, z& l+ ]2 p1 d# v6 h' a
1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled
5 a7 N1 w, H: f1 g4 r+ {1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved
# I7 S% Z1 }$ s* e# ]4 H& O: c1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components2 F/ B$ _$ x$ s1 \* v2 p) q
1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers- I6 a$ h* t: Y6 I( l
1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase. W# [# v% r1 ~& u7 A- [ @# E
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement1 K' d& d8 X1 a3 b. ]
1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message
0 |6 S* v, h+ ` {7 A( q7 K% E$ v1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011
8 e- V1 ~* \+ D. R. p% s) Z1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2
* ]4 v0 ^; x7 d q0 p1 `5 `9 ?# s1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers
0 D% T# e7 @% j" i" P+ A& O1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016
$ s/ j T9 H( Z2 _- K# m3 h+ [1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design8 Q. m' [$ o* B' z H1 p$ J0 a; {
1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors. |) M- T! J7 b0 i$ N/ I! B
1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters5 ]. P6 B% h& Z b7 t& U. O
1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP: g0 u% B3 X, D8 \& U" X% i* v
1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'
" _, [7 C3 N3 n7 d1705265 INSTALLATION DOWNLOAD_MGR Problem installing OrCAD Library Builder from Download Manager
: a! D- h! L3 u1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script
( f# i. i! L9 r: i1 }! e9 z U9 ~8 Z
0 E. c' o1 }" ]* N W# H
Fixed CCRs: SPB 17.2 HF013# l0 w; }% S+ x
02-17-2017
* v' r3 ^6 d. d% F& M6 @========================================================================================================================================================- G6 K: q" a; a) T) A4 X2 f5 k
CCRID Product ProductLevel2 Title) v% Z. }7 T* I# v }) i% o- c
========================================================================================================================================================
4 |/ S9 t3 e6 y* [5 ~1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm
' G: i- D+ Z3 [+ R& E! t/ C" t1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer
6 @5 C9 {7 J0 y2 m9 n/ s, W1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version$ @$ @) P' ]' a. K4 X
1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated
: s8 S. L4 u2 x1 W. G1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated
) i% |9 U7 h' S U! G1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board
+ \: M( \* v" A E* k! G1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor) }4 [# w/ D/ [
1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol5 _' E4 ^# o4 y! ^( y' ]
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
. @0 w8 V, B" [( w8 ?1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components2 o$ b, {$ [5 J" |
1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components- D: |+ I4 T) F4 W: Z F, O4 B# J
1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets u! [6 r1 A4 I" }
1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets
7 L0 e" l8 |6 |2 d7 |" c# D1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF
$ |" Y& p+ p& q0 C, _2 {1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement$ h$ @+ K# z) u; a7 U
1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.
. ]1 A, N/ w- q- O( B! d1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file
. ? p: _* F9 ]# Y( }5 Q1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.6 s6 k- k1 [' [& C
1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker' W6 I& o/ f) w# d, P2 G
1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates; w3 `, c" M, N9 q }
1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes
{$ N: I/ ]: ~( K: y; l/ D1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.; h% k" A3 e/ u3 r2 g
/ }" {# l+ E. R7 V
# G" u+ D/ g) X5 W) v, O5 \Fixed CCRs: SPB 17.2 HF012# ~" X4 G- u& y3 k
02-3-2017
! r l" {2 F! j- e' S9 M) O===================================================================================================================================
8 ]- f+ Y0 D% [CCRID PRODUCT PRODUCTLEVEL2 TITLE! C. |5 B1 G# P3 o- ~
===================================================================================================================================( T* h4 ?! a5 ]' @* A) {4 ?
1659641 ADW FLOW_MGR Documentation Editor does not invoke when a .brd file is opened from EDM Flow Manager
& X/ k8 z* e: H$ A( K% k4 `9 U. g1661632 CONCEPT_HDL OTHER Page skipped in DE-HDL when navigating using the Page Up and Page Down keys, e9 I: i) o- r
1668325 ALLEGRO_EDITOR SHAPE Updating shapes to smooth creates erratic voids.
+ ]6 v8 F) {/ Y, z1670082 CONSTRAINT_MGR ANALYSIS Inconsistency in Constraint Analysis Modes - Electrical in OrCAD PCB Designer Professional 17.2
8 c" u4 x# v" m% |9 \1674231 ECW METRICS Re-upload for local metric packets that failed on first attempt is not working when Pulse server name contains dots1 I, J, n; Y* H2 j. B( O
1674338 APD SHAPE Shape is not clearing slivers that are smaller than the 'Minimum aperture for gap width' of '18 um'
0 ], T: L2 a8 G1 s8 `, u1675677 ADW DBEDITOR DBeditor Issue-Searching by using the Properties method
+ U5 |& @; c8 m1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers: O3 N3 k( ]! V7 {2 H' _! V( u8 z* o
1679351 ALLEGRO_EDITOR REPORTS Missing Fillets Report is not showing missing fillets on the bottom layer
2 M) w# f+ I' V: L1681002 ALLEGRO_EDITOR OTHER 17.2 STEP output fails to produce an output similar to 16.6' S0 C9 h9 P& T6 F
1682287 ALLEGRO_EDITOR EDIT_ETCH Auto-interactive Delay tune (AiDT) rips lines that have been routed
' P. h: H" v3 v" t% ^+ K# ~$ z1682900 ALLEGRO_EDITOR PLACEMENT Moving a symbol by snapping to segment vertex with 17.2 Hotfix 009 crashes PCB Editor
9 }4 Z' ^% @6 H# i& b" B1684117 CONCEPT_HDL CONSTRAINT_MGR Property deleted from Constraint Manager is not getting updated in the DE-HDL canvas
, ]3 H# r, A! Y% t+ q7 {1 y& T, @$ Y5 X1686803 ALLEGRO_EDITOR INTERFACES PCB Editor crashes if the 'ipc2581_group_drills' variable is set.
$ p ]4 j$ h/ }* g. V1687816 ALLEGRO_EDITOR PLOTTING Export PDF Vector text option does not work
+ l5 Z# g# ?; j6 H1 O( C, }1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.
5 {( M# ?$ X/ u" s6 }$ g1 e1689881 ALLEGRO_EDITOR DFA Record and replay script for loading DFA spreadsheet not working: k3 d* `: j& I( h# g
1690958 ALLEGRO_EDITOR SKILL SKILL command axlDBDelLock is not working as explained in the documentation
( f! _# D* D9 f1692166 APD DATABASE DB Doctor returns 'ERROR(SPMHDB-252): A corrupt database pointer was detected' for a specific design
! C7 m9 P! ^# l: c/ J1693431 ALLEGRO_EDITOR SKILL Running axlXSectionModify and axlXSectionSet results in warnings and corrupts multi-zone cross-section m% }. p' H- r1 }$ [: [' R
1693719 ALLEGRO_EDITOR MANUFACT Incorrect suppressed holes information in the drill file created9 W% g# E! K1 g8 m
1693846 ALLEGRO_EDITOR MANUFACT PCB Editor crashes when running the gloss command
7 M" Y$ u, b+ _$ c* ^3 H0 Q3 v1694151 CONCEPT_HDL CORE Rename Signal for unnamed net added the sig_name at the incorrect position with small text size.
. f8 Z) d: b# l+ W8 Q. l1694867 ALLEGRO_EDITOR SHAPE Void is deleted by the shape merge command: P! ?2 k6 p5 [% e" C* P3 d0 D
1695131 ALLEGRO_EDITOR SKILL PCB Editor crashes when using the axlSpreadsheetDefineCell SKILL function
! H) s0 J% {8 J3 |) C" X0 s) r0 w) c8 Y
2 H6 B! `' H5 M# P; D0 w$ D
Fixed CCRs: SPB 17.2 HF011
$ W% \! [5 F( _! F2 V0 ]01-20-2017* w/ N+ m3 K3 c' a
===================================================================================================================================
8 q4 U" X& g. D& g6 a. MCCRID PRODUCT PRODUCTLEVEL2 TITLE8 ]* T: I8 ^& `1 g3 c2 b# e# H" g
===================================================================================================================================
2 T* l, b4 ?0 X3 y) A4 @/ U5 ]$ E% l1618986 CONCEPT_HDL CORE Information required about the DONT_FORCE_ORIGIN_ONGRID directive+ ]! `2 f+ h+ ?( O: }! k# W0 }3 g S
1629696 PSPICE PROBE After successfully exporting traces to csv, PSpice crashes on a subsequent attempt to export traces
7 N, e1 a# ]- N, g& o4 K8 K I1667213 CAPTURE NETLIST_ALLEGRO Tools - Create Netlist stops responding on Windows10. c. k6 E7 K0 ]" b
1667599 APD OTHER Wire Bond operations taking longer than expected to complete
9 X1 ~- O9 u8 r1667678 MODEL_EDITOR PARSE Signal model assignment creates ESpice models that do not pass Model Integrity checks
b) i5 v2 x+ z: C; l1670120 ALLEGRO_EDITOR UI_GENERAL In 17.2, the Static Phase meter shows up in the middle of the screen instead of the lower right corner) [8 ~6 c; l! F/ h9 n2 }7 |
1670927 ALLEGRO_EDITOR DRAFTING Using zcopy to create a Route Keepin results in database errors
( i/ Z; G3 ]2 b, j. U! Y2 A1675359 ALLEGRO_EDITOR ARTWORK Subclass ETCH/WIRE is added to artwork definition though the visibility of 'ALL Layers' is turned off
) K( V* G1 o) O7 u5 Z. V( I1675619 ALLEGRO_EDITOR MANUFACT Differences observed in IPC-D-356A between releases 16.6 and 17.2
], ~; t ^. G" w1 g: J- L5 A1676161 ADW FLOW_MGR Opening a project in SPB 17.2 flags the 'Operation load JNI code failed' error
. o& B1 r, [ M" y6 [$ p! ` a" S1677405 CONCEPT_HDL OTHER When moving a wire with a dot, the dot is not removed directly9 i+ z% o# J7 F8 f
1678061 PSPICE SLPS Simulating an SLPS co-simulation with a Fixed-step solver with a value smaller than 1E-4 results in a crash
3 F8 A2 y2 j" R& @( u* {+ {1679347 PSPICE SLPS SLPS crashes when co-simulating without opening OrCAD Capture or PSpice4 Z' H0 h. A4 U: _" o
1680113 ALLEGRO_EDITOR SHAPE Irregular void created on dynamic shapes6 H- G( ^4 {# X$ X# U
1680802 ALLEGRO_EDITOR DATABASE A 16.3 database locked with disabled export of design data should be view only in 16.6
; ?) ]' q' r7 V3 x9 I1 j! l1681129 ALLEGRO_EDITOR DATABASE Match Groups in the DE-HDL design are not getting transferred to the board file
$ V. J9 r: \% ]1681514 ALLEGRO_EDITOR UI_GENERAL Opening the Dynamic Shapes State report hangs PCB Editor in 17.2 Hotfix 009
! u% L! V4 F2 S* y5 e0 Q! M" F1681727 CAPTURE NETGROUPS In 17.2, Capture crashes when closing a design that has assigned Netgroups7 m! S" D. W+ T1 u
1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
; u' r A+ Z$ Y. e1682447 CONSTRAINT_MGR CONCEPT_HDL Extraction issue on differential pairs in the given design {% T; J3 T+ h$ q) V0 [
1682454 CONSTRAINT_MGR CONCEPT_HDL Design with NO_XNET_CONNECTION property on parts is exported to PCB Editor; many other components get the property- u( |) O# b5 F5 B+ {
1682469 CONSTRAINT_MGR CONCEPT_HDL Creating a CSet from an existing CSet leads to invalid CSet names in Constraint Manager connected to DE-HDL
( G4 ?4 @( L) S4 }# r* j$ y. E1683919 ECW TDO-SHAREPOINT Site Minder integration for login from TDA not working after SSL certificate update4 o# p' }3 c. k& _2 N+ o9 y0 X
1684111 ALLEGRO_EDITOR SHAPE Dynamic Shape not voiding overlapped static shape
4 @- _1 f% B! J$ _- F- ]1684508 ALLEGRO_EDITOR AUTOVOID Allegro PCB Editor stops responding when deleting a via8 Z v; m; a8 G1 D; n& p- e
1685540 ALLEGRO_EDITOR OTHER If text is attached to an object, the object is also printed in the PDF
# D N1 \% J6 b! V: }1685810 ALLEGRO_EDITOR PAD_EDITOR In 17.2, Padstack Editor does not save adjacent layer information for BOTTOM pads1 E! j5 x$ N% O( g
1685986 ALLEGRO_EDITOR PADS_IN PADS Translator-generated output shows incorrect unit for the soldermask oversize option% @4 P( U* ?4 a+ g# L
1686127 ALLEGRO_EDITOR SHAPE The void of shape missed in artwork.
6 p/ m1 e* C2 b2 C+ j4 M/ J1686791 ALLEGRO_EDITOR OTHER Searchable property unavailable on bottom layer pins in the generated PDF4 f! V$ f: j8 T6 u8 A! w# @
8 q: s, t" M1 F1 s/ |6 a6 F F0 @- g. \" W
# b- U+ ]% W- TFixed CCRs: SPB 17.2 HF010
! v: ?) H+ T5 T$ g& m01-6-2017
; S, g! e5 [$ y( C/ h===================================================================================================================================( {+ Z7 s4 k% t/ G. S9 w) g
CCRID PRODUCT PRODUCTLEVEL2 TITLE
- }1 k( Q7 h% }* `===================================================================================================================================
' J$ b2 o1 n2 v8 K$ r1 }2 S Y8 U1524700 F2B DESIGNVARI Variant file cannot be loaded% I: o P( O' U
1597787 CONCEPT_HDL MARKERS Save As in Marker dialog causes DE-HDL to crash
* ?' _8 b, n# O0 U _1599843 CONCEPT_HDL INTERFACE_DESIGN Moving NG causes extra elements added to it to move
3 ?1 c0 V2 A5 r; w6 Z8 C; v1620017 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053) when $PART_NUMBER property for components has a value
* v$ a1 C, V$ U. K( {& }8 Y# H1 f5 ]1632977 CONCEPT_HDL INTERFACE_DESIGN Connectivity error when moving NG members! D6 w& @: h( d! Z6 n
1635941 ALLEGRO_EDITOR INTERFACES Shape created by IPC 2581 for negative film is not same as the shape on board6 Q" }. K* t+ D8 `! U
1656357 CONCEPT_HDL CORE Pasting a signal name across pages causes the name to overlap with the wire segment1 H- l I \. U5 E
1657346 CONCEPT_HDL PDF Wire Pattern set to two-dot chain line in a schematic appears as a solid line in the PDF output
" C& E5 ]0 f/ U7 x2 q1658048 ALLEGRO_EDITOR COLOR color_lastgroup is not working in SPB 17.22 L Q& Z5 H/ T" ^$ z
1658874 CONCEPT_HDL CORE 'Insert (n) Pages' command does not work when the CONFIRM_WRITE directive is ON9 k n. b" d# y$ k
1659030 RF_PCB LIBRARY Offset is not calculated from the center if using negative values for input pins when placing MSOP symbols! @, {) T, j* `+ L
1659097 CONCEPT_HDL CORE Mouse stroke fails to be enabled on startup with left mouse button (LMB): z) c, w8 ]6 l, s9 H
1659532 CONCEPT_HDL CORE About Import Design command with the CONFIRM_WRITE directive
: f% O# Y2 P5 {6 T/ X& `+ u& J# G1659929 CONSTRAINT_MGR UI_FORMS Using wildcards in filename for Import Constraints does not work in 17.2
0 J' y+ P0 Q! F! h4 u, E1660200 ALLEGRO_EDITOR UI_GENERAL Move by Sym Pin # edit box is obfuscated+ G( b; z7 [; Q% o5 X: w( e
1662821 ALLEGRO_EDITOR OTHER Cross section chart does not show stack vias in 17.2
" }. ]0 j8 ^) G2 N1 [- d1663641 CONCEPT_HDL COPY_PROJECT File - Copy Project in Project Manager creates two designs if there are dashes in the design name
8 D0 ]5 D1 p6 Z8 ~9 e1665652 ALLEGRO_EDITOR SHAPE Critical fillet and shape issues in 17.2
1 J0 S2 y/ E# ]1665918 CONCEPT_HDL CHECKPLUS Error (100) Program Internal Error 'Create_flat_node' with checkplus run
: F5 B: ]" {% Y/ t1667056 ASI_PI GUI Power Feasibility Editor does not list capacitors connected to selected nets/parts
: a) v0 F' s Z6 d1668137 ALLEGRO_EDITOR SCRIPTS PCB Editor crashing when running Script Replay* m* t( `" V H r
1669651 CONCEPT_HDL CREFER CreferHDL values are invisible
3 {) O/ A& f( t; [+ j6 `1669707 CONCEPT_HDL CORE Pin numbers not visible on the canvas after replacing a part with the same symbol but a different part property
. D: m9 M6 |' I) y$ ]9 ~8 }+ e1670339 ALLEGRO_EDITOR OTHER Small shapes defined on the mechanical symbol Board Geometry - Outline are not converted to the Cutout subclass.
2 b6 {0 B8 y" q# H1670564 ALLEGRO_EDITOR MANUFACT Exported Gerber file cannot be imported in brd4 F. z& O/ X6 M- }" c
1670687 ALLEGRO_EDITOR NC nclegend.log reports missing columns which are present in the NC Legend
. o/ U* c% C% t9 w! {! ]6 @1670811 PSPICE AA_MC AA MC Plot settings options; Q5 F' d* a9 w$ _
1671428 ALLEGRO_EDITOR UI_FORMS Display origin checkbox position changes in Step Mapping dialog3 `9 b L, l3 f* g& X9 n; D' R6 y
1671728 CONCEPT_HDL CORE Option requested to reload preferred_projects.txt without re-opening DE-HDL% r8 R1 D4 N0 J0 i. _0 `: q
1671901 ALLEGRO_EDITOR UI_GENERAL Toolbar and menus are locked or greyed out
# n* d0 e6 ^- z. g! X1672477 ALLEGRO_EDITOR DRC_CONSTR DRC generated by Dynamic fillets/ i z5 _$ X1 S% N6 r
1673499 ALLEGRO_EDITOR DATABASE Drill table title issues of backdrill designs in 17.2
1 `* d6 e2 b3 ?+ ?; q4 r$ B/ b1673681 ALLEGRO_EDITOR UI_GENERAL F1 for Help not working in PCB Editor 17.2
; z+ }1 Q% g3 ]' }6 p3 [/ S1675499 ALLEGRO_EDITOR DATABASE Running the Gloss command causes PCB Editor to crash...
3 b/ k. M. w% W/ }# x: Y; p( z' }; w1676480 ALLEGRO_EDITOR MANUFACT Creating Variant Assy_Bot Drawing showing Variant Assy Top Drawing
0 B5 N7 C* i% |; V/ x4 t4 |/ J# [' o1677431 ALLEGRO_EDITOR DATABASE Get ERROR(SPMHA1-141): Invalid sector row. Contact cadence customer support when opening DRA File
L; q! }+ x- t7 ~4 P; ^5 x1677651 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crash on design after successful packaging
$ D( r5 d# U/ {5 O" W1677672 CONCEPT_HDL CORE Whitespaces in URL links are not resolved correctly on Linux with Firefox
5 v" _0 q" V+ \# l1680837 ALLEGRO_EDITOR SHAPE Updating the shape makes the shape disconnect from Thru pins of same net. \9 z C6 ^2 ]
1681059 ALLEGRO_EDITOR SHAPE Shape Voiding using DV_SQUARECORNERS environmental variable does not always produce voids with square corners.# v( z8 o5 I* A- R$ G: |
1682312 SIG_INTEGRITY LICENSING Allegro Sigrity SI/PI Product Choices window is blank after installing 17.2-s009 hotfix8 e2 v* z0 I [8 [6 x
2 k0 y( X3 d, |5 `
9 q8 V) R2 }2 j0 X4 K9 sFixed CCRs: SPB 17.2 HF009( z, t. I/ t9 Y$ ~
12-8-2016
" k, K- C& d" }9 N- G2 h===================================================================================================================================
- h2 b+ ]+ o$ q8 f+ H5 S9 w1 u2 tCCRID PRODUCT PRODUCTLEVEL2 TITLE
: t9 X# {- W/ y9 p2 L( C& b===================================================================================================================================4 V" D1 y% L% [: T
1212577 PSPICE MODELEDITOR IBIS translation fails without any information in log file
, ]+ j, v% \' I9 A1311687 PSPICE MODELEDITOR Timeout error while translating IBIS model. z( F# z/ @6 z) F. U" u
1327174 PSPICE MODELEDITOR Log file should list error details during IBIS Translation+ o7 s7 k1 l5 D6 R; \4 I
1499665 ALLEGRO_EDITOR INTERACTIV Offset Move depends on move setting.
7 e9 O/ ~4 P! v8 t/ I; O1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation- |- H0 g% X) A, l
1565795 ALLEGRO_EDITOR UI_GENERAL Search does not work in the Defined Variables window8 v: g8 G8 M3 [
1568817 ALLEGRO_EDITOR UI_GENERAL Padstack editor not accepting comma as decimal separator with system locale set as LANG ru_RU.UTF-8
5 J/ T2 n6 k1 r- b1569272 ALLEGRO_EDITOR PLACEMENT Get the error message 'E- (SPMHDB-394): Placement cannot be completed ... 'after creating Place Replicate circuit: F9 i3 E* A. u9 o
1577379 CONCEPT_HDL CORE Packager-XL gives different results when run from DE-HDL and ADW Flow Manager
- n8 m2 H( z/ R# C; ^& C1578523 ALLEGRO_EDITOR PAD_EDITOR Library Padstack Browser does not refresh preview
' Q4 z7 B8 L; @- ?% U1578533 ALLEGRO_EDITOR PAD_EDITOR New Padstack Editor does not automatically update the geometry {. G! T# \$ i7 y/ O
1581129 CONSTRAINT_MGR UI_FORMS Unable to dock the Electrical worksheet in Constraint Manager
& `2 u* y" }. j1582103 ALLEGRO_EDITOR PADS_IN PADS Library Import creates additional filled shape not present in source data
$ r- m3 y T" n1591027 ADW LIBDISTRIBUTION Library Distribution redistributes previously distributed models
; w3 T) W' [6 F- x1592026 CIS VIEW_DATABASE_PA View database part does not work from schematic pages of an externally referenced design
& p3 q# ?9 D1 D, r, C& n, z/ `/ ^- X1593389 CAPTURE GEN_BOM Include files in Tools - BOM not working
- C# x2 d2 Q( t0 a3 h7 z, L* D1593404 SIP_LAYOUT EDIT_ETCH Slide command moves via toward the object
& W# P, s, `2 ?, O* \ n1 ]1595872 CIS PART_MANAGER Capture CIS Part Manager PCB Footprint update case-sensitivity issue: x/ [2 i9 f4 b, g
1596955 ALLEGRO_EDITOR EDIT_ETCH Scribble mode is not working as per expectation.5 i, Z3 b( y& P9 O9 }: m7 y
1600936 ALLEGRO_EDITOR INTERACTIV Pin DataTips differ between 16.6 and 17.2
& \) i+ k0 M% t* _+ B1605961 ALLEGRO_EDITOR COLOR Wildcards not working in the Filter Nets field of the Color Dialog window7 w+ C& {, E( t$ J
1606392 ALLEGRO_EDITOR PLACEMENT Filmmask not shown when component is attached to cursor2 v$ I% F3 v5 ?* a
1607016 ADW TDA TDO crashes after LRM update during check-in hierarchy; o2 L( P1 M9 @+ `/ [, S$ _
1608059 CONCEPT_HDL CREFER Removing crefs from top-level design also removes .csb files from lower-level blocks
! A6 U U9 o# D/ \4 d1 z; @/ f1608278 CAPTURE OTHER Crystal Reports: User is prompted for ODBC password to create a BOM report
+ |. j" p9 k' U9 ~$ e1610377 CAPTURE PROPERTY_EDITOR Discrepancies between the NET_SPACING_TYPE property (or any other property) text and the actual property0 S5 u2 k. F. I* L* e' h
1610456 ALLEGRO_EDITOR DATABASE Strip design and selecting user defined subclasses results in database corruption.
$ x w% T5 X; \5 f" f3 c# f8 q) {% P# `1612793 CONCEPT_HDL OTHER Pattern-based auto-distribution of split symbols not working if there are spaces before commas2 p: \$ D: U4 T6 D8 v1 z! r7 f
1613442 CONCEPT_HDL CORE Signal names are not horizontally centered when the wires are added using different methods
) Q2 `5 j3 s1 d7 x* ~ m2 [+ V1613559 ASDA IMPORT_DEHDL_SHE custom variables from the BOM Tables are not getting imported
/ q/ J( i! |* [1 F. s1614093 CONCEPT_HDL CORE Import Design window has artificial 64 char limit for path - prevents access to some locations3 W2 c% N' C! e2 @
1614372 CONCEPT_HDL EDIF300 OFFPAGE symbol is exported as PageBorder in EDIF300 schematic X! {# K( l" `, Z0 e
1615075 APD LOGIC Netlist-In wizard fails to import the net names, but gives a successful completion Info message
: a l, ]' t- K1616131 ALLEGRO_EDITOR PLACEMENT While placing a module, the Mirror command in the right-click pop-up menu is not working
( p; T+ h- w: J J% ` m4 U1617377 ALLEGRO_EDITOR UI_GENERAL Visibility pane does not retain the correct layer view2 [ [6 G' D# {- l: _
1617404 ALLEGRO_EDITOR UI_GENERAL axlUIMenuChange does not work as expected in 17.2
0 N9 E' R7 J6 r7 b6 w3 G1619412 ALLEGRO_EDITOR INTERACTIV Script to create new padstacks from existing padstack is putting in wrong values for a regular pad% l( g, T9 o" A$ x7 x; a
1621842 ALLEGRO_EDITOR PLACEMENT mechanical symbol without placebound will not place in QuickPlace
a. N5 g' H+ V' w# |+ e& N# c1621874 ASDA PRINT Print - Save as PDF uses the default printer options only
3 p0 {( z) r9 N! @1621887 ALLEGRO_EDITOR INTERACTIV Getting a 'Could not satisfy the snap condition' message when using the Snap pick to option6 o" M8 V! H+ p4 E: ^- L; k5 r
1622680 ALLEGRO_EDITOR PADS_IN Import PADS fails with the 'ERROR: *NET* section found. Translation of netlist is not allowed.' message; o! G6 ]# Z/ v# v
1623832 ADW COMPONENT_BROWSE Incorrect part placement on schematic in Design Entry HDL 16.6-S073. ?! ~- L* U E, y& O) k. g
1624813 CAPTURE GENERAL The Value property is always left aligned when placing a symbol on the schematic
" U# z$ }9 P" b7 M- f1624953 ALLEGRO_EDITOR UI_GENERAL Custom views in 17.2 do not return to original* }* r" t, [. w0 s+ U( I8 x0 Z0 c6 P
1625000 ASDA CANVAS_EDIT File - Save Project does not provide any indication of saving or progress bar
/ t1 y) U* i9 R4 S5 m3 w& c; `1625163 CONSTRAINT_MGR OTHER There is no status for the analyze command in the Constraint Manager in 17.2/ _ Q* Y; Q! _# }% V
1626647 PSPICE ENVIRONMENT Capture crashes when loading a design with two hyphens in sim profile name. S1 q8 X6 ]- |) r
1628357 CONSTRAINT_MGR OTHER Constraint Manager shows differences if exporting and importing constraints on the same board.
+ h) o) b9 N j h( g$ @- ^1628409 ALLEGRO_EDITOR PAD_EDITOR Pad Stack Editor does not remember last used directory
& o, \ [4 `$ p2 T1631443 CONCEPT_HDL ERCDX ERC reports warning due to lower-case value of some properties in chips.prt0 N# z9 F9 u; a0 u; a/ E. P& A
1632195 SCM OTHER 'No known page border found' error in cref.log
0 i4 z* Y8 d$ G3 m1632365 CONSTRAINT_MGR OTHER Select command is disabled in the right-click pop-up menu from Constraint Manager in SPB 17.2
6 s% M, b% z' t, } h5 }7 ~7 V1632462 ALLEGRO_EDITOR 3D_CANVAS 3D View (new) and PCB Editor crash when checking collisions' }5 b8 {$ Y1 O- m5 O) M7 f" t
1632590 ALLEGRO_EDITOR 3D_CANVAS PCB Editor crashes when 3D View is open and more 16.6 boards are opened
( ?0 B6 |. ]$ q, M! V1633433 CONSTRAINT_MGR UI_FORMS Expand - Collapse feature for multiple objects not working correctly
6 F" F( f9 |0 s9 T5 ?7 d, e( P1633454 ADW TDA TDO crashes if DAO throws an exception+ J; }2 A! l# P3 b9 F# Q
1633526 PSPICE AA_PPLOT Spaces in Simulation Profile cause error in Parametric Plotter
; h5 p# g, \% G' C) A! |1633608 ALLEGRO_EDITOR COLOR 'Retain objects custom color' should not enabled as default.
! P& [; _# C) D0 H: \6 Y# O l- N1636216 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas (Unsupported prototype) is not mapping step model when assigned to device4 ^: B9 b' `" c4 T/ G" Z
1636899 ALLEGRO_EDITOR 3D_CANVAS The new 3D Viewer is not taking the Package Height set on the PLACE_BOUND layer into account when displaying it.
. v; ^9 v* m7 V4 v+ Y& i1638185 CAPTURE DATABASE Opening CIS database locks all part libraries none of which are open+ C+ {( w. ^/ A) a* }1 \* G* ~
1639409 ASDA CANVAS_EDIT Handling of MAKE_BASE property from DE-HDL designs imported into SDA
: F6 g3 {$ _) o3 A5 v1639541 CONSTRAINT_MGR OTHER PCB Editor 17.2 crashes when making changes in Constraint Manager
& O# j' [3 z: `0 g1639613 APD STREAM_IF The stream out command has created sharp angles in the GDSII output file
3 A$ N* X' M7 L1640061 ASDA HIERARCHY Incorrect message received when invalid characters are specified for subdesign suffix) E, \0 y: H- F, S
1641118 F2B DESIGNVARI Some DNI parts are not identified in the variant view due to the BLOCK
, c( Z" [0 k0 J2 j8 K' E: K& D1641410 ASDA CONSTRAINT_MANAG No errors or issues reported when incorrect topology is applied to a net or an Xnet
; {2 z w5 A7 ?& \; U- J5 L; m5 Y" S1642891 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes randomly while working on Constraint Manager6 S) s" a9 Y, N& r
1643003 CAPTURE PROJECT_MANAGER Start page shows latest as S004 after installing S0057 R/ h0 S. y; \6 s
1643532 ALLEGRO_EDITOR OTHER Strip design command fails to delete symbol text in the attached design& }7 I+ C7 q' h* D% | W8 E9 L% i& N, `
1645529 ASDA CONSTRAINT_MANAG Unable to delete the diff pair from the nets
7 G3 y0 k+ |6 [& ?, h1645639 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes when the XNET_PINS property value has a trailing comma character
: N& ?+ W. m" Q0 I7 H1646354 CONSTRAINT_MGR CONCEPT_HDL Cannot select Design Instance/Block Filter from the View menu in Constraint Manager
5 ?: A; T. e$ O# d5 f& H1646612 PCB_LIBRARIAN CORE Generate Symbol option crashes Part Developer% A4 K8 x0 T+ C& F7 P
1646932 ALLEGRO_EDITOR MANUFACT Manufacture - Auto Rename Refdes keeps defaulting to Use Default Grid even if another is chosen
5 i' T* K, B: z7 m, X1647190 APD REPORTS 'Sorted by Bond Finger' report shows incorrect wire bond connection
: ]6 }1 z- B& @$ g) D0 i1647673 ASDA EXPORT_PCB Two Physical folders are seen after installation of QIR- R' N% M& P7 U+ J w3 n: D& q
1647729 ALLEGRO_EDITOR SKILL axlFillet returns t when fillet is not added.- U' D1 Y: Y2 g, P! v* ~
1647779 CONSTRAINT_MGR OTHER 'Software Version' in the cmDiffUtility viewer does not show the correct version
1 p7 r2 f: i* ^( N4 f& p. r0 P1647843 ALLEGRO_EDITOR ARTWORK Misleading information in command window when artwork import fails' ~) R* c8 e$ S1 w; g1 a
1648575 CAPTURE OTHER Suppress warning setting must be written in capture.ini file
/ N2 A* V, z4 w; f1649060 CONSTRAINT_MGR CONCEPT_HDL Rename dcfx to dcf process results in error in log file and dcf not updated$ x0 m# \. W2 S% q
1650106 ALLEGRO_EDITOR 3D_CANVAS 3D canvas rotates mirrored components in unmirrored angle
) Z6 ^, Q8 m1 P' _1 W( W1650238 SIP_LAYOUT WIREBOND When performing 'Adjust Min DRC', the reference bond finger should not move.
+ x2 \1 B, ]1 x& |6 I) r1650734 APD SHAPE Shape on L1 does not flood properly' d8 J v* n1 Y7 z% U! A# J2 ~
1650793 CONSTRAINT_MGR CONCEPT_HDL Conflict of XNET_PINS definition between the chips and the SIGNAL_MODEL is not handled correctly
4 Q V& y4 a, U- @& v) \, \1650801 ALLEGRO_EDITOR SCHEM_FTB Running Export Physical with Update PCB enabled in Project Manager crashes netrev.exe
5 P% O! u+ P' p0 z1651011 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D viewer shows mechanical symbol mirrored+ _- |2 q; M2 Z9 q% o0 ^& K" W# i
1651063 ALLEGRO_EDITOR CROSS_SECTION Cross-section preview is incorrect
2 b( E0 a! D. j1651066 ALLEGRO_EDITOR DATABASE Pins not connecting even after running the Tools - Derive Connectivity command
/ f3 g) A. P) A1 _$ s% D: ~/ x1651700 ALLEGRO_EDITOR SKILL Running axlXSectionModify() on a layer removes the value of the material" d& P- c8 M* F+ W- S* G
1651925 ALLEGRO_EDITOR ARTWORK Searching for a macro in the artwork data file: Count for the macro does not match the actual count in the output
( O( L/ o4 i( ]& A0 c9 |1652230 CONCEPT_HDL CORE The master.tag and vlog004u.sir files are not created in the entity directory on saving symbols% d$ i9 b$ s3 Y6 G% w. e; k/ C
1653080 CONCEPT_HDL ERCDX Difference in results from SPB16.6 in 'erc.rpt' when logic_data is renamed as worklib in SPB17.2 on RHEL6.5
5 w! @5 b# P5 u. Z1653422 ADW LIBIMPORT Classifications not linked to a Part Number or Cell Model are removed during Library Import
. A) m a1 t6 a# t1653526 ALLEGRO_EDITOR DATABASE Via padstack keepout is not displayed on the canvas when pads suppression is enabled.9 F/ B- q* E5 L4 A
1653951 ALLEGRO_EDITOR CROSS_SECTION Cross Section Editor changes lost despite selecting No to the 'All changes will be lost ...' message' s+ A7 U; G5 _( O8 b
1656224 ADW FLOW_MGR Copy Project wizard no longer allows dashes in the 'Name of new project folder' field
; z7 y3 E+ ^$ h% y1656581 ALLEGRO_EDITOR OTHER PDF generated for layer with shape shows undesired voids if film is mirrored and Filled Shape is not selected6 w B. S/ F2 |% l) ?9 q2 W
1656608 APD REPORTS Incorrect calculation in the metal usage report$ ?: T: Q0 h0 a# N) Z
1656726 CONCEPT_HDL CORE Interface command always disabled in the Wire menu
$ w; g8 E0 b7 A& I9 V+ n1 T8 C4 O1656841 CONSTRAINT_MGR UI_FORMS Incorrect layer information is displayed in the Edit Via List dialog when a filter is applied
! j- [' ^- e L, b8 r$ ~1 q1657220 ALLEGRO_EDITOR SKILL axlXSectionGet() returns Primary list of layers and not All stackups% ] S3 H) V1 K+ B" ]
1657257 SIP_LAYOUT EXTRACT When using extracta, custom layer names not getting retained- M1 \; [, I: S4 g9 s
1658440 ALLEGRO_EDITOR PAD_EDITOR The location of a drill in the .pad file is different from the .dra file
( _; N' u. j7 c$ g! c2 [& J. \, u1658445 CONSTRAINT_MGR CONCEPT_HDL When DCF file is converted to ASCII, no further updates are allowed. B5 i4 ], R: B' U1 L5 K
1659473 SIP_LAYOUT WIREBOND When moving wirebonds they are jumping instead of sliding
+ I5 b- x! p# E( ?2 k1659498 ALLEGRO_EDITOR INTERACTIV Unable to turn off line on Etch Wire for Jumpers1 @- R% O0 w: {! [/ G
1659644 CONCEPT_HDL OTHER Predefined nets are not listed if 16.6 design is being opened in 17.2 q9 I% M ^" P) k6 p" `5 q
1660475 CONSTRAINT_MGR UI_FORMS The CTRL+V shortcut is not working in the Export Constraints window in Constraint Manager 17.2
* E' R3 z% t5 ?8 W! m+ z$ [; V1660492 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes when using multiple desktops on Windows 103 q7 x. y4 r% S( P, u6 {
1661133 CONSTRAINT_MGR ANALYSIS PCB Editor crashes if comma is used in the Value field for Analysis Mode
1 C+ R$ w4 Q; J+ s- t! V; j1661307 CONSTRAINT_MGR CONCEPT_HDL Prevent creation of diff pairs on VOLTAGE nets v: h9 g/ f6 w8 z: X7 g& U% W1 k
1661357 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when using Route - Connect
2 g9 u: ]5 F' ^3 a5 A4 t5 T; {4 ]7 }1661874 ASDA DESIGN_CORRUPTIO Unable to delete the ZERO part from the schematic page
4 F- d4 C2 t! K* f1662799 ADW SRM Mechanical symbols are not being displayed in the Mechanical tab of Symbol Rollback Manager
/ X5 m) p7 S) t2 y* t% e& E1664797 SIG_INTEGRITY GUI Unnecessary coupled interconnect models were generated during View Waveform.' U$ D8 @6 w0 e5 ~7 |4 u9 ~9 y. N
1664858 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes during Auto Interactive trunk route.
: ` z- ^ O- G. y7 l7 H( K1664911 ALLEGRO_EDITOR OTHER PCB Editor freezes after DRC Update is performed9 k8 z# }6 W4 y% y. n* {; W# p' V; @
1666329 CONSTRAINT_MGR OTHER SCM Import Physical process crashes cmfeedback
6 H- @6 t! E7 f8 ~1666551 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option separates imported artwork to different XY locations1 L5 S! Z. p4 g: R; ?' X
1666723 ECW TDO-SHAREPOINT TDO login is not working with Site Minder because of incorrect characters in the Site Minder login form HTML. U, e5 N* H4 x2 }' G
1667068 ALLEGRO_EDITOR SHAPE Update shape removing the shape voiding# w( A, j( a6 g
1669828 F2B DESIGNVARI Variant Editor crashes on Windows 10 T540 P laptops but works fine on Windows 10 desktops2 K1 [* J- y& v+ x/ `+ R
1670221 ALLEGRO_EDITOR DATABASE Non-recoverable corruption error is reported when saving the board after adding a layer
! q3 K" Y) H2 e ? s. k& T1672134 ALLEGRO_EDITOR ZONES TDP needs FIXED component override
5 w Q- z9 b) {( F5 B, H
, j. u! i; A, Q( D& q/ W; m' ?0 L/ c! V/ |5 Y6 b. y6 z8 Y
Fixed CCRs: SPB 17.2 HF008& K/ Q9 t. f) X4 ^4 A+ k& s
10-29-20160 z+ @5 L4 m" W% W6 D
===================================================================================================================================
/ M% b% [. e- [" x! xCCRID PRODUCT PRODUCTLEVEL2 TITLE# K$ W" Q* w9 \) @. h% K8 W
=================================================================================================================================== ?5 l6 N5 X& [4 g7 E+ x' o
1644406 ALLEGRO_EDITOR SHAPE Alternate symbol placement results in illegal parent identifier error/ v7 X$ t+ k% g. V
1647098 SIP_LAYOUT OTHER SiP crashes on symbol copy and rotate
4 t+ w( Y) P0 K0 o$ x" {" x1647154 APD OTHER Disconnected Clines not working
) e8 b+ ^: e8 B% g3 H1648817 GRE IFP_INTERACTIVE Allegro PCB Editor stops responding on adding netgroups to a nested netgroup
$ y& @% }* O8 K* |# F5 c- w6 {1649829 CONCEPT_HDL CORE A delay is observed before the sub menus of the File and Tools menus appear
3 y# c; Q) T2 h0 }1652930 ALLEGRO_EDITOR OTHER Command-line version of switchversion not working. E# {8 [# c2 ^0 f
1653109 ASDA DESIGN_CORRUPTIO SDA not pulling latest library information for part# P$ U0 q: c' Z) L) V/ w% Q- f
1655377 FLOWS PROJMGR Project Manager crashes on Windows 10
* w! B6 A+ J9 }% F
6 j7 l0 [4 C5 T6 U1 w) I$ h0 z7 K8 G/ {5 M; U. o- p y! z1 T4 [
Fixed CCRs: SPB 17.2 HF007
# }0 f7 c5 V* O! K7 i10-20-2016* V9 t6 _9 }7 z4 |& R% h7 O
===================================================================================================================================
9 T1 _0 [/ L1 K6 ] QCCRID PRODUCT PRODUCTLEVEL2 TITLE% p' t# `* R# D! \( L; n, O2 X
===================================================================================================================================) {3 y8 a* P- }2 c
1582276 CONCEPT_HDL CORE Need the ability to delete an image placed on the DE-HDL canvas; X) n1 c* x8 ^2 `* Q1 t
1594101 CONCEPT_HDL CORE No error or warning issued on specifying an incorrect unit for voltage; x$ g, r8 X' G; I% N$ [, K
1611293 ALLEGRO_EDITOR UI_GENERAL If the Command window is floating, it cuts off text from the bottom half of the last line.
+ a* g. Y$ E% ^$ l: ^! \% V1611652 ALLEGRO_EDITOR UI_GENERAL New artwork film not appearing in the drop-down list for Visibility Tab2 @4 L5 R2 j/ y7 S
1618205 ALLEGRO_EDITOR UI_GENERAL New Artwork film added is not updated in Visibility - View
2 w$ Z3 x" ~, D5 Z5 V( ^ a! _8 y1631114 CONSTRAINT_MGR OTHER SKILL functions axlCnsPurgeAll and axlCNSDelete delete spacing constraint sets but not deleting names
2 K; o: p; v( v- @/ q1633726 ALLEGRO_EDITOR UI_GENERAL Visibility tab not dynamically updating the view list when artwork film changes2 N5 x" J' K* |: ~+ l
1636404 CONSTRAINT_MGR CONCEPT_HDL In 17.2 QIR1, DE-HDL Constraint Manager allows users to enter invalid voltage units
$ a4 V$ ]' H0 {3 u1636864 ALLEGRO_EDITOR UI_GENERAL Domain Selection for Visibility does not work with Hotfix 004 unless you save and reopen the board file" r+ T- w7 c$ t5 R/ o
1638251 ALLEGRO_EDITOR DATABASE Unplated hole changed to plated hole after uprev from 16.6 to 17.2 version+ I! U) Q5 f" j$ g2 u
1639483 ALLEGRO_EDITOR EDIT_ETCH Manually routing discrete components with incorrect constraints causes PCB Editor to crash
/ L8 w7 Y+ ]2 p6 m1641435 SIP_LAYOUT IMPORT_DATA Need SiP Stream mapping layer count to match Virtuoso stream layer mapping count1 w4 m+ w& y: b Z
1641483 SIP_LAYOUT WIREBOND SiP Layout - Modify the wirebond report generation for Start and End height when using a DISCRETE class footprint* w8 w* g+ M$ }3 A; r& U- \, Y
1644131 F2B PACKAGERXL Option needed to package a DE-HDL design with ptf errors into a board file6 b8 }- X! ^% j) g) l9 J+ X1 J
1644807 CONSTRAINT_MGR ANALYSIS Unable to set electrical constraints modes with the OrCAD PCB Designer Professional licenses
) s4 a( C( {0 X! h0 N9 ` `1646228 ALLEGRO_EDITOR UI_GENERAL Running the axlUIMenuInsert command to add a submenu after running the axlUIMenuFind command crashes the tool; g" Y( N) D" k+ a) N
1647402 PSPICE PROBE Unable to print on Windows 10 as no plots are displayed in the Probe window; k/ S7 G. \' o; R. J% v
1648183 ALLEGRO_EDITOR INTERFACES Allegro STEP Export: Using the 'step_3D_copper' variable, pads not exported in the same plane as traces and shapes
" J. H: J% c# p" S7 l! q1649222 APD ASSY_RULE_CHECK Allegro Package Designer stops responding on running the Acute Angle Metal DRC- f# B6 S) K! ~4 [6 p7 C
8 Y9 P6 y M- x
5 c) x/ A7 e9 ^/ `" M+ f! IFixed CCRs: SPB 17.2 HF006* [( x9 g% ^* g" u0 l# g9 e8 g; U, A
10-7-2016
1 f' o. C' x5 D" }# [9 E===================================================================================================================================/ ?8 d+ y) t" j9 A! G. R9 W( I" ~
CCRID PRODUCT PRODUCTLEVEL2 TITLE5 _' U- C$ B6 L4 Q' f' y! d
===================================================================================================================================4 V* Y0 i+ ^8 B/ [
1585203 ADW DBEDITOR Optimize check-in of footprints with multiple padstacks" M( a% n6 l% @8 l' U% K% u3 v
1607954 ALLEGRO_EDITOR SHAPE Dynamic Shape not updating correctly
: Y# |5 H* `' C) M1618173 ADW SRM SRM does not automatically run when a .brd file is opened from EDM Flow Manager in 17.2 Hotfix 003
4 N* n* G! Z3 ~7 L+ q0 f8 h6 c; `. V1618832 ADW SRM SRM marks parts as updated even when they are not updated& A. h( a+ c, n2 W9 F3 y' \) W
1623823 SIP_LAYOUT WIREBOND NO_WIREBOND property is ignored by Add/Edit Non-Standard9 ~& Y, u. U6 Q8 N5 K) D1 K" g
1626001 ALLEGRO_EDITOR SHAPE Shape to route keepout DRCs reported for dynamic shapes in the attached design+ |# P& k1 w* E( c$ J+ w y. E
1626546 SIG_INTEGRITY FIELD_SOLVERS Extra RL elements in via spice circuit model generated by Via Model Generator
& C" {4 P7 M; l$ @/ b1631792 SCM OTHER The NC net has re-attached itself to another net, RIGHT_LEFT_N, in the design
3 y, v0 \9 p" H4 }5 |5 v% x1632223 ADW LRM Checking in a hierarchy causes a crash8 B' X( O) C- G/ |% ~" j; e
1632844 F2B DESIGNVARI Part is simultaneously defined as Pref and DNI in Variant Editor with no error- ]( N d$ t% \2 d) Z0 i5 M
1633647 ALLEGRO_EDITOR MANUFACT Variant issue: Create Assembly Drawing command not creating filled shapes for keying pegs in attached design
) @1 _+ U9 z% q( x! G1633707 ALLEGRO_EDITOR DATABASE Cannot remove Route_Keepout associated with a pin
. r5 O3 Z! {0 z: g! F1634392 PCB_LIBRARIAN OTHER Launching Library Explorer without -proj option crashes the tool" m5 Z7 u+ K6 r+ u
1635049 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes when trying to create layer set from Constraint Manager
/ y, f: |3 h1 }* o) c7 ~# c1635593 ORBITIO ALLEGRO_SIP_IF Importing .sip file reports undefined argument error while processing shapes" Q7 l# f' W z' Z2 H) X6 c) K
1635858 ALLEGRO_EDITOR ARTWORK Get 'WARNING: Null REGULAR-PAD specified for padstack' messages in log file when generating artwork for all layers; u, h0 Y0 J4 N
1636097 ALLEGRO_EDITOR ZONES Technology Dependent Packaging footprints not updating in the design) S5 K: k9 V- W C1 t0 `; P
1636185 ALLEGRO_EDITOR ZONES Import Placement not placing TDP footprints in zone
8 g4 l' E: `$ n. a5 w, f: s1636867 CONSTRAINT_MGR OTHER Millimeters shown as mils in the Analysis Modes dialog box6 s0 [) t9 T5 k# O: x A D, u
1638094 SIP_LAYOUT OTHER Cross Section Editor not seeing updated information9 n0 D/ l8 U: q' m9 Q
1639845 ALLEGRO_EDITOR INTERFACES Step file not generated when board is exported to a folder with special characters in name4 n( _8 z, J Q) X. u3 `7 W
1640611 APD SKILL Launching XtractIM from SiP Layout with the attached design crashes both SiP Layout and XtractIM W4 u5 M9 I0 c- {/ b
1641339 ALLEGRO_EDITOR INTERFACES DXF_IN does not show all the subclasses available in the design' i6 u& E' B7 _4 t+ `: `+ \
1641879 XTRACTIM GUI XtractIM crashes on extracting a SiP design if 'SI Ignore' is selected for a die stack layer in Cross Section Editor
) ~6 ~$ g) x8 U; k3 e# A9 V5 d) n1642012 CONCEPT_HDL CONSTRAINT_MGR Schematic-defined net groups without any members cannot be deleted in Constraint Manager( ]4 u' [' U1 X5 x: C$ [. }) h
1642015 CONCEPT_HDL CORE Pin exists on block but no corresponding port exists in the underlying schematic
) d% B" H3 W) \1642597 ALLEGRO_EDITOR OTHER Importing .tdp file: Footprints not included in the .tdp file are updated in the design
9 O7 S7 P$ M$ N: v1643557 SIP_LAYOUT DIE_GENERATOR Die Text files will not update the design. V" ] L, k# C# N
1646086 ASDA IMPORT_BLOCK Importing a DE-HDL design into SDA results in error 'IMPSHT-42 Alias cannot be created'
1 ]2 ?6 {2 y1 a N6 K! A1647580 ASDA IMPORT_PCB SDA-File Import from PCB Editor has duplicated RefDes on schematic.( {) S! m; k9 [& m
4 c( s' |1 E9 d/ b# X
* j7 d% J# z B% _1 A2 T: C- {/ l0 EFixed CCRs: SPB 17.2 HF0051 A) z8 L7 p [$ ?9 |+ z
09-10-2016, c7 V$ x' Y6 W1 [1 ]
===================================================================================================================================
# Q9 b& \+ ^) x2 A8 XCCRID PRODUCT PRODUCTLEVEL2 TITLE
+ \6 L+ `! }/ |7 ^===================================================================================================================================8 d& O1 {2 z: u# P5 {% n/ ]
1496199 ALLEGRO_EDITOR SHAPE Overlapping route keepouts result in a broken shape
2 t" Y, v$ y6 N3 i. A1519972 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase DRC at incorrect location
7 y7 A7 @9 V9 L' A) E) K3 D$ f& y8 w9 P1521940 ALLEGRO_EDITOR DRC_CONSTR PCB Editor not recognizing the correct pin pairs of the differential pair# u( A) m. E' ^ a5 U' U* A
1536713 ALLEGRO_EDITOR INTERFACES File - Viewlog still checks for brd2odb.log file
( d! ~. z1 B/ h* v3 O8 ^7 E1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once" u g0 \* p* n% M6 d
1586846 RF_PCB PLACEMENT Get an error while manually placing RFCOMPIB part
2 h, F0 G& Y) ]1588769 ALLEGRO_EDITOR UI_GENERAL ALT+key shortcuts are not available in 17.2
* T8 N8 ^' G* q- x0 x1589396 ALLEGRO_EDITOR UI_GENERAL Need option in 17.2 to change the placement of the Find, Visibility, and Options tabs
1 B! d9 z; r3 J& h) Y: _1593258 ALLEGRO_EDITOR OTHER Adding German letters to database diary deletes all the entries
% C; S) _) @" D" O( P# C7 o: w1597413 SIG_EXPLORER SIMULATION SigXplorer crashes when simulating with a via that was added to the canvas. v" \: E, n; I5 Y- i6 }6 Q
1599680 ALLEGRO_MFG_OP ALLEGRO_INTEG Documentation Editor crashes on opening a specific database# B* Q1 p3 b" h! T
1606682 ECW ADMINISTRATION ECWBackup and ECWRestore fail when data is 1GB or more
e: g! r* W0 ]1 j8 M4 V8 a1607250 ALLEGRO_EDITOR DATABASE A board file created in release 16.5 crashes when opened in 16.6 Hotfix 69, ]8 S1 D' S/ m
1607565 ALLEGRO_EDITOR SYMBOL Default values are not consistently converted when adding pins after changing units.
, F4 G( m! ^+ \( ]$ ?1 p1607956 ALLEGRO_EDITOR OTHER Unable to generate the model index file from the command line using mkdeviceindex
o' G! s j7 Y3 i* P1609794 ALLEGRO_EDITOR UI_GENERAL PCB Editor: Shortcut keys to menus are not available in 17.20 K, m7 l r2 M# R$ Y7 v
1609817 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes on opening project
3 f1 H! g0 L8 l. @9 m% v# i1611446 ALLEGRO_EDITOR SHAPE Inconsistent break in shape when creating voids in a design in 16.6 Hotfix 69
4 Z' g+ q5 l. }8 H2 C' t" x1613512 ORBITIO ALLEGRO_SIP_IF Unable to read the OrbitIO database file (.oio) in SiP Layout* r9 C& d( A. s, t' q. e- U
1619610 ORBITIO ALLEGRO_SIP_IF Some mechanical pins appear rotated by 90 degrees when imported- _ F# I! G0 C/ r% M1 T1 q: |4 t9 A
1620814 ALLEGRO_EDITOR PARTITION Etch and Via are not imported with the partition
" ]5 R" U) N0 X( d/ D% V1621390 GRE CORE Design Crashes during the Spatial Planning phase
: @6 Z, ?& p3 d+ W& S7 G0 F) \1623112 ALLEGRO_EDITOR OTHER SPB17.2 switch release is unable to identify 16.6 release when 16.6 is installed in All-Users mode$ l1 E1 Z" X5 P0 a8 M7 B) ~
1623113 ASI_SI GUI Aggressor waveforms are not displayed in waveform viewer after crosstalk simulation0 ^3 P5 A/ w1 a0 k
1623231 CONCEPT_HDL CORE Unable to make the Attributes form part of the standard display in DE-HDL
- C& M; k% ?' J; e' q1623666 APD OTHER Incorrect vector pin syntax appears in the chips file written using 'RF Module - Export chips & connectivity'
, j3 H# s5 \" I% Y3 v* q1623888 CONSTRAINT_MGR CONCEPT_HDL Ambiguous and inaccurate mapping errors reported when an ECSet is applied to a differential pair object( p& _$ N$ y, @! Q8 N
1623904 ALLEGRO_EDITOR SCHEM_FTB Logic import fails, but no error mentioned in the netrev.lst file
5 D% P( O' c: M1623935 ALLEGRO_EDITOR SKILL On running the SKILL function, axlSectionModify, Shield and Etch Factor are not updated
8 }0 T# r2 q$ X _8 {( U" b1625610 ALLEGRO_EDITOR SHAPE Modifying a shape boundary leads to other shapes losing their voids
# Z0 V' J3 m$ s" Q1626716 ALLEGRO_EDITOR UI_FORMS Z-Copy menu is not available with OrCAD PCB designer Professional license
! c0 q# b9 g8 \+ E$ u1628403 ADW TDO-SHAREPOINT Objects remain checked out after multiple failed 'check-in hierarchy' attempts
' b& q5 M7 Y4 W& f+ |& \; U1630458 ORBITIO ALLEGRO_SIP_IF Import OrbitIO Database file (.oio) in SiP: Bill of Materials report does not include standard dies8 j% v- `. L4 f O2 n! [/ C9 C, Z9 _
1632504 CONCEPT_HDL CORE DE-HDL core dumps during Save Hierarchy on Linux
0 ^, `/ \1 ?9 S/ V) J; w4 q" Q* V1633581 ALLEGRO_EDITOR PLACEMENT On mirroring a part, the cursor moves to the origin of the board9 J3 W& o6 U7 G% R2 ]% E0 U
1633601 ALLEGRO_EDITOR PLACEMENT Place - Via Arrays - Boundary command: Via arrangement pattern deteriorated in Hotfix 004
! s. X" [* I+ {& q$ V0 J
0 B' Y3 z, {, ~, H" N3 ? _$ T$ z
Fixed CCRs: SPB 17.2 HF004
+ _2 `- B' @0 u2 M# b08-14-2016
, V; M$ B8 i7 G1 t% p# b" ^7 v===================================================================================================================================
# M: k/ B; F( \/ y0 ~CCRID PRODUCT PRODUCTLEVEL2 TITLE% A& f5 l, S. \+ a# |( T: t+ M
===================================================================================================================================' E) K4 ^+ {9 n5 f) \0 f* [
908816 CAPTURE SCHEMATIC_EDITOR Few graphical operations are active even when a page has been locked. o* o1 e& j( R& w8 O" ~& r
1213923 ADW LIBIMPORT Cannot delete parts in the Library Import project (XML)' R- L3 a3 E. x
1250476 PCB_LIBRARIAN LIBUTIL con2con does not check for PACK_TYPE value set to question mark& U1 p3 P" | e, o8 G! M2 h
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
5 w8 h5 R% P' M4 G3 K1322242 ALLEGRO_EDITOR INTERFACE_DESIGN Using Add Connect with the Replace Etch option causes PCB Editor to slow down for certain constraint nets) m; V, Q: n6 Q( T5 M
1326716 ADW DOCUMENTATION Dataexchange documentation correction needed$ n6 J7 R5 Z& B. G
1356948 APD DEGASSING When using the Degassing tool on shapes the size of the file becomes very large
% c |) d3 H' b* m! o1376510 ADW DBEDITOR DX output ERROR after Property Display Ordering of Part Classification.% [/ b, u' v$ p2 ?/ K% x
1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file3 T$ v& B. ~/ O
1410485 CAPTURE SCHEMATIC_EDITOR The 'Autowire - Connect to Bus' menu command and the 'W' keyboard shortcut are enabled on a locked design% l( [2 D) F$ D! K& t, A. `
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only, g X. Q3 n3 ?) S, a$ v1 k& G
1413287 ADW LIBIMPORT Library Import converts all Attributes to uppercase when reading CSV1 x1 F7 l9 I8 ]4 e0 j
1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
4 q* F5 E y- e4 S1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins! M; ?+ p D! K% ^/ u" _: ]
1430251 ALLEGRO_EDITOR PLACEMENT Quickplace placing symbols outside of a polygon shaped room
" {. L) L) _( i" R% V" G1440509 ALLEGRO_EDITOR PLOTTING Ratsnest does not follow the RefDes position when plotting the BOTTOM layer with the Mirror option1 F; \" |9 }2 c% L! A( Q
1441086 PCB_LIBRARIAN OTHER Changes made to a package with sizable pins generated from the 'sym1' view are not saved
. y/ W/ ~- e/ H+ V2 R4 c/ U1443339 PCB_LIBRARIAN PTF_EDITOR ALT_SYMBOLS syntax in PTF file not checked
" ^5 J; v7 Y0 W# e: r1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC5 U# r( B4 H- @) C% D" l2 R2 B
1451766 CONCEPT_HDL COMP_BROWSER License error message should indicate which license is required
' M6 U0 c. e' X1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set0 O2 \+ H/ F2 h& B; d; e
1457138 CONCEPT_HDL CONSTRAINT_MGR devices.dml: difference in content generated by _automodel add command and Constraint Manager launch( {) M& N% K( B! D$ u4 h2 q
1458439 F2B PACKAGERXL The Packager pstprop.dat file reports false conflicts in net properties
+ E. M1 P" q8 X6 Z; \1464865 CONSTRAINT_MGR ANALYSIS For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM
X5 O. d8 m: [9 u1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
! j7 o0 q. Y% T$ G; {0 ^0 Q. F1467826 CONCEPT_HDL PDF PublishPDF from console window creates a long PDF filename
2 e- {1 {# t5 T8 q; n+ e0 N. d1470106 ALLEGRO_EDITOR MANUFACT silkscreen program cuts auto-silkscreen lines excessively
7 ?' a" C( i8 `1 r1471287 CONCEPT_HDL CONSTRAINT_MGR Pages imported from other designs with different units should inherit the source constraint units
9 z, ] `2 c0 F" h( A1472046 ALLEGRO_EDITOR OTHER Gloss routine, 'Via Eliminate' - 'Eliminate Unused Stacked Vias' is not removing unused microvias from the stack* [0 V- \$ u' a- f) U( |
1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region
$ X5 X3 m- i7 @: a6 B* ?! F0 M1472444 ADW ADWSERVER Multiple errors in adwserver.out after SPB054/ADW47
5 h) z- |2 y: V2 X4 {1473056 ALLEGRO_EDITOR ARTWORK Gerber export has additional phantom data not on design
, k! N a; p ~9 i1473900 CONCEPT_HDL CORE DE-HDL stops responding when a hierarchical block with variants defined inside the reuse block is enabled
' w& K5 O5 z5 F; [, L( Z" B1474020 ADW DBEDITOR Unable to modify schematic classification when a part is checked out previously by another librarian
$ f. }( r% \+ d- @1474066 ADW DBEDITOR Bulk edit performance lags when parts included have a large number of properties
. Y7 C2 g8 E+ ]1474764 ALLEGRO_EDITOR PLACEMENT In Hotfix 56, the 'place replicate create' command does not produce desired results if a fanout is marked
% @% w6 n" _5 `6 O1 ~9 [; Z1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.
, v( C7 o `* y6 d+ b1475650 ALLEGRO_EDITOR OTHER Using Outlines - Room Outline gives WARNING (axlRemoveNet): No match for subclass name - 'BOARD GEOMETRY/__EPB_SCRATCH_'
# i5 L- k( C6 Z7 X1476528 ORBITIO ALLEGRO_SIP_IF While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown3 ]: Q# b) i+ E" H
1476920 CONCEPT_HDL OTHER Genview consistently fails in some indeterminant manner.6 B; @+ ^( H* u' W
1477369 CONCEPT_HDL INTERFACE_DESIGN A significant number of problems are reported when running genview with port groups
0 n1 v: A7 q! f( F8 w1478111 F2B DESIGNVARI Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release
% S0 i! ^! u3 X6 V/ [. {* F1478200 GRE IFP_INTERACTIVE PCB Editor displays the 'Low on Available Memory' error when updating shapes and then crashes u. S/ f/ V3 B. m V/ [
1478680 CONCEPT_HDL CORE Unable to move components in a schematic using the arrow keys
, L" S& I5 H1 j# a- b0 b& R6 G! x1479135 F2B PACKAGERXL Hierarchical design reports conflicts when signal names change through the hierarchy
8 M5 x! m- @1 t, _: U& w! i1479153 CONCEPT_HDL CORE File - Save Hierarchy flags an error and does not update subdesign xcon
0 k0 ]5 A9 }4 s4 h' Q- Q, u1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
. b0 M& ^3 J E1 K; Z1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
4 B9 M1 K, _/ v( y# P" Y& ]1479569 PCB_LIBRARIAN OTHER hlibftb fails with error SPCOPK-1053
( _9 v7 z7 ?2 b9 s5 `" t8 H1479785 ORBITIO ALLEGRO_SIP_IF BRD file is not loaded in OrbitIO
8 S+ f/ d l' ]1480005 ADW DBEDITOR The DBEditor or DBAdmin GUIs do not allow the same characters in Property as LibImport CSV Files
& r5 Z$ z: O* H, k! k3 [. l1480367 SIG_INTEGRITY OTHER Differential pair extraction SKILL error* I/ |* e3 y @
1480499 ALLEGRO_EDITOR PARTITION Cannot delete partition
0 e" I' ?3 @( W' q4 B1482544 ADW DBADMIN Hierarchical Preferred Parts List (PPL) is not functioning correctly
9 \' v, ]* }/ a e8 e& z6 x1483136 ADW COMPONENT_BROWSE Error flagged when searching a property value with parenthesis or comma in Component Browser in the ADW mode
! G7 Q% E+ Q+ t1 G, q' g3 V& x5 Q1483617 ALLEGRO_EDITOR DATABASE Delete islands command crashes database with filled rectangles
/ Z1 t: N4 Q) m$ d1484100 SIP_LAYOUT INTERACTIVE SiP crashes when copying and rotating a symbol* ~3 g$ r8 x! e4 X0 v8 T/ r, u
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues0 n' V5 K& A3 z$ ^3 l* U
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only) f) b' f& W4 m) |
1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file1 m, D+ p$ q; @, k( f, V
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project
; j6 g6 \) c8 n8 O" _1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.0 D b. O' g" d' A9 A
1486378 ALLEGRO_EDITOR PARTITION Unable to delete orphan partition as it is not listed in workflow manager." i0 Q, a" x& B6 ?
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems4 {8 Z: M; D7 F) L& k. E3 Y
1487125 ADW COMPONENT_BROWSE Results not displayed in Component Browser for parts with no associated manufacturer parts* E# H& L( G9 u3 G: {( Y2 k3 K" E, n
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior1 E+ c3 X3 G: S/ M) b# g' ~& g. I5 J
1487496 ADW DATAEXCHANGE DX changes checkout ownership when override action is set to remove existing relationships4 e; j; l9 N! S3 W" _( Z
1487656 ADW LIBIMPORT Pre-analyzing a project reports false warnings
( v z: E! @- M5 T2 u* K1487733 CONSTRAINT_MGR OTHER Export Physical takes more than two hours to update PCB Editor board" u' k7 `+ q( \! H2 B' w- h7 h% ?
1488753 CONCEPT_HDL CORE Import sheets in a design with no change in models: CM_VALIDATION_ON_SAVE variable is triggered5 j ~" e* N6 j- e. y) Z% U
1488758 CONCEPT_HDL CONSTRAINT_MGR Disable Constraint Manager launch if CM_VALIDATION_ON_SAVE is set and the database goes out of sync
% I. R. c. F3 X9 a( j$ o* d5 z X1490299 SCM OTHER Allegro System Architect does not update revision properly( s/ r* E4 T8 |/ W9 ^
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer
; X3 C7 a# X7 e1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints# K" c. x, s4 x( S5 w; K
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working9 G5 D p& {! ^9 m5 d; |& ~
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)2 c% U7 p' x2 y
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong0 |0 L+ d& d* Y
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit
# l1 c c, v. E' r" ?1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO crashes on importing MCM
8 }- x: b1 E7 a" o; A, Q6 z3 e$ q& y1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL7 \/ Q+ N% C- f3 q$ ~* h) X4 [8 N
1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs# r4 t- k, T8 u6 Q9 @' N
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size
- X3 V5 b% e4 i; q2 H! R$ e: u1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
9 d. s1 c6 b L# m/ ?1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file6 F$ h; ?$ e( y
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60: m: n$ v* N4 m% ]+ _8 v4 F
1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch$ i" H& k# S4 X! v! Y5 e" `
1500725 CONSTRAINT_MGR CONCEPT_HDL Unable to clear pstprop.dat file conflicts8 n/ l: h* M6 }& d& I/ ]
1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant7 C$ l, H: @1 G/ S. y
1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out" n6 X, S& c" k3 R
1501294 ADW COMPONENT_BROWSE Some tabs missing after the migration to ADW ISR 053 with SPB ISR 060
3 F3 @1 a; p* A) ?! q, m1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
) ], [; q( _" ~3 w+ }1502282 ADW CONF Configuration Manager: Clicking 'Set up or Manage Company & Site' gives an unclear message
5 N* C3 W) W1 F! \4 G5 }1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings
/ H2 W0 C: Y) b5 r1 M' }1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized
& @7 P5 X; `2 d' b+ `4 A2 r1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
0 _; |$ x$ V) f9 S/ r1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin( Q7 r% ?7 X- l) c8 @' w1 ^
1506654 CONCEPT_HDL INTERFACE_DESIGN On moving, Netgroups break
9 s: u5 X5 L2 i8 @9 N% I, C" L1507497 ADW COMPONENT_BROWSE Switching rows in Component Browser does not change the graphics of the symbol6 }; x, @: M- ^/ G- G
1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork* u9 }# n0 _$ q
1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
' ~3 o+ w, e ]1510570 ADW DATABASE ERROR: Cannot check in block model because the part with instance id used in the model is not available in the database1 \5 {% |7 B$ @/ E
1511180 ADW DBEDITOR Database Editor: Incorrect message about a schematic mode displays when associating a footprint to a part number9 E5 T* a: k$ b, ]' |; I7 [- Y
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
8 l* V% v- |$ @) t; F1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance6 b( _0 {1 u7 I7 G! R" f3 T' a2 d* n
1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.
: P/ K1 y( q$ ]7 h" R1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
7 g, m4 P" f+ C) J1513085 CONCEPT_HDL CORE NC symbols in the schematic are being renamed to NC_1 in pstxnet.dat and are routed as one net in Allegro PCB Editor6 i o% E& O% N* W- x
1513092 ADW DBEDITOR Create Footprint Model name is not working properly if it already exists in the local flatlib- H7 f$ |' }0 a: Y% t! G+ a
1513737 ADW CONF DesignerServer from a different network domain does not show distribution data
! Y& m5 K3 Y* I3 _1 z1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property! u# D. a) ]0 H( ~# _
1514942 SIP_LAYOUT CROSS_SECTION AIR no longer permitted in stackup in 17.0
: r1 `+ L5 z# B1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly' L9 g" E+ `8 V( r5 {( Q2 \; A; B
1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol
" x/ y4 n: s6 Z9 @+ b% y* v# K1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via5 _1 J+ s: Z' b1 e
1518032 CONCEPT_HDL SECTION Error SPCOCN-2009 displayed even when the user has not manually sectioned the design \) e( n5 J! t% k& Y# z
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes
: G4 l2 g* m/ b5 B% S% e% x3 s1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.
) \% g5 y2 q- }0 v1 r$ i" |1519518 CONCEPT_HDL OTHER Genview does not generate split symbols
v! z. p$ J* r1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas5 Y! Z. L) h) ]* H( ^
1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
0 r: Q+ d0 {6 P7 o& ^; X% T# Q1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net2 Z; r$ F) g; a$ @( }/ R* {8 B
1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
' i5 X( X/ d9 |$ g3 e7 [6 R1520207 CONCEPT_HDL CORE Genview crashes after renaming ports% a1 T+ @* e4 O- m! d
1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic: t( o) d! [( D
1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor7 G4 i5 ^- W5 p' Z% e; H) `
1521871 CONSTRAINT_MGR CONCEPT_HDL Constraint Manager launched from DE-HDL allows space in the name of layer sets
6 U" S& ? F0 q1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.
: J; ?! G* z$ I6 k. D! ]+ ?' b1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP Layout design$ y, k. {- w0 M7 V
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash( } }/ [2 }1 v8 g. r# y
1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated, o$ W/ P/ x5 {" W; T/ t
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine
' `1 e K( d, d; W3 ]1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor
6 M& Y3 e, ~7 M. q1525883 ADW DATABASE Invoking libimport on an existing DB should verify that the 'libimp_su' variable is set correctly
* x' n' H8 v' A8 q- k1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct. a9 h6 f) P# r
1526914 ADW LIBIMPORT Cannot import to new library database* a+ h, e* z: L0 u* c; ~
1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63; M3 u# k, J9 @/ q2 ^' s: o- I% l
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
. x& _0 j: d1 ^' y9 \. O1528235 ADW DBEDITOR Running rule 'Validate Classification Property and Property Values' results in property mismatch error( d1 A/ K' q+ ]) w/ ^6 p
1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes$ i6 E# C; h$ R3 p! |
1528398 ALLEGRO_EDITOR SCHEM_FTB Netlisting of pins with NC property results in error
: V% ^% L- q3 G& J1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design
# n: Y( ` V7 x" b8 T& \1528894 ADW DBEDITOR Lack of PTF_SUBTYPE in the classification prevents the release of the part
8 H" {- [1 B- e9 t5 K7 D1529178 SIG_EXPLORER OTHER When an ECSet is created from a net, values are not transferred correctly for PinPairs
! [- P. i( Y# y; O9 _6 v1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions
) @8 T X: u5 d1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file1 S. G" I: h4 M& H O! ~ {
1530445 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when 'Add Connect' is used
8 H. J) w. N' K2 h( F! ^1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes
' b* I9 ]( W: R1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup6 D2 n+ ]& K& }4 o7 P |5 T. S- a
1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr7 R7 p g" ^$ G# b4 V0 \
1533543 ADW DBEDITOR Component Browser free text search returns 2 parts when only 1 exists& d, a1 ^% ?, O6 u, z9 H' p' J% L
1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue
, z2 b, J. B' t1 O/ |, @! ?0 K0 f1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
. S% C& Z: _( @1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net$ q) S' U- n- L. }7 O- L: d* g* P7 E
1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform
4 A6 o* p/ S( ?) M# Z9 R1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing 'Layout - Renumber Pins', B2 Q- I: J; U) E' ?1 D' c
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
& D/ ?! K4 Z) n1 j1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run' e0 L/ a3 t+ Z& Y% t
1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error% t3 C3 Z# r3 Z3 J0 e
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib
( s ^+ d/ y3 l- M* w1 [( P1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board6 u7 s5 `/ k" r
1542949 ASDA EXPORT_PCB The Export to PCB Layout form: The file name specified in the 'Output Layout File' field is not accepted6 M+ z( \) f6 B
1543537 ASDA NEW_PROJECT While creating new projects, the new folder name is not visible clearly in the explorer) k$ R; i- A5 `, h, w
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
: Z5 V# D* \, e7 B% i. x9 q9 @1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash6 }+ z* M) ?, J9 E# N4 e2 D
1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked
2 n! I- |* k( a6 }. y1544856 ASDA CANVAS_EDIT Edit > Find places the process (UI) behind the SDA tool.+ i* y. O- L. p% Y: I' Z2 C. C
1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with4 M. u" P1 Q2 _
1546062 ADW TDO-SHAREPOINT Failure to launch TDO Dashboard, need to update error message with more useful information
6 i! S% P* i; ]1 l+ ?7 h) r* ]1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'
, H* Q& j% q" f, t( e& C, r1549658 ADW TDA An unmapped network folder in the Team Design Authoring option results in an error9 s/ t' z5 T- T3 L7 G% q" \
1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols
& ?$ i" Z2 Y5 U. @7 z) [5 {# G1551635 CAPTURE TCL_INTERFACE GetSelectedPMItems returns error for design cache objects) @1 X9 a4 d2 s$ i4 `4 d$ a
1553027 ALLEGRO_EDITOR UI_GENERAL PCB Editor canvas stops responding for tasks such as resize and workspace switch
- T9 S; C& x: U8 L1555246 ADW DBEDITOR Part Copy As does not copy AML and reliability model relations.
) o# ]( B/ C0 `$ d, }: m" b1555254 ADW DBEDITOR Text in Free Text search box is removed if it loses focus
# `5 W1 S. J: G7 Q1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon% E5 W( g1 q6 E
1573039 ALLEGRO_EDITOR INTERFACES IDX returns control to the general interface prematurely during an incremental IDX export
: b' n8 X9 Q$ T4 Q6 @/ o8 x9 [4 J) V1580571 ADW DBEDITOR XML files continue to appear in flatlib even after the padstack/footprint models were released' u7 k X. P" M/ m; y) C
1580580 ADW LIBDISTRIBUTION The .lis file contains references to old models even after they were purged.
3 j0 A b- D w6 [ ^1582064 ALLEGRO_EDITOR UI_GENERAL User-defined menus not working in PCB Editor 17.2
; W5 p) G. G: i1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes: p0 U* v, h5 @1 `7 Z3 Q
1582856 PSPICE MODELEDITOR Getting 'ERROR: [S2C3471] Base part library does not exist when Export to Part Library', though olb is created. _, U( F; i' c2 ]/ B! i' a" m
1584719 TDA CORE Caching errors are flagged for a board-ref project during block update7 D* q. r7 b, L
1587045 CAPTURE IMPORT/EXPORT Unable to import PDF file
$ {: {" Y4 m+ ~, G$ L" P; F1 [1587259 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not working correctly for the 'bottom' option5 _6 \( E9 D5 ~! ~8 B, h
1588736 PSPICE MODELEDITOR The Model Import wizard displays 'Invalid configuration' message when a .lib file is opened in Model Editor
5 u. u8 N" Q$ Q8 d1588742 PSPICE PROBE Browse icon is missing from PSpice File - Export - text
5 J4 ]' C+ F) V8 f+ m1590006 ALLEGRO_EDITOR UI_GENERAL PCB Editor 17.2 crashes when multiple browse windows are opened$ L. T4 ?0 `7 f
1590597 PSPICE PROBE Problem with the adaption in the Probe Window icons
& V. B5 l* o9 j/ T1591264 ALLEGRO_EDITOR UI_GENERAL Film order in Visibility View is sorted alphabetically and does not match the manufacturing artwork4 `3 Y' Q! d1 y' ]& j2 O
1592089 PSPICE MODELEDITOR Cannot get the PSpice DMI Model DLL while using PSpice DMI Template Code Generator0 {7 T1 Z+ f( G, w; |$ A6 r
1593436 ADW DBEDITOR Cursor does not automatically move to the model name cell when creating a new model( p& N* c6 C* o9 Z( S: H4 Q
1594076 TDA CORE TDO crashes on concurrent check-ins when one of the blocks was not modified.
0 {; d ~% E0 {- ]9 C3 C( c1595987 ALLEGRO_EDITOR PLACEMENT Subclasses not getting updated in Placement Edit mode
& b/ u5 m2 L1 f- L8 o) ]1596162 ASDA IMPORT_DEHDL_SHE Importing sheets from DE-HDL imports the block as well
9 {1 i5 O4 ^. [+ V) K Y1 E1597000 CONCEPT_HDL INTERFACE_DESIGN Renaming a NetGroup does not work if several segments of the NetGroup trace have the same netnames assigned.0 i! O8 Y& |* S7 ]; P7 @
1597406 ALLEGRO_EDITOR SHAPE Dynamic Shape does not void the traces and voids open areas4 J: \2 Y) ]1 q( ^
1597957 ALLEGRO_EDITOR PLACEMENT Quickplace: placed and unplaced counts not getting updated
+ O. Q2 q8 M8 B1600194 ALLEGRO_EDITOR DRC_CONSTR 'drc update' gives a different DRC count each time the command is given in a multiple-cpu system+ ?# v+ c5 l* n9 [, ?! J
1600800 ALLEGRO_EDITOR GRAPHICS LINUX 17.2 operation of Update DRC is not the same as Windows – graphics not updating
0 y ?3 h: x H, D( \1602605 CONSTRAINT_MGR OTHER OrCAD: constraints not getting saved
! R# p/ t9 r- x7 U* P& Z8 B1602801 SIG_INTEGRITY OTHER Dielectric Warning message when opening SiP tool.
% b* Q# C: D+ U7 d G$ ]1603377 PSPICE ENVIRONMENT Running simulation with the 'At Markers Only' option does not generate the .dat file* k/ {- G& r8 @: V: [
1604166 CONSTRAINT_MGR CONCEPT_HDL Audit ECSets does not work from 'Referenced Electrical CSet' column header8 X/ q/ a( g+ I4 S7 r" r
1604741 ASDA CANVAS_EDIT Tcl console changes the present working directory when you open Project Preferences and close it.
! Y9 d* O9 X3 X- t5 a7 Y1 Y' G0 j1605310 TDA CORE Join Project wizard: Random crashes in the Team Design Authoring option
- s: o O) P* {1606861 CONCEPT_HDL CORE DE-HDL crashes on Linux during the Generate View operation
+ B6 s3 l) e" i5 E, L% `1606917 CONSTRAINT_MGR CONCEPT_HDL Importing tech file in DE-HDL Constraint Manager is creating a duplicate 'DEFAULT' cset4 j$ x6 p. `; ]
1607157 ALLEGRO_EDITOR INTERACTIV Edit - Change allows lines to be copied to Cutout subclass, but that subclass requires closed polygons" J' j+ m2 | L$ m; v# V
1607330 CONCEPT_HDL CORE Variant view schematic PDF corrupted with attach_props set
4 h, _ ?4 }; O; }7 H% E. Y1607568 ALLEGRO_EDITOR NC PCB Editor shows wrong drill legend for Top-to-Top drill
# l7 t+ E; T$ j5 z& s. [. @! C1607986 CONCEPT_HDL SKILL cnGetSetupProjFilePath: The SKILL routine does not deliver the full qualified path and name of the project in 17.25 Q+ \+ P) d) J* d
1608524 SIP_LAYOUT MANUFACTURING The Display Pin Text tool fails in the 16.6.073 version with a parseString error.
8 ]* T# @' A$ L8 S$ E: J5 z1609400 ASDA CANVAS_EDIT The 'Assign Differential Pair' right-click pop-up menu command should be grayed out when a single net is selected
9 [; w4 P# ?# l& }- d6 r0 j8 a3 O1609809 ALLEGRO_EDITOR UI_GENERAL Crash in Allegro PCB Designer version 17.2-2016 on Linux9 D7 U' h$ {% h5 P8 t$ D
1609856 ALLEGRO_EDITOR ARTWORK Embedded paste and soldermask showing up in both top and bottom gerber files.
' i0 X" Z# x& t. u5 f0 k0 ?0 c5 j L1609922 CONCEPT_HDL INFRA Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only
9 d+ S( T' b( `8 A; U" g. d. t1611226 ALLEGRO_EDITOR SYMBOL PCB Editor gives a crash message while saving a flash symbol! S7 k5 a* p k9 {6 u1 K+ h; g
1612108 ALLEGRO_EDITOR OTHER Netlist Import is crashing with the .SAV message.
/ q. [' @6 a g$ w1613123 ALLEGRO_EDITOR SKILL DrillType for Oval Slot should be 'OVAL_SLOT' not 'OVAL SLOT', B4 M" o8 p# o# V% V5 {
1614000 ADW LIBDISTRIBUTION Library distribution (lib_dist) does not complete; lib_dist.lck cannot be deleted when Configuration Manager is running$ U# z* j1 s8 ^# r# U. n
1614667 SIG_INTEGRITY SIMULATION Different results from Probe in Allegro Sigrity SI and SigXplorer* A" t; B) p, T8 y
1615601 GRE IFP_INTERACTIVE Delete Bundle then try to delete plan lines results in fatal error. T! R# J, V! H `; u
1616235 ORBITIO ALLEGRO_SIP_IF oio2sip import does not map layers correctly
/ h9 h9 ?! Y& c l, m- |+ O5 B l$ |1616540 SIP_LAYOUT DRC_CONSTRAINTS Same net DRC Line-to-Line reappearing after dyn shape update! x$ m, A: P* m% j* X. O
1616733 ALLEGRO_EDITOR INTERFACES 'genrad output' no longer working in 17.2. Gives the Error 'extracta process failed. Command terminated' ] a: x& O3 p
1618751 ASDA DRC Zero Node Net errors flagged when DRC checks are run, though RETAIN_ZERONODE_NET is set to 'NO' in Site CPM file
; t [) \, A! N0 O& n3 C1618797 ADW FLOW_MGR Flow Manager cannot execute a specific command in 17.2.
' l) t0 `8 s! q- _, U; m1618930 CONSTRAINT_MGR INTERACTIV Hovering over row column cell causes the application to go into a not responding state.8 U& q$ J) L2 W9 o
1620350 ASDA EDIT_OPERATIONS Pin number is lost on updating the version of a connector pin# w/ i- c$ S3 Z5 M" Z
1621963 ASDA SELECTION_FILTER Selection filter: Pins in the symbol used in connectors are not selected
9 w) ]6 F! U% }/ w+ y. Z1622715 CONCEPT_HDL CONSTRAINT_MGR Extracting an XNet crashes DE-HDL% M# i' X- m1 Y: g5 e( R( v/ M
1625209 ASDA IMPORT_PCB File Import from PCB Editor shows board differences7 Z8 q. K$ u7 Y. Q* e
5 M7 B5 _1 \9 U! b5 u; n \
" ?0 G1 s, ]' T% V' {( i
Fixed CCRs: SPB 17.2 HF003 Z& i- B+ [/ v
07-28-2016
8 x; ]" s3 e$ i6 J$ Y. q* o===================================================================================================================================
X! Q4 x6 X2 @CCRID PRODUCT PRODUCTLEVEL2 TITLE7 A( h" z; {% U! I7 }5 P
===================================================================================================================================2 ?6 a6 m! \& R, [
1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result
9 N( v4 c1 q" ~0 ]2 y6 N/ Z1461626 CONCEPT_HDL CREFER Cross-references shown to the same pin on different block instances though the signal names differ
$ p y( ^% @: _1472456 CONCEPT_HDL CORE The design connectivity (XCON) file and design data are not in sync
# t: w! q7 d) p; I1546151 CONCEPT_HDL CORE Add port, Genview, move pin on block - the pin name disappears
! S8 J5 f1 E: a' d: g9 K; |1547356 ALLEGRO_EDITOR EDIT_ETCH AiDT gives different results in ISR S034 and S066
) {7 C& x5 h( n B5 S6 ]1560102 ADW FLOW_MGR Flow Manager: None of the eval commands working% d# a" `- x' O% }/ m' ]
1570032 ALLEGRO_EDITOR GRAPHICS 3D Viewer shows flat LED for a specific design
, e& g: i) q8 w q; W6 e1574676 ORBITIO ALLEGRO_SIP_IF Updating the OrbitIO database with a modified .sip file gives errors4 Q; y5 E ?& u. w9 N
1578876 ADW ADWSERVER Component Browser crashes when trying to show details of a part number
4 o3 j) Z7 k. g. T1580744 F2B PACKAGERXL Running Export Physical results in error SPCODD-114
& p2 v% m9 ?6 V4 N9 w1582863 CONCEPT_HDL CORE Generate View creates non-existent ports/ P9 }" v x- g$ P
1584317 CONCEPT_HDL CORE Provide an option to open pxl.log from the Design Sync window when packaging does not complete successfully
, [2 S* s" f: D1587018 ADW FLOW_MGR User is prompted to specify the flow name each time the project is updated
+ m* H7 D8 t& E# R+ l* K1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties
* K% H+ D" y2 K0 s/ N* y" P7 Y8 G1587498 CONCEPT_HDL INTERFACE_DESIGN Need the ability to tap individual bus bits1 O3 y7 E* \8 f( E$ E* u
1587718 ADW LIBIMPORT Library Import - The Pre-analyze tool does not report errors
; N5 C J* G4 D- G6 A3 f1588197 ALLEGRO_EDITOR INTERFACES STEP export fails when External copper is selected on Windows 106 ^) X; t- x9 Y5 G. c' [: O9 ]( U9 i
1588786 ALLEGRO_EDITOR OTHER strip_design reports 'Design has been corrupted'" T2 b6 _4 m) D& V) j
1589252 CONCEPT_HDL CORE Search results zoom into the page origin instead of the selected components" S: v) P, t( Z+ \7 @) v9 k/ T6 S1 c
1589318 ALLEGRO_EDITOR DRC_CONSTR Via to SMD Fit DRC reported between embedded pin and via which do not share layers
% e l# v5 j# L. ~: |% `( `! V1 X1589979 ADW FLOW_MGR Design Name change does not reflect in Flow Manager in the same session of a project( l }! l0 ]3 R) w8 M2 v' c; p
1590538 CONCEPT_HDL DOC Open Archive: Some observations on the random behavior i9 r5 K9 N/ Z$ A/ C: N6 L4 ^+ e* V- `
1590639 CONCEPT_HDL OTHER Importing a design in DE-HDL results in a crash
) A* U P" n9 N8 j1 D: x1590651 CONCEPT_HDL INTERFACE_DESIGN DE-HDL: Duplicate NetGroups created in Interface Browser and Constraint Manager; }; Y0 a. W% D- u
1590720 ALLEGRO_EDITOR INTERFACES Exported Text Size Parameter file does not load names into the text table
7 @% }$ A% r5 G! w1 I8 V1591070 PSPICE PROBE PSpice crashes when using the Trace - Measurements - Evaluate command" [) |- W7 c$ a& C( h/ f
1591223 CONCEPT_HDL CORE Variant information for lower-level schematic not displayed
8 s. ?- T$ R) i/ u+ m. x1 t& ]& u1594240 CONCEPT_HDL ARCHIVER Archiver is not able to change the permissions of the cells archived: a# `" k; h1 C, Y; S3 j
1594416 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when you create a new pad
3 x$ C( w* l4 B2 `/ A$ v- o: ]1596615 ADW DBEDITOR Unable to search parts: Component Browser did not launch; Database Editor did not return search results; S2 s; ]8 }: [4 p* {6 k8 i
1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save
' z" w) s. {1 @# X C1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor8 S- o. P$ N; l3 a& \: m) V
1597385 F2B DESIGNVARI Some 16.5 variant DNI parts appear in 16.6 as X-OUT and some without X-OUT or DNI. T4 E$ D/ N4 k
1598629 F2B PACKAGERXL Export Physical crashes after flagging error SPCOPK-1458
. C0 }( d K* R% B% V1599452 ALLEGRO_EDITOR ARTWORK Import Artwork with Mirror option does not import pins or shapes6 b( S4 T' T, M* C( y) A
1599744 ADW FLOW_MGR Flow Manager: Commands associated with some of the buttons not working
; I" q" {5 H/ s' H+ z1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.( ~" I0 S4 H* F+ ^5 W
1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group) g% ?% B! {: H0 _' Z" X0 a) E. k. W
1600618 ALLEGRO_EDITOR DRC_CONSTR Casing of property names is affecting results when working with Physical Constraint Set5 P9 W2 ~/ J8 v" ^% n
1600914 ALLEGRO_EDITOR INTERFACES Exported PDF has unfilled shapes despite enabling the 'Filled Shapes' option
7 t; z. I1 `. M) P5 s0 F1601165 ALLEGRO_EDITOR DATABASE Thermal Relief is not added for Rounded Rectangle pad
" v6 ]* h6 |( Q- c9 V1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol
Y: j( A y6 |: G$ o R9 a1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name.6 g0 d7 }$ ^3 z0 _5 }
1602514 PCB_LIBRARIAN METADATA References to some primitives missing in block metadata;TDA errors reported for missing parts after joining a project
. V0 h5 U* D' c8 D0 `' }1602823 SIP_LAYOUT WIREBOND SiP crashes when using the Add Wire command
1 S" b7 [6 y& H3 ^! I! Z1602955 ALLEGRO_EDITOR SHAPE Shape to Route Keepout DRC not reported for attached database' y" R. G# q& z! r1 _: W
1604223 CONCEPT_HDL CORE Tool stops responding after error SPCOCD-553: Connectivity Server Error
& W: d* C7 W" X1604746 ALLEGRO_EDITOR OTHER In 17.2, layer data is getting changed when importing extracta files into other thirty-party extraction tools( o% g# i% e7 ~* S8 R8 M9 d
1605322 ALLEGRO_EDITOR TECHFILE Generating tech file in 17.2 takes much longer as compared to 16.6
5 s$ R/ S( n" _' u$ {
# C6 \2 B6 b2 ^1 p* ~: l* L3 K6 ?! K- h) A
Fixed CCRs: SPB 17.2 HF002( [2 c7 s) n6 Q, J9 v* L
06-31-2016; \( Q) a5 S. T6 D+ W! {! ]
===================================================================================================================================
7 A; O- p1 p' d4 N7 i4 w4 L3 mCCRID PRODUCT PRODUCTLEVEL2 TITLE
- V% l, g R0 b===================================================================================================================================
4 s1 ?* f2 h2 N9 Z) C P1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets
0 U5 c& U' j% n0 b( b' a4 w1469146 ADW LRM Packaging error reported after updating the design using LRM
. ]+ {: O, x B$ W0 r! Q! p1481802 ORBITIO ALLEGRO_SIP_IF Import of an OrbitIO file to an existing SiP file offsets the results incorrectly `8 h( {8 Z; M' \( N
1518957 APD SHAPE Shape void result incorrect
% h7 l: B. X$ n6 R4 u1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error
7 d" ~3 ?! O2 d4 `# `1524947 SIG_INTEGRITY SIGNOISE Custom Stimulus is not recognized correctly in Allegro Sigrity SI or PCB SI.
8 p6 u# J: D6 S- ]+ ~+ F1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.
5 A% Q2 E$ h5 e8 ]: Z1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in the attached design.' N' d. O" Y( P; H' T. U( y
1544675 ALLEGRO_EDITOR OTHER Export Libraries corrupts symbols if paths do not include the current directory (.)
7 z+ w) a* H* N" R) u1549097 CONSTRAINT_MGR XNET_DIFFPAIR Show warning message if differential pairs are created for nets with voltage properties
4 Q6 q0 g/ j3 H& S, h. }' M1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None'+ q7 F' G2 z3 Y( j
1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library
4 [0 g( W( z3 y! y$ J8 d+ _1555009 CONCEPT_HDL INTERFACE_DESIGN Unable to rename a NetGroup.& P* r) |/ X8 E8 Y; K
1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets# U7 t7 r% O, R9 F$ F
1559552 SIP_LAYOUT ORBITIO_IF device offset in oio2sip translation
N- m* v/ P2 b! _" d1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
5 `, s, @( I/ v$ \1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
2 S' C$ ~& y0 k1 b$ i# | N" V8 [1561501 ORBITIO OTHER OrbitIO stops responding when refreshing a design in SiP Layout
}2 Z- K% \ r1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC- v, o+ i0 Q7 [
1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins6 r( z+ k6 `8 ?8 k
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas
8 y6 M9 N. Y5 n+ x1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions
. k6 r1 B/ k, f1 q( @% [$ N1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete4 P2 n; f. m. |- C% E { J
1566942 ASDA MISCELLANEOUS Several extra files in the /tmp/ folder on Linux3 ]) S/ ?4 N* R
1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.6 ?/ r2 w8 F' `, Z; E% W+ t+ T$ {: V
1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct
0 z6 R3 w- |, E0 t, J+ {1569056 CONCEPT_HDL CORE Opening the same drawing in multiple cascading windows view displays non-existent artifacts. z4 r) n* X) X
1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'
# w' k2 @, m# n1 t1569147 CONCEPT_HDL CORE The signal name auto-complete drop-down list is not displayed correctly
& T5 W3 f+ @* f# s/ ^/ P* i2 O9 u1569394 ALLEGRO_EDITOR SKILL axlPadSuppressSet( 'on 1 '(via)) not working on SPB17.2, k7 x r6 G5 C; R2 l7 G$ O
1569924 CONCEPT_HDL CHECKPLUS Checking in a large BGA into ADW results in an error related to negative signals
$ V. {5 W: w d- U; e8 Q! u1570398 SIP_LAYOUT DATABASE Diestack layers cannot be deleted if there are unplaced symbols in the design$ \7 `' |$ C8 S4 u
1570419 CONSTRAINT_MGR CONCEPT_HDL Need to add a customized worksheet custom property weblink in Constraint Manager
8 D0 m- q& @- ]; B1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short; n( b8 A, i% B1 T1 B/ U8 e
1570678 F2B DESIGNVARI Variant Editor: Error when adding an RSTATE property' U. {5 e. B X
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only3 }) T; T$ h1 `! `7 \
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display6 ~: N- d0 R# N4 N; A
1573127 CONCEPT_HDL COPY_PROJECT The CopyProject functionality creates an incorrect 'view_pcb' directive value9 m ~/ M7 N, ^. }- ~: X
1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)
$ j1 d0 v' E# I( e1 Y6 ]1573625 CAPTURE PROJECT_MANAGER Toolbar customization is reset when Capture is re-invoked in SPB 17.21 E, _( v6 _6 d% }" w* n9 k
1573755 ALLEGRO_EDITOR CROSS_SECTION Changing a layer's type is also changing its material in Cross Section Editor& F) K ]' S! S) \9 \* O, J
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the project CPM.arch file
7 ^, h4 |2 ~) z1574381 CONCEPT_HDL OTHER Packager crashes on repackaging a design with RefDes related advanced settings# I: Y/ z$ C/ [2 O5 C
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'! G% C* V! p# j+ E
1577381 CONCEPT_HDL CORE ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure8 Q. ^6 b2 |0 P: y/ X, r8 V* N+ f, P
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files* V" \* Y% e, }+ e
1580891 SCM REPORTS Dsreportgen crashes in different scenarios2 L) }+ ?& j8 U% e. |& }
1581254 SIP_LAYOUT CROSS_SECTION Cross Section Editor crashes when adding a layer, \/ B, y+ \% S* e; c( m8 x1 f A$ o
1584957 ADW FLOW_MGR 17.2 Flow Manager, JavaScript - Tool Launch Error% v' _1 a9 t/ I
1588823 ADW FLOW_MGR Flow Manager: In 17.2, using back slashes in the UNC path results in problems in working with the tool
, W! K0 P6 w: D) p2 r9 ~: e1590064 ADW LRM Allegro EDM Flow Manager - An empty LRM dialog opens on design load in 17.2$ f1 Y0 R! d& z" `) V4 G
2 j" W4 t! r y
* K, t. Y9 @$ `$ vFixed CCRs: SPB 17.2 HF001
" e# f' J- g6 T. ?2 g8 R! V05-06-20163 D8 k' \- G1 v( N4 Z
===================================================================================================================================
[" L* S8 W( j+ L0 v" ?CCRID PRODUCT PRODUCTLEVEL2 TITLE
. {, G# d& G& n2 k. f8 y===================================================================================================================================3 y, y2 c, }6 ?. H+ o% G
1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output
5 v' ~, M" y4 G8 G1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group
. }) h+ w" `: }! g4 d* _! e7 K1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
' p0 W4 w- {5 {( u8 q7 e4 j1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail
4 X$ D& t) ~/ h. S: w1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
+ L7 `' w1 K, o( `# U3 S# X4 I1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
8 R( |5 |( k k1 k) h3 ]! G \) f1506672 ALLEGRO_EDITOR INTERACTIV In the attached board file, when using Replicate Place, some shapes are missing from some layers
( u* P" w) }3 a1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager
! s7 M& h# H5 s2 {1523532 F2B PACKAGERXL Adding subdesign names in the 'Use subdesign' or 'Force subdesign' sections hangs for more than a minute
9 C& G- H9 B9 u& C; u8 {5 d! U1525783 CONCEPT_HDL CORE '\BASE' scope does not work for SYNONYMed global signals g: F! K! d' T) |3 j6 n' B
1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash in the interactive and batch modes) {) e ~" S5 V6 ]# X% ~0 S
1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork/ g" m# K! X8 H
1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed% `0 V/ @- {$ }
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.
7 s& B( b% B8 ?, I) [! K1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
1 J/ z3 ^) j% A- U1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols u- j/ {) T! d; d0 p5 W- T' l- z
1543410 ADW LRM LRM shows confusing part status; reports that update is needed but clicking update does not work
( a M" u" L, a2 p5 A6 q1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file1 Y8 k; v/ G- w1 n: q3 Y
1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design6 k$ q h9 ~# I* f$ B
1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license
& N+ @8 ^ m! V- f' s4 K1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork5 K1 a* V! O& ?4 U
1546877 CONCEPT_HDL CORE Align Left on wires fails with incorrect error message
* j' ^8 c+ h8 D8 |% i1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system
$ p2 ~0 {. h K1 ]7 l6 D M1547584 SIP_LAYOUT OTHER SiP - Design Variant: Delete embedded layer if not selected
: _# X' {$ z6 @/ Y3 N+ b1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol
d* w0 ^' d+ v+ M8 l% t1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file; c( W* \ b/ B$ X: z# R f) u) u4 W( r
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report. \& b0 Q2 q2 r) I+ x
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines
# T4 d4 I3 j- W9 {3 Z# t+ b, @1549662 ALLEGRO_EDITOR OTHER Import Parameters Path fails if parampath does not have the current directory (.) set
: j: h- P! C; _" o# ]9 l' k1549836 CONCEPT_HDL CORE Tools - Customize - Keys - Reset does not reset keyboard shortcuts6 c5 f b3 `2 u0 `
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems
/ Z" B1 a9 r% I% p1551713 ALLEGRO_EDITOR DRC_CONSTR Hole to Hole DRC between via and pin not shown1 k7 `1 W! o4 o9 c% R3 H0 H
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl(pixel2UserUnits) crashes PCB Editor
% \9 C" v4 l m1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to NetGroups
- c: U5 ]& I' v* ]- e1555092 SIP_LAYOUT DEGASSING Degas offset is not working with hexagons1 P" U0 O) j2 L& ]% i2 |7 m0 f
1556261 ALLEGRO_EDITOR DATABASE DBDoctor crashes with the error 'Illegal database pointer encountered, Exiting DBDOCTOR.'0 K6 M$ A# H0 {
1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted
8 K0 H0 I" S1 H# l0 Z1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor - Refresh co-design die0 c* r$ C- E9 p- J. K: F
1560197 CONCEPT_HDL CORE BOM-HDL adds extra characters to subdesign_suffix when generating hierarchical BOM
! z. ~: \% D- Q. ~1561077 ALLEGRO_EDITOR INTERFACES Beta - IDX User Layer export fails on Linux
5 A! O7 K# v# _7 H2 s3 o, M1562537 ALLEGRO_EDITOR MENTOR Using mbs2brd in 16.6 gives a fatal error
" _6 A9 N7 G4 f! u" s1564203 ALLEGRO_EDITOR ARTWORK Cannot generate negative artwork# o5 \( a' U; ^" P6 n6 [: Z
|
|
发表于 2019-11-5 13:54
楼主