TA的每日心情 | 开心
2021-4-22 15:40 |
|---|
签到天数: 73 天 [LV.6]常住居民II
|
2#
楼主 |
发表于 2019-11-28 16:45
|
只看该作者
我感觉Mentor的这种原理图检查工具功能挺强的,只是它的数据库是联网的,对我这样小公司的人来说是不太可能的.难道大家都没有想用工具去检查原理图?人很容易形成定势思维,对错误视而不见.下面是Mentor的Valydate的介绍
8 l/ I9 t* w ~$ o, U6 K+ P: O# T9 I5 v3 @: a
Pin voltage parametric verification for maximum, minimum, and logic thresholds
; M3 ]9 X0 z: xBus flip errors (MSB to LSB, TX and RX errors)2 p" b8 A8 h9 D; L) N' H
Full multi-board and backplane interface verification
0 r" C8 I4 \* c6 x1 ePin function compatibility tests3 E) W1 @' ^4 K* \3 j
Symbol mismatch (to datasheet)* |- ]7 X# C6 M1 u4 a3 q
Driver/receiver technology matching8 J, {: x! G7 o8 s
Diode orientation verification9 E. o# b: W7 l% |; L4 P
Driver/receiver function matching
5 y$ Y% ^/ k. W( u CPower/ground/open collector/drain shorts
^% s3 K" h( c# z: ]! i2 aCapacitor decoupling sufficiency checks1 g8 p* _9 n5 v, ]6 z
Capacitor voltage derating (to user derating rules)4 f8 |# I, g6 w! j( @4 B
Redundant resistors (on a net detection)
0 b/ g1 W5 r/ s( f: W) n' _2 ~5 r6 I* u V% r. |, Z/ Q
Open collector/drain verification
: ]7 B& \; I$ V8 g/ SPoor design practice checks (e.g. using pull-ups, pull downs when needed...)
: L- J$ A, i' I+ S6 W. ^Power/ground plane connection verification; X( a4 v% Z2 W3 _( n
Component power checks0 L3 K3 O0 n) z# \
Multiple or missing power supplies (on a net)1 _4 l. g5 H8 Y" J5 A6 _
Differential pin verification
/ g" {" F& }6 x2 S$ }( r m& H, A2 oUnconnected nets or bus detection/ N% |/ U0 F3 T7 Z
Off-board nets detection
; t/ z0 C R0 J) _! J3 b: C- V( MOverloaded pins identification! D" s/ O3 K n. N8 S
Unconnected mandatory pins identification
) r9 D5 K! f2 w- o! \Nets missing driver* P( D) Q# Q6 z$ _
Nets missing receiver |
|
/1 
发表于 2019-11-28 09:46
收藏
淘帖
支持！
反对！