求救—谁能帮忙改一改

zhong0985

library ieee;
4 |( u. \1 G8 m8 B$ nuse ieee.std_logic_1164.all;
+ ^$ x$ W1 r5 m, v2 t$ |3 D/ i2 O( wuse ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity hour is
port(clk_h,clk_t,tp_h,res_h:in std_logic;
3 t  ]5 b1 u( S6 |$ a. B% F$ A# q' R  hset:in std_logic;
/ _' S. W! h3 O, z6 U) Q  sig_h:in std_logic_vector(2 downto 0);
* J5 l3 Q. \0 ]2 P5 C  din_h1ut std_logic_vector(3 downto 0);
  din_h0ut std_logic_vector(3 downto 0);
) A9 ]. X3 _/ g& F  pmut std_logic;
, B: K: D: c1 K9 V) O( Q  cp_h:out std_logic);
  
end hour;
1 ?" o3 V' f8 w8 _+ I, _4 rarchitecture behav of hour is
1 k5 a: @( e/ Q9 P. f, V2 msignal clk:std_logic;
/ g( y- ]- m, s: [# Cbegin
    process(clk_h,clk_t,tp_h,sig_h,res_h,hset)
. p% N" t2 h3 O* v5 a$ ^     variable cq1,cq2,cq3,cq4:std_logic_vector(3 downto 0);
5 Y7 ~& l5 {( W1 U6 @     variable co1:std_logic;
     variable co2: std_logic_vector(7 downto 0) ;
6 C1 v9 \0 g: S& c+ N& I1 x9 S$ S. r   begin
    if sig_h="001"and tp_h='1' then clk<=clk_t;
' m. v% i0 y" c( w% P   else clk<=clk_h;
   end if;
0 X2 r8 ~; k) r- R. G! L# z5 {    if res_h='1' then cq1:="0000";cq2:="0000";cq3:="0000";cq4:="0000";co2:= (OTHERS =>'0');
" y1 M8 S; C7 P# R- [; k, E       elsif  clk'event and clk='0' then cq1:=cq1+1; cq3:=cq3+1;
/ C" s9 t5 Z- \      if cq1="1010" then cq2:=cq2+1;cq1:="0000";
& S. K! q6 X# M' H% x$ o            end if;
7 ^8 W! h7 B& |; @& V0 z            if  cq2="0010" and cq1="0100" then
& [  ?  e5 Y, C5 M    cq1:="0000";cq2:="0000";
1 O: B7 l# Q" G2 S& R    co1:='1';
   else co1:='0';
! e5 K0 k+ v+ W" d      end if;
      if cq3="1010" then
      cq4:=cq4+1;
+ A2 n0 a+ E# Z9 ~1 |: R5 _) U2 r      cq3:="0000";
6 d) o) d: p! c4 Y6 |9 \    end if;
4 N2 C- L. y2 v. {7 J   if cq4="0001" and cq3="0010" then
         cq3:="0000";cq4:="0000";co2:=co2+1;
      end if;
6 `& q6 k4 m* J$ H# D2 T; M' f    end if;
7 C  h* f3 W; d+ s( a  if hset='1' then   
          din_h1<=cq2;din_h0<=cq1;cp_h<=co1;
3 q* ?( y3 ?0 _" n% B         else
" L5 S* m3 x9 p4 d           if co2(0)='1' then
             if cq3="0000" and cq4="0000" then cq3:="0010";cq4:="0001";pm<='0';
- `6 x" c0 H( c. n3 u9 B& ?2 E$ [- i             end if;
             pm<='1';
            else pm<='0';
            end if;
            if co2(0)='0' and cq3="0000" and cq4="0000" then cp_h<='1';
  W/ b) m, ?9 g% p8 O7 l              else cp_h<='0';
             end if;
9 X% b4 ?  Z# X3 B           din_h1<=cq4;din_h0<=cq3;  
" B: ?5 i9 w6 y  b2 n        end if;  --12/24转换
  
( i5 F% |2 v2 D6 ]" P     end process;
end behav;

zhong0985

报错：
Info: *******************************************************************
  Z5 b6 N/ N; s! i! `Info: Running Quartus II Analysis & Synthesis
        Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
) G( p' x1 q2 m- {# F( e        Info: Processing started: Sat Oct 31 17:04:02 2009
8 W7 C% ~5 G* o  Y0 [8 d  f1 IInfo: Command: quartus_map --read_settings_files=on --write_settings_files=off hour -c hour
Info: Found 2 design units, including 1 entities, in source file hour.vhd
        Info: Found design unit 1: hour-behav
        Info: Found entity 1: hour
Info: Elaborating entity "hour" for the top level hierarchy
5 E" O4 F+ J$ A7 p6 H% [Warning (10492): VHDL Process Statement warning at hour.vhd(29): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at hour.vhd(20): inferring latch(es) for signal or variable "pm", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "pm" at hour.vhd(20)
  J# k1 u' r1 W! x* VError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[0]" because its behavior does not match any supported register model
( d8 _9 r' H' r8 q& F5 P7 l- kError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[1]" because its behavior does not match any supported register model
) q, X3 |* [4 O. V; V8 MError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[2]" because its behavior does not match any supported register model
; r) s* L7 w6 k0 \7 QError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[3]" because its behavior does not match any supported register model
( @- h  O1 I7 c0 t- Z! KError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[0]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[1]" because its behavior does not match any supported register model
3 u4 P4 x- D, U) J# p( zError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[2]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[3]" because its behavior does not match any supported register model
' Y* N; S. e7 {Error: Can't elaborate top-level user hierarchy
3 ?  z6 r: `' R5 a6 RError: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 2 warnings
        Error: Peak virtual memory: 184 megabytes
        Error: Processing ended: Sat Oct 31 17:04:04 2009
/ I2 R8 C  O% \% P* C- d* v- S        Error: Elapsed time: 00:00:02
        Error: Total CPU time (on all processors): 00:00:01
' t0 ?  X$ w1 w8 g; y/ l# P0 n* r" SError: Quartus II Full Compilation was unsuccessful. 11 errors, 2 warnings