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Cadence OrCAD and Allegro 17.4-2019 QIR1

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发表于 2020-6-8 02:00 | 只看该作者 |只看大图 回帖奖励 |倒序浏览 |阅读模式

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本帖最后由 金志峰 于 2020-6-8 03:33 编辑 ; L) X. E0 d: r; W
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cadence orcad and allegro 17.4-2019 QIR1新特性 3 b6 V) J% p  \- \0 A9 k- e  B* [
·焕然一新的图标及UI4 \  y+ k5 y2 Z2 f

" j. s) g! E1 L8 RQIR1中全新启动界面 (点击图片放大)( \$ i" g2 F" T0 A( z

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$ `7 O  k; f5 Q5 L) SQIR1中全新启动界面(点击图片放大)( s0 g( @. x- d  Q% n
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0 n1 ]! U+ P( T, c* ^! EQIR1中capture官方Dark主题(点击图片放大)(QIR1中UI界面中所有图标也全部更换全新并统一了)
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8 O" Q- W2 y8 k! q- }: VQIR1中capture官方Light主题(点击图片放大)/ ]1 Q1 h0 x7 Q6 r
(QIR1中UI界面中所有图标也全部更换全新并统一了)
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) y' s/ h9 @, l) f$ y: KQIR1中PCB Editor新增官方Dark主题(点击图片放大)% T% \3 I: B: b8 W
(QIR1中UI界面中所有图标也全部更换全新并统一了)  y& d$ X8 r$ \7 G/ @% h& I

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1 h3 V7 f" G( y6 xQIR1中PCB Editor官方Light主题(点击图片放大)4 n8 _2 ^/ ~  e; X8 l
(QIR1中UI界面中所有图标也全部更换全新并统一了)2 h* y# j7 E1 C2 ^, C- H: `* j
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Fixed CCRs: SPB 17.4 HF007( U1 u0 `) I5 e- k1 R# d
05-21-2020
% D- U+ c- X' V! P========================================================================================================================================================
9 J' G* r6 ~( k1 j2 L7 C9 i& `CCRID   Product            ProductLevel2 Title
3 O3 I9 n5 U1 X1 B- h3 _  @% `; l4 ~========================================================================================================================================================4 ?! k; d( `$ n% H1 A
2247686 ADW                CORE          Allegro EDM: Unable to create a project using a newly created flow; i7 ^) d) T# P" v8 e
2137594 ADW                DBADMIN       EDM is not allowing changes to STEP models
: ^/ {' e0 q" E7 B2135452 ADW                DBEDITOR      DBEditor poor peRFormance in high-latency networks: u$ S$ h& E1 o
2113265 ADW                LIBDISTRIBUTI Various database operations take a long time; rebooting server seems to fix the problem
  P+ o& m  s; [2122941 ADW                LIBDISTRIBUTI Lib_dist execution taking a long time to run; Capture CIS DBC file appears to be taking the most time
  B, L$ i, [  \) P- s9 {& w2 g2127319 ADW                LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250)5 F4 l( |" v' j4 o% f- ?, t
1975317 ADW                PART_BROWSER  Space at the end of the line in CDS.LIB results in zero libraries being shown in System Capture library search
# f# M6 e/ Q* t! z0 Z& m) D" C2078057 ADW                PART_BROWSER  Symbol Graphics preview is not available in Designer Servers
5 B6 V' ]( {1 O2092863 ADW                PART_BROWSER  System Capture library search is not displaying the symbol and footprint preview
) U1 U4 w5 ]5 {% n" P2086463 ADW                PART_MANAGER  System Capture cannot add components when accessing remote machine via Citrix2 _  I" f5 z% I6 K
2092868 ADW                PART_MANAGER  Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not flow from pstchip; [% K  g3 u' k7 X5 V; l
2092872 ADW                PART_MANAGER  System Capture stops responding when importing from DE-HDL6 _# ]8 q4 x% ^& j
2113226 ADW                PART_MANAGER  System Capture stops responding while importing DE-HDL sheets
! b0 m% i( g$ }# r- o2212406 ADW                PART_MANAGER  Allegro System Capture: Part Manager is deleting properties from all instances upon Update
0 W1 R. t" D+ \& D) W6 ^2025147 ADW                TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name/ G$ t* O0 ?1 R! Q/ s1 J
2025201 ADW                TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to Team Design
$ x7 ^' {! t% B2056694 ADW                TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object, i7 ?) q$ V6 f  g" C6 Y
2048086 ALLEGRO_EDITOR     3D_CANVAS     Wire bonds are not linked to die pad when component is embedded body down4 ~8 q0 z2 F! s' J* L- t
2051277 ALLEGRO_EDITOR     3D_CANVAS     Vias are offset from board in Z direction in 3D Canvas  \) ~2 m- E1 }/ U# f; u6 r
2054243 ALLEGRO_EDITOR     3D_CANVAS     Plating is not shown on stacked vias in 3D canvas# L' P' }3 t/ G; p
2054327 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation, }- [5 n* v' ?
2079732 ALLEGRO_EDITOR     3D_CANVAS     Enhance 3D Canvas to merge the lines segment and overlapping lines and shapes. U6 P; ^6 i6 @, Q+ ?
2206045 ALLEGRO_EDITOR     ARTWORK       Artwork Control Form fails to create film if Film record has a period (.) in the title9 L+ |. b6 r- ~- S6 l4 L
2209200 ALLEGRO_EDITOR     ARTWORK       PCB Editor stops responding on rebuilding apertures without rotation
/ w6 K, W/ `, k$ @. S$ w6 O2244407 ALLEGRO_EDITOR     ARTWORK       Automatic editing apertures with rotation takes time in the General Parameters tab of Artwork Control Form
8 h, a$ ~$ u; D  X3 O- @2267942 ALLEGRO_EDITOR     ARTWORK       Allegro PCB Editor stops responding when generating apertures in HotFix 006' T) `8 @" P0 K
567342  ALLEGRO_EDITOR     COLOR         Add option under View menu for 'load color view'
4 V& G1 O; K9 F3 j4 J637828  ALLEGRO_EDITOR     COLOR         Line highlights in 'shape select' command
$ M5 q. F! J5 s/ A720274  ALLEGRO_EDITOR     COLOR         Add menu option for the 'colorview load' command
" D% }3 u- d+ t* W  r1602652 ALLEGRO_EDITOR     COLOR         Color/Visibility behavior variation using "Enable Layer Select Mode"
' r) N- J+ q/ g) r; E6 b: j/ C3 w& T5 Q2072695 ALLEGRO_EDITOR     COLOR         Clines of colored nets not colored when 'display_nohighlight_priority' is set- q' [+ d8 s2 K6 ?; j1 I
2207580 ALLEGRO_EDITOR     COLOR         Component color is inconsistent when display_nocolor_dynamics is set.
: N4 n! @2 z/ T( [+ p4 {2056497 ALLEGRO_EDITOR     DATABASE      Place manual is slow
. I8 m% v+ k/ H" {2250988 ALLEGRO_EDITOR     DATABASE      Inner Layer keep out as illegal subclasses: Shape object may not exist on layer ROUTE KEEPOUT/INNER_SIGNAL_LAYERS
$ `$ _# |3 d" v' I6 B% M2096958 ALLEGRO_EDITOR     DFA           Cannot launch Constraint Manager after assigning CSet and closing
) B/ X1 A3 ]0 y- p# {2049681 ALLEGRO_EDITOR     DFM           DFF check for plating in via should not flag DRC for surface mount testpoint Via4 H  L# I1 o; S
2155060 ALLEGRO_EDITOR     DFM           Inconsistent behavior in displaying DRCs for Via to Via spacing
- Y5 v* x. q  B2166431 ALLEGRO_EDITOR     DFM           DesignTrue annular ring thru pin pad to mask checks compared to smd pin to mask checks are inconsistent in behavior, J  W- I! L8 K/ W8 t
2221975 ALLEGRO_EDITOR     DFM           DFM missing mask check reporting mask is missing when pins have a mask geometry overlaying them.
2 r" f: V: _9 U3 G, I2249498 ALLEGRO_EDITOR     DRAFTING      When a Symbol with a Dimension is placed on the board, an extra Dimension is added to the Symbol origin.
8 ^0 s! z# f0 \% i2 ^2250631 ALLEGRO_EDITOR     DRC_CONSTR    Cannot import netlist into design due to illegal DRC element: no DBDoctor error& J- Z5 w" K' Y/ J6 ^& |, T6 c
1794593 ALLEGRO_EDITOR     EDIT_ETCH     Unable to deselect return path vias selected when creating High-speed via structures, o" {" F3 z- u: `& `
2099538 ALLEGRO_EDITOR     EDIT_ETCH     Gloss - Via Eliminate shifts traces to another layer
* c; T' J  w4 ^9 u0 |7 A2204339 ALLEGRO_EDITOR     EDIT_ETCH     Differential pair line lost during slide operation
% n5 F& o, z2 w6 s  l7 n* ]- D2208938 ALLEGRO_EDITOR     EDIT_ETCH     Slide operation makes one of the differential pair cline invisible
1 g1 m4 ?7 U+ h8 i, b" k; u( o2222047 ALLEGRO_EDITOR     EDIT_ETCH     One of the traces disappear when sliding a differential pair in single trace mode
( w6 R- M$ h7 B& `. ~) o: l2233991 ALLEGRO_EDITOR     EDIT_ETCH     One cline of a differential pair disappears temporarily upon sliding the Differential Pair in Single Trace Mode. ^, x1 H' v- b0 T
2240827 ALLEGRO_EDITOR     EDIT_ETCH     Cline of a Differential pair net disappears after sliding the other net of the Differential pair9 W3 u( c6 g* ?6 Z5 F" }. {+ K+ R
2245775 ALLEGRO_EDITOR     EDIT_ETCH     Differential pair slide in single trace mode removes other trace! _) h  M; H' R& g
1813358 ALLEGRO_EDITOR     GRAPHICS      Allegro PCB Editor enables shape boundary when disabling etch layer in Visibility pane
; Z. p7 ]- L$ A9 l' {% p; M1911613 ALLEGRO_EDITOR     GRAPHICS      The subclass for boundary class stays on, even if Subclass for Etch Class is turned off from Visibility tab
1 _( g% C0 K4 x' J4 |1966343 ALLEGRO_EDITOR     GRAPHICS      Shape boundary remains enabled even after turning off the etch layer visibility6 }' p7 O9 h+ f$ K: b$ i2 ?  Z
2195276 ALLEGRO_EDITOR     GRAPHICS      Selecting File view is slow5 z2 J) e! T' z+ `" g( d: C
2031883 ALLEGRO_EDITOR     INTERACTIV    Sub-Drawing: Clipboard origin point is not set correctly
  Q& z# g) ]' y( o0 P) g2050177 ALLEGRO_EDITOR     INTERACTIV    Letters need to remain aligned and uniform after performing Shape ANDNOT operation& P0 s8 a3 ]( p8 t1 X  {. m7 E
2069247 ALLEGRO_EDITOR     INTERACTIV    DFA bubble on wrong layer after mirroring the part
5 P7 [9 p5 v5 E/ K# T2103711 ALLEGRO_EDITOR     INTERACTIV    Placement edit mode popup 'Rotate' leaves ghost image in the background
, n& B& [% o9 h7 B) Q6 W6 T( h2136859 ALLEGRO_EDITOR     INTERACTIV    DFA Problem if we mirror component while placing
1 y/ d# B& y+ r- y# P7 G0 ?# o( i5 f2165027 ALLEGRO_EDITOR     INTERACTIV    Different behavior in OrCAD Capture when using crossprobe to select Power nets
( m" E6 w2 [6 F2240235 ALLEGRO_EDITOR     INTERACTIV    The design file name changes automatically to board template name while creating new board (wizard).
: F6 t0 _! ]4 o+ I7 G6 }! Z2244765 ALLEGRO_EDITOR     INTERACTIV    License 4150+226 does not have AiDT/AiPT in release 17.2-2016
( ~. b% z4 G$ W5 Z6 b- m" p2259800 ALLEGRO_EDITOR     INTERACTIV    DFA DRC circle not shown on the layer of placement in Placement App Mode
/ Z' v) x$ U9 ^" b9 Q# @2120420 ALLEGRO_EDITOR     INTERFACES    Drill figures missing in the exported PDF if drill legend deleted( L  B2 I& w1 m6 F" n' `1 e
2136454 ALLEGRO_EDITOR     INTERFACES    Export - PDF output is not correct
1 V# y! `8 F8 E4 N2116748 ALLEGRO_EDITOR     IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets) e8 A; K$ [* B% @' ~: {# ?
2138977 ALLEGRO_EDITOR     IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to 17.2-2016, HotFix 057
+ Q1 T, s& A1 u# f$ ]5 z7 m& n2247167 ALLEGRO_EDITOR     IN_DESIGN_ANA IDA Impedance Analysis: Add an option to export CSV automatically
% h" W( {  d& ^, J1 x7 d0 j2222638 ALLEGRO_EDITOR     IPC           Documentation Editor crashes with error: Failed to complete the job because of unspecified error
% k4 b: A( W1 I& y3 a* w2106425 ALLEGRO_EDITOR     NC            Disable undersize regular pad and oversize soldermask pad for start layers in Backdrill Setup and Analysis
: t0 q' z. D% N: i8 x% U2091932 ALLEGRO_EDITOR     OTHER         Unsupported Prototypes command missing for the OrCAD licenses
6 A0 K! R$ [+ H! }: K' C2221345 ALLEGRO_EDITOR     OTHER         Speed up Allegro PCB Editor startup by removing check for defunct PCB/Package co-design capability (NG_450)/ a- }% l) L. b9 E
2257934 ALLEGRO_EDITOR     PLACEMENT     Error (SPMHGE-626) on place component: Symbol not valid on any layer
) @9 i0 @( Q& K  R1001000 ALLEGRO_EDITOR     PLOTTING      File - Plot in PCB Editor does not plot more than one copy
- |1 I# F8 z. Y2 d0 i) u3 T2234538 ALLEGRO_EDITOR     REPORTS       Allow Unused Blind/Buried Via report to run as Batch Process through the reports batch command
0 J! m$ J+ H, G, I2222738 ALLEGRO_EDITOR     SCHEM_FTB     Netrev not completing, showing error for electrical constraints data (pstcmdb.dat) import
* W9 x& r) C3 ?, r% ?2255426 ALLEGRO_EDITOR     SCHEM_FTB     Netrev is running for hours without closing3 [. }6 D+ S0 Q- R7 g
1702190 ALLEGRO_EDITOR     SCRIPTS       Allegro PCB Editor script file: Some sub-classes not created and error for form field label7 V8 x( y5 r% F0 U. d( S/ [
1791099 ALLEGRO_EDITOR     SCRIPTS       Allegro PCB Editor does not terminate when the script is run with '-nographic'+ J" |1 x9 ]+ Y! F5 C
1791267 ALLEGRO_EDITOR     SCRIPTS       Allegro PCB Editor script does not run with '-nograph' in release 17.2-2016) {1 |/ V" t" M4 @9 Z0 R6 b& ?
1892520 ALLEGRO_EDITOR     SCRIPTS       Allegro PCB Editor stops responding for script when run with '-nographic'' [6 T8 u- }% R7 |3 |
1962010 ALLEGRO_EDITOR     SCRIPTS       Allegro PCB Editor stops responding for script when run with -nongraph option& J" k1 x! J8 K# Z% |
2056857 ALLEGRO_EDITOR     SHAPE         Shape boundary error by shape parameter
' ]: E& |* j9 R' U5 W* y: G2081946 ALLEGRO_EDITOR     SHAPE         Shape Update takes twice the time in release 17.2-2016, HotFix 053 as compared to HotFix 047  m: N- H$ M* s; \$ o4 \
2104559 ALLEGRO_EDITOR     SHAPE         PCB Editor crashes while performing shape operation 'andnot'; [7 k4 v: z9 y( B. u+ Z+ r& y; c6 J/ z
2108207 ALLEGRO_EDITOR     SHAPE         No Void Overlap option is not working in  Auto Metal Balancing (AMB)9 e0 r% U/ h; @2 q; j/ o, ~( o
2240996 ALLEGRO_EDITOR     SHAPE         Detecting Shape Island: Ignored for copied or moved shape
  n5 ^, o1 M+ K' {! W( g( e2258758 ALLEGRO_EDITOR     SHAPE         Allegro PCB Editor crashes when routing two signals together
0 M8 J, u" M/ h- {+ G717389  ALLEGRO_EDITOR     skill         Ability to set and return the application mode using SKILL
0 }7 T5 D5 a0 s5 t1 m853160  ALLEGRO_EDITOR     SKILL         Need ability to get and set application modes using SKILL
$ q" N! p$ U5 l1 K7 n* [( a6 G981446  ALLEGRO_EDITOR     SKILL         Request the ability to get and set application modes using SKILL) M) ~2 J. l4 u& Z! E) J$ N, E2 D
1235409 ALLEGRO_EDITOR     SKILL         SKILL option to get application mode( V# w, L5 K" q+ E0 K# \; `: v% ^
1316962 ALLEGRO_EDITOR     SKILL         SKILL option to switch between application modes2 }/ z% @: F) y% K# N: o3 \4 [. h
1553621 ALLEGRO_EDITOR     SKILL         Ability to change application modes using SKILL function
  ?2 x" c: n$ z4 u1885442 ALLEGRO_EDITOR     SKILL         Ability to change application modes using SKILL function.
2 R+ T, t- Y! ]$ g% z. o2 s2080351 ALLEGRO_EDITOR     SKILL         SKILL to determine current application mode, n: A3 h  |7 `" H) @! {: m. z
2195645 ALLEGRO_EDITOR     THIEVING      Thieving pad cannot be added on some areas in the board in latest hotfix but could be added earlier
( [, |; H/ u. J1721594 ALLEGRO_EDITOR     UI_FORMS      STEP name Filter for STEP Package mapping form should be case insensitive
4 e; M9 }/ Q/ A2090604 ALLEGRO_EDITOR     UI_FORMS      Undo/Redo UI grayed out when invoking Color1928 ^- M4 z& |: i; b, D8 Y
2203278 ALLEGRO_EDITOR     UI_FORMS      'Width' keyword in Place Rectangle field is grayed out when Place Rectangle is selected
+ D' i- @3 q8 w& ]2209172 ALLEGRO_EDITOR     UI_FORMS      Labels truncated by drop-down lists in Options ('Manufacture' - 'Drafting' - 'Relative Copy')2 Y% N7 l9 j0 d6 j
2239426 ALLEGRO_EDITOR     UI_FORMS      Cannot start text size with decimal in 'Design Parameter Editor' - 'Text' for English (Denmark) regional settings
* ?2 l2 i7 x" K2245035 ALLEGRO_EDITOR     UI_FORMS      The right edge of the default Define Grid form looks cut off in 17.4.
8 B$ U( t$ ~; f# O! n0 |( i2245955 ALLEGRO_EDITOR     UI_FORMS      Resizing of 'Reject Item Selection' window not possible in release 17.4-2019, HotFix 004
4 V# E8 M4 h0 w# I& t: }9 R  w2249202 ALLEGRO_EDITOR     UI_FORMS      Extra click required to activate Pass field in Autorouter form
0 I9 U9 `: [5 j" O/ g2259605 ALLEGRO_EDITOR     UI_FORMS      Add ability to resize Reject pop-up2 L& Y( i* B  T8 N) l7 G
2090517 ALLEGRO_EDITOR     UI_GENERAL    Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane) ]& v1 r+ v4 B8 D( o( t
2092436 ALLEGRO_EDITOR     UI_GENERAL    RefDes length of input string for Modify Design padstack is limited to 20 characters0 l/ A, R' @' Y" Z+ T
2134781 ALLEGRO_EDITOR     UI_GENERAL    The Pin Class is missing in Options tab when creating or opening a Mechanical Symbol
! ^" ^* g% v" n' x) ^8 t% ^2168026 ALLEGRO_EDITOR     UI_GENERAL    Edit Properties UI slow to launch for boards with many drawing properties/ g# L1 {- C" t
2191267 ALLEGRO_EDITOR     UI_GENERAL    Changing Visibility of any object type disables links in Layer Select Mode in the Visibility pane, A3 ?1 \$ L" `% Q/ U9 q
2208018 ALLEGRO_EDITOR     UI_GENERAL    Text on BGA pins not visible in release 17.4-2019 if not zoomed to maximum
, r% V+ s2 h" V0 q! R4 d% K; {2225753 ALLEGRO_EDITOR     UI_GENERAL    dark theme does not respect TRBICON size for 4K monitors! Z# x1 h* q! m( W* m
2256841 ALLEGRO_EDITOR     UI_GENERAL    Enlarge the Shape Copy to Layers form as the window is quite small and not resizable
' G5 q- @% S: s/ ~2 `2258019 ALLEGRO_EDITOR     UI_GENERAL    Canvas turns white after closing STEP Package Mapping window4 |0 Z: x& v/ n* {& b* ^
2258167 ALLEGRO_EDITOR     UI_GENERAL    Enhance 'Shape copy to layers' window in release 17.4-2019 to expand or resize, P$ t) H  U4 S2 I$ H3 O# h1 C
2262305 ALLEGRO_EDITOR     UI_GENERAL    Assign Differential Pair form list box size too small to add signals
+ y; {6 O' t9 p1 ?8 Z; z8 V2086574 APD                OTHER         APD is showing duplicate layer text on the vias. j6 A; o4 S# b% b9 L6 ?! x
1723825 APD                SCRIPTS       Allegro Package Designer in release 17.2 is not writing out to either jrl files or script files in real time.& h& n) _  r3 s# w, s
2186363 APD                UI_GENERAL    Text on the Pin is not visible until zoomed in to certain extent% v; m" y1 w1 e- Q% \: }& I
2253484 APD                WIREBOND      APD stops responding when running 'wirebond soldermask create' with 'Measure from soldermask pad'
( X7 I. e4 g" w/ G7 T. d' c2241725 CAPTURE            DRC           Waive DRC option not working from batch DRC window1 |9 Y: f1 X6 i  N# ?
2243645 CAPTURE            DRC           Online DRC bug in release 17.4-2019, hotfix 004 - offpage connector does not have wire' u7 ?: s# N" M1 ~3 e
2250867 CAPTURE            DRC           Hanging wire custom DRC not working when selected standalone. z0 |, R6 m; |0 D( f
2252912 CAPTURE            DRC           Unable to create new DRC file using Browse button in DRC window
9 P% B9 D# x) y( f. w& l2 i) `4 g2047391 CAPTURE            PART_EDITOR   Pin type cannot be changed in release 17.2-2016, hotfix 051
& v0 N, Z# f, [1 ]" }: M2183187 CAPTURE            SCHEMATIC_EDI OrCAD Capture: Ctrl + N seems to call a legacy dialog that allows projects to be created with no name1 j# s5 h0 j9 `. Q1 s
2190602 CAPTURE            SCHEMATIC_EDI Cascading options of Window menu not working in OrCAD Capture in release 17.4-20194 V0 y% N0 {' i, r: j1 k& R
2194374 CAPTURE            UX            Design Sync issues: Session log does not report information about errors0 u, e! ]+ O- S
2183037 CIS                LINK_DATABASE CTRL-L shortcut for Link DB-Parts for Query in CIS-Explorer not working" M% ~7 w/ H7 d
2201323 CIS                PLACE_DATABAS Capture CIS displays empty dialog on placing part from database in release 17.4-2019
, K& O0 ^0 ^2 M( F2216963 CIS                PLACE_DATABAS Light Theme: Warning text not visible in Capture CIS dialog
# u7 o2 y7 a9 F7 }1 d( O! i2246354 CIS                PLACE_DATABAS Warning (ORCIS-6159) pop-up window is blank.: z  i- `% i" I* ?+ A, u* [. E
2230651 concept_HDL        CHECKPLUS     Discrepancy in the 'checkplus' marker files
6 b" T2 m$ j) _3 S# d! v3 l8 L2237145 CONCEPT_HDL        CONSTRAINT_MG T-Points match groups get deleted after saving a design
6 q+ I) I/ T. D2246452 CONCEPT_HDL        CORE          Page information gets removed from 'master.tag' of the top-level design when subdesigns are read-only
6 k) X/ t2 m! a: m2057490 CONSTRAINT_MGR     CONCEPT_HDL   Constraint Manager Worksheet flips after running hier_write when CM is open6 g2 x% t1 K6 b* q3 X* s+ t
2236329 CONSTRAINT_MGR     CONCEPT_HDL   Pin Pairs not added to Match Group# W3 ~& N4 L* _; x/ }4 [% T
2214367 CONSTRAINT_MGR     INTERACTIV    CSet assignment matrix sorting in Net Class-class random in Capture to Constraint Manager flow
: J& U4 ^1 W. m# K; V' p1 U& `2243574 CONSTRAINT_MGR     OTHER         CM SKILL cmxlPutAttribute() cannot set constraint value
) j. V: _' L9 R8 _, R3 h2259598 CONSTRAINT_MGR     OTHER         Importing netlist: Error for electrical constraint data (pstcmdb.dat) import2 k. `* b7 m$ u  L* k
2207862 CONSTRAINT_MGR     SYSCAP        Save icon and 'File' - 'Save' menu in Constraint Manager is inactive
7 R5 Z" x/ f( B* X/ \( u2200316 CONSTRAINT_MGR     UI_FORMS      Expanding 'Analysis Mode' form resets column width# Y) _; ]) H3 I4 @+ t1 ?
2097479 PCB_LIBRARIAN      CORE          Symbol import in Part Developer does not show the correct pin shape.$ B3 A9 D5 L8 D: m) U3 L
2145385 PCB_LIBRARIAN      CORE          Error-SPLBPD-972 reports missing parentheses in the ALT_SYMBOLS property of a part  ?5 U7 Y6 ]1 A4 X
2202622 PCB_LIBRARIAN      CORE          When adding a new pin to a symbol in Symbol Editor, the space between pins changes$ A7 N2 [( l0 S/ R3 R* }6 a
1955570 PCB_LIBRARIAN      FLOW          Using the PACK_SHORT property with more than 256 characters does not work or report an error on packaging
% t8 W8 K2 S1 G7 a  d9 ~% y2072190 PCB_LIBRARIAN      FLOW          Allow PACK_SHORT property value longer than 255 characters
5 B4 B; R$ L# _( ]: r' T1720395 PCB_LIBRARIAN      IMPORT_OTHER  Converting OrCAD Capture OLB to Design Entry HDL library adds braces to pin number
2 }! y/ }! y8 V# V% K9 p2141340 PCB_LIBRARIAN      SETUP         SPLBPD-216 Error logged in PDV even when MAX_SIZE Sheet is defined) Q3 ?$ V. R% s. p
2214973 PCB_LIBRARIAN      SETUP         Unable to apply symbol property templates when PDV lock directives are set- `1 I! I! O5 N% z
2257527 PCB_LIBRARIAN      SETUP         Locking PDV directives prevents applying symbol property templates$ W% U2 N7 {: j; R5 i9 m1 \+ F
2033898 PCB_LIBRARIAN      SYMBOL_EDITOR Running Symbol Editor with no arguments results in a background process, not an error.1 O$ O" l6 g5 b9 x  P% Z/ E
2093849 PCB_LIBRARIAN      SYMBOL_EDITOR Symbols and font sizes appear different when placed in designs
9 u8 [3 I0 r3 @/ |/ [5 a. a& Q2200399 PCB_LIBRARIAN      SYMBOL_EDITOR Multiple issues observed when editing parts in the New Symbol Editor
' C$ B  q0 |9 O* e4 _5 _$ K) W2218940 PCB_LIBRARIAN      SYMBOL_EDITOR Duplicate pins cannot be removed' e# [  g' Q5 M* z1 P! m
2230542 PCB_LIBRARIAN      SYMBOL_EDITOR Bus pin location changes after expanding or collapsing pins in Symbol Editor1 m7 B6 Z+ }  ]: [/ a
2239303 PCB_LIBRARIAN      SYMBOL_EDITOR Expanding and collapsing a bus is changing the msb and lsb for the pin name
0 p. B& S% Z6 ?2243431 PCB_LIBRARIAN      SYMBOL_EDITOR Group of pins that are not adjacent cannot be moved together
6 Y* h5 ~9 h% n$ W; e, z8 x0 u: O, G2029056 PCB_LIBRARIAN      SYMBOL_EDITOR Unable to change Grid Settings in Part Developer  U! N6 R+ l) A3 T
2149948 PCB_LIBRARIAN      SYMBOL_EDITOR New Symbol Editor and System Capture moved pins from 0.01 grid to 0.05 grid.
+ t2 V% M+ _6 Q! {( B- e3 c2206975 Pspice             MODELEDITOR   PSpice Model Import Wizard symbol preview readability improvement requested% d! w' ?% ^" v: V4 q
2211187 PSPICE             MODELEDITOR   Model Editor color scheme not readable: q5 b" {7 ^; G' g: W4 X
2214415 PSPICE             MODELEDITOR   Symbol view in Model Import Wizard has a visibility problem! `" _2 ]/ c! B. G
2199570 PSPICE             PROBE         Unable to 'select sections' after Monte Carlo runs with Temperature
6 K0 Y/ W5 e2 A' h& M: m0 g2244140 PSPICE             PROBE         Not able to select multiple sections to plot in probe2 o7 b4 c9 b. n5 D
2249565 PSPICE             PROBE         Selecting multiple traces for PSpice A/D Monte Carlo run not working
0 A1 {/ f4 n% T- E3 D! W2171626 PULSE              CORE          Pulse crashed with error related to third-party development kit platform issue6 d% ]) ]1 `/ j) s( l; i* u& y7 M
2221523 PULSE              UNIFIED_SEARC Cannot log in to third-party search providers but can log in to Cadence Online Support
0 K2 @9 D, j" ^1 T% |2019229 RF_PCB             OTHER         Layer conversion file data does not update GDSII layer mapping using Package Symbol Wizard; l; C8 d. c/ i' `
820288  SIP_LAYOUT         COLOR         Layer Priority command does not seem to be functioning
1 g# D8 R, D3 U/ b1 f820305  SIP_LAYOUT         COLOR         Layer Priority menus do not match the Color dialog in the package substrate tools
) A2 Q& U" q4 {3 V: U! e2256044 SIP_LAYOUT         DATABASE      Fix teardrop does not work for some situation: Deleting fixed fillets
3 G# l- L8 a* d/ x8 A: V0 H2254932 SIP_LAYOUT         DEGASSING     APD Plus generating assertion failures when running degassing mode with script# h# x% j4 P0 a1 T; S. U
2106314 SIP_LAYOUT         INTERACTIVE   Large design causing severe lag in Windows Server machine/ Z* g* z0 b& O) d) [5 M) S
2096239 SIP_LAYOUT         STREAM_IF     Database fails to create stream out file
3 v7 j0 P4 y8 s) {1 g4 n5 x, K0 E" G4 i4 |2079071 SIP_LAYOUT         SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die
" k  Y$ j: S. g% Y) K2251630 SIP_LAYOUT         WIREBOND      'Change Profile' does not change the diameter of the wire bond' s3 u: K( u9 f( Z8 v9 V
2253633 SIP_LAYOUT         WLP           Advanced degassing passing illegal arguments to dba routine
; M& c6 U" y8 u& M) o2259630 SIP_LAYOUT         WLP           Advanced WLP: Import PVS DRC results in error/ q( W$ e) q  d2 g
1968437 SYSTEM_CAPTURE     ASSIGN_SIGNAL Net name pasted in lower-case though uppercase input is enabled7 H7 C( c+ Y: Q8 @+ q
2131976 SYSTEM_CAPTURE     AUTOMATION    syscap exits when run with the -tclfile argument and an invalid Tcl file
6 ]+ F0 h. y& i' F& S, A1983063 SYSTEM_CAPTURE     BLKDIAGRAM_AU Auto Shapes are being shown as part of components# D9 y4 j, T( {. g& @
1977673 SYSTEM_CAPTURE     COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
" g4 G+ D# E% G' i1 t% F- O5 c1 q; E& I2247567 SYSTEM_CAPTURE     COMPONENT_BRO Symbol property placeholder changes not updated on the canvas
% r* `7 i' |& H* Q; {0 Q6 I2027100 SYSTEM_CAPTURE     COMPOSITE_FIL pstdedb.cdsz and netlist preview in System Capture is not being updated when individual netlist files are written
9 w3 `1 J; E9 v' M) o1863460 SYSTEM_CAPTURE     DARK_THEME    thumbnail preview of pages is in light them but dragging the page the previes is dark& p$ W% k, v! v% L/ h$ v: K. f7 j% ?
2168622 SYSTEM_CAPTURE     EDIT_SEARCHRE Reports from Find Results are dumped even when the operation is canceled; M+ L! z; V: |
2168625 SYSTEM_CAPTURE     EDIT_SEARCHRE Sort icons for columns in 'Find Results' are incorrectly placed: appear to be in adjacent column. q' m/ o6 ^( m, x& x% D
1895142 SYSTEM_CAPTURE     EXPORT_PCB    System Capture incorrectly reports unsaved changes when closing after running export physical
. o- O+ O6 s& ~* b) }8 u+ ~( y1931660 SYSTEM_CAPTURE     EXPORT_PCB    SDA is non-responsive while Allegro launches and opens a board when launched from SDA2 \/ Z2 N8 D3 K; o* f" L, }  @0 t
2087387 SYSTEM_CAPTURE     EXPORT_PCB    System Capture: After Export PCB completes, busy cursor shown for a while4 k3 }4 {' e$ l! U! R8 z2 H7 k: X8 q
2202179 SYSTEM_CAPTURE     FIND_REPLACE  Replacing a net name with the same name by using Find and Replace results in a crash
/ K0 E. G0 E' g, P! j7 d4 G3 S1843885 SYSTEM_CAPTURE     FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
& K- y$ b5 s9 k2 B" g* b1993208 SYSTEM_CAPTURE     FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
# T( A: S! q; U' l9 Q+ `1 {2231399 SYSTEM_CAPTURE     IMPORT_BLOCK  'importBlock' Tcl command not working when using a script/ C# e, {: x% `4 V1 a' \
1907729 SYSTEM_CAPTURE     IMPORT_DEHDL_ Import DE-HDL sheets -  differential pair properties on nets are lost% ~$ t  D3 h9 V/ ]& G4 ?
2025949 SYSTEM_CAPTURE     IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not  translate in System Capture5 h2 x4 r) n, Q9 I2 ]- _6 P9 _% ^% y
1942542 SYSTEM_CAPTURE     IMPORT_PCB    System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks: G) b9 }3 l% s7 O2 O
1982320 SYSTEM_CAPTURE     IMPORT_PCB    View files are not created in the schematic-to-board flow
6 ^' b2 Q! y) u' s$ w, b5 F2117532 SYSTEM_CAPTURE     MENUS_AND_TOO Ability to customize menus for a site
6 A! V( t. U. o. `1 h2213478 SYSTEM_CAPTURE     MENUS_AND_TOO Help - About menu item appears twice
4 M6 [( c+ v1 T5 A1910941 SYSTEM_CAPTURE     MISCELLANEOUS Parts that are not in any schematic page appear in netlist and BOM; h/ R$ w! Y6 x0 d* `$ |" G; D
1967614 SYSTEM_CAPTURE     MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
( g( M" N' y0 P+ p  T' D; X2189846 SYSTEM_CAPTURE     MISCELLANEOUS Inconsistent display of same font& j) Z! Z8 x# F* R3 ^6 e
2178961 SYSTEM_CAPTURE     NOTES         Cannot add Japanese text in notes in release 17.4-2019 on Windows 10& E: i! n; C' @- y+ U7 ~( v/ e- ?
1973437 SYSTEM_CAPTURE     OPEN_CLOSE_PR Opening a design crashes System Capture" R. K, \! E7 F, p
2079857 SYSTEM_CAPTURE     OPEN_CLOSE_PR System Capture: Unable to select design to open if license selection box is canceled the first time* q& ~5 e. O% X8 I: z
2065025 SYSTEM_CAPTURE     PACKAGER      Export to PCB Layout reports wrong path but exports correctly
/ }# X, K2 N, E' l% i' R. z2229611 SYSTEM_CAPTURE     PACKAGER      Path for the 'packaged' folder shown in the 'Export Physical' is incorrect
4 U) S, b) U1 d! R- i; d1993146 SYSTEM_CAPTURE     PROJECT_EXPLO Cannot move page up by only one position5 Q+ |# O4 K2 w5 }3 g: J  ~" w
1892120 SYSTEM_CAPTURE     PROPERTY_EDIT Some parts are missing reference designators and some have two properties - RefDes and REFDES
. T; o+ ~9 W* s0 f% P2201060 SYSTEM_CAPTURE     PROPERTY_EDIT Some of the icons in the Properties window do not have tooltips
( a& `6 Z6 Q: `( R9 _- \* I" P8 u2246667 SYSTEM_CAPTURE     SCRIPTING     Running the 'replay.tcl' script gives an invalid command name error
$ w% A& N5 t! F+ C6 X, I2010032 SYSTEM_CAPTURE     SHORTCUTS     Cannot enter Page-Up/Page-Down as shortcuts0 k1 a2 e% w4 p* n: q* d
2017985 SYSTEM_CAPTURE     TDO           Allegro System Capture ability for multiple users to open a design3 K- L0 o# b! J9 D! d
2106743 SYSTEM_CAPTURE     TDO           Ability for multi-user access to the same schematic5 {! V0 B3 u0 y8 ?
2209628 SYSTEM_CAPTURE     UI            Tooltips for Design Rule Checks are getting truncated
5 ]* W. n+ J* C& [* M6 k: |1990258 SYSTEM_CAPTURE     VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number# k! l% ~1 G$ ]2 L* E. I% O; c
2032005 SYSTEM_CAPTURE     VARIANT_MANAG Custom variables not saved for variants$ W) M5 o' S0 H, Y( o2 Z8 A
2228299 SYSTEM_CAPTURE     VARIANT_MANAG CAP parts should not show up in the Preferred Parts list when changing a RES
1 I+ Y8 l6 e4 M" e$ |0 B! O1627835 SYSTEM_CAPTURE     WIRING        Inconsistencies in wire movements
7 m8 S4 o* J6 D1670888 SYSTEM_CAPTURE     WIRING        Rotation error when a component is connected to a power symbol
7 A4 j- x5 ~: u1721863 SYSTEM_CAPTURE     WIRING        Net names move to random locations when components are moved around the canvas.
+ ]( @! m! G. E: {. x* ^1960130 SYSTEM_CAPTURE     WIRING        Disconnected nets when using the mirror option4 u' N4 c2 N- G* u
1961274 SYSTEM_CAPTURE     WIRING        XNet removed during pin swapping
8 Y- n* ^1 V- {! @1968463 SYSTEM_CAPTURE     WIRING        System Capture should not allow illegal characters to be entered for net names
6 N0 j3 Q0 B4 _4 z+ I/ H; O8 X2 Q) F1973426 SYSTEM_CAPTURE     WIRING        Selecting multiple net names and trying to delete only deletes one net name.
( q6 U6 _6 h. B1978381 SYSTEM_CAPTURE     WIRING        'oops' does not remove the first vertex placed
0 `* ?; a6 w2 V. \( A/ }1985029 SYSTEM_CAPTURE     WIRING        Net aliases are not dragged with circuit, they appear to move after the circuit is dropped
2 d9 _+ L' w3 B/ I7 x2 ~/ T. K2013647 SYSTEM_CAPTURE     WIRING        Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections, |5 C, [  y0 E! `" Y. H/ x
2014188 SYSTEM_CAPTURE     WIRING        Context menu not working in Variant mode
+ b* b! S2 N7 O. N. ~5 `8 z3 S2041879 SYSTEM_CAPTURE     WIRING        XNets generated for nets with pull-up resistors
4 m$ k0 _! @, S- t) {2050533 SYSTEM_CAPTURE     WIRING        Need an option to increase junction dot size
7 x/ B. k3 k4 B+ G) o$ G/ q2061877 SYSTEM_CAPTURE     WIRING        Unable to add a power symbol with the Place - Special Symbol menu
& R, A: Q& `, c  }+ i  I/ V2079409 SYSTEM_CAPTURE     WIRING        Increase the size of the wire connection dot in System Capture# A/ V3 Z5 P, N( e# x& l. c
2081884 SYSTEM_CAPTURE     WIRING        Symbols take a long time to move, and results in DRCs and broken connections% n: u3 X( U0 P- l- ~( ]
2085263 SYSTEM_CAPTURE     WIRING        System Capture: Focus lost from the Format tab if font name starting with typed letter is not present
$ d% s8 C. g8 n' V! ~& p2089569 SYSTEM_CAPTURE     WIRING        Ability to specify the solder dot radius size6 `3 x! c. u+ Y8 r8 A
3 K; g  |8 }: O/ h  @' N. a
QIR1详细特性说明: Hotfix_SPB17.40.007_README-Release_Notes.pdf (2.51 MB, 下载次数: 55)
% V" @' W+ I+ m6 i$ x- }; ^待我上传完后附上链接,这次QIR1比较大,4.59 GB ( z6 C8 o8 h/ T- ^7 h. D
# a/ p- T" j. Z1 D8 E+ L

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  • TA的每日心情
    开心
    2024-2-21 15:59
  • 签到天数: 313 天

    [LV.8]以坛为家I

    推荐
    发表于 2020-6-8 09:10 | 只看该作者
    已在本版置顶帖中更新了该补丁, B' M$ E! |; m/ G4 P0 _
    https://www.eda365.com/thread-276156-1-1.html

    该用户从未签到

    推荐
     楼主| 发表于 2020-6-12 13:26 | 只看该作者
    laurence 发表于 2020-6-8 11:35
    9 k6 Q; B9 C; B  O6 Z. ^更新QIR1后,出现严重bug,一导入网表PCB程序就会crash,请问大家有同样问题么?
    ' d9 p; A# c/ @6 E5 k) L
    强烈建议不要再之前的基础上安装补丁!必须完全卸载之前安装的17.4,然后全新安装,然后再装hotfix,否则会有些奇怪的问题!
    6 |) u# ~" R# V2 l$ p1 P- H

    该用户从未签到

    推荐
     楼主| 发表于 2020-6-12 13:29 | 只看该作者
    金志峰 发表于 2020-6-11 08:527 m' ?/ ~9 @7 _& \# q
    试着把.动态铜自动smooth disable掉试试,我这边更新动态铜会crash掉    不知各位有没有遇到过。

    + w9 s  l+ J7 ^动态铜自动smooth后软件会crash掉已经解了!全新安装17.4,然后再装QIR1,就没有问题了& O/ n) c* z0 d

    该用户从未签到

    2#
     楼主| 发表于 2020-6-8 02:54 | 只看该作者
  • TA的每日心情
    擦汗
    2019-12-12 15:00
  • 签到天数: 13 天

    [LV.3]偶尔看看II

    4#
    发表于 2020-6-8 08:49 | 只看该作者
    感謝大大的熱心分享囉!!

    该用户从未签到

    5#
    发表于 2020-6-8 09:06 | 只看该作者
    希望早日上传链接. 感谢分享.

    该用户从未签到

    7#
     楼主| 发表于 2020-6-8 10:50 | 只看该作者
    本帖最后由 金志峰 于 2020-6-9 01:39 编辑 ) d* c; M9 M: d3 E/ @4 w& X
    dzkcool 发表于 2020-06-08 09:10:19
    , J, m- T9 w3 k) F# G已在本版置顶帖中更新了该补丁
    $ [9 ~+ [  n* nhttps://www.eda365.com/thread-276156-1-1.html
    7 I. N# {! x. p- W7 \( \1 U
    OK,那我就不上传了3 f! H9 x4 W4 p( A

    “来自电巢APP”

    该用户从未签到

    8#
    发表于 2020-6-8 11:35 | 只看该作者
    更新QIR1后,出现严重bug,一导入网表PCB程序就会crash,请问大家有同样问题么?

    点评

    还是不行,PCB导入网表就宕掉了  详情 回复 发表于 2020-6-13 17:57
    我也遇到相同的问题了。  详情 回复 发表于 2020-6-12 17:54
    强烈建议不要再之前的基础上安装补丁!必须完全卸载之前安装的17.4,然后全新安装,然后再装hotfix,否则会有些奇怪的问题!  详情 回复 发表于 2020-6-12 13:26
    试着把.动态铜自动smooth disable掉试试,我这边更新动态铜会crash掉 不知各位有没有遇到过。  详情 回复 发表于 2020-6-11 08:52
    我这边没有遇到……   详情 回复 发表于 2020-6-8 17:25

    该用户从未签到

    9#
    发表于 2020-6-8 13:06 | 只看该作者
    给力,给大神赞一个
  • TA的每日心情
    开心
    2022-6-29 15:11
  • 签到天数: 378 天

    [LV.9]以坛为家II

    10#
    发表于 2020-6-8 14:30 | 只看该作者

    该用户从未签到

    11#
     楼主| 发表于 2020-6-8 17:25 | 只看该作者
    laurence 发表于 2020-06-08 11:35:23
    1 v6 g1 [7 B6 X+ M" M更新QIR1后,出现严重bug,一导入网表PCB程序就会crash,请问大家有同样问题么?

    / B# X* L% G# w' @+ |6 Z3 Y3 B7 @# `! ]8 F/ h0 }1 p
    我这边没有遇到…… 1 t6 v( m( I' j, e  N1 N  _

    “来自电巢APP”

    该用户从未签到

    12#
    发表于 2020-6-8 20:47 | 只看该作者
    感謝大大的熱心分享!
  • TA的每日心情
    开心
    2020-7-25 15:21
  • 签到天数: 1 天

    [LV.1]初来乍到

    13#
    发表于 2020-6-9 10:45 | 只看该作者
    能不能做种子呀,那个百度网盘真的太慢了  只有28KB/s
  • TA的每日心情
    无聊
    2021-8-31 15:05
  • 签到天数: 1 天

    [LV.1]初来乍到

    14#
    发表于 2020-6-9 11:23 来自手机 | 只看该作者
    我的破解完后pspice不能仿真了,怎么解决?

    该用户从未签到

    15#
     楼主| 发表于 2020-6-11 08:52 | 只看该作者
    laurence 发表于 2020-06-08 11:35:23: N$ R8 a8 A# {. f7 C
    更新QIR1后,出现严重bug,一导入网表PCB程序就会crash,请问大家有同样问题么?
    ; _% _; m, t3 E; y/ ~

    - A! R2 z4 u: e试着把.动态铜自动smooth disable掉试试,我这边更新动态铜会crash掉    不知各位有没有遇到过。
    ! M" o& I8 X4 D7 M! V5 i; F9 w9 a

    “来自电巢APP”

    点评

    动态铜自动smooth后软件会crash掉已经解了!全新安装17.4,然后再装QIR1,就没有问题了[/backcolor]  详情 回复 发表于 2020-6-12 13:29
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