这个层次原理图为啥总报错呢？

winz

尝试画个层次原理图，很简单，就几个电阻一连，可是画完了DRC的时候总是报错：
Checking Misleading Tap connection
- L3 d: y+ Q! J: C1 f3 aERROR [DRC0039]   Tap may not be connected with the bus Check Entire net. DD1:  SCHEMATIC1, top  (3.55, 2.30)
ERROR [DRC0039]   Tap may not be connected with the bus Check Entire net. DD2:  SCHEMATIC1, top  (3.55, 2.30)
1 E0 M5 ?3 A- p8 X, b1 V$ j, s8 QERROR [DRC0039]   Tap may not be connected with the bus Check Entire net. DD3:  SCHEMATIC1, top  (3.55, 2.30)
6 M5 }, o4 p8 t; O' |: ~# kERROR [DRC0039]   Tap may not be connected with the bus Check Entire net. DD4:  SCHEMATIC1, top  (3.55, 2.30)
hierarchical pin name D[1..4],
& ?! c% M, X2 tbus name DD[1..4],
1 a* o1 v3 F7 L: q$ D+ \, l5 dnet alias 分别为DD1，DD2，DD3，DD4。
. F* L- n! S( M9 }, C问题出在哪呢？如果把根图上的bus name 去掉，就又报警了，
" T/ D9 m! H  V' L3 F/ ICheck Bus width mismatch
N06946 has not connected with proper width
6 H: [/ }3 |0 b! z- TWARNING [DRC0030]   Bus width is not matching with the port Width block1,DD[1..4]:  SCHEMATIC1, top  (2.45, 2.30)
5 r/ ^. d0 I& Z1 r" x2 fN06946 has not connected with proper width
7 Z4 z+ \$ S0 @8 |/ ]WARNING [DRC0030]   Bus width is not matching with the port Width block2,DD[1..4]:  SCHEMATIC1, top  (3.55, 2.30)
! Z' w  G1 U" I7 H