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偶也跟一贴！
: w# i9 G. H( p以下内容来自《high speed digital system design》。
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A via is a small hole drilled through a PCB that is used to make connections between various
1 e1 O! [" [( X. I% Tlayers of the PCB or to connect components to traces. It consists of the barrel, the pad, and
1 y Q0 I) l/ u: m% jthe antipad. The barrel is a conductive material that fills the hole to allow an electrical
8 n! M" F" f& w: S5 |6 M$ tconnection between layers, the pad is used to connect the barrel to the component or trace,0 Y; w( w/ q- d4 _- e1 M
and the antipad is a clearance hole between the pad and the metal on a layer to which no
* X2 `5 M7 Y! V( {' |$ Y( y1 hconnection is required. The most common type of via is called a through-hole via because it! X+ p7 r9 A3 {
is made by drilling a hole through the board, filling it with solder, and making connections on7 R: d( {* }- V0 G% `4 ^% [
appropriate layers via the pad. Other, less common types of vias, used primarily in multichip. _3 \' P/ S7 V1 a5 I# p
modules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts+ Y/ K1 W3 c5 z9 c, |1 c8 A4 D
a typical through-hole via and its equivalent circuit. Notice that the pads used to connect the% d; ^4 Z- J/ M0 K
traces on layers 1 and 2 make contact with the barrel and that there is no connection on
! w" E, Y3 @+ K7 {. W, S" mlayer 3. Blind and buried vias have a slightly different construction. Since through-hole vias- D2 }7 D' h7 r& f) a3 A
are by far the most common used in industry, they are the focus of this discussion.9 d" F ]4 h P6 x% r1 T* o7 q& d% g
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Notice that the via model is simply a pi network. The capacitors represent the via pad5 Y8 F/ \4 r6 ~, w: c/ U
capacitance on layers 1 and 2. The series inductance represents the barrel. Since the via! N9 z i# n* {+ Y. t: H# o
structures are so small, they can be modeled as lumped elements. This assumption, of
- Z! b. y, Y: M* c1 x% O+ D9 ncourse, will break down when the delay of the via is larger than one-tenth of the edge rate.
; G! }, n; \& |) f- OThe main effect that via capacitance has on a signal is that it will slow down the signal edge# M7 r5 f, A4 `* \$ ^ U% _
rate, especially after several transitions. The amount that the signal edge rate will be slowed$ n3 z! U9 G5 k0 [- p
can be estimated by examining the degradation of a signal transmitted through a capacitive
$ s' E" Y2 g( J W9 wload, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive( L0 K0 x2 i: |% W7 p
vias are placed in close proximity to one another, it will lower the effective characteristic
$ X0 u/ l* z$ N1 G0 ^( K* s5 A5 [impedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is# h7 J" @" B( r3 e' ^- g/ Z
[Johnson and Graham, 1993]
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[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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支持！
反对！
发表于 2008-1-17 21:53
发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!