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< DRC ERROR >+ Y5 b1 _/ G2 {1 h. g
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Class: DRC ERROR CLASS
; P$ S$ w1 `6 H% v- n, f Subclass: TOP- i6 k0 k. |2 s8 d3 \
Origin xy: (380.49 358.53)% f: p' }8 ]5 Q. J6 Q: E
Constraint: Blind/Buried Via to SMD Pin Spacing5 E% x7 W2 w( K- I" _0 l
Constraint Set: DEFAULT
1 k, u4 A8 g3 r( K/ ] Constraint Type: NET SPACING CONSTRAINTS
5 H/ `" e( d6 ~- R- h" L, g" Q% s; S& q5 ~/ y( x" b) B$ Q& z
Constraint value: 4 MIL
6 ^% o+ N, _4 |+ e' R Y Actual value: OVERLAP |
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