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08的是这样的，装了09会多出前两项，我没有忽悠大家，冤枉啊 ( Y* ~. \* i& f4 q: i+ w$ T, J
; `( z$ P9 K7 O& _, PDATE: 10-21-2011 HOTFIX VERSION: 008
5 Y( v8 i+ w& f: ?" ~ V( C) Z===================================================================================================================================
# ~9 q8 c5 G7 w* LCCRID PRODUCT PRODUCTLEVEL2 TITLE5 J5 j# O' A8 A7 N2 E# ?+ B
===================================================================================================================================/ \6 G, j1 n, W
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.* w! x. z' k! i4 i
923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
' @* s% r, o" L' p; X; J# J926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it( N* M7 d$ E* i9 b8 X, L
929348 F2B BOM Warning 007: Invalid output file path name" V4 O3 s# M' t0 d3 R
929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error
' P+ P8 K$ t2 Y9 S4 r: q( K4 c& k930783 CONCEPT_HDL CORE Painting with groups with default colors
& o* Y% q+ p! k+ F7 L936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.* \, n. h/ B3 w) x- g$ J$ H
938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR a+ p) M9 B ~8 B4 ~
938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins; D+ z5 k% x/ g
938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.
; t/ @/ m: ^. F: z5 m9 \939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window/ T* h8 R. P2 X2 s$ v4 |
939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.& F6 Z0 q% w1 Z9 F7 M0 a
939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)$ n7 }+ W( Z: ~/ M0 z0 D* {
939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.. s8 Y/ E; F2 G. E8 t
939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows ??on lower hierarchy level nets after Upreving to 16.5 version.
# Y1 M$ M3 x. ^- X9 _. U# ~. w939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.8 R8 Z2 J( e+ u* a' v j
940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'5 A( h0 w2 x% t, q4 w0 r1 w. q$ n
940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost! ^; R. b) G% m( i4 z
941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks
( K S P6 p0 c6 h( x941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
) O5 D2 {% d$ `, c7 E+ ~$ i* E942210 SCM OTHER Is the Project File argument is being correctly passed?& D( W4 i [* C- {8 _
942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache
{7 D2 M3 E z, a' E" ?% k942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible5 S2 {, ~/ Y& `) N# n
943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash |
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发表于 2011-10-30 10:29
发表于 2011-10-30 13:29
