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2 P- S3 x3 \$ v8 L. ?/ c3 B" S5 hDATE: 02-17-2012 HOTFIX VERSION: 016; b; w' P4 x" E5 {* q, L
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1 J6 u, J% e, [% {& T) W* RCCRID PRODUCT PRODUCTLEVEL2 TITLE* h! v; B% u e8 \# U+ C3 z5 E& F
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" e9 j, b8 f+ [# Z$ F+ R! h840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV& \4 @6 I( I( D+ o3 d! m
873075 Pspice PROBE Decibel of FFT results are incorrect.
4 B/ p. Q! |+ N9 f938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property0 Y' A: a. W4 e$ N$ ]2 X
943003 SCM REPORTS The dsreportgen command fails with network located project; o3 | Q, _9 u: p# G
961530 allegro_EDITOR INTERACTIV The problem of Display measure command& A( N+ D6 u4 ^% u9 ~% y/ v7 D
962157 concept_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?
( C* b4 D& Q- H; L962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend
* W6 x4 ?/ ^4 s! o5 f! p4 N: \2 H968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design. A3 x& W) y# p7 x' U$ t# R+ ^" H- u
968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.
' Q/ o7 R1 Y( l, X* e3 I969450 LAYOUT TRANSLATORS orcad Layout to Allegro Translator crashes
* }# ^$ D) D2 i* i/ y969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~1 x+ r8 | F/ T( L; j u
971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.
& V& e G K: S/ e \. z% E* H6 \) I971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure
1 [8 r8 L6 {" j" S# G/ z& ?973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR
, V; g( H7 h$ |8 O; e' Y973859 PSPICE ENCRYPTION Pspice crashes with encrypted model
6 S- T; {) @) A* c0 d! a+ J0 q1 [973938 PCB_LIBRARIAN VERIFICATION pc.db is missing
, h8 H1 }$ s2 G& u974540 CONCEPT_HDL CORE Graphics updates are real slow
1 \+ O8 j5 ^9 l5 ]974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?
, q. h$ J9 S5 [* u p( U! y974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported.
4 y0 c0 r z1 W' O: T; A- L1 N" c9 [- c974945 ALLEGRO_EDITOR skill Why is axlPolyOperation is giving different result and not working0 }( ?! f7 D4 m& D+ ^8 c. _
974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology
- `' b0 X1 r: Q( j. C: U975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5% _: a( b- b$ L( F. R7 F9 m: Q
975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)
7 F: y+ ^7 ]6 @! n$ f4 Q& w975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move
! @8 e f4 n- y X {7 p975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits
% K6 s/ R s7 s# x# r" J976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.
1 J- h8 k! g4 G! P% G7 ?976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views3 T9 s' K+ X* y7 K0 c( X! ]
976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design; T ~( ~/ H4 L0 l2 b
976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design9 Z$ f( d; t ~5 ?$ q4 f
976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC7 B4 [5 {1 `- q9 O* U& T" T
976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value
4 d( W$ Q, A8 a; _6 A976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash
2 Y' u; u! J0 A; M4 ~3 c& b4 o2 n0 w976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.9 v& h; g! y5 t) g
977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3# g4 a0 l; E8 E# m& `
977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro
% l( _3 N) m/ D5 N. G/ P2 C, G/ E3 ^978652 ALLEGRO_EDITOR pads_IN PADS_IN fails with ERROR: Finished with errors.- y5 i" o& Y$ U0 D$ T3 P4 W6 W
978744 APD DEGASSING Some shapes will not DeGas on this design
' \. k8 \' r/ l3 c e979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection+ P+ f3 l. E9 Q+ x" P+ V; A6 i
981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 158 S6 l/ O; n6 V: L9 L/ o
* ^1 Q, |1 L5 c6 ]5 o
DATE: 02-03-2012 HOTFIX VERSION: 015
& k9 u- X( a6 l8 S4 |& T3 E+ ~===================================================================================================================================/ U& O) Z6 C5 d/ j
CCRID PRODUCT PRODUCTLEVEL2 TITLE+ G+ n7 J p4 f
===================================================================================================================================
. M+ q ^0 _, S871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager8 H7 {4 ^0 p1 Q: y3 {6 O
921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension8 }! B3 v) c3 P% h9 [
941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design
1 S- I1 x% M1 E" k" @954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning
Y0 A: A P' h' j! k5 {961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version
1 t! s+ P6 T; l6 y964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project: f# o. `: V7 b! c) V
967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only
; [8 O# [/ |+ M$ T/ }5 c968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol6 V- c8 r% l# R4 y% ^
969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5( J0 s* R0 o( h1 i; [3 m
970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance
9 `+ b/ W8 y H/ |970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins
% `0 I5 T6 u& N% o& o) u/ e# N970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.
* w1 ^+ x, p, ]3 X& ~970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.* E. }) C5 K, X$ M# R, U8 X/ H' `
970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash4 _# B0 E6 _8 J
971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design
% m5 P% z9 ~+ k; F, g971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances5 G" ]! X" b( L6 ], S
972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM$ c% f3 T7 a9 @5 k+ P7 E
972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT+ I2 D* A, \& w; ^+ w, l
973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.
. e5 j- {* n+ ~# h o973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized
* q: I8 X, [2 ^973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value" k- _0 v6 w! U0 d: A/ _
973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.
, v7 t) h! @. y: }6 n973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net
8 O. J3 V1 ?/ h, g( R1 W/ ?; @973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application
( ~3 M7 { R" x- O# F974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.
& M) X; P! A% B: j' r% L/ u2 h: J974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working
9 x' z% g: }6 T9 Q) n0 `6 _976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index
, _1 j( I' y- }# c
* v, d8 T) e3 S3 d% \DATE: 01-20-2012 HOTFIX VERSION: 014% A# s/ {$ D" D
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
% a3 k& {/ S; M: Z: M' Z. c6 y===================================================================================================================================% A) C6 v( j3 h: U3 \* M( z
733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server
2 @, w4 ^; e$ E9 l H, k941020 SIP_LAYOUT OTHER Soldermask enhancement
& _1 f$ i4 r9 z. W5 B946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?
4 w, {# E5 f4 g' g* ~953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable" e8 K. k3 H9 C* f& e
954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic' p: i( Y: z( {2 H& b: {
956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs* u: v9 C5 A& ^( T2 p8 F5 f3 I
958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive6 k6 r5 C8 r! R
958395 ALLEGRO_EDITOR SHAPE shape voids won't merge
* O8 m ]: o9 ~' V) v7 Z959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.
' f) v: D5 ]( O8 q3 x- |# {959940 APD AUTOVOID Void all command gets result as no voids being generated.! Y' u$ v! {* J$ }
960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message
. S) X" K# R* u2 `9 C& b961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI% m5 h+ g4 D+ g1 v, K% o
961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.2 E5 Y- \/ L1 y* X0 k/ P
961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification5 y& q% O5 `7 ^& G. K' J9 O% u/ g7 u
961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.! p1 P8 W. W) Z# K+ V h$ P
961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.
* ^# D* _) q+ s5 {961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM9 F# z+ W4 `; A; a* k$ s5 J" Y
962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine
# K& h: N* H% Y( `% r4 O% w962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires+ I5 ~& c1 o% c8 `/ } u# Z
963232 CAPTURE MACRO Macros not being played in Windows7
2 O6 ?; |0 {* s# r963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3/ f, Q3 k' }( R2 O) C' r( W
963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux5 T+ N; x; Z5 n2 e# W4 y
963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design; r+ f3 k9 _2 M( Q. g
963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length. N9 c& [, Y8 B, Y7 t A
964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym...
' l, I" d9 H4 P( G4 l964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs
7 M! N! e( l" L* w+ L: L7 t1 s964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)
! b4 [/ @$ J8 E/ e' F966148 APD INTERFACES Character Limit for DIE Files (*.die) Import
* X5 t/ s; r; e$ O966416 F2B PACKAGERXL Cannot package this design5 P9 d! o" l; {+ U( U
966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks7 |- K0 e! o" j4 B7 t
966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open
5 w# [; ]0 T6 Z9 w966795 ADW ROLLBACK rollback utility does not honor -product option from command line6 A, }2 n# u3 J$ n
967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object. L' Y4 a! \8 _( f( q
967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing% \ f3 s7 Z* h0 J4 [* y
967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program% _# u" H, \7 m
967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.( Z2 {8 X N6 Y1 H+ B3 J: x
967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL r5 k) J$ f+ q9 @" M8 u" R
968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.6 i3 J. H+ V* Q5 U6 _8 w
968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell
' B; L( W# J5 j% U4 |968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager
$ s( h5 @% W/ g969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes
3 }, n5 H% A- M t4 }
1 R* `- a: |' h% [" E3 u6 ]DATE: 12-16-2011 HOTFIX VERSION: 013
& [& c: P$ {# Q. v===================================================================================================================================. s; G! ~3 f1 L* `( S
CCRID PRODUCT PRODUCTLEVEL2 TITLE
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+ ~3 Z+ ^1 c3 J! k, R4 z6 s" c875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.
& V! u, t5 d% |2 P0 V+ F927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design1 @2 R) s4 J$ g3 _8 \0 I. _0 i
938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
, l; G3 [1 J' h) _941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
7 t/ J% h- f8 A# h9 S4 i8 ]945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command r0 Z* c; g: ?: X* c; l5 j& C: Z" A0 {
946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
4 I; F. v3 `) R* r946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.3 W2 s1 u6 X9 D& ?; R
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function& l5 u! {3 h2 O! K$ U" C$ @7 S
953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
2 G$ R) ~, ~4 ~; h( ~' J# C953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block/ F6 ~( Y! ], {0 M6 D" n# O
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
# f& \# G4 `, o5 f8 N- [953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�" ]3 T- L; I" L9 A F/ t9 W- J: ?
954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.
: G. ]- r8 l5 ^$ t# A* H% o" ]7 r( c' ?/ T954498 SCM B2F SCM crashes when importing physical
: d g( @& n& S$ U6 H, h' q954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
+ R) }9 v; k7 @( G) |954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3% s: M9 C- {7 t: G( \& B2 L
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view9 D$ x+ U" y2 H- N+ b
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.. x$ Y; ~, s# t, g9 X& F0 p
955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window) ]1 O* d, Y% v4 q" B
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039. K! v: ^. N# _0 J
955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
. M7 D3 E0 s, c' Q955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL$ O) ?& r# Y/ {+ ~- F! \
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly, T. t* H; w$ \; O, U z9 l6 |* G
955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass
/ s% p9 B6 @* {& Q+ x955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void) B& r# ~0 ]5 N9 Z
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.9 X; u( a5 w5 p7 F
956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
q& L7 ?' m; V7 W956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box." K. _& b4 ~' y( h4 v/ Y* `7 G0 T+ y' o
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found0 G% Y) W7 s: f. n( L X8 D, {
956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined
; r: Z. x+ X; N956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board
9 t1 E) [% F3 J956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component
# L1 c0 P/ O; O( R956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly
8 v- E4 X" P/ |- ~. R% A! h+ e956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
) @% D1 f/ z3 V956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results" A! B* {6 b. w' Z0 E9 n# ]
956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
3 m( n/ n8 Q+ p, D* a4 }: l957009 CAPTURE NETLIST_OTHER Problem getting database property in mentor PADS PCB netlist
: S b6 z# t$ h957137 APD DXF_IF DXF out command dose not work correctly.
2 K J% U. R3 @' V1 F3 o* S957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
9 a# c2 z2 K* y# G% f957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.
6 E k7 Q- Y( J% g8 N+ F957267 CONCEPT_HDL INFRA Packager Error after Import Design) I( Z d$ u8 k% T& i7 c1 H
957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file$ N( J8 F/ @( i4 @8 y
958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.
0 ?, H' f8 N5 p& ]958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design9 _& g2 E' r0 F0 r8 d) y& S5 D: B
958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
& E- D, z5 r L% J/ D, L958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
+ X' P) _7 q/ d, n+ F$ G3 `4 l958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
1 G+ N" g' R/ T. a! R/ x0 Q: {" E8 ^959011 ALLEGRO_EDITOR OTHER copy problem of via and cline& J+ e% L% F4 Z& u9 ]
959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs
( B) ~) s/ c/ U; p3 N* m3 G959253 CONCEPT_HDL INFRA Design will not open
+ i- S' i5 |5 z( q6 `959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
7 b% f. H5 i( F/ Y: x: b959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.( S$ Q. m8 v- |( w3 a2 x3 F
959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred& b$ L% ]6 {$ Z* E& W% ~
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.5 D1 p; ~* F: c
960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
4 s9 q6 l' X' z4 m# `# f1 B960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
6 S( U% V8 A% h# {4 P961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3) E' N* `* o0 n2 `. ?0 K
961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol7 B2 s8 \8 z# X5 r T5 ^9 f
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers* x( [6 [9 t, {# s" a7 R
& ~1 K z$ d+ T2 J, y2 f7 ^DATE: 11-30-2011 HOTFIX VERSION: 012
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3 A) U8 t4 b, }! [+ l) CCCRID PRODUCT PRODUCTLEVEL2 TITLE
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9 l" s# G: c6 c5 ~7 H q959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats
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DATE: 11-18-2011 HOTFIX VERSION: 011
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. U6 X5 _7 _/ \5 J! gCCRID PRODUCT PRODUCTLEVEL2 TITLE
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735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape
% t( |1 a! U2 Y: Z894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?
5 {1 G- Z& U, X- g9 b903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
6 }7 P0 F+ z2 d9 c909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?3 ~% ^' \( {: {5 [
911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.
$ U. w! D/ E9 |" H& E919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode6 z; D, d% H! e2 t3 j. s. _3 G
921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined
. p; @+ q0 E. a' ?% j925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once., F% E3 g1 [- Y, i
926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows# e5 H0 h7 p9 N. D9 D( g
927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list
$ [$ ]. w/ v3 |' D8 S934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.
5 Z2 J+ W$ q* q, s/ l935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic5 R' N* W1 T: S+ `2 ?
937165 SCM SCHGEN Can't generate Schematic( C' j7 B* N; t) L
937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search: \( h o2 C1 c2 M) M% w. y
937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails
1 |# q: b: W( J939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License
, o/ Z: ?0 p7 B/ J' n5 y e940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup) T0 u) t6 K# s( a
940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in9 {& c0 q, a4 X; O$ t$ w. u. a
940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad4 N3 ?1 h4 w* P7 `9 W m
940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.3 e8 n9 P5 }- s
940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq! v7 p3 V' O% P* f
941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups7 Y6 x4 r2 h: @9 S
941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.
" I& N6 a7 ?5 v+ `- Y5 e2 Z941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script
5 V7 a, b$ `5 u# Q941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?
! y% L# B" I5 R6 g% T942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture
8 A& L" a ?6 u942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel
; F' N4 [: ?' }- \, U9 y942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash. A+ r: I: B% ~, w% l0 e! H) e& U' [" k
942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon
; ~7 V' M8 [& v9 i" V. a9 ?- B942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.
3 b6 Y7 u) A5 p1 I P7 Z942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised2 t8 Q# e# O% x" k* U
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.
5 z6 w0 q4 v" U943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup
; w7 a( \9 U% T944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently
, a' J2 Z5 L2 v; V944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5
! g8 _& ~1 d! n* ]' A6 \. l+ Q944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines/ i a6 f% _1 ~. @" p8 }0 {
945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints
1 `7 p6 a0 b# K0 ]+ G( \7 M! U2 R946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.51 O" C& j; \6 @/ d* w8 N, x0 j6 c$ E* Y
946350 F2B DESIGNVARI Variant Editor rename function removes all components" \5 k0 D! I. Y; n1 {. ~) e- [
946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?
" j' t [! N. x. q946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form# J6 p6 d5 a- } Y* {
946458 SCM SCHGEN Schematic generator adding an unnecessary page1 a. T6 X/ z: n3 ~8 u4 e% G
947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC
! P& e9 H, {( }7 ?' e947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.0 H8 T: K2 v8 A( h& h
948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM5 y* [* p+ I3 \ O4 s0 a
950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.
, H" G6 P" u0 g1 w5 q) e6 X951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved
0 H& D0 ]: f( U( _& b3 M5 h p9 n951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original( M. r1 q7 p( s; ~
951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?% X5 K! W5 G% k9 n- k4 `
951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages
8 t0 @/ P! p3 w1 p! j% @/ p. g951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5& s, d1 I8 z( g
952057 SCM PACKAGER Export Physical does not works correctly from SCM
: @) T/ ~/ t5 l952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor
) V8 O# @- j# W7 o$ m952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5% |- `1 j& x( y/ {
953018 APD REPORTS Shape affects Package Report result.
" X3 n- Q1 r5 g p/ c* K: u \953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.
' ^+ P; `) R: h" Y4 e953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro
2 R# s7 ]& r% m. w, G; F953918 GRE CORE GRE cannot route second and third row of pad in die symbol.% F/ f# |5 n& R, x0 a
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path
/ Y0 ?$ D" E% ~, e954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report: ~7 Q0 \; \6 ^/ j7 t
, ~2 a5 i# \9 x6 ? IDATE: 11-7-2011 HOTFIX VERSION: 010. V3 S& F5 ^" ]6 g* x* J# _8 w. V$ {
===================================================================================================================================
0 _. z+ b4 K" v( F2 _" ?CCRID PRODUCT PRODUCTLEVEL2 TITLE
" { d5 s1 ?& A===================================================================================================================================0 F. J) }$ P6 w$ M1 `9 x2 s
658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline
' k$ n* a" v2 o- A7 x3 j928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
; p% B7 o7 w7 N* x: v/ i2 R934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile u; V- p9 j l4 \1 b
938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem
- d2 G' M a, e, x% f2 U! o938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.; x! A& h, j& s' _
938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer
% D2 I; i; v# m5 J6 M v+ ^940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete; G f8 w/ f- E9 L8 W; G$ `" B, o
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!: W3 J. @1 L# y6 d* C0 B* ?2 M' |
941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning/ s% D& I& G! u9 ]* E
941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen
) V# Y% c7 f6 @- t942914 SIG_INTEGRITY OTHER ZAxis delay calculation
, \+ Y" c% Q( w! L/ f943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash
3 |' t! u! S" U; }945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die7 S8 [8 b O+ ^# G
945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.+ O) Q, A' @ e1 [
945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.$ }+ ^: N0 X; W" Q& E, y
946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions
7 o% q8 P! F$ Y% C, D946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch5 O, o; G: L" S# L1 y
946819 SIP_LAYOUT DEGASSING Shape degass command. n( F4 k h+ q3 _; t/ Z G
946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up
( U0 Y3 ?' @/ M947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3) `- S. M$ F, S% g2 z \
947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file
) r1 z, n9 j% M3 P% F$ P: X950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic3 h% |! U8 N$ M x" d
951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37
* N" z2 d6 B: q7 Q7 Q951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol. K% ^$ }4 g8 b9 k1 ]$ p
# L2 H1 U/ X% a5 y6 @; oDATE: 10-26-2011 HOTFIX VERSION: 009
5 w3 z( `0 h& m( {===================================================================================================================================
2 r1 h7 v% y: q& Q8 q& w7 ^CCRID PRODUCT PRODUCTLEVEL2 TITLE
( O9 k2 a* f" }; k& g===================================================================================================================================0 c6 K0 }& ?5 r$ I n* C6 i
945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet/ d4 M6 T' O$ s7 X C" A! [( ~
945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference3 y2 b$ x6 G6 L6 F- \ j) ^
/ X2 m6 R! |; `% TDATE: 10-21-2011 HOTFIX VERSION: 008" e' G- v3 y% L- `4 Z+ |
===================================================================================================================================, [8 n' s0 g: ?* r1 J
CCRID PRODUCT PRODUCTLEVEL2 TITLE& M# W! x5 @- w7 m. G* m( O
===================================================================================================================================! Z" a: h# l1 |/ H; Y- |
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.
' t8 x2 g. j7 ? P ?923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5, b; T; k; E) O @0 ~/ t
926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it
( Q5 b8 ^" R' `' r( P0 Y929348 F2B BOM Warning 007: Invalid output file path name! W3 ?- }1 ^/ G5 E+ q* j9 d
929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error
' R8 W1 t) N) y/ ~930783 CONCEPT_HDL CORE Painting with groups with default colors j( F$ s4 T7 ^
936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
/ Z% B! a" K* Z% S2 I+ `938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR) \: P. V5 j' ?* p
938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins) E0 `% E- ^2 z" k" p' g
938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason., t. z' W% E2 ~1 ^
939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window
& A# i$ p" r0 m+ J939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.3 q- H0 b- J! ^4 J( q; T6 [9 O7 \
939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)
" [) Y, Z3 B" v; t939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.
) ^% B) d+ g7 {9 d939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.
0 d I0 n& F7 ]939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.
) s9 R+ t" d2 U2 r# [940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'
0 x0 L; H1 e( N) f* B' G7 z940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost2 p0 j4 |+ M7 K6 t% V- f- d9 ]3 U
941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks
! W6 l8 z& r$ n4 a- i941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
K% ~ C( ^' I; p, l) E942210 SCM OTHER Is the Project File argument is being correctly passed?
3 y1 J. X1 f- w# X! ?* L' R942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache1 C9 ]# p7 L. k, [ u( N! U
942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible
O7 s5 |9 y6 c# A943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash
5 F* L* k1 c1 E* P) [8 v9 e- O: Y/ {3 @, k
DATE: 10-21-2011 HOTFIX VERSION: 007
2 f! M# _3 J g; u===================================================================================================================================
% C; m. R- |# l# z7 Q: o# o% O; HCCRID PRODUCT PRODUCTLEVEL2 TITLE
2 u$ l% a1 P0 ^: z+ \, s7 e* b===================================================================================================================================" ]2 S, S. [2 A
841096 APD WIREBOND Function required which to check wire not in die pad center., x- g! m0 B$ q' t; ?7 P! b5 H) ^
903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
- H: s! z( ~& a' Z; q906692 ADW LRM LRM window is always in front when opening a project" |& i) q/ h( {& O! I: A
912942 APD WIREBOND constraint driven wire bonding
, G) D8 c+ t8 s912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems8 h. ]9 K/ U7 Y; e" Z
915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design
/ y. k9 U& I G, e7 M3 L _" t917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
9 ?1 G% S6 N) w& S/ F923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure
0 V: c4 U& r( @2 u& a* f g7 |927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license
4 |/ p6 s8 C# O927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp7 t4 p4 a; V5 R8 M$ c3 \% I# K/ q6 y6 P
930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one
7 k. r6 P t$ d, ^. [+ { X930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation+ D3 w7 ? N# e1 S) Y: M
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.
3 R8 h" x0 t8 {; j9 Z4 D( V930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
* U* E% r" C" V# k; X( w2 H930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
# j& t5 ^7 E! F" a x, i0 l! m! s930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form' Z- Y1 ?3 u$ S: p, Q# t: r
931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC. T5 u, F( H J0 W2 v8 }9 P
932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property `; K" L+ Z* }
932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear
% }7 k6 T% p5 u& \7 d' U! d932292 ADW LRM LRM crashes during Update operation on a customer design
, n- z0 x$ W0 p5 G& d+ a932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.4 U! A' o" |/ D5 c* u) v+ t
932704 APD DEGASSING Shape > Degass never finishes on large GND plane! x" ~( T: F! h7 ~( r% n
932871 APD GRAPHICS could not see cursor as infinite
- |, z0 J: u% f+ f1 j932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
1 t9 G! g/ }& [: D5 t4 f+ x932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
/ v3 |. X- |& X c$ X- l933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members
$ ?7 T' Q$ P* M933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
4 i, M2 r" j* K" Y z933214 APD ARTWORK Film area report is larger when fillets are removed
9 t, r% \2 \% Z! m. @933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
: m$ N1 j, r& ^" P933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
1 T9 g }, L7 W3 r6 j933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.8 U3 g, z2 N. F, C
934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values2 |9 P+ e& o4 }9 r) X, N
934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs/ e: r9 L/ V! N5 K! m( h+ D3 ]( l4 H. B
934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash
2 C) L8 [6 A2 d- P# v, l934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.
9 q# `# [4 i! S8 ]$ s934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
, I: E9 D6 k. H' i( R934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound
( m9 c3 D' R. ~; D+ R934909 SCM UI Require support for running script on loading a design in SCM
1 h, @' M/ [; c" d, f! _8 }935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.
0 u# Z( K4 e/ ?$ |1 P935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.39 \) ~( x' o0 P9 K$ w6 }' ]
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash
- o( A' l( L3 t. U# {; g! k936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol. f) w H8 A+ q! M( n4 t
936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.
* k: r- s! ]5 h$ ^( o936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack
h' x3 u% K% }' w n0 L936797 CONCEPT_HDL COPY_PROJECT Copy Project crash5 j7 L0 u5 r" u9 b# \
936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol( I5 _" ?1 ?4 I3 G& Z) _2 k0 D
936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM
9 _4 [2 R9 \* S% M3 ~5 ^3 u937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE# N3 K( H9 o8 \, H& n& d! ~! K
937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About. E7 P& l# M5 w- L$ @, j- L
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.1 y7 ^1 k; G6 A- V0 F1 a2 ?
937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.9 C7 H" d2 v) U( H1 H$ y
938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.
. `, f8 b+ H9 u ^6 `938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set
0 b& t* v! ~# q5 Q( ]& s# A! X6 h2 B% V3 J7 O
DATE: 09-16-2011 HOTFIX VERSION: 006: ?& O0 G+ n5 a* h- R
===================================================================================================================================
& g% S; }* Y. ICCRID PRODUCT PRODUCTLEVEL2 TITLE
6 {% d- w" O5 x& [8 p6 M) z1 P/ o0 w===================================================================================================================================
( w+ p1 h5 B6 A6 p1 O) M820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.
) ^ f1 s6 Q; S5 {863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints
" j0 B' s3 A5 `- q# X: z919822 TDA CORE Cannot configure LDAP to only list the login name! o) g5 {: ^) Y* M% z& S" g
922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error
* s8 B& z$ u3 {7 k% d5 U% }% \924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results
8 _; O$ }0 |" }4 c; f' @+ F, Q l924448 F2B DESIGNVARI Design does not complete variant annotation
2 G) l2 a3 O( U7 [3 w, T925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB
$ K7 E+ @# B* v+ \ `4 c# `927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report! s" b2 b8 ]# s5 l/ ?
927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values* ]6 Y1 z$ p1 y! r
927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line
1 ^9 {% P: z- ^1 y1 m5 g4 |927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets$ b! W; W0 z8 V4 L4 V" P/ P6 g! `
927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
9 ?( M6 f7 @& u927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl5 p$ f" r, z) K9 s
927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display) R+ N9 h& @: b1 M5 Q4 o/ T' }
927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database% W8 ]' j$ d! P; n; S
927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.1 D2 z& x( f/ }' k8 X
928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.$ Q/ h; v1 k# J# Y
928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list" _* G( B7 j& n6 i# N( z
928738 PSPICE PROBE Y-axis grid settings for multiple plots- F. ^5 A! o( R4 ]) y
928748 PSPICE PROBE Cursor width settings not saved
% V; t- s5 F+ m8 {6 A928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release4 M7 M! n3 N4 t1 }" @$ C
928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.55 s J0 h3 b5 i! L8 U% @ u, y& l
928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe
- j0 W$ x$ `9 J( }6 h; s929284 CONCEPT_HDL ARCHIVER archive does not create a zip file6 L, u- ]6 r Z1 [2 i
929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP
8 T8 f6 |* `5 S" D% S929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error
f4 {4 H6 D2 p, [- u! [; o" S930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape
0 w+ L" t7 T* g3 B930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP. P N. u5 P& R& B
930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
/ O" U3 r$ _1 R( n. e930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.
9 |+ @ r- h0 k, N1 Y$ t. E6 ]1 Y; t( ^930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well
# e& F' h- y' c& g- _7 _* P7 m930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name
; Y0 h) `% R4 U3 q4 J930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked" t+ e3 U! V! l. d' ~# I# v+ c+ q5 N
930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens' i% r9 Q7 ~6 l, k" Q y7 O
931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.
' d, p: w6 B2 |# k0 W& ]' K. q# b931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version
+ z0 H: f+ P; B9 t1 O) W931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.5 s' u. v% U+ V
8 M5 F5 n3 ^) o: H. k$ }) j
DATE: 08-31-2011 HOTFIX VERSION: 005
: m3 O, ]: [( p===================================================================================================================================
% e, L% ^0 I8 [2 U/ ]' hCCRID PRODUCT PRODUCTLEVEL2 TITLE- _9 L, q: \/ e! j- q. h
===================================================================================================================================$ N. i( Q; ^; h6 q6 h: s) f
825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole
9 h' s5 V9 x3 W837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show
8 Y; F- j! [+ k; b& T) F891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode
* {5 [0 ^+ {- E. s! I5 R( H- D, u910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.
0 X+ V4 H; Z: z# t- E* l914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.
# F0 f5 m2 q/ ?! y }914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs
( \. J' U0 w# j [' w8 p5 z9 e1 v. R G914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity
( ^2 B% C7 Y! y* p915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location8 N1 v3 |6 `0 J1 w; j5 d1 k9 T0 T
915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape. e. R H* P" C4 R. W
915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working
7 S% |( T- }+ v$ N* R916321 CAPTURE GEN_BOM letter limitation in include file0 T; y( o/ T, Y, `3 @7 d
916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects! }" {& p" g+ h7 d* F
920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.
9 ?' Q# J% ]) N920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.' T& ~ M4 f) b% G
921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set
3 b& \0 F3 I; }: {* z8 [921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.
8 W( i* v7 G! k; d. T921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002% W/ {9 _+ {, ^/ h
921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions
& P% m* V& p- {% [6 Q- R$ z2 ^1 \921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly
( b8 H7 _4 T. B: b) g7 Y922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.
9 K* r/ I/ N' F& W/ x0 [, V922117 PSPICE PROBE Label colors are not correct in Probe" z4 e6 n6 Y$ A; N3 {# w
922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all1 j1 U: v# f, c+ o& V% ^; h
923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002 H; f) d- `- \4 X0 Z2 b: C
923286 CAPTURE DRC DRC markers not reported for undefined RefDes
! ]+ t5 R& x. s$ v( G923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5' S: O+ F9 _3 \6 l K* X1 ^9 H
923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top) c9 S9 r+ u, c+ _
923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)/ i8 U+ p+ k: h2 I9 {1 K& u
923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.
0 F5 i, u4 O; ]; ?923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design
0 l/ }. @) }( K3 V! u1 ?) Y923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on
. A$ N/ X- m! Q$ G" ?) Q923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error
6 \) _$ ^" t5 |) a/ A( I6 N3 U- G924458 SCM OTHER Project > Export > Schematics crashes
- `- Q5 W" ]# m924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
# T S1 I6 G0 V, Y, m% _925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect
4 E; ]- t3 {$ G; F. L925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error3 w' t( T# T. o& n3 M) |
925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
1 ?6 l# p5 H9 j, t, @1 F+ K5 B925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.
, j+ d: W4 P f% d: b, D' E) V925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?
+ L$ U* ^7 L+ C7 }925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS. D" t8 H& v/ W% u
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data
1 V% J |1 w3 u, h# V: D926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.+ Q9 M% N$ r$ H; d, I* X- K* p% s# ]
926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.3 m U# N# E o3 }
926503 CAPTURE GENERAL Memory leak Capture/Pspice+ ]3 @0 `" Y6 p$ E# j+ h
926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet1 t2 [; _6 m- `* }) m9 _! l
926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.
+ O1 U( @3 K/ Y L! {926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical' {( F) m6 E5 n# a! a7 R
927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is '') |$ f6 ~5 X# B' o* d
2 \0 Y0 _9 |+ E9 I- i! C
DATE: 08-19-2011 HOTFIX VERSION: 004
. ~: p, H+ A+ n$ }0 ]===================================================================================================================================
6 s8 n& S6 \" d2 W0 k4 q' kCCRID PRODUCT PRODUCTLEVEL2 TITLE
1 J1 z" @; N7 v3 ], H===================================================================================================================================
2 O- O- L% [3 m! T+ o785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error6 x |) U8 _- K; s3 b1 [' u
851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.
: I& Z% J: ~; t# a868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments
% P; `+ u8 `9 v g: O, q# @870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file! G; t) H3 P( Y: l. I, o
877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form! U4 ]' I8 V% ~" C1 ^4 z$ M% v
894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window* y; u* w, x2 }! K9 f
895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1, U# ?0 L. I, s
895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement# E! `, W/ I) @& A* A: i6 j
903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.
5 ?5 ?! w L$ \( t+ c- l% s6 g905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.! Y) ?; r4 b% E: a1 B
909469 SCM TABLE ASA crashes when opening project! p# d5 U( L W+ z" k4 d: w
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap( _3 U& f- A/ l0 g H% V) i5 y2 f# P
911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152
1 n( H" W; q/ a; v911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?' Z0 q$ \( j$ r4 Y% o* k; H
915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability
% U7 t" b% u! K1 O; ~915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP
* C# @( ^! h2 T# p* h916062 CAPTURE GENERAL Auto Wire Crashes Capture" z$ P% R3 R K6 Y
916820 F2B OTHER RF create netlist with problem
0 y. e3 b" i' j7 [' E" t917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.
c/ [ b" s0 b3 f1 O' w919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file
/ Q9 I D* V% j% l& g919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working
! O- f. @" j3 q% r919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL0 J4 C Q# ^! c8 U: ]; g9 D
919976 APD DATABASE Update Padstack to design crashed APD.; f6 a7 G3 j, n8 i2 C2 {' {
920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition
( h; @! P' ^0 N* g6 w) z920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run
, L) }$ ^6 I% ^) D" b920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork
2 Q! F: v6 d9 T; l6 _1 y2 k920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins" W$ }7 y- S& E! ?' I5 W
920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min( }& t4 u5 P! w6 m) E9 X& ]$ b& u
920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net
( v% a X9 ]0 x4 T0 i4 W921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.
/ I2 d& L. h) B9 G( a922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
+ y1 P6 H2 g# q! z% Z6 s922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named% N; V% b8 n! y* q1 M0 Q
922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin w$ c" o/ B# W( _
922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.
* d! K- N* h$ y923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log.0 E D' q* b( _ K3 E' L' {
924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf# Z0 p" ^4 m+ N, _ }( L
y- o' a8 ]5 Z/ c- w% H" `! i! U7 m
DATE: 08-4-2011 HOTFIX VERSION: 003' e5 l% m: v( M6 k! c* Q. I( P/ }
===================================================================================================================================
7 Q2 ], }% p* T5 |7 L! }CCRID PRODUCT PRODUCTLEVEL2 TITLE
% _/ d% H+ E' q4 l2 H===================================================================================================================================
3 w9 ]# D$ D+ q* b787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.
5 K4 d1 j( @/ F1 g7 j4 K7 I+ D903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics- b6 _4 `$ H1 W$ G* i
904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.
$ q. ]. t# j2 i E2 E3 C" e904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result
3 T3 _ S. k- l905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged8 x2 R6 H* @5 X- [8 q
906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.
6 Y/ P' b; C2 M0 P0 P6 [908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance
6 n3 N* g2 s& X) `( y5 ^909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.6 e/ ?. E5 b4 e0 ]: X. H0 X
910315 ADW LRM Import Design with ADW causes partmgr and pxl errors
+ i. h+ i$ i9 J; D& R910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5. ~) _9 F$ M! A9 V3 h
911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5( \9 A! G3 i5 m- C1 M8 w, U
912343 APD OTHER APD crash on trying to modify the padstack2 X( @5 o: u- J0 E0 B1 f: Z1 x) ]
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys
$ C0 I3 i5 @+ P, R$ c# Q+ P912853 APD OTHER Fillets lost when open in 16.3., _, _' k2 K/ X9 Q; \$ j( A" X8 c
913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.
0 w1 D3 K Y, B+ T1 R. O914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.6 @8 e- n5 @1 k0 I& \) z
914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks
) o) C) v+ W8 w6 B+ v9 O914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.
0 m% ^2 [9 X( l, B914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design5 V4 H3 L( e8 H; Z% {, O: ?
914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape
5 v% D% a2 X, \5 ~+ o$ y1 Y914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.
& g3 W3 e1 U* d3 V$ C7 ~3 E914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset
( L3 }+ T& O, u914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.
6 {6 J% t5 k& H* o4 t6 s914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling
9 g; m- e7 l! u& i915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.35 L7 t3 @/ O- u0 F a
915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models
* \- d3 B6 \' r7 G915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol
0 y2 [- W& t( G916154 SCM NETLISTER scm crashes when exporting physical database to allegro
7 @# L- }, z9 E1 p916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors3 `. h+ b7 V! C9 m5 z7 S2 R
916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor
+ C) N0 a7 B5 N6 W; B+ U916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report+ @1 h( z: U' k7 l6 P; a
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer
* q; A5 M# k7 b$ V8 }) M7 x916889 CAPTURE NETGROUPS How to change unnamed net group name?1 n. U" e8 |3 V- {' G4 h
917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film
- a9 w7 ^5 L* C917434 APD OTHER Stream out GDSII has more pads in output data.* z3 d; S; | j. x
917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net( J* M; l b0 N
918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.3 Z0 u9 d/ \* I
918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol
/ o- ~' ]$ \: M. c
+ T! ` q; ?4 z9 [DATE: 07-24-2011 HOTFIX VERSION: 002
; z! q) Y- j/ T% A( k8 F===================================================================================================================================. V3 V K# t( G
CCRID PRODUCT PRODUCTLEVEL2 TITLE% s& X, g) p5 _1 n- D8 a8 u& T# ~) \6 i
===================================================================================================================================
: _" U' Y/ U6 t527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings
$ q6 A8 w4 p* } h3 ^* h$ _& t8 Y7 k583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings." |0 r4 Z" V4 Y: Z
592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.
# B) g, Y7 `5 e: l: K. R% s745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.2 C: s) i6 B# u9 L- x3 I; h
773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3." Q9 Q) c( q: D. y/ F1 Z2 x
774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.- e( i) L6 ?! j; d# {
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs8 M- _0 B+ i6 N N5 H0 A
809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".$ `* _- `. ^2 [2 @
810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
. _# a' X. O8 R4 j821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format
7 f6 u4 W h9 T1 w C831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself% t. i9 W) e/ c2 j- y3 q9 b; O
842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.
% n7 @2 k1 C4 n6 `854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group
& R; A' j y& A: C860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser
( ~8 Z* Z0 p1 x/ B2 V867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"& f! |+ s! Z1 E
868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets. X, J' e3 a; j- s7 {: b4 ~
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE v' C4 \$ a4 n0 R% ~
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments2 `% T4 N/ D6 @
893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.* Q j# E9 E4 Q# h+ t" D
893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.% S. L4 C8 w: a. d4 k
894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command
4 W0 f4 u9 [- b2 B895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs5 k; l: q4 \6 z! s
896598 ALLEGRO_EDITOR PLACEMENT error message is misleading& W# k! d6 ?( G; ~ x* W8 Y) B
897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library# t! u8 n: i+ D( t4 Q* D
898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.: _5 C- Z9 [7 O% O3 a
899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.9 u0 C1 w6 g4 P, f9 J- J- V2 _
900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5# R# N- M! t3 n) ` l+ k* S3 z
901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.
" ]% i \9 I) o2 M3 Z901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page( H$ h+ b% G' x4 V
902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
7 }" Y( W- V* g Q4 o# H; u5 ^902349 CAPTURE LIBRARY Capture crashes while closing library+ ~+ ]+ o1 g7 i
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3
6 e* T$ q8 j8 i: {902841 CAPTURE GENERAL Capture Start page does not show
! k1 f, {. a) d3 q902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5 H9 C% N- E x
902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design9 h) k: ^" i6 E+ a7 H
903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?) z9 d f; d; R
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition
* X* S, a- M" ~903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor1 c S9 N4 \ m' l8 w5 \% O
904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable
9 `6 k) [) N( |. W/ [- X; P l904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE$ I. w: v9 R8 l9 w
904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3% \) F2 o! q2 }4 C
904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places- F6 J" b+ N" n' }; |2 R" l/ c& r# `
904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue." e9 F2 v: x: G: s2 T; l
904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3
- B* h$ n1 }6 Z6 }" ]# M7 I905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
9 O4 v! N+ K( e905314 F2B PACKAGERXL Import physical causes csb corruption
- k- V) y6 E5 R9 |# w& u905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.( z6 }, z2 D8 P1 l+ B: Y
905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
/ N8 s# P8 k' N( K' Q905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues$ f4 i/ P) M+ z" y* y5 \0 s
905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid
( [ D4 M* T, t6 r x5 Y" F- J k906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.* p( K# E/ L; O2 R2 t$ Y
906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
4 k+ D! G$ S4 N6 o& Z1 `& E906182 APD EXPORT_DATA Modify Board Level Component Output format2 X' a5 [; f: |
906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element+ ~8 j* K9 I) k! x7 ~ }9 d
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.
; f; X# J, p/ O+ h906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.% v% M; F+ r) B3 u, f
906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run$ Z; I5 d8 b% y9 R- s- X+ H
906673 F2B PACKAGERXL Ignore the signal model validity check during packaging
+ {+ ?4 K% Z4 c) [* `8 V906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'
j* ^2 J) S: J4 U: {! O1 I906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation3 i2 x9 U2 P2 c6 l: x
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin
" L# `& z2 @3 U4 X" t907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
. ~* C. x% E+ o4 T1 f0 T907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display2 a( Z. }0 I8 k+ `! [; `! t
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.9 W, W0 W5 A2 A: K f
907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"
9 @/ [; Q, m6 B g6 k! T' }907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31, D$ @3 X! G( i4 o
907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly
+ W' _/ j: }* o% S8 C; g907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional i; T5 C: k: I3 @1 D. z: m0 C
907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
9 ^; h o7 I" X, d0 I, r2 u; x908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.5 }* t( x. T2 q
908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name
2 L: a1 l+ ^! R1 |% Z. Y908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.35 y! t4 P/ K7 \8 N
908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component4 q" `+ W' L! O, G& ^& P4 @
908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5
% y1 [7 f8 p% K* J1 O) A+ i. T908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place
1 ]1 s2 F3 [8 }. r% _5 n6 W2 _908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays
5 ]2 [+ h& q" S2 i908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes
8 w8 S) J9 x* E3 ^908595 APD 3D_VIEWER cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b1 v1 ^% Q0 U4 @9 m1 \' _: \
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design
* E; u- C5 f7 R$ C/ n908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature, l& Q; H: }0 u$ D( u- P
909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN7 _: `! C9 ~" B3 } V
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.
$ n0 s. ?* n& \# n909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux
# M* z5 \( R; k: W3 x1 r) A; X' Y909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
; ~. \7 L3 ?1 J909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning2 ]1 b/ I6 x, l
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack$ r! K7 F5 u+ A' C
909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
1 x8 T" G3 v. e2 L, d$ P' g910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted. x% V! c8 S" F# i0 J/ s- Y
910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector+ m- \7 q& n4 m+ E3 C/ D. f
910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.
; T' s% T2 f9 r" Q910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5. ]# j. c# ?6 f6 P$ P1 d
910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.
) C' g+ @% z3 d! R' u910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent9 f7 R/ j9 }/ @* E
911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
2 J* S9 `! }- x- K6 B) u911631 CONCEPT_HDL CORE DEHDL crashes when opening a design# V. H1 d2 O" x) m1 s/ U
912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default9 m! H# f5 E3 x q9 X
912459 F2B BOM BOMHDL crashes before getting to a menu
2 a& W* L) p' p# d; O913359 APD MANUFACTURING Package Report shows incorrect data+ @1 M& H9 @9 H
- Q1 i) g; J$ E! Q. SDATE: 06-24-2011 HOTFIX VERSION: 001
0 q b z+ h5 l5 z===================================================================================================================================
6 _5 [5 E: t5 x2 B8 k! i. x SCCRID PRODUCT PRODUCTLEVEL2 TITLE
$ u' R; z# i& }+ u4 @===================================================================================================================================
. Y& y' {6 C1 b6 a/ C: q4 e0 R293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol" ?% {+ z! q% V6 C6 _% }
298289 CIS EXPLORER CIS querry gives wrong results
r. P2 p$ y9 @6 a# u366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text4 J: E( K/ S& r2 `& a2 L$ H
432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs( i- K" L1 H a3 b0 ~
443447 APD SHAPE Shapes not following the acute angle trim control setting.
" A1 J4 s& I, t! \1 i P* Z473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam
- T( w; Y. r4 u+ O9 i517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy. N$ X; e" h' o7 y& q
548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.: X. V% g( ?! m( Q7 T
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart4 n* Z: |' B4 i0 n$ h+ d: m
616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled) Y: y0 U; _( N+ q
641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)
# b, g* q7 Y+ \- ~644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor
) f6 H2 n9 D, L5 H645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board
- J5 u+ K2 _0 l/ C3 ^725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.* L* ~' \% U! e7 J6 r1 }
763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI
- t; q, M$ l* u6 A6 ]: |7 H770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers' w9 w5 y8 o7 {- `* a
792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets
[' G5 d$ b% Y6 W, W* q799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write
5 r% H) U- m0 `6 `5 @% |803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part5 R- Y2 i8 v9 t4 _9 ^# Z
804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.& w3 p& w l1 J) a& T7 [
809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs! ~$ i# A' i3 V8 U- D7 B
816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch6 f% M" h3 _/ q/ B l
830053 CAPTURE STABILITY DXF export fails if schematic folder name as /( D; n% J6 o/ L# w* H2 } x- m
832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.$ C7 n% C7 S6 d( L
833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
3 z" r9 Z/ w, Z7 N4 S* U+ F, M835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error
/ J; ?5 U: J2 u: i1 Q837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version
# I% ]3 i3 }+ T844074 APD SPECCTRA_IF Export Router fails with memory errors.% ?# y& T+ @4 ?8 g: c# q
851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size7 Y& M3 c$ ~+ P& I' h) u" X. @
852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?
2 A1 n' H9 J- a# i0 f855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.* S- K# K3 `6 [+ b4 p9 {, W; J% x
859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs! F# { I8 r8 z/ C3 g- e3 P! W& q+ \
866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.) D( c5 ?$ I0 V2 U: d1 W
866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line$ t- `" j! M7 Y4 ^* b
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF
. b: t# B5 G( i) d, ^' \868618 SCM IMPORTS Block re-import does not update the docsch and sch view1 H2 J+ `- Q2 R1 N9 G' f9 N# H
873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP
1 u0 q( e- d T b. C874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.3 M0 M2 w$ ^& x5 Y: `+ u5 f% S
874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command/ l6 Q" B2 s! Q- N
874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file
8 d1 Z, I2 p# _) q875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1
w# P7 M1 T( e8 @876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net& @) W! _; @/ U! Y1 D* D
879361 SCM UI SCM crashes when opening project! s6 o( ~ E7 C+ C5 M0 x, G! X" f
879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.
1 Z5 H, `! m: Q879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE.
1 I. b0 [. u0 j+ ^9 _881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape
4 m5 [, o# y ~882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets
, s2 C4 R0 t/ {3 k5 h: k5 A; I1 p1 U882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier7 m( J" x: X0 j0 S# X# E
882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.
' Y2 z6 k! e" ~& }% w7 y) H" v- o2 P: G882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement
! t {; w& h9 B" r; I883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component
5 a( M2 O6 _ C7 g& f% P* L, r; k/ ]883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager) L7 E4 q1 h* s& i& ~$ H9 s! D
883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder
5 o1 a' Y) Z; x9 p# f8 L4 J885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.
) P7 z8 G7 x" t885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string
p- h) i* R, P; |- D, M885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations
+ v: {) |9 R' i/ c( H/ `886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid* h6 A2 J4 r7 I, ]- N
887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses6 k* {4 g/ o: y7 r
887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.& R% h/ _. o) e& u
887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message
' }/ V( c* S: w, o' i- ^887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane." a, E. o' `/ O* D
888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.
! P- Z* Z9 [# o$ _888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic, v5 M' ?5 J. H* v( w
888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.. L1 I, j0 x; y% g/ T! _! f6 ?
888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.% E& O+ x% r+ N/ E9 B; E
888945 CONCEPT_HDL OTHER unplaced component after placing module
$ e+ @$ U$ k8 N9 n$ }) a889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.: @8 r% p* Q) A7 @
889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3 l" k* P: W, s1 w, m
889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.
- m) |; P( J: q" y889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net& d4 ?. O% Q1 Y7 B
889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form
+ d; o* z7 y+ h4 R- u5 b: \* P9 v# @891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file
0 p6 w, y" A- w6 G' K3 c891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance) ~2 X, ^8 D( S% y; q ]$ J
891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs
5 m! o, O- x: P892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
8 h9 h) f& r" Y6 Z892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?! _6 Z! K4 ~$ F! W7 @$ e
892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness
) v$ r/ d( E' Q+ U1 l2 q892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode1 n3 d0 e7 I) U- L* f7 m/ I' u
892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations
; c' q* R2 u+ q1 a, M |: \* n892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR
/ ]; ^ h' h. o* g" p2 {; X892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".6 D* E% o. X2 K2 W1 V* U/ ?
893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.
: e' `0 ~+ Y4 w; L+ A893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board" D# k) z7 N2 _; E9 \* L0 f
893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.
9 A, T3 V1 ?3 c2 R893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation
: r, ^8 P. k( S7 V0 ^8 G, q894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.
' b0 S- s n2 I" ?5 ?! Y894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.
' B- T: D, ?% I9 X$ G3 i' {894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.( P! J% i5 k+ w7 f0 b6 B, E* i
895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON8 d+ U" X- [9 T
895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers
& P# Z5 p# K/ F) r6 u/ d! t4 _895757 APD ARTWORK Import Gerber command could not be imported Gerber data
: S8 c4 w* N7 p; N! i2 O895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly
% P# j5 w9 b9 X, O0 Z2 a896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced+ E; l) Y% S: q# a& D. ]0 `! P
896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture ?& Q( ^6 w3 k0 F9 S& y w
896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing
0 z2 Q5 l+ r4 m" u897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap." w- P1 b. `: I2 B& {5 P
897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.
. K, n/ S* `- u. O$ n& w e. i899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing
% g k+ I4 D# `% c899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof7 d4 r l1 i3 {6 l/ t9 y
900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
# U9 ~ X2 F0 @! G4 ]900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration
6 F' r1 \8 J# l) u. K" i$ |1 U900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.% k3 S4 M8 L/ o% V: y
900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.
1 @0 p/ P! l+ W: q7 b- E( `901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.58 _7 X% J. i1 W( c+ e$ G8 l
901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong" D+ b* L) `, Z
901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page
7 J1 L. _* q- q) e% d/ H6 j1 [902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic
; L6 D" h5 U# }902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file
) w$ N J" H6 m; X, P9 |4 C1 N; ~902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional4 V# j6 Q1 g; P! ] ^; F
902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization
0 h/ y* U& C3 U902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components0 k7 Y1 f7 n3 S, i+ v6 e5 O# A
902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes
2 u( ]6 ^9 A* I) p/ L+ k( ?902909 APD WIREBOND die to die wirebond crash
2 |# Z" u- c9 a# D, P, p. N902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body6 E Z( v& T5 i. g$ U( H! R
903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline, O- ]- i3 v$ O# ~8 Y1 ^- p+ `
903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.0 q- J) d% E4 {: o
904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
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发表于 2012-2-21 14:58
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