|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
! L& O4 I; u! c5 r- s
DATE: 02-17-2012 HOTFIX VERSION: 016
) B) q' B- T7 B0 c5 ?: o0 C1 s! M+ z===================================================================================================================================- _/ i0 U5 M9 h* ?
CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 N. C5 s1 \" s2 Z% O+ x===================================================================================================================================
, D" n/ _' ]' ^$ a6 o840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV3 F4 L: c& w. ?! U+ A
873075 Pspice PROBE Decibel of FFT results are incorrect.- ^$ R4 ~/ @& t
938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property3 o/ I6 G5 q! S Q
943003 SCM REPORTS The dsreportgen command fails with network located project3 Y4 \ Y' Q ~' W
961530 allegro_EDITOR INTERACTIV The problem of Display measure command
" i% t" I$ t7 F962157 concept_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?; ^' ^4 u; e6 L
962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend
/ ?3 [! [, H3 t6 s# z& S- P968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.5 g, n' P8 i3 c" W. f
968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.; [2 |4 _" |3 A! {1 f4 n
969450 LAYOUT TRANSLATORS orcad Layout to Allegro Translator crashes
' y( o: w. o7 Z5 R* [969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~
7 H4 u2 r; p" g" l l971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.
0 E7 y, d8 z( l6 O971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure, F4 n( G8 y& Z7 e# T ~4 I c
973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR
2 g& x7 K- A) {& ^# U1 |3 J973859 PSPICE ENCRYPTION Pspice crashes with encrypted model
! e% I4 f$ [5 ^# B, S973938 PCB_LIBRARIAN VERIFICATION pc.db is missing
6 }" z! ~0 z# K, n, k974540 CONCEPT_HDL CORE Graphics updates are real slow
0 o( Q5 \' X# S974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?: D2 Q) ]: g0 U+ D P4 H9 x$ C: o7 r
974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported./ o% _# M9 N' e r- q! ?
974945 ALLEGRO_EDITOR skill Why is axlPolyOperation is giving different result and not working) Q1 G: \1 i4 ^- W
974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology+ j+ M e# V5 l
975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.52 o+ Q* c6 P: q {4 s" t5 n
975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)
6 B& L5 @/ _6 g975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move8 o; d/ d& }3 I, b0 U. _
975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits3 E6 h* H( g9 U. G
976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.8 ?$ `8 k1 x/ m1 V
976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views+ Q* S+ M! w5 v
976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design
5 B; m) @0 Z- p7 `$ e* x" M, T/ y976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design1 F" n( d0 A! D: {! z1 P
976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC( L+ J |" P+ N. d5 R
976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value2 c' ?/ ~9 ^% }. B, ~4 c
976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash! ^2 E' d4 q ?7 l+ V( E
976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models., `) `- U* Y- q
977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3
5 F# A+ a/ u- R* \% X" t977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro
1 @7 c6 ~. l( o* \" M, Q- o1 {/ O978652 ALLEGRO_EDITOR pads_IN PADS_IN fails with ERROR: Finished with errors.
~0 P7 i+ ]1 F$ T; E+ C978744 APD DEGASSING Some shapes will not DeGas on this design- n/ v1 e- y; j, e+ Q
979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection/ x5 U! ?4 [% g0 k
981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 15
. P" I# H* |. ]6 _# F/ T+ l3 ]- H2 i" F# F+ I# q1 N, k. U
DATE: 02-03-2012 HOTFIX VERSION: 015
- U& w( t) f- p# W===================================================================================================================================
}# g6 O5 O/ H$ R4 W) xCCRID PRODUCT PRODUCTLEVEL2 TITLE3 n1 s/ [' z0 r% z
===================================================================================================================================
7 X- F6 d8 r# \+ C. T+ w871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager
! L7 }1 _. c8 v S& d& x, I921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension
. m: T% e% B2 L% ~% l% _941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design7 A( c8 v! D" O$ h
954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning; `* k; [) d, A4 ?! _% \. I! d
961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version H& U8 F5 x9 b) B/ Y Y
964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project# O; h: n( e: |7 g
967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only
0 |* [; j. @4 k/ g$ L+ T. Y968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol! U* h: t' E; w- {" ]; {# i s l2 l
969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5" ]8 P9 E: D* D6 ^
970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance
|8 f$ D! E5 L! ?970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins8 E" s$ `/ V2 t X" m0 v
970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5./ s( V g; S( t. ^+ _
970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.
2 `$ H+ a X0 q: q/ {970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash& ^2 p$ d% b- y1 _
971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design/ f ] I/ R4 s4 S4 L( w% I
971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances! G# D# o" W9 Y1 x" Z
972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM
2 u4 E1 a7 A* u6 ~* G& T$ k) b f972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT+ Z& P6 t, J6 i; Y" I! ]* \; m
973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.% u g$ [2 S6 S. ^
973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized
0 S/ O( ]3 p3 N1 A, J @' Z8 a; p973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value2 a" R- a: y1 ?5 d
973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.1 Q5 g, y* c( v! p1 c
973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net% c. }8 j4 I% w. z0 q, V+ U$ S+ o
973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application
C2 w! z+ W; v( _3 C. g, s974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.
% Y7 \. D! p& o2 ?+ F974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working5 \0 k5 z" B& [8 `5 y
976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index' M& w; s/ P' A
/ g4 f( H5 S5 U" H4 B
DATE: 01-20-2012 HOTFIX VERSION: 014. G3 D: X+ ], b7 P' L! X
===================================================================================================================================4 g$ N( r+ e5 V0 J
CCRID PRODUCT PRODUCTLEVEL2 TITLE
: w3 ?9 W/ A3 O: i0 q5 v===================================================================================================================================7 F9 a- m- n8 G# O, {
733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server- }' s+ g2 ?" y& i; H
941020 SIP_LAYOUT OTHER Soldermask enhancement4 h' P% ` A' C% J
946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?
$ J4 F0 I* P G* p953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable7 n1 Z7 ?4 g! |% ?
954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic* P' e& L7 F3 g% k8 w+ \
956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs1 f' k. Y& D) F( B6 C* V: F
958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive* B* H3 c3 x4 Z& @% A
958395 ALLEGRO_EDITOR SHAPE shape voids won't merge
7 t" q, p5 E7 S# Y959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.9 P6 r) N8 v1 L+ c! Z1 }3 C8 {
959940 APD AUTOVOID Void all command gets result as no voids being generated.
0 K( m7 R" ~1 i/ t( \0 c960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message( d) P. v; S* \- K1 M
961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI0 {- H7 i0 C% _' X
961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.
. E) \% B( x6 D) ]961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification
0 [2 W9 v( _) G: a, }5 k961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.
) Q4 o# }+ ^' A6 p961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.* T- I9 U- _' H: I9 [3 u% G: m2 k7 {
961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM
) I# g* X ~. Z5 ?2 Q$ a3 o. U962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine0 K6 i& t0 [) B$ j
962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires
. Q( v3 Y7 f" |/ E$ Y, T; _, H963232 CAPTURE MACRO Macros not being played in Windows7
6 E' Q6 F& v4 f& J( P4 I* G: D963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3( ~2 _+ f+ T* [2 O8 p
963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux- c* x/ G& `; o, v. O2 B
963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design
' P7 D( S7 C. P: T963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length
2 y" N& v4 r5 z) l# u: i1 _964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym... ~- I3 U( [+ D( ]% V
964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs
) Y1 E9 T) n0 ]/ m& \964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)
x0 T7 w5 k5 b) v8 P7 X966148 APD INTERFACES Character Limit for DIE Files (*.die) Import
1 A) s/ R4 K: ? m966416 F2B PACKAGERXL Cannot package this design
1 k( V: K3 p8 l# G! c966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks
2 ?( H+ W5 j, j% d# n4 }966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open4 n, O$ G4 j" h+ P" g! C9 p7 @# z# ~
966795 ADW ROLLBACK rollback utility does not honor -product option from command line0 {+ c2 Q+ l9 W! I; _4 H& r
967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.
* H6 v/ N6 f& @1 \- h967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing
2 } A) X% C' y) @9 V- k967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program
1 S( _. l5 C, H D5 b* O+ k0 Q967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.
( k9 T5 P8 ^% M8 c967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL; [9 K6 z* l. n! w; ]
968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.
8 E" N9 ~ M/ _# ~) f6 y( G968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell" r+ e2 m# T I/ R* V' a6 N+ r& G) }7 N
968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager
6 a0 t6 R' I" \) {2 D* {969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes3 k: I6 p) x; I2 H
: u/ @% s3 J2 m6 nDATE: 12-16-2011 HOTFIX VERSION: 0134 m# |1 W: A Z* G4 ]( l4 b7 o; E
===================================================================================================================================
, E* N2 ?+ q" l7 jCCRID PRODUCT PRODUCTLEVEL2 TITLE8 H3 \3 O+ l7 ?9 Z2 R
===================================================================================================================================
. T& M, P( p, l3 B875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.. ]$ G; V% A( t" \# o
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design% T* A( ^3 @5 L" d0 H) {, |
938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
~5 | A1 i8 J5 N4 }) \: y941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window9 }! p b) X" } @9 K& e8 i x
945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command% h; B0 b$ U. D
946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat' Q4 U% N; K+ v4 x6 |
946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.
1 K$ J# p& i n; M7 e950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function0 G! f4 f# z6 h
953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
: v/ n, O- G3 i+ i9 f. ]1 S953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block% j6 i& e7 C) a* D# q
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly4 x. M& a3 ~4 @% p4 H# b
953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�# b. [6 E7 ^6 J8 t
954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.
! b! O) K6 a W- L954498 SCM B2F SCM crashes when importing physical
3 N: g7 w3 M! V ?) }/ N$ _; O954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
1 V8 U6 a2 F/ g5 v& @/ W* w' S954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3( G, Z4 l4 V# \9 e+ e3 O! @' g$ v
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view6 d( C8 J5 V( W' t
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side. ?* m4 Z* ]3 R
955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window0 i; Y( T% e. D
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039, F: P) n% A1 Q' r3 s
955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
& m* q/ i6 Q2 X6 d# L' t955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL
+ C+ I2 i7 r5 f% \6 F8 m X! p955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly$ w6 A+ }! _% M2 t
955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass
0 D* J, Y$ a& Q" w/ D955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void7 r9 {4 v% Z+ s' r- n% ^( t
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.* ?$ k$ O9 Q3 t, R: b
956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
, \6 \7 \1 T- i% v- b; j; Q6 b956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box.* l% ?$ S# z$ @! @! i
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
# j( F6 R" H5 o( o4 ~956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined& x& T9 |. }) T2 q4 }# ^2 e8 ?
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board
: z7 l0 X* \# G9 h# t956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component5 c5 ]' Y! @1 }$ Q M0 o
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly
) _6 Z% L- \' s( }1 l: W4 e( G+ S956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5' u/ N( |( j$ | j' @- ~9 N
956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results4 o1 B/ ?* `+ v) ]: w I6 X
956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty, G! O2 N" Q- j
957009 CAPTURE NETLIST_OTHER Problem getting database property in mentor PADS PCB netlist
4 i6 [& |, F# j957137 APD DXF_IF DXF out command dose not work correctly." q# {7 w8 a" ^+ D4 a3 Y
957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
v9 y* n" O8 z; _* O8 t- I( ]957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.1 c n* i* M* D. J+ x
957267 CONCEPT_HDL INFRA Packager Error after Import Design
* y3 z% A( M" O' k% V/ {957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file, a; c% m) P! }' c
958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.) z1 C H$ D2 D, H
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design7 ]# I2 E) ^6 z0 p
958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
; q( ?: ?9 z( S958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
# E0 _/ w* b- A7 n+ \* d7 g& k( x3 `958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5! P8 V7 n, z0 o/ \
959011 ALLEGRO_EDITOR OTHER copy problem of via and cline4 [" B# r! z/ T4 f0 W9 {$ ]
959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs
?- P8 Z9 g! [. L959253 CONCEPT_HDL INFRA Design will not open* e/ N/ O0 |8 |- x* A3 [" I
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
% U, f! g7 z& y' \959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
) q7 C9 d7 f8 E7 ?959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred! |( S2 }9 {: a# R9 {2 V2 ~+ h
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.: J7 p" _0 u& |. s. w
960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.2 H( X4 \& d: N+ i
960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
. e8 x g( T/ R5 C. E. @961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
$ |0 S9 b' G0 T( m7 m961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol
! F/ ^6 ~5 y" [( x5 N9 W7 s- A( B962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers
& K$ y+ y* n# H; N* c& `. Z% a3 }! {
DATE: 11-30-2011 HOTFIX VERSION: 012% W% t9 |/ j3 X. p% T6 V! P3 Z6 G' v
===================================================================================================================================
" L3 f7 l' n) ?: F8 [( `CCRID PRODUCT PRODUCTLEVEL2 TITLE
# p6 d; J/ i$ V! c5 ?===================================================================================================================================
; J8 W0 p1 v& l0 A; F/ j8 `959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats) c( |& u" ]" f }% @( }
3 I2 l9 Z# w) \, m" Z/ I# W
DATE: 11-18-2011 HOTFIX VERSION: 011' \% r n2 N% X+ {5 F6 U
===================================================================================================================================
/ M5 X$ ]5 O9 o- J6 @2 X( H! bCCRID PRODUCT PRODUCTLEVEL2 TITLE: a: t; n1 r2 M
===================================================================================================================================; h4 g0 I( y# f) c1 o
735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape- j) s, C; i( }, w
894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?; A+ Q4 S. a6 r/ |
903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL0 h, k- p( j- \/ S. ?
909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?
& @/ h6 w7 w9 d/ c) N911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.
, C; p; M2 a' \) F2 w919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode0 s2 g" |5 p5 ]; J6 m$ A
921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined9 Q0 j0 H L, ?+ H' l/ x7 K3 m1 k, u
925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.
; o' [, u/ K0 O1 Z9 f" {926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows: ]% C1 N/ c. F
927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list. S% M# z( p9 _" F3 I: x; i; p
934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks. d/ s& o' E5 R1 u, m& ~
935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic
2 }0 e7 y! v# m1 F' c# V* ]937165 SCM SCHGEN Can't generate Schematic
: l8 W! r% B+ |) S' U937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search
: C c, C) L2 J% @; P937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails
' U% ^0 c5 b6 A" f1 }" X$ ^; Q939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License' P3 \$ J. Q2 Z9 X* t
940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup8 B3 O$ w! x T4 _, F5 ]2 d$ J- E
940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in
z, c+ n! u, d9 O8 l: k) S940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad
; C: c" X0 y. o940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.5 o& w p$ P) M' W$ _' M
940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq
]; i/ |. ]1 Y941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups! d8 ]; S) N* B& H7 \
941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.% H0 b) } i$ s9 X' p K/ s: j$ g6 H
941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script
& N7 v8 H, j0 G8 G9 Y! ^* u2 D941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?+ b: ?% R2 O; }6 I+ R
942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture7 `3 S: W4 s# [
942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel
0 Y$ w2 ^5 f* y a5 O9 y( Q) ]942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash
+ q2 t( M" R1 F* U$ a9 V942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon
- W- d% h4 C5 a+ Y5 g& [0 J0 w. l942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.
' ]& F, _0 q; s/ }942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised. a7 E+ L" v, C* r
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.
' d7 t$ K5 a2 ^943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup
, ?, v+ t' g0 y4 T944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently
$ y' J. o9 E' ?# O7 I, x944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5
" O0 `8 G$ h8 E, j) P6 a944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines+ x; L' P. y9 I5 V& k7 t2 A1 X- C
945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints
) `, }' ^" }/ n, M5 K! V946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5. s; \. M) ^+ }5 X# J6 w' T
946350 F2B DESIGNVARI Variant Editor rename function removes all components3 t2 T1 U: ~' `2 B6 U
946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?
7 H8 l s& y/ Q& p" p3 y9 M946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form. L* |; V$ ?) O# `2 M
946458 SCM SCHGEN Schematic generator adding an unnecessary page
- Q% d4 z! R! c, B4 ]* P947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC5 }- ?/ j4 ]" a s# e) m
947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.
+ y! n5 n: r. q7 ]% p948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM
- l; U. j7 @: h: O6 R1 h950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.
J2 ]9 \6 @: d951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved
, M' @1 ]: m$ | y5 g951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original
2 @/ |/ _, `) f" ?# J: I951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?
: E4 ^& i" L5 Q" ]( s* v# A: j951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages+ ~+ b* [+ J y/ A; H- M( V7 _; b3 S
951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.50 k5 Q( y4 ^: e! y
952057 SCM PACKAGER Export Physical does not works correctly from SCM
! s# C( S& ?' M& k952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor
1 E* f1 v3 X* e: [6 z7 }8 ^1 c$ S952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5
6 _/ e2 `- B8 n3 F953018 APD REPORTS Shape affects Package Report result.
. O# c6 p: C, j. ]+ N6 T3 y% b953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.
! A) c& D+ q. O* s9 Q, @2 j953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro
- s' F0 a( x. @) p* l, o953918 GRE CORE GRE cannot route second and third row of pad in die symbol.' [. G6 C0 Y2 U0 _* }
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path; i/ J9 c1 _# }# Q5 l6 P4 l
954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report
0 W; y: i" [. Z# B% D& l6 |
# r/ V0 x/ ~: L$ r: zDATE: 11-7-2011 HOTFIX VERSION: 010
, M( [6 t9 s) F/ t6 h( M; S" O===================================================================================================================================
4 C1 N5 N( o) [8 P) m. `2 rCCRID PRODUCT PRODUCTLEVEL2 TITLE' ?% v7 a C' A7 G) J
===================================================================================================================================
' S8 Z) G0 ]) I- W) K4 S2 O658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline9 ~2 C" _- O1 B( ]
928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
1 z" Z. A' |% r8 V% n) O/ Z" R. P/ h934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile
k- K/ _# Q, ], J938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem4 \) V7 Q2 N1 }
938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.
9 d8 u; @, g+ T0 C938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer: w# [* r% n9 i; Q, o( N
940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete
7 w9 D2 h* ?6 w* N A. F7 [! D941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!8 b& g% R6 C w8 R6 r. G
941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning% o, E8 X( Z6 c2 ^1 S
941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen1 e6 ^) y& s3 `. f
942914 SIG_INTEGRITY OTHER ZAxis delay calculation# p0 H. F% j! K( x3 e5 |3 q
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash3 M6 d- f2 h9 r3 I$ `
945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die
& r a t' c' F/ p0 u945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.
3 J* I+ D3 d! V4 ^$ x' B945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.% _8 z' u. w; B9 p; A, s
946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions
; |, i5 F. _- G9 Z946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch
8 H- W9 v- W) I+ F8 u946819 SIP_LAYOUT DEGASSING Shape degass command
7 K b: F/ V0 [( k. @946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up
1 f2 l' \* s) @2 A, f1 ]5 i; h3 G947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3
/ P* l/ D x- m9 w! ]: l947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file1 A5 p) q9 u5 a, Z
950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic
: x v+ |3 v8 R8 d% E, N951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37 u7 C( E! i; ?$ M8 x
951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol$ i3 p$ ], z/ r
0 ]- m3 p+ [% V, c9 P, O2 eDATE: 10-26-2011 HOTFIX VERSION: 009
! i$ h) |/ i/ s& [+ v/ j- l5 H===================================================================================================================================1 o" f# R# {2 |$ R a" e
CCRID PRODUCT PRODUCTLEVEL2 TITLE
' m) E/ `- Q2 O' d+ A2 A===================================================================================================================================
5 v$ b8 v1 Z: E" x1 B6 b( p3 c945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet+ Q$ m0 E6 b8 U" ?% u. D) `
945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference
6 d# U$ r# V& S& i j+ A+ S
/ N; O7 x2 N2 `4 s+ a5 gDATE: 10-21-2011 HOTFIX VERSION: 008# |7 w3 a, P# r9 |, l; g; W
===================================================================================================================================
6 C+ S) u% N% E# M5 ]+ hCCRID PRODUCT PRODUCTLEVEL2 TITLE1 o; y) t" i7 z, ^: ~; v# v
===================================================================================================================================* P& y; r7 d# _ F
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.
$ n% G& H* @5 Y# W' o' ?5 |923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5& k7 @; q4 r" y3 o! Z
926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it& m$ }7 G2 A4 r
929348 F2B BOM Warning 007: Invalid output file path name
( `1 b: ]) B/ ]2 k4 U/ i, Q929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error7 F! L5 a- }* N4 x: N n. k; c
930783 CONCEPT_HDL CORE Painting with groups with default colors
9 c6 C2 B8 V. c9 ~: ~ u. {0 o- Q4 Y936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
6 A; R5 K4 v6 u; F6 H0 A0 P938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR1 D: M( ^( q/ R o( K
938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins: S9 q) w/ ~" d4 Q
938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.1 @+ z, ^3 t/ g/ J
939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window
# c* Y: G* X/ z) ?3 K* V7 q# x: T939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.
% F) |* i! d/ E3 \; t939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)
, |/ T9 C* N% X5 ]% e' b939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.4 ^3 P3 ]& x1 N# j3 Y) z, i' x
939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.: C. w: a! o' B! W! M1 Z
939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.
; D* A5 @& X7 f: c2 D940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'
; N6 b0 l$ q5 }/ N& y% j940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost- k' y+ i7 G( K. ?. c
941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks
2 t5 B( e0 O9 L3 p941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3* K5 i z* _& I# l8 d8 i* ]
942210 SCM OTHER Is the Project File argument is being correctly passed?9 A* y9 g) o9 i# c- M8 R- l
942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache
* H$ ]$ C, s% D$ R/ x3 Z9 E' q942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible
6 ^5 j7 X9 r# S6 N) B- d1 K943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash
' p5 v) S0 t0 k1 q5 `" w3 A3 d2 H1 Z3 v3 p+ w8 m2 J2 |
DATE: 10-21-2011 HOTFIX VERSION: 0077 n% I4 f+ v p: {6 M! A
===================================================================================================================================8 m- V9 b1 j' g% \* n
CCRID PRODUCT PRODUCTLEVEL2 TITLE
f L3 F5 c8 N% F===================================================================================================================================
Y7 G' z! S2 S6 I7 G1 z$ t841096 APD WIREBOND Function required which to check wire not in die pad center.
( O( e9 L# p* |1 X903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
3 Z v. y$ A) n2 ~: V. [8 }: A h8 h906692 ADW LRM LRM window is always in front when opening a project
' b# } ^3 k8 y `" k% ~2 Q* y! P912942 APD WIREBOND constraint driven wire bonding
1 h& V' y( r) z912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems: ^* `4 Z5 O+ v# {( K; w
915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design& Y& K! \1 y b. ?
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
2 o: V7 ~5 o% N923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure, \. ^! c. o, j$ C
927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license: V3 k0 h H/ N; r
927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp' g/ F" Q$ E) E, _2 B
930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one7 {9 p6 m/ F/ [% X
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation/ M0 k& f% Z9 S! R+ P- H
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked. u) f7 d, Q+ l/ C
930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
+ V, U' S4 L% y930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
4 t- P5 h, T& q0 o: |- N* P$ x930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form6 @6 n$ c# B% r( f( \: G! w- `
931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC. I. u Q! T7 c% m( ~, i; Q
932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property
0 v! r6 E, h! p; E4 J932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear9 M: |# ~/ a, i7 T& T- X
932292 ADW LRM LRM crashes during Update operation on a customer design
% f% t7 f7 o% s5 }/ l932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
% G7 W$ E8 d6 a! u932704 APD DEGASSING Shape > Degass never finishes on large GND plane
2 p [* i# X$ [932871 APD GRAPHICS could not see cursor as infinite" F5 R/ f7 A/ k
932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05/ D& Y7 a% J# U$ N7 a
932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05& |* X6 k8 {1 Q1 M# o! F
933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members
' O+ m* ?: M% r8 p3 J9 {; L5 _933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
4 t7 Z( L5 A4 O& L& s933214 APD ARTWORK Film area report is larger when fillets are removed
2 E6 S4 M8 X7 u* b: t+ v( r933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
$ l) V t k- h( M6 v7 t: B933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass8 F8 K( K% F5 f( H* Y
933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.% o' k8 u' t, K1 F3 n5 x( `7 t
934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values$ N: q/ n3 b- Q: L
934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs9 ~) ]! G. j) V2 I+ L
934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash5 j, l6 N( r8 K' x' o
934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.
) M/ [/ \* e4 e- L8 V934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
" [4 q- L5 q5 C Z* k( {" _8 N934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound
% E) D0 W2 V8 G. M+ ^, \934909 SCM UI Require support for running script on loading a design in SCM8 M" b; U1 I% i, s
935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.
" l: Y# L; H. t: V/ b: ]% ?1 m: A935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3' ]7 H& p7 ~+ H4 J( f
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash& o% E' i$ O) I( M$ J
936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol
: P" J+ L. ^$ y* I8 ]7 e; c936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.
1 j% k( p, j. _$ D( s936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack
* `7 A% J0 G) J7 J; O- z% t+ D+ G936797 CONCEPT_HDL COPY_PROJECT Copy Project crash$ f5 w7 V$ q" T: Z' y
936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol
7 ~+ t, O" Q/ N936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM" p2 a. ^6 K2 d i6 y
937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
5 t& x5 ~/ W" _937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About
1 ^: p3 T7 O% c937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.
( `1 g9 G% H7 e8 n* T9 ?3 _$ e937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.8 z" }. t# m: }
938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.- q' C# s. q% o5 H# F
938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set. ]- D0 E+ ^+ X! s( }
6 N, F5 _! F$ l
DATE: 09-16-2011 HOTFIX VERSION: 006- \2 L; J! U7 i; V" o! F, U
===================================================================================================================================% E: Z0 k; `0 k3 U
CCRID PRODUCT PRODUCTLEVEL2 TITLE3 g% ]* x3 E& D# S9 G$ j
===================================================================================================================================. |7 j7 E* ^6 Q* T
820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.
: s. V* z: [4 S/ y7 f5 o" {" w863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints# Q _: ^, B6 X% @" [: w9 r
919822 TDA CORE Cannot configure LDAP to only list the login name; k; ?. f! ]7 u* Z: o
922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error/ H7 v9 J- |- |1 W7 Q" Y7 M2 O
924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results0 ?; ]3 ?) S" ?6 Y
924448 F2B DESIGNVARI Design does not complete variant annotation
8 [7 P$ R) b2 o+ G, S6 y# R; z0 z925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB
8 Z& r7 }. E q927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report
0 L* f" A% N/ ~$ ]927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values0 d! ~3 E( c; M5 C- z8 L% b
927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line a/ y% N0 a2 o) h+ n5 X
927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets9 I$ f6 w' T' t4 O* v$ {) g9 V
927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor7 P8 @. {5 w" j2 |' E) X3 a
927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl
{' w; c: _- _9 w4 O8 u927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display
' j- p! X4 ]& k( s+ z927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database
( c1 i& s# W. r. W; V. ]" p+ ~+ ~927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.
$ G6 G: i" o5 a928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.
" i# U$ i6 @" }+ d# B928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list* @0 R# Z. v- _' J. z
928738 PSPICE PROBE Y-axis grid settings for multiple plots& P' M' C5 T* D3 A# X1 A3 \& O5 Q6 ?& M
928748 PSPICE PROBE Cursor width settings not saved
' p( ` [' h; q# I; s, s6 Q6 t e928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release+ c* [* \; ^3 y& k1 C' f
928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.5
3 D9 f: v2 y' n' B928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe' \, U/ Q7 F) Z) F0 ?, H; I9 X! O
929284 CONCEPT_HDL ARCHIVER archive does not create a zip file7 Z, m9 n) u, U. L( U- y
929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP. P4 R [! M: e. z2 }
929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error/ a; H' B+ D# r" g% t( q
930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape
& W" V6 l! K" D2 M- v930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.& n& q" r9 Q' ]
930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command: }" U1 Z. d2 `; C
930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.5 F5 f, r/ B0 ~5 e. U9 d
930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well
4 ^( X( R" a; f0 s% Y9 U4 N2 U930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name: P- \7 M7 m. @2 G7 x# M
930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked5 y2 }9 N! u7 ?
930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
% _4 `: s+ q/ R( ?& q; y6 p) m931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets." s2 `, y# B5 l% o: L* b% L
931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version, F; w: k* ?- b" K& n5 M& E* l3 A
931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.# P* C2 l. V, q7 z! u# v$ ]
7 S5 R+ n1 o1 m/ M' X( T O
DATE: 08-31-2011 HOTFIX VERSION: 005+ f. n0 v7 c/ P
===================================================================================================================================2 }, z. n& l/ T' R( E
CCRID PRODUCT PRODUCTLEVEL2 TITLE
- _) s5 v6 R! ^- @===================================================================================================================================! N) w s4 f' J7 n+ D
825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole/ Q1 w2 d8 A P6 L/ c! R& B
837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show
' h) i U/ j {891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode+ p& o6 n, Y6 o3 _6 @
910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.
. g; w5 @& `! s e914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.
4 }" A8 K' x% w! y/ \914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs
3 S+ ~. r4 C' w' E914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity
) r0 @5 J3 e% x# k- K915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location
+ B r% V6 y/ g0 O915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape
6 B& g8 u1 m8 \4 ^8 @$ K915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working
7 |( J c- T4 G) w5 }' }0 D916321 CAPTURE GEN_BOM letter limitation in include file) n ~2 m2 \ `- M' {( M9 a
916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects
; U1 e. _- E6 W( W0 M7 P9 _8 o! ]920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.
% n$ l" y. t/ y* D0 D* s920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.
: U1 d5 L- f6 e; j921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set& D2 q4 f% m' Q
921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.3 i0 K# Y9 A' N
921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002% |( D& _, k" [1 ^' C
921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions
, t0 z- Y, g& Y9 r7 Z9 T$ [ } p" c921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly
M' _: F+ A6 g922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.
( a# @5 U( E! M9 v7 P922117 PSPICE PROBE Label colors are not correct in Probe$ ^; i0 P; y9 m) g# ?
922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
& c; y Q8 M; I: l5 T923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002
/ ^2 C* ^/ e( D/ ~8 s923286 CAPTURE DRC DRC markers not reported for undefined RefDes
/ Z- U( q3 _/ y) E# h- f1 P923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5
) X {4 _$ `$ [) X923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top5 I6 P; O8 ?$ ~+ t
923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)
- P+ G" I" F# f" w2 R8 k923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.
9 \/ ^7 D9 F9 l$ K/ z8 X& ^3 Z923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design: {/ P i. Q( J9 ]0 f o: q
923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on
) r, ?5 E- b4 [* g. d( R3 ~923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error
! W$ H) p; F9 _924458 SCM OTHER Project > Export > Schematics crashes4 t; b8 L5 T8 }6 J6 e
924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
h' c8 L/ v4 v925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect* Y" V6 `, ?! S
925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error
4 h$ K" D8 M" Q: Q' I925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
" Z, U1 `9 `# `; b5 H925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.
! K2 f2 C, @" ~" F1 {+ s925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?
- C- S4 o, Y& L H: \925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS
/ H" \3 f( S7 [) U @" z, |925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data
. E- x7 K( {. b* p' e926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.
# y+ d1 j' }/ m& S926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.! a5 Q2 X( X# c( L8 ?
926503 CAPTURE GENERAL Memory leak Capture/Pspice
* t: L# v: t" n3 Q% L2 J926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet/ `" Z7 B( R; D" ~$ i
926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.
+ N7 C1 {6 r! D/ {0 l926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical
8 h$ [1 E5 P# l: F# \7 T927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''6 K) [! a$ H g5 a7 Y1 d( l
$ `5 o# u5 Q1 oDATE: 08-19-2011 HOTFIX VERSION: 004
5 h3 q6 ]+ ]5 s" y* |===================================================================================================================================% V3 V( ]0 e" L+ o5 t
CCRID PRODUCT PRODUCTLEVEL2 TITLE
9 y# u% ^$ L. [0 X3 b* s8 X% u' l; u===================================================================================================================================
# Q: R9 L- l# d; a$ r1 z785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error2 K! t# q5 ]' E8 }5 ] z
851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.0 k8 a! r& ~& b2 i9 B4 G. x
868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments
9 j& q; j! r+ L, P, b870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file
& O' I( b8 a, k% i& E' M+ H1 s877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form- M' f" X5 L1 D+ V* v% q
894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window! m: A% d2 ?! P# O, h+ J/ [
895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
" X& k6 P5 {. o4 l7 }& }) m0 u5 |1 L895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement7 X4 X6 u: _, }/ `; b; B) B
903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.
) \: s, b- e7 T! ?" B- M3 ^' q905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.7 i% x+ L$ U" ]7 b" f* [
909469 SCM TABLE ASA crashes when opening project% u" q4 h c; f" B% F2 f4 k5 q/ r
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap) n$ `! C" }& {0 c
911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152* C+ b; \# O+ i9 K) a3 u0 E( p
911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?. `7 j( J" f$ ~' G4 W X
915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability7 Z8 n0 D u) b' T
915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP
4 W2 h# I5 K( `$ U* t- N916062 CAPTURE GENERAL Auto Wire Crashes Capture' N/ z% E. \0 {5 `
916820 F2B OTHER RF create netlist with problem j' I* }8 f* s1 @9 L$ t9 \" I
917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only./ Z) X, a$ V, v6 x2 ~" \- N
919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file; U& @! }3 V1 p, g$ j& A
919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working
: o" v1 w' U& x0 g919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL
0 u2 O2 p* H' c- S9 P' x( _& \8 j' C919976 APD DATABASE Update Padstack to design crashed APD.
' c: b$ W) X7 Q4 ~7 X3 g, P920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition4 e' D% T5 m( b. {' z
920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run, f# _: ]# l- R, [8 B
920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork3 D/ ?' ~) R0 A6 {" C6 y+ n( c
920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins
( _! u" m3 ~- R- X920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min7 e" f& Y: x1 G
920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net
$ o: ^( O* U7 i; I5 ~4 O9 `7 X+ k921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.
& _* W# v+ ?% x. I' E# M0 I' p922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets3 V$ U/ {3 o: {* G
922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named) v1 ?5 N i: c/ U
922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin
# J& e O: d6 S0 f& g2 t# j922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.
Y- b7 @# i* `7 f. E923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log.
0 j. g# y4 r+ F- s" G$ F. t9 o# D% _ S924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf/ b4 I9 g! ^) k1 o$ r$ X
& H" o' ?9 P6 F: I2 e' o# G9 oDATE: 08-4-2011 HOTFIX VERSION: 0034 w; z! A7 J5 d: n
===================================================================================================================================
4 u- m, U- D6 k! u! @1 JCCRID PRODUCT PRODUCTLEVEL2 TITLE
5 d5 s; X2 e8 A# r3 m===================================================================================================================================9 q+ O! N( v" Q$ ?! q, V
787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.3 W, b) Q3 }3 E# R. l) W6 i( O
903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics( d+ A) e, \% O. q; {# W% z6 M+ N
904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.
: ~9 P2 Q8 x& B0 V+ @+ T' Q3 [4 g904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result
/ s* K( u. e0 R, _# y905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged
9 ]) v2 c! A% E( l/ l }) h906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.2 U( ?3 h, Z. I) v
908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance8 r* y, M5 \* I' t. Y
909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.0 ~* ?9 v9 e5 b8 a' ]
910315 ADW LRM Import Design with ADW causes partmgr and pxl errors
0 _& T# p: G u A M8 L910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5
g( m: l- i5 a# V0 x911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5
& C8 k/ }* M7 }9 Y912343 APD OTHER APD crash on trying to modify the padstack
) {9 i' q, S& \; t" ^5 H912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys/ H7 V: u" h5 H4 ]5 G* S) E
912853 APD OTHER Fillets lost when open in 16.3.
) t& A- H) R2 G2 V/ ^913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.% t. p* ^0 {! \4 s" t) r+ m, v: K" o
914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.
9 B8 b$ I0 H& e; A) [, c. i914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks
: S; I& B- b5 M( O914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.
7 C3 s+ U5 K% n/ E- l1 T1 F914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design1 @* U) q# z7 ^! W) ^- c; }0 q
914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape8 ~' l) Y0 n" l( I6 H
914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.
5 z" n- j0 T4 g) C3 S! C914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset [; }2 p5 Y* {5 o! N
914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.
$ K+ p( P' C, U9 I. @5 l. B; B' K914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling
$ U2 ^) k$ l: k4 p u: p915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.38 `: }' ~7 M; ?
915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models) J7 E7 Z8 |6 ~
915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol- K$ F0 v7 z+ ^& Z6 v
916154 SCM NETLISTER scm crashes when exporting physical database to allegro
: p1 Y. u" S% y1 D" a0 A' [916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors" y, ^; k6 Z! d
916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor7 z0 c5 I# e5 S7 ^9 d2 Q
916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report
" p8 l' \* s" l# v916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer/ ]- c0 `3 l* o
916889 CAPTURE NETGROUPS How to change unnamed net group name?" [, C8 e5 B+ n/ J8 H2 i
917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film l' d! L5 y( E |% ^
917434 APD OTHER Stream out GDSII has more pads in output data.
! y& ?" B: S* l. Z; i3 P917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net- D. f2 ], r9 Q) V
918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.4 H& X! j8 r! u0 O
918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol
" H4 ^% ^ N0 w4 X1 X7 ~' C: ^1 X- p, ?* O2 m) N* H4 ?! k
DATE: 07-24-2011 HOTFIX VERSION: 002
% V7 p6 y* M* B5 _===================================================================================================================================
7 k6 z( N7 ?* D7 z) F: sCCRID PRODUCT PRODUCTLEVEL2 TITLE6 p; F! R& H2 @: r% B& T
===================================================================================================================================1 g5 t4 T/ E- L0 A" M
527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings5 \4 Z x4 J4 V. j* J
583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.4 Q* G! n* v, r6 q6 X
592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.
. y5 z2 o4 J6 D4 m745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.9 G% c8 Z* s. L) U. S, R% M7 Y6 ?
773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.- W2 ?2 s) J- a* W: `' z
774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.
! {( B3 p) V% g9 T% G8 I* g1 T799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs3 T& e0 C2 z) V3 s; o
809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
$ ^# y; c& {) f7 w8 |- c3 U810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".6 Y& x- A9 U9 r
821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format% G W4 f: r9 [
831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself2 G% g0 _& d+ f# m
842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.
# u1 W% C0 F8 M: J854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group4 \3 l4 `: L! {; f
860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser) f0 o8 z; ~& P6 w
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"
" a# k+ a% A9 `& B8 t6 t868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets# c" E& S4 J6 x7 S2 ?* F, `
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
. o- n7 d/ ~$ m& n/ Z9 j' |% z891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
( x# p' g/ C( w/ c. g/ Q \893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
% W+ w* N7 q0 Z5 X893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.
9 P/ O. I4 b7 P8 }894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command
; j) w0 z+ T- c8 U( E1 J895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs
8 B5 N0 s8 X* x+ W6 C0 S" @896598 ALLEGRO_EDITOR PLACEMENT error message is misleading
6 f( G. `9 e. c3 E# |897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library; O: o6 |9 X5 d( R- m. u
898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.
" ^6 I4 }; }. l# v) L6 {899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.9 a+ M2 o" l2 w" l9 r
900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5. X- v( c2 J; O7 G$ `% G- P F
901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.
# L2 |: t3 k B! n6 k. {1 Y; ]% n901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page; T! P; E+ @/ Q7 ]+ R) R
902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
( }& x; U5 [, I5 x) l0 Y& J902349 CAPTURE LIBRARY Capture crashes while closing library8 G% b( Y; x1 A; O( ]6 ~
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3$ H) M h* \5 g2 e6 @0 k
902841 CAPTURE GENERAL Capture Start page does not show8 C) j( d) K; V) K) g1 C- T" {
902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5( R' q2 @9 T% `. O
902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
" E2 y5 |5 W) y: E903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?: {% U/ f* \' b
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition9 q5 i/ D3 B' Z( T/ G
903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor7 o: M2 B& K* L4 a r' ^" h8 }+ ]0 G3 D
904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable
- }- h9 V/ Z1 {1 |2 j6 k8 F904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE3 g# x& V' h4 g8 P# P u9 F+ H5 E
904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3) y: l* `0 H/ F3 B! v
904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places0 |" _1 v- r1 g9 [* _
904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.& ^$ I: Y6 }4 Q5 c! L
904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3/ q3 i; \. K V
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM/ L: X1 ], o1 q9 v+ m
905314 F2B PACKAGERXL Import physical causes csb corruption
: s% o9 y: r$ `* J/ E905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
& C% l- Q/ H1 o3 Z( j$ M: T905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
0 G2 T+ k+ s7 |9 p905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues
@8 W- }0 d! m7 B6 \0 D905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid: L) G; u0 O: U D
906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.
2 h7 x$ s" S3 Q9 E' A/ ?906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.- x7 Q; b% j$ t' Z7 U6 n
906182 APD EXPORT_DATA Modify Board Level Component Output format
+ s+ K- `$ Q- g906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element& l# U/ z1 V- Z7 [
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.
* a$ e. ^" c1 p4 y# _# F! Q0 _906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
% M- o1 M5 H$ d6 s( |+ [. P906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run, s8 W+ D! Y- u% S
906673 F2B PACKAGERXL Ignore the signal model validity check during packaging3 V7 U. O/ {& n, _0 ^
906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'
* Z. c$ |4 s- ^5 p W! [906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation
, b$ I" L9 b1 x, M- P/ o906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin
( J0 A. `' V: q; `2 b1 y907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used0 ~6 o% X! o8 d: p9 v1 h
907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display% Y, o# g$ F% s l0 H7 m
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.( w3 v( t9 f4 ]
907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"1 e3 q5 `# q/ P. Y/ Y# R
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31
x# f0 u' _" i. i K, `907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly
" d9 _& P0 T4 \907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional( f: i3 L3 A% F8 [3 W; m; l8 Z, a' u
907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5; p6 w l5 @" v8 }
908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.
3 r9 `6 i' a+ f) Q' j908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name" S- |! X/ e6 y6 `$ @) _3 b" `" u
908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3
' m' R1 O8 k8 l3 q1 R908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component
' Z0 m( H& t, t, u+ G9 L908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5( z" u0 O e: M! O* V- ^* w1 E7 ]6 i
908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place
1 M1 \. D7 X0 N* A4 s908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays. A" G$ E/ N- T& Y
908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes
/ k2 P; T1 [* X; D% h$ |908595 APD 3D_VIEWER cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b, B) t/ y& A0 S; B0 t( r
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design' d! q2 _2 Y: f; P6 x3 t& d) k
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature5 d, Q, P) v; d' Q4 e7 c
909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN6 { I- U m8 g
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.$ H" q u" F( x9 | u1 f# p
909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux
J4 C( P+ _) a) c909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout7 G% i1 f" ^$ l. W- ~5 C4 @' p
909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning
2 j7 C" C4 @" ~: i5 _' ~909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack% x0 w. r" l, M
909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.0310 D. Q+ p/ K: _0 f3 j$ s: C$ c
910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.
) F2 j9 c1 b/ B/ e" [# r910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector/ y# a3 @9 K0 T. N: I
910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.3 }6 K9 B. p- O2 E8 U8 m
910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
; G- Z! Y9 K! S: T910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.
6 m3 Y1 \. _1 _( u6 ^$ q910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent
$ j/ c w/ T9 V7 }911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
: s2 s+ @+ M, G3 P8 X& v911631 CONCEPT_HDL CORE DEHDL crashes when opening a design
# F* O' Y7 `, J912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default
2 L% t+ R# a3 @9 A1 G. ]912459 F2B BOM BOMHDL crashes before getting to a menu
% o; `& C5 N. ~, \9 M& s913359 APD MANUFACTURING Package Report shows incorrect data
1 h9 L1 _' J* Q/ y
4 s2 x, S A0 `$ g* b9 `DATE: 06-24-2011 HOTFIX VERSION: 0010 r5 K: f; y" U$ A! O6 T/ B( `' _: v
===================================================================================================================================0 S1 u5 t! ~, G9 o* `: {6 S7 o
CCRID PRODUCT PRODUCTLEVEL2 TITLE) c% e+ Z8 L- O$ ]7 `
===================================================================================================================================
# }! X: ~; q2 C! P9 I$ k293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol& ? V+ p+ b" k Y% H: n6 L( C$ z
298289 CIS EXPLORER CIS querry gives wrong results1 S/ f* C) M! Y4 B* x; n: S/ n
366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text* {. w. ~7 {* K% L# A
432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs X: D8 M5 z4 K
443447 APD SHAPE Shapes not following the acute angle trim control setting.# U4 M/ F) R6 Y, o
473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam
6 y6 f1 U- K, L/ X* Q& e3 i1 @! m517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy
5 `# R9 V9 W0 e! U* J+ ~548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.: f m: E* ~$ A6 B+ a) Y
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart
! k: Y: D. l* L4 n, V+ ?; \616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled* u; X8 R& D$ o- S* ]% x, E8 r
641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)) N% u* m1 _$ e! }8 R
644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor/ j: q, }7 m* b9 x* P4 ^
645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board
" Q' d+ P f$ t+ p v( n% d5 v725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.
8 H3 n4 C8 _+ }3 u" r763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI7 B$ u+ t( l$ `
770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers
4 y6 H9 _; H2 K* @$ z792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets
4 A h- B. j' v K. m799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write
5 W, |+ C, r% ]0 W; l) u% F803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part
8 f8 Z1 `/ E/ P; m. E: K- ]& t804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.
( ], @3 Y. |; s+ V. j/ P2 l809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs
# ^3 |' x T, D% Q# T: N816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch. e$ h$ f' E( C) p% J" f
830053 CAPTURE STABILITY DXF export fails if schematic folder name as /! v% o q5 O3 g8 l# ?
832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.
8 q, C3 u* R }* F833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
' J' d# J/ }7 X9 i0 N |835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error8 g- n- h c* y6 d7 q) W
837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version
9 T- H* f* f2 J! M7 U! a844074 APD SPECCTRA_IF Export Router fails with memory errors.( [- a0 d0 Y) y9 a, {- A
851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size
% v* H+ O+ n9 ?- _, B852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?, b2 g! S7 v# T: ~& t
855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.1 X. @/ Q# Y# ^* H! d8 T
859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs
& e7 @" w% @5 Q# b- c9 o1 r& Y+ [866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.: v T8 F2 H, |$ ~, V2 j
866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line" @* Q4 S- x- r
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF8 }' J* ]' @( ^; B( B( v
868618 SCM IMPORTS Block re-import does not update the docsch and sch view: }3 T: ^) X$ T; W& m% f
873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP" Q- e6 i# c( R6 m7 x. c. L
874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.
% b7 V3 C+ u5 x874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command
2 F9 u( x+ [1 \% k. ]% K6 g874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file
! n% H" J g0 A875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1! n: a: c: _% {/ ^
876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net
^7 K: g* c5 x$ }3 R- P879361 SCM UI SCM crashes when opening project
# w. X* P, l$ D: g( W5 v" ]879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.$ [, d2 E8 e/ U$ \
879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE.+ H! t* L- T: l( P3 H( ~6 b
881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape; A% ]8 v- P4 j/ \: m. d* N
882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets
/ |6 W1 @7 i8 G0 D- H882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier
) a" [, j% N0 l0 J1 v882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.
* k+ e# b1 z1 Y882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement( N7 C% ~8 D" p6 K! [0 m
883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component
* p( o; Y4 B7 P# y# D5 N5 c! G883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager
+ E H* N" s+ C883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder2 _# l2 x2 A( C+ Y/ t8 L* \/ f2 n
885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.9 x, b2 c$ Q5 {* V
885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string
5 C& }) b S8 r+ O885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations& L* a( W/ a( n$ }0 z
886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid
9 j" d# |; F$ E) o887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses. V9 J4 ~3 C; c) |. U
887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.
# L/ k; Y/ F+ p. X3 [/ q- p887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message
! }0 Z j8 H9 d) G! x" s- N6 l887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.- _8 W) M7 Z6 }8 h5 w) b5 e
888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.
" z1 R3 { |- r8 g4 ^888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic) O, ?" T; k9 \$ R0 }2 M
888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.) M4 f# ^& `! M( K5 h
888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.
. z! N7 t4 g, d" ?9 a6 G$ V888945 CONCEPT_HDL OTHER unplaced component after placing module* l2 b6 l: q1 J) `& h+ D) r
889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.
7 f: u! b. }& Y2 M889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3
- `% @3 }6 _. ]7 U889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.
; h5 n$ w( w! P3 E889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net; o+ V U& x( j: J* G
889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form- H* x8 b4 X5 o/ S
891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file a1 q# a ?! x% |* N4 W9 N! L
891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance
- y! _; y5 R Y/ W2 o) {891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs' A% g+ O: O+ l8 }
892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
! w. x: W( @) K7 |892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?# M, w; E) O" L$ d% l
892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness
- T. i3 Y' W" o. u892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode
+ ^, D9 [+ J! C; N6 X2 U# B892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations
& y d0 b! q0 r& C8 G& x892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR
# |! k) `0 {- G892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".3 ^) T2 h, z4 n) D) C
893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.) e- A* H, m# K+ P, d
893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board+ i. ]; g+ m8 Q: H/ W: ^: L
893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.
! z* t3 f# b' y* D893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation
5 O" q0 ~, l+ P. L2 @# }894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.4 Q G8 o0 l2 J& n
894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.+ r4 E7 `4 A; @- u8 q: N$ W9 q
894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.
) W% a$ `/ O5 x5 o* P q5 X895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON& k, T; W+ h% V1 H8 f* f6 b; Z
895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers
1 U! F: O: @; x2 Z) q( m895757 APD ARTWORK Import Gerber command could not be imported Gerber data* i7 S. G5 C5 d- _2 m
895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly& F }* z+ D: \& I+ ~
896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced
: Q7 @4 L% I/ w, c3 f4 r: O896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture. c% C( ~* U+ f; `4 l
896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing( z2 ]% L, S9 A) I4 |7 I
897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap.) W. s$ L' d9 m
897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.1 l7 h8 C$ ^2 R
899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing
( Y% M$ _$ x% l899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof1 ~. V5 M2 `9 M
900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.1 l/ T4 }& }. _, y, [
900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration H0 w/ g. D9 p, r' s
900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.
- O/ } k8 q2 h) J; S900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.
" C6 q L" I% ^# B901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5
& p0 d; P8 F8 Q( w0 A8 E U901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong1 N/ m1 i( O2 m/ e" q0 y
901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page4 p ?9 \8 r8 U& h Y
902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic7 n/ R( ^# l7 \) h; K
902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file, q% U* L' s, T2 N: H
902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional
3 K, `0 [# }; O, C: B' }902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization. X* q7 W- L& G) a* T9 Q: d
902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components4 ^9 h8 R/ d7 d: {2 I2 C2 F" h! ]
902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes2 C' h/ v- P( i* ?2 e7 q& C8 U; ^; Y6 O
902909 APD WIREBOND die to die wirebond crash
, p5 X4 R5 l C0 T902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body. e \6 r. ]/ I8 r4 W
903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline% P! z1 J2 D2 G7 n* u( {. t+ Y
903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.
% E: h" X! T8 Y904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
评分
-
查看全部评分
|
[复制链接]
/1 
发表于 2012-2-21 14:58
收藏
淘帖
支持！
反对！
