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DATE: 02-17-2012 HOTFIX VERSION: 016' \. c1 V$ ?7 d9 S
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) y7 d s4 A9 |+ o7 a8 Y k840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV1 A: E7 E8 z6 @8 C
873075 Pspice PROBE Decibel of FFT results are incorrect.( M" m' h9 p T; y
938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property8 B" W. A+ N& @
943003 SCM REPORTS The dsreportgen command fails with network located project7 Q2 i. H8 D; y9 p2 ^9 h6 Q- H3 F4 V
961530 allegro_EDITOR INTERACTIV The problem of Display measure command6 }- i3 d" S5 ]! d2 s8 I- d3 B) q
962157 concept_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?" n4 a3 C1 @4 a4 M
962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend
N" x; e) ` l S9 O968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.
- G! c. w! S4 w! l968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.6 ^: o! p9 }, `. m3 w; \6 y
969450 LAYOUT TRANSLATORS orcad Layout to Allegro Translator crashes
3 m5 @$ }6 c( l2 H8 {# e9 S' }2 i969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~
+ |& J- k5 u4 D& V7 v; \8 Q: W7 `* f971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.
- O/ S4 k! G+ S& E971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure6 H4 {& H. t. W7 t+ |; d+ _" {
973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR
8 m" A6 x+ L: O' S973859 PSPICE ENCRYPTION Pspice crashes with encrypted model) ?$ [( I4 U/ z% @
973938 PCB_LIBRARIAN VERIFICATION pc.db is missing
7 Z ^# S/ D# o) D# f2 \& x w974540 CONCEPT_HDL CORE Graphics updates are real slow+ R5 o/ u6 P- U2 E+ I# k
974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?6 `: B0 u0 ~: p$ T7 L; L
974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported., c/ X3 N( E' G$ z& M
974945 ALLEGRO_EDITOR skill Why is axlPolyOperation is giving different result and not working
1 _4 K: ?9 T, }" l1 p6 H4 }974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology( E& W& I. g3 x* D1 a, Z( ?* y
975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5
/ m3 f9 g0 D% S4 F& M" t* |975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)
( U$ p. k% Y) a& t975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move
2 D: ~! I/ B. T6 Y6 |- z975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits
: B. o; ?% k% I' M0 E$ P976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.0 J( G$ a' W" _3 ^( i# R2 @
976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views
- A- s0 C( W3 f/ i976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design( @$ _3 }+ g5 q( d" U0 q
976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design4 L) d% F9 y5 ]8 t
976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC
/ U$ |* [, U* c0 V976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value$ x: j1 o0 f; L4 @8 N3 |
976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash* u% u; |8 x! F% d; M9 ~3 h U
976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.
9 l4 \9 ?+ E5 F/ i; c977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3" l2 }* G$ u5 J/ B& A* S7 Z
977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro
) f7 K; c& r" f$ T. B% r978652 ALLEGRO_EDITOR pads_IN PADS_IN fails with ERROR: Finished with errors.- n) f$ }4 ?# n# R
978744 APD DEGASSING Some shapes will not DeGas on this design
) ?7 h. x, B* X8 N979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection
) E* s9 i* `1 @3 H |+ M" u981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 15; O: i! r; `$ [/ B% Y" x
, N4 u- q0 T- b9 \
DATE: 02-03-2012 HOTFIX VERSION: 015
% e! o, m z2 W: u1 a( v===================================================================================================================================
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===================================================================================================================================
R6 t& S V2 s1 N; D; Z4 i1 b1 ^871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager
/ W' g: F0 e* |5 D$ t/ i, O921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension l6 V0 z" R2 s2 l3 T
941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design9 }2 ]7 a; ?: b+ h
954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning8 {0 C+ i" R) f' u% |, b; ]7 n
961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version
5 \, R1 J0 r8 X n7 r964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project
4 P) u! x P9 | D, V6 u$ T! o. c967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only
3 p4 m6 K% R j; F& O( P968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol
7 l# B" i2 _& J: ]1 F6 n" Q969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.55 @. Z0 Y9 q; `4 H- ?- l, W. c% _
970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance+ P- n6 N3 _' b* K
970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins
9 r" P! u& o1 V6 E4 g970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.
. F1 Z9 H) P* _4 D# U970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.
2 R8 L7 M% D6 E. h! [3 w0 R5 ]2 Z T970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash
: K5 Z+ q% F( Q( U5 p3 L5 h% l971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design2 O& ]$ V' f- p
971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances
: C9 l: C, ]" }, I972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM
, U* H+ b$ N9 E2 o8 L" i& _972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT( L* V5 {& k w- ?
973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.9 U1 ^" {0 }0 ]' T; _
973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized0 _2 v$ [, [% X4 @- u) @
973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value/ i) ]8 o- s7 {: f) G3 h/ g
973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.! E1 c. u, L3 {7 t) [
973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net3 Z/ i6 k3 k: B
973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application4 c, I+ \2 d3 I6 h
974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.
& N; p3 b3 K" ] p974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working' T! q$ | L) \, j
976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index
$ J3 } m5 d1 U7 @0 \$ a8 x: d6 f' K7 @5 j$ @; t
DATE: 01-20-2012 HOTFIX VERSION: 014
( u6 l- R% i' {6 \4 A* J+ v, [===================================================================================================================================
4 ~, U- s3 V* Y. d, bCCRID PRODUCT PRODUCTLEVEL2 TITLE
, q2 Q0 t- a' q _, z# l===================================================================================================================================# N4 i6 m8 K6 A2 Z1 d! l6 ]5 {; \
733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server
$ j8 w3 _ Q9 m, p2 V941020 SIP_LAYOUT OTHER Soldermask enhancement6 C W0 V' s3 q) D3 T
946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?
4 c1 y- N$ m$ n/ e G z3 _953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable o' I! ` ~3 j
954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic
1 r1 g, j" b! b6 E956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs
! D& y5 |% q/ @) q958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive4 v3 ]3 w% I6 |$ t- C! T0 }9 x
958395 ALLEGRO_EDITOR SHAPE shape voids won't merge
; F' n% S; b$ K$ n' O( x3 ~- L2 M% \959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.
! |3 l% _8 U4 b. y$ l959940 APD AUTOVOID Void all command gets result as no voids being generated.
/ X# N5 W4 |- ]5 X2 r( Y+ m960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message5 h$ g/ C5 ~7 ` t- e+ f
961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI
& X0 k _0 z# ?) W. s% t961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.! ^) k0 i! s. w, K0 Z
961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification
& A _9 ?7 G3 ]1 F961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.# N6 X C2 M7 h5 U1 e: E
961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.
+ I$ U; Z/ z% C961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM! g9 n. c* g E5 i* o
962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine3 w8 ?% m; o# } g
962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires, b, X0 F$ H7 O3 A
963232 CAPTURE MACRO Macros not being played in Windows7! L7 C; l# H1 z# s5 V$ X% k6 z
963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3$ A6 Q: K4 Z" ^
963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux( j7 B3 d0 d) S f/ x
963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design
; b, M# h; \! L! @7 j963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length4 Q; O1 x6 z1 P! A% q
964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym...% L/ B# K3 l6 V9 v3 ?
964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs6 }5 J+ i7 k( v2 Z
964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)
, u' J& l* {7 H# k$ a3 ]" z966148 APD INTERFACES Character Limit for DIE Files (*.die) Import
( P8 t; a0 G8 R6 e% D p) _0 ]966416 F2B PACKAGERXL Cannot package this design' ]6 x& @2 O: ]4 d# R: [
966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks( M( ^; _. } }' ?4 i2 j$ p
966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open
3 `: {+ J, V( E: T" |966795 ADW ROLLBACK rollback utility does not honor -product option from command line: n! p8 H+ I e) i+ f
967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.. Y% t: \, ?0 ^+ S9 v9 W6 R' X5 N
967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing
& i0 K4 h6 ^" k8 n9 m967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program7 m* e8 _& y# ]# Z
967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.% L3 w+ W s8 w. x/ I( i* D! d* t
967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL+ Z. H5 q- i1 I' }0 G
968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.! s8 ? b5 n, a0 ?. l
968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell
4 N' I7 h8 C0 M% v6 _" l968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager+ k% X8 w8 T" l8 P8 c
969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes
, S" I3 X, _2 r, P c; J! f9 k4 H8 j2 y* x8 c: C
DATE: 12-16-2011 HOTFIX VERSION: 013- } B7 M( _% a* U: D4 G
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6 V; a/ p }, T. D875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.% a7 ?9 @2 o' a
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design
1 P/ s1 e# D0 q3 `938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT) V, ~' g* ]1 ?- x/ F- [
941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
3 E. x" b7 P& U' o ^5 f* v( U3 b945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command
& f& Y1 d5 A+ w/ O( [# P& |; _946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
$ e: [6 v" a* |7 m& e3 K. q" w946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.* N5 c, \- U5 _/ v, z. X9 B( x
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function3 X2 B$ R: O1 \4 y( W
953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
5 E" M2 c- ^4 J" X953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block
9 i" ^0 ]1 P0 |953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
% ]& c' n/ y$ ]7 d& L* t953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�& y5 D0 F8 t3 g/ V! m) v
954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.( b+ e4 g! K9 |
954498 SCM B2F SCM crashes when importing physical
& s+ \* v* B/ S+ W( [6 O: y0 C954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
* r* ? g& ^! H# W/ i) c% K2 Y4 V954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.32 b2 j$ ]6 \4 U
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view: D& p3 C& ^+ c6 Z. n
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
* M$ }0 @& V2 U955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window
& z: j" o0 l( m/ j! S, Q* a955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
2 [0 w1 l* y6 Y; u7 M955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
9 Y5 d$ Z9 J+ }1 u- C955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL+ i' f" r- Z) p0 \9 W: J( X
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
/ Z0 A b ^7 A955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass9 g: e q4 }2 p2 [6 U
955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void2 m3 g5 a9 b. g- w- k1 | Y! f, u _7 Q
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.' P2 R$ Z V" u$ y4 c) e5 V
956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
) x2 Y, W8 p1 w956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box.
6 w9 l- W4 n7 m. X9 S/ |' u0 _/ ~$ q7 \956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
7 \. {1 E: @7 e, G7 ~* B956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined( n4 P$ i3 t* M8 p) w1 x. \! ?' l! G
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board! c4 D( s; U/ K, p* ?& D4 a
956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component, R. d9 M, Y% k+ S! m$ i' ^" B7 O
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly$ k8 O) a9 b' ? A G/ x7 r. B' k
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
; c" U2 F! k/ u! J% \8 q956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results
! T" U2 @- {7 P* b956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty4 f( {& r6 y z) {, e5 D
957009 CAPTURE NETLIST_OTHER Problem getting database property in mentor PADS PCB netlist
4 v* r9 u8 v: w5 q7 J- d5 O6 k957137 APD DXF_IF DXF out command dose not work correctly.. y* d7 @! j r7 d
957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable." M& B) p! V- `5 Q. k; e
957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.
$ f( P) K0 ^( G8 [" Q6 ?4 o+ c957267 CONCEPT_HDL INFRA Packager Error after Import Design
) ?8 R" `% }; F4 h3 B957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file. v2 d4 G% a/ Z" ?
958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files./ P2 V- i. F+ p8 U+ ~
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design
+ t: A, G) d; @, y958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.7 G' ^6 ]9 H- m, I( l
958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs9 v( J' z' W3 f; I1 B+ W
958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
& I9 u; s8 J1 ?4 E2 ]3 E9 V959011 ALLEGRO_EDITOR OTHER copy problem of via and cline
* i- `+ t [, o% v6 A! x959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs' b; `+ I6 x5 I2 o# Y) c. P1 U
959253 CONCEPT_HDL INFRA Design will not open2 K6 k# x: \6 H4 ?
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side: f- K8 f9 T( Z) l3 {) B! I9 y; } |
959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
' o. k: E* A' _# x9 G8 f959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred2 K3 D; l7 D5 l( k0 q
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.9 f7 h: J9 S, s5 L& y; s y6 z# }, |" F
960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.% E$ v+ b Z9 T5 r5 m, F
960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
* {6 u' y1 e/ k- s961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
% @; d3 h4 i4 ^, M961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol, B3 t+ _- `4 T1 _. [' m& Y$ J# L
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers
9 v# @ x% L0 R5 p
) k2 ]7 S/ e2 `* ?- eDATE: 11-30-2011 HOTFIX VERSION: 012
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959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats: n8 j1 E4 R, S( J8 W) ~
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DATE: 11-18-2011 HOTFIX VERSION: 011
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0 O4 q Z/ }" z8 H1 x/ \7 z735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape
! o1 f; g4 s2 K; ^894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?
0 I' a( k4 t/ s' w' I% k903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL0 R' F9 E, F3 b# v, S6 O+ F9 ?
909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?
7 a5 H% m( E% f1 z( b+ I2 H9 n3 b911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.0 O$ J, Q& q5 u' O \( P
919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode
6 b4 v9 U7 ` o7 a- q" V+ E( @921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined- y0 j8 W/ _4 C7 d K
925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.
& O6 a; k- m6 L6 k4 }. H+ D926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows
. G8 m C# T% b3 c1 ~! ?927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list
1 Y g) E* D$ ?9 p" b; ^- t934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.+ ?+ Q$ F+ A; P% q. T; G% ^( R
935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic
% q) Q* i3 i0 o: K937165 SCM SCHGEN Can't generate Schematic
6 b& E9 C- u& a- Q1 U937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search
8 o$ g8 ^1 r9 c5 l( U# e937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails
% ^1 d( X6 |+ D4 z0 X: x1 y939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License7 _# J% Z# C! Q3 e2 M& W& Y
940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup
" \# ]/ i: d! v940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in, s- O7 Q/ z9 U( [
940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad
' }7 B" W8 G( @3 h# S# U940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.
% j$ c4 e9 X. w940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq+ U1 R( [2 j9 F* W) G& N
941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups& v: @ C7 \" B* [- J: f+ R& q
941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.8 Q# {- {' i5 T) O+ l
941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script
3 Z$ T N+ A0 e941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?
) d, |( t0 O6 {9 d$ s942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture; o! ^+ V E) T8 v
942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel0 R, i: ^4 n6 w* B3 S, Q9 q( s
942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash) k& D Z# I# _
942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon
7 V5 \3 i# G& ^$ q d( R; G. N942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.
! y7 T: [2 h6 b }6 V942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised
: ]1 ?% l. R9 G8 c2 a$ F) ~943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.
7 B4 z; ~' q" Z- Y943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup
1 L9 ~; j+ y! C1 p, w5 l5 ^+ B8 E944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently
% T# a3 [$ v; M$ E- e944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.59 I! o1 m( J2 }* K8 w0 D2 E8 O
944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines6 a2 x. A5 ~5 T8 l/ Q# w7 `
945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints
# Q5 \' L' q }946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.58 i& ^, H( E# M% E9 w2 v( S/ m4 I$ J
946350 F2B DESIGNVARI Variant Editor rename function removes all components8 L- @) f& o! }/ b' Y5 W! P. g
946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?' ^2 j7 D4 S% \" \# Y& s$ R
946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form1 {" L% _1 F3 i/ z
946458 SCM SCHGEN Schematic generator adding an unnecessary page. }/ P1 \. ^/ K5 {* P3 C9 l
947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC8 f1 {/ c* W% k8 n+ f
947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.8 q( c4 Y. f4 |6 @1 D2 V
948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM/ h2 j8 _0 q, p" Q4 H1 ]
950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.
: j6 i* y/ O$ z& J951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved3 h/ c+ ^+ U& n g
951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original& t8 Q* G! q) r# S1 e# E* g
951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?
- m& w; {' O# x951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages
' l! Y! a" f; U, C& Y7 V* e951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
$ k9 e3 T3 ]# G: [% d% i. D952057 SCM PACKAGER Export Physical does not works correctly from SCM
$ W2 k7 R$ C+ h% ~+ R0 z5 {952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor; i2 f: \' `7 y7 a; r! Y( w
952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.55 \: W& O" p0 X' ~7 d2 j
953018 APD REPORTS Shape affects Package Report result.. x9 b. R2 d/ N6 |0 s1 G
953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.' [# I6 T" I f
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro6 |5 K2 N0 Z% n7 R G% [0 s, S
953918 GRE CORE GRE cannot route second and third row of pad in die symbol.0 M i& @5 ^6 L+ O/ _$ H( L/ _7 H! D
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path
) H: g7 f* J2 W8 T; q954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report
) [4 k5 |9 ], W& m1 L/ O% N5 H% Y- g% o7 c
DATE: 11-7-2011 HOTFIX VERSION: 0105 f- F4 B3 k: G9 |2 d- o; j: ^
===================================================================================================================================
, X" l/ _- O7 f2 H: DCCRID PRODUCT PRODUCTLEVEL2 TITLE. s d% k- j% s* y
===================================================================================================================================
9 r& q! r+ r8 b' A- Z4 o" g6 b658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline
3 V- f! | _* j' Z) z: y- v$ A928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
/ _1 {# A( A9 Z9 u" h a# l9 H- A! ^934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile
5 ]9 s; c3 m) f/ |: P5 M938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem
9 [; f% [6 g( V( Q4 I938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.5 V, p4 ]: O- ]$ f
938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer1 ]( y! D- u, \9 R
940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete' R8 A0 h, X4 h) ]; L
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!6 g8 W; }9 l1 C7 ^& V5 s% x
941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning
, X. A$ `9 `% R. a% n( E' f+ T; D941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen
$ E+ k' C% U1 ?6 _& |942914 SIG_INTEGRITY OTHER ZAxis delay calculation3 D, v1 `) k0 y" D8 i
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash* t$ N; u6 o: N' |* v% y2 ~) A4 }
945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die( ?/ G9 G* b4 K) ]. w( Z
945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.
. I' L) J1 F0 k& v/ i) G9 Y* B$ ?945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.- o3 O# @" ?! B H
946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions
# t% N- { C: i0 V# d: N# Z946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch
5 h) Q# r' `% d# k/ t3 W946819 SIP_LAYOUT DEGASSING Shape degass command7 |9 o& L- g7 u0 f7 Y; g
946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up
; i$ p- n9 v( i5 }: c947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.37 Y2 T. V+ o4 U+ I9 M* |
947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file
! L( {! b8 o' q( T7 z! r6 s/ z9 M950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic9 Q7 L9 O, A- ^% p
951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37# A4 A. X9 n- y* r% C' k3 V- m
951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol
5 \' r! p8 U- g4 e8 D* U, K. L
5 b, E$ [) T5 ?+ ]DATE: 10-26-2011 HOTFIX VERSION: 009
1 k! N# r5 J4 M4 e0 @===================================================================================================================================1 a$ W; C3 c! p- H& F
CCRID PRODUCT PRODUCTLEVEL2 TITLE
4 T/ y: Y# ^ B- u===================================================================================================================================
- g/ ~4 s# b k# {( m4 ?945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet
4 N! y9 }( N9 \! c9 o/ y1 a9 B; Y G945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference
+ F. U4 f# `. M7 t( E. F: J: I, V$ Y0 m8 r: f
DATE: 10-21-2011 HOTFIX VERSION: 008
$ G% S$ P( a) ?# {4 B. j( N===================================================================================================================================$ m" g U- b) A
CCRID PRODUCT PRODUCTLEVEL2 TITLE$ O7 w2 S7 q% @7 v
===================================================================================================================================. y& r* W4 i# F6 c6 j
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.
- g& l: d- b3 [923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
2 q& ]! _6 F7 _6 m' ^1 z926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it
9 ^) q* b1 Z7 a7 g929348 F2B BOM Warning 007: Invalid output file path name4 E# ? m2 f; B& `
929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error
( }2 N. b9 i- B, U: X930783 CONCEPT_HDL CORE Painting with groups with default colors$ \* |6 ^4 u" Q/ O7 a2 N, x4 x
936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode." P# a: x: `2 Z. @1 f
938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR
- K, F$ E4 W0 l6 u! C938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins
' e: _; ?) ?# Z938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.' X% z. }" c5 v) c" n9 @
939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window) H$ M$ I: ^3 w' ~4 \- f! Q$ F& Z: q
939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design. L6 k. [9 G. n
939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)
9 }: R4 ]) g6 `, b1 n. H8 k939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.
1 H6 t# R/ d5 u% c/ [% V4 W939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.
; r3 G5 a- v8 F1 y0 E. f939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.
7 Y6 v5 a/ D# z! A/ ~9 M' g940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'8 l+ R8 |# n- [( B; T5 s
940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost* s8 Q9 P& ]: ?' ^
941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks( e3 M( \3 B7 R, @. g- B
941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3) i3 Q4 j+ Z; O1 @/ T" Q- e
942210 SCM OTHER Is the Project File argument is being correctly passed?9 b) I) e) O9 Z/ R8 c
942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache9 z1 @7 j' f+ P& Y, F6 x( J
942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible% h! l K( O H$ I: m3 o0 [& B9 R8 d
943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash
1 e/ ?+ q3 U( `: c1 ]# \3 S$ q) ^' c+ g. l+ n
DATE: 10-21-2011 HOTFIX VERSION: 007
" H7 V7 F( U9 P6 I===================================================================================================================================
4 t& m \2 n8 h! QCCRID PRODUCT PRODUCTLEVEL2 TITLE9 M( |$ N' x. g* t) _3 @0 u+ T- \
===================================================================================================================================. }' w% O. H' @/ ~
841096 APD WIREBOND Function required which to check wire not in die pad center.: \+ H( @* h5 j; S/ S3 _
903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.6 h5 u3 `4 `$ L/ ]
906692 ADW LRM LRM window is always in front when opening a project8 ^( ?2 E5 n2 Q9 J- Z3 A7 L
912942 APD WIREBOND constraint driven wire bonding7 t( F* G$ ]3 L3 [
912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems
0 }+ O4 C, J* ^+ A. \; b915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design4 b: F! p, P* C; }" a$ F
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors1 U, u0 \( r6 T! G) ^$ X
923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure" b5 L, I3 J5 G: w T: E
927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license' O% x! Y% I* @! ?$ \4 a% X8 \' @. ~
927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp6 J- Z; _+ F& u* |: D3 h5 T
930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one: w! w, e* S z! C0 Y
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation
+ o9 \+ K/ {8 r R; V) E930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.
' Q4 h0 s9 z) N8 m930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
) @* C! x; e* k9 e g+ P930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
/ ?. Q% K3 S& V5 ?1 z930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form6 q1 P: f3 |5 l) r! Y
931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.7 o9 ^- p3 b$ x* M1 C6 \' u+ [
932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property1 a# f6 L) U; }
932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear4 z' {2 y' \ P! J0 Y
932292 ADW LRM LRM crashes during Update operation on a customer design
6 F h( _% |- `5 w* y932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
9 n$ f4 d, Z6 _) W9 Y932704 APD DEGASSING Shape > Degass never finishes on large GND plane% P; m7 V! H& Y( Q
932871 APD GRAPHICS could not see cursor as infinite
& `# v$ l* H4 R# M932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
5 ]9 o R8 c4 i: C7 |932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
, y7 I8 Z$ ]3 i8 a( J5 u5 [933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members( V" N2 p& m/ V* I2 ^
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown0 B6 j$ V5 G, G9 h
933214 APD ARTWORK Film area report is larger when fillets are removed B" ~- d) h+ q2 d8 `" I+ y
933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
1 g* s) }( Z) E& T7 K) @933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass( l! R7 `- {& v* m2 K" f
933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.
2 }6 b! ?! @' s. m! ?934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values5 c+ f9 F7 \6 n3 [, Z9 h% W
934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs: Z) d9 d2 u% A: p
934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash
) ^6 B. }5 J/ v' Q0 }* S$ U934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.3 f* X k+ o1 a& C2 ~0 F% r! }
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
( I5 l0 z' {. X* t* u& V934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound/ {# U" \9 }# h- L+ l! O4 o q
934909 SCM UI Require support for running script on loading a design in SCM. c; n( P+ v, N
935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.
( B2 I E: \6 |% Q. ?935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3
/ z8 D) A1 O; C; {4 M+ e935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash
, d% Y. o# k `/ i' {1 w: o936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol
7 T3 _0 `7 y# F; ?936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.3 K9 E5 _; O% K( @0 P- j4 E/ n C/ L
936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack
) r; n2 y h( n2 L* y936797 CONCEPT_HDL COPY_PROJECT Copy Project crash- V+ v. J6 {$ f. L2 E6 P* w% W! ]
936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol( Q' d4 l2 M9 M" B* o: u
936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM
! B& C* N% K& l* Q- u0 H% Q4 K; l937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
( W) e! [2 c/ |3 C# z937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About+ M$ X4 J8 z. E) [5 ^8 S/ u+ H
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.9 S& ]$ C* v; r- b/ I
937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.
; y: A- i2 h7 R938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.- }5 ?, r5 T$ s0 B) x4 Z
938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set( n: d; U3 x; T
3 l$ ?6 d7 y% O$ n2 ~$ R
DATE: 09-16-2011 HOTFIX VERSION: 006
. W: ]+ t1 {! s8 n, G3 D: H===================================================================================================================================
1 l8 U) ~5 E8 o+ l3 l- QCCRID PRODUCT PRODUCTLEVEL2 TITLE( M4 ~6 X* @* j4 i k. b
===================================================================================================================================! \1 q9 n, z9 k* L1 o/ J8 O
820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.
! l5 o1 X+ a, I& e1 T4 Z- O; Z$ Q$ y$ q863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints
7 V0 F+ n9 d' T+ k919822 TDA CORE Cannot configure LDAP to only list the login name
- A$ t8 w3 k8 b$ h# E; }. `922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error% r! R6 ~1 a6 w( p2 x% \8 C& @1 u
924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results/ o+ J9 f7 R' s3 ^- U
924448 F2B DESIGNVARI Design does not complete variant annotation5 F6 X9 @5 ^4 \5 r; {9 U. r; l
925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB9 \$ b" I$ z% i
927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report
! {1 K2 l+ F( ] r1 d927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values
4 S, V2 h9 |+ [4 E' m6 e5 R" I927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line
) v! S2 S$ c* h- v927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets
& I1 Q9 g1 i1 Q) D0 E5 r& m927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor% H" L9 ]. L5 Z m% w, I
927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl
7 v( `! S: `1 u6 ]& I927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display
7 x. ^& ^2 a5 l# E, a927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database
6 H: T% [( D) E+ O l' U$ d927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.3 j+ N4 M) V+ v- G7 F$ }' O
928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.# F/ J$ c3 L# X& G4 M, J* @2 J
928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list
* i' B& h) x- C) M0 s928738 PSPICE PROBE Y-axis grid settings for multiple plots
. `, [" l" ~" M2 [6 \928748 PSPICE PROBE Cursor width settings not saved$ T* o% C# V# m* @2 k3 R
928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release" H# Y, a# B; g3 L* l( Y
928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.5
" u4 l3 {6 g/ m' w9 U8 m928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe
+ e- y0 W5 Q ^9 h6 x929284 CONCEPT_HDL ARCHIVER archive does not create a zip file
: w R- t* J& S* j: E0 o929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP
+ {+ c9 l$ ]% Y" O5 ?& H929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error9 ~: g3 s6 O* S' ]; L$ a
930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape' n& O, _. `$ C, P0 a6 L* b5 ]
930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.9 |. L3 \! w& z! g' C
930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
7 n+ X2 ~: W" i' ?' F P930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.
" i" [6 Z) z" N# o% O" f0 e r. O930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well
" U( x. @, E; q/ B8 }930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name
9 D* N$ {0 @6 t1 p2 I930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked" U0 d# Q# N6 c/ J: b
930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens. e' r" [3 y( P$ V1 l3 ~6 L
931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.
' [, q+ c, q- a% _931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version
6 h. |. A" d, X5 }! u931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.( Y% F3 X. t7 y, x- L$ X7 Z
3 D# M. v0 f* B
DATE: 08-31-2011 HOTFIX VERSION: 0058 w; V% i: B% ]- S+ C. b/ l
===================================================================================================================================/ ]# F5 _3 a5 A8 {& p: d, f y
CCRID PRODUCT PRODUCTLEVEL2 TITLE+ A4 h/ B) \4 W& G
===================================================================================================================================
% Y8 u6 P( P+ Z' F7 C1 K4 }825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole
: U `# J( Z' m$ E! Y' I837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show( ?! q0 U+ @7 I4 D2 H
891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode
; U/ x \, D! v( w: ^1 r9 J910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.4 m$ p/ ?0 n: v; b# C. ?
914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.2 h: _& ?/ _7 ~3 ~9 ^2 H% n% ^
914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs
7 B7 X" D. h+ c( i914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity6 W* |8 B4 e, L7 a& \: `
915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location
- _6 X5 H$ T4 O. R+ F" | @& m915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape
& L+ S. u; A( N4 e: I915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working
5 n0 L& Y7 J' V5 Q: U- c4 ?916321 CAPTURE GEN_BOM letter limitation in include file$ I2 k \% c: q) l! F! e q5 [9 b% l
916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects
, c% E& G, x( H- [6 F$ m4 d' Q920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.
# r5 K8 d+ v. f& F920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.
4 {( T: I7 a3 g( h( A: H* b921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set
& z, m( m- H: a, k921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.0 a/ F M, E9 }" k0 ^$ M
921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002
/ e8 p2 }+ l' I921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions4 I, f4 U' {+ {: A
921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly: D* ]2 _4 V; [4 h; J! a
922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.
6 W/ q9 I) n* p) p8 l! @/ F6 U922117 PSPICE PROBE Label colors are not correct in Probe
9 t$ K- s: d8 s5 i* E1 v2 h& e922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all5 c1 S! ^$ u% J3 {( T
923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S0020 `; S- Y0 V% e' E& ]& v
923286 CAPTURE DRC DRC markers not reported for undefined RefDes) O) R/ |1 O3 l
923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5
' {; w) Y+ h5 R- w: ]923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top+ a( |4 z( J! q& l/ l; Z* \/ D
923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)
9 F, I% L* s3 r1 e0 G O4 U923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.8 ~& w* F0 a0 u5 U: F; T
923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design
8 r( b5 s) H7 j; ^0 ?. O t923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on
) a, G/ \, h! O6 m; N& M+ Q# v923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error
: D, M1 }# y2 G9 t' \& s924458 SCM OTHER Project > Export > Schematics crashes
. I7 e8 r. b, m/ O- M9 X1 k6 S2 K924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
! {+ F1 T2 Q0 r% [925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect
$ p `+ U3 m. U+ [925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error
/ E! Q+ H+ M" ~925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
) r3 P: b% Z( x4 b: g |925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.
0 G+ y2 Q5 i) j- [ J' V$ v925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?' r9 l0 J' b* ^% n+ Q0 y# [/ J
925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS
! ?' c) Z1 X0 o! I9 x+ W925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data
0 ~1 D8 I0 h j) n7 b$ K926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.
$ o5 X; O4 z2 a- s( B' u926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.
. ?5 J8 e8 L9 b' P926503 CAPTURE GENERAL Memory leak Capture/Pspice
" y! D5 i# P$ R. d- n926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet b% g' L" z( V4 m9 p! b
926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.5 G: U, J4 E7 d& n# \/ U, u, P( }/ m
926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical' e2 ^8 H( h8 r/ E
927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''
' o$ O' [( d$ D3 c+ ?" S5 y, w0 M, \0 E5 b; [$ \
DATE: 08-19-2011 HOTFIX VERSION: 0047 x. k# t1 U, i& |4 l! N" Q3 y
===================================================================================================================================
7 w8 c9 K5 C& K+ q/ j9 f* p8 kCCRID PRODUCT PRODUCTLEVEL2 TITLE$ l% F0 y( }' X* S6 E$ M
===================================================================================================================================4 D3 ^" P) i" n2 k- o9 j
785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error* |6 W$ _7 A$ N4 i
851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.) ?; b4 g5 i5 k, _8 E0 b
868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments
; \5 C/ a2 {6 L; u1 L870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file
" R8 h. i3 I/ f# @, P ]) s877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form% q) Z6 g. v% x" K
894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window0 I& h0 D" p' a d; z
895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 13 Q) B( v6 @+ ]; E9 {) y$ K: {
895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement' ]7 ^6 B7 r7 F* S6 K
903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.
% ?4 e. p) w z( R4 E8 ]905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.
! f4 i* E4 U8 b% G( w+ V% V4 v909469 SCM TABLE ASA crashes when opening project$ b& h- S: A7 `( [9 G
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap
: [! E2 G/ e7 G+ G0 h) F911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152
8 d* O/ a X+ a911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?
' a- u% Y, x o9 Z ` j4 \8 }915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability. }6 Z, z+ ~* C/ b: Q2 N
915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP8 C4 I7 B" T/ b2 |) h2 D: n
916062 CAPTURE GENERAL Auto Wire Crashes Capture
. u8 C6 b( c' X916820 F2B OTHER RF create netlist with problem
/ r. i0 ]8 E0 H2 U, z! C7 _2 @917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.
' J: C% ?. q) O7 P4 T% [ H919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file+ ]) s( [2 S2 N2 y3 a
919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working" ?* u* h( @; v1 l
919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL
0 w; p# T" C- z6 X9 d4 `! M% `) n/ v, D6 V919976 APD DATABASE Update Padstack to design crashed APD.
6 z: g3 B6 i3 o; {# q920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition
3 b# f1 S u/ R920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run
& u9 q, F0 x# E& J' T% b. X920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork- H6 b+ W% [4 R# n7 F
920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins
; D; V% Z% c: |% T$ e" W8 f5 q- p920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min4 W8 J) O0 c9 K7 P* L
920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net7 _+ j1 q2 @7 j' M$ E9 F. Z
921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.
3 W6 {7 O+ p% D3 |922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
2 o5 G k! d! Q+ m922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named
6 a, B4 @/ E( J/ H& B! N922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin
! ~3 \. v% \# g# M% d, Y' t- T- I922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.
. z3 L7 F' w% P! c1 t923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log.( m2 U1 E9 j; J/ b
924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf
( K0 W$ i& ]; }: E6 T. @6 y. u8 h. w
DATE: 08-4-2011 HOTFIX VERSION: 003
7 V. g" w0 Q8 _# b, c===================================================================================================================================
/ M* K V6 X4 XCCRID PRODUCT PRODUCTLEVEL2 TITLE
* w/ l# ]) t& U5 N===================================================================================================================================
P. Z, ~2 S! w3 i4 c/ C787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.
( {/ i8 m) k X; Q$ c' Q# l903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics
: z! ~) j* W7 S5 ?: R/ e% W904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.
) h4 r; b. {# t! G2 y; v4 H" l5 o904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result- H/ _3 R- J6 }7 Q' \" n' h
905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged
% V: E' O5 d2 m8 r" b \, E# z5 Y906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.8 n! y% N, \4 I F0 a
908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance" l3 t8 e9 c% t7 G; K5 M; [
909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.0 _" A* f& ]* y5 \' A
910315 ADW LRM Import Design with ADW causes partmgr and pxl errors! N* A) L" h# }4 n( u+ K
910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5$ u$ u, `5 f) h" G' |6 F* T+ B
911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5$ M* Z+ n. E4 S R9 }- t$ w6 `
912343 APD OTHER APD crash on trying to modify the padstack$ w: Q7 t8 c' r0 L# Q' ~% o
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys0 c* o- p" X$ n. a6 u$ \
912853 APD OTHER Fillets lost when open in 16.3.! j+ ?0 Z4 r0 t0 o: |, Z B
913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.; O3 q& W$ \* K; D) E/ A& i+ K6 M- D
914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.
6 n1 \# @+ ^1 T4 x914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks$ Z' u1 V' ?- a$ [8 Z& y6 T/ Y1 e
914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.
P7 q9 D: c" b( J7 v* t6 N914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design
7 V) Z$ B [8 |- r8 O9 F+ l914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape5 R& D4 Y& O8 `+ R1 h! m
914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.
9 p8 `/ s) `. ~: k4 m/ e$ @914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset
0 Y/ Z( w, [# w. ^. U% y914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.6 ]0 _; d' _9 v7 l) o6 X, ?
914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling; s6 K( f( R: y. m
915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3
4 M& z: _$ p2 E915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models4 E: Q3 [3 N3 Y0 F7 c
915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol
, c V- b/ x& r$ k* o1 @9 E4 S k916154 SCM NETLISTER scm crashes when exporting physical database to allegro
: ~3 V& O+ i2 d, `" Y' i4 K916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors
, h$ R3 v; z3 r U; ^5 n( w916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor
/ y/ f7 a: }% e, m9 n: Y& C% ?916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report
6 C2 I* p1 K% V) z) B/ k916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer
# V h4 E/ @, M7 e916889 CAPTURE NETGROUPS How to change unnamed net group name?
8 w* s6 y( s5 ? t' r; F* M917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film0 J' W J/ F6 q2 m5 n% |! l
917434 APD OTHER Stream out GDSII has more pads in output data.
% y5 Y; s0 V" a917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net0 A3 o* l; c t- X( i' g5 u
918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.; W' U+ R5 [2 t5 F4 B
918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol7 ~8 O; N' p/ V4 k
6 j$ c, n# p! Y- n1 `; KDATE: 07-24-2011 HOTFIX VERSION: 002% S6 r3 p% H6 u- G: Y
===================================================================================================================================
6 t5 G$ y, n/ _2 yCCRID PRODUCT PRODUCTLEVEL2 TITLE
# M i( Z5 v; r1 Y5 [ S===================================================================================================================================
& A: H9 B5 M( S( s$ {2 U8 B527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings! Z2 N* p5 ]. J) s: l- d& m: T
583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.
5 F- K: H3 b* F4 O( \8 o592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other., I V6 C$ |4 _7 a7 ^
745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.- `# W3 `% v) V9 h
773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.
5 ~( s6 Q v* C( ^1 D( \774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.
; T2 ?0 O/ S( a5 o% }6 w2 s/ N799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs
' p3 r/ ]) y0 Z# V9 z7 U+ P' D809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".9 u; y/ h. [6 }$ h* `9 x. K1 B
810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
# d- P- j8 v% H- H6 N821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format2 k7 D. N3 c: [. {
831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself- a9 q6 v4 {% ^9 \& M. p
842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.
/ R0 {8 M" E" ~ o854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group
* j3 l7 n8 \, x P4 e860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser
# X/ K* t$ ~5 |: z4 M1 \/ L6 q867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location" @7 }' c+ a- {8 k
868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets% j8 I [/ F9 v% f9 _& S! v5 r; H
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
# B. V) ~5 [- y891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
% R9 Q) s- F2 F+ K893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
* O9 Z) ?6 j# P& G$ S: I x893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.7 E& I0 c7 t1 A( }, v9 h3 ~% F
894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command/ r/ ?7 Z( W6 _
895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs9 O5 I* K: u( x/ M
896598 ALLEGRO_EDITOR PLACEMENT error message is misleading
6 u, w6 X* l; }6 a# s) r4 D897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library: h) N* x# O" l' T+ ?
898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.# l& D2 B, {' |7 k \
899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
- K7 J q! w# B900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5
" q4 I. @+ ~! s+ j* P2 W901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.8 E& A2 L9 ~0 R1 e! A- @. B
901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page* w6 Q1 h: w" H5 D1 q
902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
. L/ g4 ^" I% w. _; l# n902349 CAPTURE LIBRARY Capture crashes while closing library7 ?9 u- X% [: P) B- i1 e
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3
8 o% V8 Y/ H* y' h3 t! n902841 CAPTURE GENERAL Capture Start page does not show
$ t& Q/ d: @* c4 j, z902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5: o9 ?( i& _( v
902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
* ?! g+ b- y$ S903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?
$ b5 K8 L% D2 [: {4 y c903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition
3 r& d, Z5 H0 s) F903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor
! ]6 R. N. S% ^$ x- d/ _904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable
' t5 L. r; ?4 M3 f3 {# D904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE7 }* r: F* x& {3 Z/ E9 J0 E9 v
904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3( ?* J1 A) t- f9 P4 g! p5 G2 s
904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places Q; [; P6 H. G( {" O2 U
904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.
$ h: t/ _) H! @( l1 i# h( F904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3
& c) l7 w6 t5 \) i& B% F905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
& H' p8 ], D* z! ^9 a; n: |+ J9 F* S905314 F2B PACKAGERXL Import physical causes csb corruption
) q) U3 Z: c: N5 Q& b' ?6 {. n: k905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
4 R' k! |8 W( V/ z" z% i, U0 p3 o8 l905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
; l! Z0 q1 W% q: o* d: | M905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues' n2 }5 m) z# c: [6 Y& G5 O- i
905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid
/ R& c' }) x& v2 ^4 a* O3 L906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.# K$ I) c' s& L3 N1 s4 V
906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
% W' |5 ~4 \7 {" z( ]- i906182 APD EXPORT_DATA Modify Board Level Component Output format/ S: j& C3 S/ [1 J9 W% A. `7 q8 x
906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element
9 ~+ Y% X+ M2 ?/ J; i6 T" ~% K906517 PSPICE PROBE PSpice new cursor window shows incorrect result.
( G4 E9 Z0 @4 l; F2 t4 Z% x1 ?906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.% `; d F+ A0 [0 W% K+ h
906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run
! i7 e2 m0 ~8 d9 Q: `906673 F2B PACKAGERXL Ignore the signal model validity check during packaging
+ G% X; Y; ~. k; H0 f( q906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'% l( A: \4 @6 h; o7 I
906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation' S: K& ?) h% E1 X$ z+ l J
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin
3 u e5 c3 ~1 D$ u: R907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used. x- X; i- p) r
907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display6 N: x6 j# P# X# @- ^, U( b6 ~ K
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.
1 d* y5 Q, N8 s" G907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"
( s9 v$ v! O- A# x907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31; J3 ?, T3 c1 V3 ^/ l
907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly
. b" ]& g- `. V, i. H* K907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional9 Y$ W; a9 n( O8 |: t
907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
, U9 }( @/ {9 R+ P. Z908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location. O/ V- ]6 T, s4 k/ p
908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name: j7 n: H0 A, R$ A* q3 W# V" U$ S" u
908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3
: j6 F7 J& D7 r8 g" A& w* |908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component* v9 v% Y" v" }# d7 {
908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.55 s7 e9 k9 {$ V9 [
908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place* Y9 q3 N4 f) a0 Y& }
908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays7 i. j/ M# D2 v
908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes& A3 n" q) X1 P5 U N6 E
908595 APD 3D_VIEWER cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b; H( f& N2 m G$ Q
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design7 @/ `6 e \5 B7 i) @
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature2 t! D4 ]( N4 j3 y# y0 t7 e
909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN
0 ]0 {! S$ y4 R909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.5 `7 t( S' T! a: I
909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux$ Y g2 a9 J% v3 D) j
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
. _3 h3 p6 x1 r( S- n" d4 e909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning
& ?3 s! t- K5 |7 m909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack3 B. A: Z5 y! c6 c
909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
' t3 W3 v0 J; g910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.# \: m. ?7 h" g; E* U2 V& J
910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector, d' k! H) Y# P( ?2 d' Z9 |
910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.
0 H7 h$ e- ~; m8 m' A9 v0 K6 _( f910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5% ~) Q, M2 l/ w W6 X1 o E
910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.
% R" X% ^9 Q* h910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent: G5 I2 l R4 x1 S9 @' |2 c
911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
8 k, \9 f. @( {6 [7 ~911631 CONCEPT_HDL CORE DEHDL crashes when opening a design
8 x+ K, S d$ ?1 a$ `# m1 E: T912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default% O# g0 y: I7 n, T& M
912459 F2B BOM BOMHDL crashes before getting to a menu
* f. K8 h# l6 D5 s913359 APD MANUFACTURING Package Report shows incorrect data
`% s" z! Q, j% R
; `/ u/ b- B) j# rDATE: 06-24-2011 HOTFIX VERSION: 001
! }7 z5 N* F( x0 [. p5 x# d===================================================================================================================================9 u0 C. A: g! i8 ~3 I) P1 A4 }' G( m
CCRID PRODUCT PRODUCTLEVEL2 TITLE2 U7 T" R; W% K) }0 j {. h
===================================================================================================================================
/ I/ A; y: K& Z. A; ~. r& Y6 H293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol
, A. h% e- l' x' g298289 CIS EXPLORER CIS querry gives wrong results
) F/ B' L. \! B9 R: t+ f# B366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text A, v. F% v+ g, z! I, Y; D: n
432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs1 n$ ?$ a9 o D1 u& Y7 S) Y
443447 APD SHAPE Shapes not following the acute angle trim control setting.
/ d9 d) ]$ D) V' L473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam
( Q; w8 a. n$ r517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy: M" W! r- \+ N9 ]9 e- f# P2 n/ k
548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.
8 |, {" E- v5 `6 D% X606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart- R1 P5 c/ @& Y3 |5 j1 @8 n* ~
616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled
# I2 L8 G& Y, X7 H7 I641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)
* \" ~5 ` y# W+ X, L5 E) i644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor$ q$ g9 j& b$ T' ~6 f4 |* ]
645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board3 B. m8 l4 x2 X% i/ |9 ]5 p
725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.1 y% f0 F4 y# a8 }
763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI$ M0 r5 w. n" b$ S6 J1 M) m
770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers
8 C1 a7 d6 }/ a2 e9 ^6 R$ W- @ _792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets
: }5 S9 {6 K! p2 ~! h. ^% s! a799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write: g( C; L$ j: x0 |4 _5 [8 z
803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part
( K$ ]" e5 d" `& j( c804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.
5 R$ m" e. _4 s( o; p/ m3 f! @5 @809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs+ l' @ w4 ^0 R4 p6 K. w3 V' x% q1 L
816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch
9 i8 W+ m8 m2 d- r5 `9 p. L) H B830053 CAPTURE STABILITY DXF export fails if schematic folder name as /) `) P I5 B5 Q. V7 e# b& i
832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.9 l# K" }) H- A) I9 o: `
833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
6 w2 o- d; h" K4 H0 r835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error+ e; c7 c9 M8 M4 ~ b
837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version
" l# E: n4 R6 }2 i844074 APD SPECCTRA_IF Export Router fails with memory errors.& ~& q% a" O% B& u# j" e
851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size
3 m5 \' M% s5 {- @- k852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?4 e, [4 S; x% E h
855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.* | o1 R! T( F
859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs2 x+ @5 n$ g; e1 ]8 I- J, l
866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.* I4 \) W& n( q1 C+ C+ t2 | o
866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line
2 `/ _) ~4 a! F5 B L866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF
# s1 ^- j4 x) a" l" t$ c0 p868618 SCM IMPORTS Block re-import does not update the docsch and sch view
* s+ k G( f2 {/ S# D; k873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP1 h8 a" [% M; S* b' F+ L8 C8 ]0 \
874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.
3 M9 ]+ e* d6 G874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command
/ d- O4 u" E. z3 n* o874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file$ @7 q# ^ l& P
875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1
9 f3 g$ h; o$ u; Q- E1 }8 j, ~) ]876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net I) C4 Q8 X- w+ ^
879361 SCM UI SCM crashes when opening project; F3 t: ?; B% b) W" K
879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.
1 h; p: D* \5 o" z879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE.* A) f9 S' u! F$ V) N1 T" X7 @1 f! L
881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape
/ [. \2 c! ]4 V882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets7 _+ H% y M+ S0 D* e
882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier* t# C. G# [4 S% s
882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.
* p; d" {; l9 ?' t2 C882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement
0 P3 q% @& q- X8 P# ~4 |5 z" k883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component
+ T7 U" D9 e! ~1 Y' V883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager
8 ~+ B& M- m, k1 \9 a; A' e883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder" q4 A: [. s/ t" y c) b) K
885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.
9 g) W2 {2 B1 X) }' g# z885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string# s: V- B: a" k
885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations+ o+ N. o2 ?2 X/ n& @, G
886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid
/ @1 l4 u' }: K/ `7 L887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses' A" `' X& J3 b/ |( b% k
887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.
. i( b7 k/ K. Z- Z: o$ S( K887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message& @$ x3 H# I) d( L% S7 o
887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.; ?* r5 Q) {, n% f0 W9 \ Q' o
888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.
, [) Z) \% t5 H888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic
( @, L0 |$ S; [888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.
T. T1 y6 \8 Q* M. v888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.* g. L7 Z: B9 K1 }* X' M' t
888945 CONCEPT_HDL OTHER unplaced component after placing module, D8 E- j( e8 ~0 N6 Q7 ^
889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.
3 N. g: J0 I! t* I5 E! O0 M, F889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3
1 R& ^. F# g4 W- M# B889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.; O( D5 y" ?* G/ C0 Z2 y! N
889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net
- I) I/ j# I* f% c! D3 j889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form
: a! z% g9 x& Q& {) V4 Y1 C891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file1 j( b4 P8 O3 z2 H9 r8 k8 |- a
891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance
$ ]$ }: ?1 x8 C7 `9 f891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs s& R/ l+ n1 N8 T/ M( K4 B
892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
* v/ `$ K# p3 d% ~; \- o8 n5 H892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?
. P+ b" c4 A% v2 j1 j892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness
6 i# \6 e/ n$ Y2 h7 }, l1 `892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode
! R8 {/ i' @0 \; y% X& s892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations$ p% N- k! P5 F
892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR/ ~; ^6 R- P% K
892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".
% s) E: i& ]5 P# z6 U, |" n, A893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.7 {7 i- F6 I z1 G
893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board d8 }; e4 N8 M; f9 Y
893743 APD EDIT_ETCH Route behavior when spanning pads not as expected., @, s% C2 Q0 K6 O3 q& q9 ~) }% c
893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation g7 q( `" _# B7 [8 }
894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report. N* ?/ U m) I, ?
894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.2 E9 y7 J6 n4 g- [6 Y
894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.
6 L( ?/ E1 |( ^ q! W/ @6 M1 N895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON% |* y+ k3 Y( f* n3 L3 u
895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers
7 ~7 R( S! ~! [' Y- B895757 APD ARTWORK Import Gerber command could not be imported Gerber data) n7 |9 N- d! a, p8 U* r2 W2 s! v J
895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly2 _/ G# r1 m& h
896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced
' Z7 b8 {) \0 B+ d3 a896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture
. {/ V% X( @( }' h, L$ j8 S896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing8 K7 n, ]$ a5 t. ~
897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap.
) `2 z5 x0 M( h- H. j897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.
; w o0 j# @. ?( f) M% J* g899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing- [/ C9 T: ^3 y2 [4 x
899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof1 m1 z. ?9 N7 S/ D) |# r5 [
900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
$ Q; N6 ^$ B$ m8 u- d% p900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration
$ j/ x) T7 C; \: M& ^/ y900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.( T& |+ I9 b( A8 b7 j9 [5 h, ~
900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.
" m) q( d2 @2 E, r' n5 U J& E) P901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5
8 M* D+ m' t$ L" ]7 g* W901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong/ B& O, P0 e' R0 L: d( [
901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page/ s1 r. ^& m: z% `9 Y
902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic
* K4 h# Z8 {7 {+ b# r' W1 r+ W! j902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file
/ K7 } Y9 ^- q; N" i902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional
: l+ c( s* s; W902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization
! u% V! D1 [# O t6 b+ }902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components& i- i m8 @8 p: b) b; e" J0 M! X
902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes
6 ^0 p7 S2 i( i( w+ |. g2 ^; o, \902909 APD WIREBOND die to die wirebond crash
8 f% Z( e, Q1 }. E902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body
/ X' r- H( s) z& i7 g9 {903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline
+ O+ w9 e) s- W6 t7 ]903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.
2 X0 i1 i! I; p% e y2 T$ t904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
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发表于 2012-2-21 14:58
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