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各位大侠,在给DDR2做Relative propagation delay时,发现Constraint information中除了ETCH LENTH还有一个ZALL,请问ZALL是什么?是Via等的等效长度吗?谢谢……附对DDR2 NET的Show Element:$ s* M& T, r, g
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LISTING: 1 element(s)
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% k7 l/ p+ x$ s* L3 D8 N < NET > / Y: a2 Y, G5 z9 _, J+ ~
2 _- ]/ s/ [7 `) F7 l- x' F Net Name: MFPGA1_DDRD23
; L4 x9 Y1 B, j+ D: i Member of Bus: MFPGA1_DDR_DATA2
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Pin count: 2, V: f4 u! s0 @
Via count: 26 x+ @$ f" X N) `) \
Total etch length: 1964.069 MIL( S: w+ w8 u Y" U. i
Total manhattan length: 1135.851 MIL; J4 ]: d/ c: b/ s3 S$ R
Percent manhattan: 172.92%
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Pin Type SigNoise Model Location
0 b4 M; a& u2 c3 J% f1 M: P6 I { --- ---- -------------- --------
3 v6 I$ r' ^2 |+ z' q U801.F9 UNSPEC (-1984.000 6603.717)! Z" }* c9 ]7 o8 j4 r
U796.C18 UNSPEC (-2351.016 5834.882)
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1 |& C5 |5 }4 E0 w No connections remaining
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Properties attached to net( e7 K8 o$ O& } j3 }) {
FIXED
4 h) `" z2 m& K$ K8 {% W1 n LOGICAL_PATH = @dw5vlx_all_20120504_1800.schematic1(sch_1):mf) J9 Z7 G( X- F+ @
pga1_ddrd23, @, |8 G# Y7 s. C; O
BUS_NAME = MFPGA1_DDR_DATA24 k- R( T1 @' k5 S4 s9 R. m
' V7 {/ Q1 a( v1 g) ^. Z' { Electrical Constraints assigned to net% l2 ]2 n; e/ t
relative prop delay: global group MFPGA1DDR_GROUP_DQ from AD to AR delta=0.000 MIL tol=10.000 MIL
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' u8 }( F7 |! Z3 |2 Z Constraint information:
, y* ^( f) u* k (RDly) U796.C18 to U801.F9 min= 1966.14 MIL max= 1986.14 MIL actual= 1980.741 MIL) o( Q( _1 @ h! X. A, z) c9 G7 D
target= (MFPGA1_DDRDQS3P) U796.G20 to U801.B7/ f0 g9 R6 K! O
(-2351.016,5834.882) pin U796.C18,UNSPEC,TOP/TOP
2 ~* q- p7 G8 S' K 24.812 MIL cline TOP
z. a9 u+ g6 v* }+ r& u: f/ p; Y (-2333.471,5852.427) via TOP/BOTTOM$ Y, n8 f; G a
1917.397 MIL cline 03IS011 w& W8 |% c* C( m) A
(-1999.457,6588.260) via TOP/BOTTOM
; d$ v; ^2 j0 C4 i, j 21.859 MIL cline TOP
* j1 N! A% l$ L- _4 d. i5 I8 h (-1984.000,6603.717) pin U801.F9,UNSPEC,TOP/TOP,Zall=16.672 MIL9 J( L5 o% x; [5 o/ P6 D$ B
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Member of Groups:
a8 S- s5 M) [5 w9 ]1 y6 S MATCH_GROUP : MFPGA1DDR_GROUP_DQ: p% [9 u' t1 J3 L5 E7 j
BUS : MFPGA1_DDR_DATA2
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