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本帖最后由 qaf98 于 2012-7-11 18:05 编辑
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6 m6 o# K8 w7 r# Y1 O: W再次查看相关手册。搞清楚了一点点$ a9 A& {" o1 X9 J s( K2 Q1 I
简单来说就是CLK-DQS自动调节DELAY.: e6 s& ?8 a- V# W2 h
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[$ b5 i, E% Y6 p8 m' x! z控制器发信号给DDR3,DDR3根据DQS的上升沿采样CLK,如果是DQS早到,DDR3就使用DQ传输0到控制器。* ]+ O8 ?+ M" [) y
如果是DQS迟到,DDR3就使用DQ传输1到控制器。 控制器得到反馈后,增加或减少DQS的delay,(0就增加,1就减少DELAY), 这样反复操作,直到DQ反馈信号第一次从0变成1后,控制器锁住DQS delay.7 @+ o! m! g& T7 W. S. I" ~: \) N
Write leveling过程结束。
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The memory controller can use the ‘write leveling’ feature and feedback from the DDR3 SDRAM to adjust the DQS - DQS# to CK - CK# relationship. The memory controller involved in the leveling must have adjustable delay setting on DQS - DQS# to align the rising edge of DQS - DQS# with that of the clock at the DRAM pin. The DRAM asynchronously feeds back CK - CK#, sampled with the rising edge of DQS -DQS#, through the DQ bus. The controller repeatedly delays DQS - DQS# until a transition from 0 to 1 is detected. )
: G% v9 [5 t2 u' ]上面就是我的中文意思" _0 s6 U6 D( Z" X4 [! ?1 p( V5 Q
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