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cadence最新版软件SPB 16.5及其Hotfix下载链接如下:* n" N7 r! {5 V7 q4 c% `. g; P
http://dl.vmall.com/c0t5v9lbyp
R# _0 Y: c6 ^9 E9 o" v0 fHotfix中只需要安装最新的版本即可。8 W) C% D+ Z+ J" M8 G
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Hotfix033对以下项目做了修正:* j& ?' M% P4 q# {
DATE: 10-31-2012 HOTFIX VERSION: 033
8 |5 n$ ^* E# E' o n1 `6 F. j===================================================================================================================================( P) ?/ a: D8 ?1 V" I5 M! A* A
CCRID PRODUCT PRODUCTLEVEL2 TITLE
+ O: \4 v9 Q @) L===================================================================================================================================
! _& m$ Z$ C! C6 @3 V% s103395 COBALT-COMPILE COMPILE et3compile fails if compile for 3 boards in 32bit mode% u2 U. l; u2 c H) s0 J- C
715653 Pspice MODELEDITOR Change in pin number assignment with model import for capture symbol
1 {% r- ]) s. J5 `9 J h745682 concept_HDL CORE Attributes window requires resizing each time DEHDL is launched: L" F& `, z/ V$ K0 }+ `6 ~+ B& W
825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted Z+ w* f1 o6 e; P/ o8 `. }$ {
846658 CONCEPT_HDL CORE About Change the NOTE with DE-HDL& B$ O: X; q6 K2 f* V
938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic% K* [' [3 E* j: T2 G
942044 CONCEPT_HDL CORE ConceptHDL crashes while opening the AMS project
1 W3 T0 w- L. X$ p: e$ Z946640 CONCEPT_HDL CORE Import Design should inherit module order defined in the imported block
/ y" _: L8 \' X6 v5 J, e968646 allegro_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
- P6 V0 p& p1 _4 T; T3 |# N969535 CONSTRAINT_MGR SCM ASA retains information in the DCF file for parts/blocks that have been deleted and this causes problems.
+ N m$ R# H( g976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor7 O) }& |- @+ v
981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.7 f: @9 O! D* s6 ^" L
988355 PCB_LIBRARIAN CORE PDV moving line-dot pinshapes left to right or visa versa places pintext wrongly- i! B& |. Y& I, h7 z2 g6 B9 V
988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command4 P* X( B& p% K3 @ H" a$ U
993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).- X* c! w8 Z/ d& c) L: r- b, j
996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections
; V* N% y) H3 k0 _& L9 M997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
4 G( V: d0 a, u1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model: ~) f, @, W" j ]+ F$ P
1006400 SCM OTHER Incorrect warning in SCM due to way voltage value is stored in tabular and schematic blocks9 r# y! ^( ~/ F! P) R
1011502 CONCEPT_HDL CORE Undo has an error on circle in DE-HDL during create a schematic symbol s8 H3 v4 A/ w# M
1011798 ADW LIBDISTRIBUTION generate a differential report on parts in DB vs parts in PTF while running lib_dist
0 B: Z; G7 i. _% I, w4 X1012685 SIG_EXPLORER INTERACTIV SigXP: traceEtchFactor value is not used.6 p1 a3 J6 y) K) F+ J0 j
1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg7 s. ^9 @) p; Y% D8 E5 w
1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
% m5 }/ v. t$ O: c! ?, I" B1014319 CONCEPT_HDL CORE renaming HBlocks leads to crash, t X. q1 P7 C8 ?* T
1017724 ADW TDA TDO update should force the schematic to re-read data from disk
. b$ `" p7 u" i- s1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin) A0 h( B+ n6 T( G( ~' u: ], j. [
1019979 SIG_INTEGRITY LICENSING extracta batch command result is incorrect, I4 L8 L+ A p0 ^1 Q- `4 X
1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs, {% _4 }$ U% D8 @: u6 c
1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140/ W0 ~2 s6 a! G# g) b# R
1023057 CONCEPT_HDL CORE Strange message when opening DE-HDL - INFO(SPCOCN-2055)4 K/ M$ B* \5 P7 b7 n0 O
1023281 PSPICE AA_PPLOT Bug spice advance analysis parARMetric plotter stops after 6000+ runs
Q/ f6 Z% `+ m1023702 CAPTURE GENERAL orcad Capture/CIS copy and past page to other design Issue2 @. K4 j, Z* A
1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
* [# Z& ?1 S# A5 y# \4 v" i7 `1024890 PCB_LIBRARIAN METADATA con2con -metadataonly does not find footprints5 A4 e" W" J' a5 b6 Q$ [
1024899 PCB_LIBRARIAN CORE PDV symbol pins grid select all does not respect the filtering
0 d) }* Y, g* R1 J8 f3 Z9 H1027147 CIS UPDATE_PART_STAT CIS gives ERROR(ORCIS-6274) when updating Part status from Part Manager1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist
5 c" f* D0 {, z9 G6 o" ?, G1028432 SIP_LAYOUT DIE_ABSTRACT_IF Support pin numbers in die abstract flow/ G3 i. v6 |% F* A/ ]
1029369 PDN_ANALYSIS EMVIEWER EMViewer: Unit of Current Density.+ p6 o! f: I: d. M
1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed
; W; e, H- s& \/ l+ v# k1031474 CONCEPT_HDL ARCHIVER Uisng Gtar as the compression utility causes the 'delete archive' to fail
2 l) W& y; S$ ^& c# L( B1031765 PCB_LIBRARIAN OTHER librarian_expert feature is kept checked out for two hours9 X# L0 C6 r3 s u
1032703 F2B DESIGNVARI Enhancement Replace Variant Component form needs to be resizeable& e, N% Z( S& ]* D7 o3 v* S
1033607 CAPTURE NETGROUPS Capture crash if netgroup instance name has square bracket 縖�
1 n0 A5 z2 |' B9 x9 f1033853 SIG_INTEGRITY OTHER netrev crashes when importing logic) Q) O/ U; \0 T! W
1035624 CONCEPT_HDL CORE Options pre-selected when launching base product! E6 M+ @1 {" R
1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.
7 D0 l: u, A; r7 `$ t1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
+ J% W% R7 _0 C, a1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol2 j$ ?: F4 z" w ~
1038285 SCM UI Restore the option to launch DE-HDL after schgen.
6 ?0 |9 @/ n. E8 D6 W1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing& q x6 {& X/ D+ w0 B9 P# Y5 Y
1040257 CONCEPT_HDL INFRA New license files causing slow tool peRFormance: S8 ]3 a3 f$ Z5 x' H# y* V
1040575 CIS CONFIGURATION SQL database views are not visible in CIS configuration step 2.; d8 l/ W/ R8 k1 J4 b
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart2 K0 z2 B2 V5 v
1040869 CONCEPT_HDL INFRA About uprev problems to SPB16.5 from 15.70 k( l: R- C1 w" p- b0 }0 h6 G
1040976 PCB_LIBRARIAN CORE PDV replace pinshape on Linux shows very slow performance compared to Windows8 {! o! W. w$ ~% ^+ D2 L n
1042603 PSPICE SLPS About SLPS simulation interrupt
+ T, N: B2 f1 s9 _( W1042695 CIS CONFIGURATION Can't see database views of an SQL database in CIS configuration7 U+ Z9 h. |# u: L$ h5 | A) g
1043339 CONCEPT_HDL PAGE_MGMT The .con and .xcon files aren't being updated.4 n; W, a/ b: a
1044029 PSPICE ENCRYPTION Encrypted lib not working for attached$ m$ ]' z) j( u/ V$ H, F+ d
1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory
2 r$ n# K* M: s3 @! R8 z! |1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
5 C6 k( O: I7 W9 e% R0 t- Y, m1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.
5 J& s$ r$ M( y, \: l! s+ v1045609 ALLEGRO_EDITOR PLACEMENT Statement in the Viewlog for Update Symbol needs correction& l/ ]3 r' \: L3 \' a$ i
1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?
' q- d3 O( ` f- h1045734 ALLEGRO_EDITOR OTHER Missing padstacks and layers information in cross section chart6 i- C3 \( I+ Y
1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.
, t' c% ]& l2 g% Q1047361 CONSTRAINT_MGR OTHER CM fails to convert static phase tolerance value to database units.4 I6 T- A# R/ U+ f! o ~
1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll
+ ~" w- U2 k9 S- k8 m; C4 M. t: a1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.
0 V6 U3 j; X% D7 X2 Z1 h7 ^1047869 CONCEPT_HDL CORE How do I define a custom pwr/gnd symbol for correct Verilog syntax?
6 @. ?5 {, }1 [; j+ O- z, T0 m1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.52 C2 \ u% ~* m+ q5 Q
1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5
+ T( M( K5 a1 c) V. Z1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value$ H' u# o7 v. x0 V5 S" b) ?0 L
1049993 ALLEGRO_EDITOR EDIT_ETCH Loss of Y axis when adding via in manual group routing
# x" ~8 W3 ?# G* Y$ Y3 |0 T1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.
+ |- T- {6 H! p0 i/ Z/ u, V1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes% y/ ~4 d# c$ g# `, e$ ]' N) f8 D
1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.- ]- y7 Q2 }# k( s& F; g
1052056 ALLEGRO_EDITOR PADS_IN Pads to Allegro translator fails with error message " ARSE ERROR: Wrong label format:Translation aborted."
: W7 Q: Y, s# H8 g$ S0 q1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file
3 ? e; K. ~9 x3 r1052479 PSPICE PROBE Cursor2 (Y2) displays the same value for all traces1 [5 Y& g3 v& S
1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.
6 F' ] z* s, I H- l; e1052817 CONCEPT_HDL CORE Getting packager error after renaming nets
p) h! U; A$ ?0 Z* u# X1053319 CONCEPT_HDL INFRA Change in property scope in windows mode is not retained
: |9 p/ z* y. | v/ m- ^' r% I1053602 CONCEPT_HDL OTHER Using the attached .NDX/DML files causes a lot of delay in invoking Tools > Model Assignment.
. Y# r, ?, Y" l: a7 C# [" @" w1053660 CAPTURE PROJECT_MANAGER Find Part Pin name or number is not working6 _- l, _. `/ j" Y1 G
1054010 CONCEPT_HDL CORE MAKE_BASE2 H+ f6 Q9 P. q
1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.
# X8 x: {. p1 N" m O3 K7 b1054846 CAPTURE PROJECT_MANAGER Crash on pressing Esc key. L x9 W, f8 @8 u' S
1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy) c: J& f3 ]& a% m3 e( l# ^: s
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection, p. r/ s' ]7 u( `9 l
1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.1 x0 c& X3 u: Q+ j, w5 V
1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline
4 H8 B: U1 `& r8 f1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.: N9 ?1 y! H9 Z" x) q
1058364 ALLEGRO_EDITOR skill axlTransformObject() is moving refdes text when only symbol pin is selected for move) x4 @- e9 ~; m+ ]- B3 u1 {9 b
1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value7 G; M0 _+ L/ q4 @. ?6 l
1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.2 e ]' P; c! `( a# }. p7 b
1060428 CONCEPT_HDL CORE ADW Flow Manager Copy Project fails to complete0 }1 o& G( i6 Z% u' U$ s
1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
5 u' {/ L# x7 p/ v8 s7 H1 U& {1061172 CONCEPT_HDL CORE Unable to delete Voltage/ |; l8 {+ ?9 L) n+ @
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values./ A6 f7 S5 L' v2 k2 F4 ~
1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00
. X1 |' I- E. M% |1062532 CONCEPT_HDL CONSTRAINT_MGR Our customer saw different DIFF_PAIR contentsevery time they invoke the Constraint manager.5 J8 V& K8 G- p1 U. v0 J
1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
1 X) P/ l |9 o1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design
+ T. F& l2 U$ f3 D: _1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV
9 U5 b3 }8 o9 K3 J" E0 Q1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application
& u# d/ \$ `! o1 j1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report& V F' N7 w4 l, Q/ u0 i0 v5 W
1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC% N3 e5 u, _8 C0 ^! [
1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic
6 m, Z _( m; v6 z6 L, f1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command
# E. q, [# x; x5 Y1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067
* j3 h3 l1 k8 {2 q+ p3 Y0 R1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design
! f) q4 G/ Z! {. j1 V# N1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify* ~1 H, T: n+ O% g) f, C% P: O" E0 `
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