Cadence SPB 16.5及最新Hotfix下载地址（Hotfix更新至033）

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cadence最新版软件SPB 16.5及其Hotfix下载链接如下：
http://dl.vmall.com/c0t5v9lbyp
Hotfix中只需要安装最新的版本即可。

$ H7 w+ g8 G7 T" ]6 h+ [; W" R& bHotfix033对以下项目做了修正：
DATE: 10-31-2012   HOTFIX VERSION: 033
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3 r1 x; U6 u) I) h2 a+ U: hCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
  H: U5 c4 C) |) G  }$ F103395  COBALT-COMPILE COMPILE          et3compile fails if compile for 3 boards in 32bit mode
715653  Pspice         MODELEDITOR      Change in pin number assignment with model import for capture symbol
745682  concept_HDL    CORE             Attributes window requires resizing each time DEHDL is launched
825846  CONCEPT_HDL    CORE             The module_order.dat file gets corrupted
846658  CONCEPT_HDL    CORE             About Change the NOTE with DE-HDL
1 y1 p7 }( I/ X: s) S938977  CONCEPT_HDL    CORE             Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
942044  CONCEPT_HDL    CORE             ConceptHDL crashes while opening the AMS project
946640  CONCEPT_HDL    CORE             Import Design should inherit module order defined in the imported block
968646  allegro_EDITOR EDIT_ETCH        The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
( ], l6 e& N0 l4 M8 q# M: s' ]969535  CONSTRAINT_MGR SCM              ASA retains information in the DCF file for parts/blocks that have been deleted and this causes problems.
* w5 u) I; Y  e5 u* j( c976723  ADW            MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
981767  SCM            UI               Add series termination in ASA will crash if both output and input pins are selected.
' q; i6 j9 K- b; T- O988355  PCB_LIBRARIAN  CORE             PDV moving line-dot pinshapes left to right or visa versa places pintext wrongly
+ N( X  ~& V! \. w: k6 j: e988438  CONCEPT_HDL    CORE             Visible constraint disrupts MOVE command
: M4 b/ i- A3 ^0 t& L993562  CONCEPT_HDL    INFRA            After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
# L1 E+ L9 O2 w, K# m/ v' u996577  SPECCTRA       ROUTE            Specctra not routing NET_SHORT connections
/ U/ m$ p7 j! _8 y- u997992  CONCEPT_HDL    CORE             Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
$ A9 v9 O* y% [1001300 PSPICE         MODELEDITOR      BUG: Simserver crash with encryptedm model
1006400 SCM            OTHER            Incorrect warning in SCM due to way voltage value is stored in tabular and schematic blocks
1011502 CONCEPT_HDL    CORE             Undo has an error on circle in DE-HDL during create a schematic symbol
1011798 ADW            LIBDISTRIBUTION  generate a differential report on parts in DB vs parts in PTF while running lib_dist
" v0 W2 u$ h1 N# }1012685 SIG_EXPLORER   INTERACTIV       SigXP: traceEtchFactor value is not used.
1013656 SCM            OTHER            create diff-pair should honour diff-pair setup or ask user for positive negative leg
1013721 ALLEGRO_EDITOR EDIT_ETCH        Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
1014319 CONCEPT_HDL    CORE             renaming HBlocks leads to crash
1017724 ADW            TDA              TDO update should force the schematic to re-read data from disk
1018506 ALLEGRO_EDITOR INTERACTIV       Edit copy with retain net of via will assign net to pin
) C- L/ P0 x" V. `5 Y: ]1019979 SIG_INTEGRITY  LICENSING        extracta batch command result is incorrect
1020746 CONCEPT_HDL    OTHER            PDF Publisher tool behavior inconsistent between OSs
1023051 SCM            UI               Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
1023057 CONCEPT_HDL    CORE             Strange message when opening DE-HDL - INFO(SPCOCN-2055)
1023281 PSPICE         AA_PPLOT         Bugspice advance analysis parARMetric plotter stops after 6000+ runs
1023702 CAPTURE        GENERAL          orcad Capture/CIS copy and past page to other design Issue
1023807 SPECCTRA       GUI              Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
  S9 h' j  _; l8 D1024890 PCB_LIBRARIAN  METADATA         con2con -metadataonly does not find footprints
4 A; J3 m* L3 G, _( Z+ q" y0 l1024899 PCB_LIBRARIAN  CORE             PDV symbol pins grid select all does not respect the filtering
9 {6 r1 O* \7 A  Y, ~2 r1027147 CIS            UPDATE_PART_STAT CIS gives ERROR(ORCIS-6274) when updating Part status from Part Manager1028237 CONCEPT_HDL    HDLDIRECT        Error binding design when generating simulation netlist
4 m' y3 |4 D% \* I2 [+ o1 A1028432 SIP_LAYOUT     DIE_ABSTRACT_IF  Support pin numbers in die abstract flow
& U& k% y3 @' H$ ?+ ]. |1029369 PDN_ANALYSIS   EMVIEWER         EMViewer: Unit of Current Density.
1030591 CAPTURE        LIBRARY          Library Correction utiltiy locks the library and deosn't frees it even after being closed
. |. l) _! l8 Z, A& ^1031474 CONCEPT_HDL    ARCHIVER         Uisng Gtar as the compression utility causes the 'delete archive' to fail
# L, ]  K8 e5 W+ E( M$ s5 ^3 W! [1031765 PCB_LIBRARIAN  OTHER            librarian_expert feature is kept checked out for two hours
1032703 F2B            DESIGNVARI       Enhancement Replace Variant Component form needs to be resizeable
1033607 CAPTURE        NETGROUPS        Capture crash if netgroup instance name has square bracket 縖�
1033853 SIG_INTEGRITY  OTHER            netrev crashes when importing logic
6 C- p  c" Z+ l, t! p. ^1035624 CONCEPT_HDL    CORE             Options pre-selected when launching base product
  h, Y0 A- g1 w  v" d1036580 ALLEGRO_EDITOR MODULES          Module created from completely routed board file has lot of missing connections in it.
1037345 ALLEGRO_EDITOR INTERACTIV       Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
, n; y% z. i4 n& l  R+ h1038180 ALLEGRO_EDITOR DRC_CONSTR       BGA escapes not being calculated in phase tol
1038285 SCM            UI               Restore the option to launch DE-HDL after schgen.
1039147 ALLEGRO_EDITOR COLOR            Need an option to change color of Text marker and Text select in Display listing
1040257 CONCEPT_HDL    INFRA            New license files causing slow tool peRFormance
* K. t' U/ A/ m7 Y5 V2 M1040575 CIS            CONFIGURATION    SQL database views are not visible in CIS configuration step 2.
1040678 ALLEGRO_EDITOR MANUFACT         Text spacing is inconsistant for top and bottom SM layer in xsection chart
1040869 CONCEPT_HDL    INFRA            About uprev problems to SPB16.5 from 15.7
1040976 PCB_LIBRARIAN  CORE             PDV replace pinshape on Linux shows very slow performance compared to Windows
& `9 r$ M0 U# m. A6 _( E6 Q1042603 PSPICE         SLPS             About SLPS simulation interrupt
8 p) W* M0 l5 [6 n8 O1042695 CIS            CONFIGURATION    Can't see database views of an SQL database in CIS configuration
. R! L0 ]* n  j  a1043339 CONCEPT_HDL    PAGE_MGMT        The .con and .xcon files aren't being updated.
6 r3 f2 J' ^% V$ L! t% o. e) R' A1044029 PSPICE         ENCRYPTION       Encrypted lib not working for attached
1044222 ALLEGRO_EDITOR INTERACTIV       Capture Canvas Image changes working directory
1044264 PSPICE         SIMULATOR        Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
1045607 ALLEGRO_EDITOR OTHER            Component get placed even after Cancel IDF in form.
& [2 I$ S! V* }$ @  R  F! c1045609 ALLEGRO_EDITOR PLACEMENT        Statement in the Viewlog for Update Symbol needs correction
1045694 CONCEPT_HDL    INFRA            Why to package the design twice to pass the net_short property to the board?
1045734 ALLEGRO_EDITOR OTHER            Missing padstacks and layers information in cross section chart
: W, y# k/ g- k  Y. j9 f. b  A9 T1046929 CONSTRAINT_MGR OTHER            Unable to create physical of spacing cset after rename the default cset in design entry.
9 p5 E" i# j+ @4 Y+ h1047361 CONSTRAINT_MGR OTHER            CM fails to convert static phase tolerance value to database units.
- h9 ]3 ]2 r$ B; J. f/ ]# F9 o1 ^1047756 CAPTURE        NETLISTS         Not adding user defined properties in netlist generated by orDump.dll
5 h) _4 Y7 t3 }7 M# r) Y, z7 f1047823 CONSTRAINT_MGR OTHER            acPutValue predicate text not being displayed at bottom of Constraint Manager window.
- l" x$ m& y7 ?+ z9 K6 W1047869 CONCEPT_HDL    CORE             How do I define a custom pwr/gnd symbol for correct Verilog syntax?
1049303 CONCEPT_HDL    CORE             Block rename deletes schematic data immediately in 16.5
( \% Y' t% \% K" M% G; ~1049317 CONCEPT_HDL    OTHER            bomhdl with scm mode not working on RHEL in 16.5
1049399 SIG_INTEGRITY  OTHER            Toggling z-axis delay in CM shows the same value
1049993 ALLEGRO_EDITOR EDIT_ETCH        Loss of Y axis when adding via in manual group routing
1050483 ALLEGRO_EDITOR DRC_CONSTR       DRC has been waived but after updated DRC system generated a new DRC.
. d$ s. }+ t3 i# T0 w1051588 ALLEGRO_EDITOR PAD_EDITOR       Pad_Designer library drill report omits some drill holes
1052005 SIG_INTEGRITY  OTHER            Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
) z. ?5 u1 y" c  V1052056 ALLEGRO_EDITOR PADS_IN          Pads to Allegro translator fails with error message "ARSE ERROR: Wrong label format:Translation aborted."
4 h9 q9 S8 T4 d7 T$ {) i) R1052449 CONCEPT_HDL    COPY_PROJECT     Copy Project does not update all relative paths in the cpm file
2 F) d; k5 \+ O7 S1052479 PSPICE         PROBE            Cursor2 (Y2) displays the same value for all traces
1052753 ALLEGRO_EDITOR DRC_CONSTR       Allegro showing soldermask drc only when the symbol is rotated.
* q3 u8 Y7 ~  j: b" e9 Q# w4 R  p1052817 CONCEPT_HDL    CORE             Getting packager error after renaming nets
+ f" A+ o9 ~$ u4 Y; `8 G, ^8 v1053319 CONCEPT_HDL    INFRA            Change in property scope in windows mode is not retained
: v* ?) F8 _4 T3 g- U( P& v1053602 CONCEPT_HDL    OTHER            Using the attached .NDX/DML files causes a lot of delay in invoking Tools > Model Assignment.
9 W$ D" N0 t0 m) _5 B+ M1053660 CAPTURE        PROJECT_MANAGER  Find Part Pin name or number is not working
5 b) ]4 p( L# @7 r! w- y- X* `1054010 CONCEPT_HDL    CORE             MAKE_BASE
1054235 ALLEGRO_EDITOR PLACEMENT        Cannot place alt_symbols for mechanical parts.
" v; p8 @  n6 S! X  }1054846 CAPTURE        PROJECT_MANAGER  Crash on pressing Esc key
1055328 CONCEPT_HDL    COPY_PROJECT     Project Manager - Project Copy
1055729 CIS            GEN_BOM          Standard CIS BOM per page is not working correctly with option  Process Selection
/ ~/ m8 {1 [6 w7 e1056418 ALLEGRO_EDITOR OTHER            PDF exports the blank text markers whether or not the markers are visible.
1057003 ALLEGRO_EDITOR SHAPE            Z-copy to create RKI does not follow board outline
1057976 ALLEGRO_EDITOR DRC_CONSTR       No Same net Spacing DRC on attached design.
$ E' d( M8 E4 K, d2 I2 e; @1058364 ALLEGRO_EDITOR skill            axlTransformObject() is moving refdes text when only symbol pin is selected for move
7 Y& J" }- x1 p" p6 P6 S( i, }% d1058940 ALLEGRO_EDITOR INTERFACES       IDF(PTC) out command output wrong angle value
6 h1 b' \" {% |7 V7 W  \, Q6 A1059901 CONCEPT_HDL    CORE             Global Property Change and <<OCC_DELETED>> property value.
5 T- z" F! f: D# g- T/ ~6 [1060428 CONCEPT_HDL    CORE             ADW Flow Manager Copy Project fails to complete
$ e1 V& ~, n0 q3 m" r8 R1060589 F2B            PACKAGERXL       Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
% g. q2 r8 j5 R3 B, k/ ]1061172 CONCEPT_HDL    CORE             Unable to delete Voltage
# e+ s" {, f# b9 Y' l1061424 CONCEPT_HDL    CORE             Customer creates <<OCC_DELETED>> property values.
1061659 ALLEGRO_EDITOR DATABASE         Unable to return drawing origin to 00
8 r: ]" T/ z; _# E2 X1062532 CONCEPT_HDL    CONSTRAINT_MGR   Our customer saw different DIFF_PAIR contentsevery time they invoke the Constraint manager.
( w5 ]- w, n5 N$ F+ B$ p3 O) i1 ~( F1062558 APD            DXF_IF           If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
1064707 CONCEPT_HDL    CHECKPLUS        Rules Checker core dumps on design
; r& W! q  `* }- r) c1065124 PCB_LIBRARIAN  SETUP            PTF properties cannot be deleted from the setup in PDV
, h) J* k5 G$ \/ R% E# ^7 P$ ?9 `1065745 SIP_LAYOUT     DATABASE         The logic assign net command crashes the application
0 x, Z4 ]( z* D! M1065860 ALLEGRO_EDITOR REPORTS          Design crashes when running a padstack usage report
1066051 ALLEGRO_EDITOR TESTPREP         Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
4 y7 _* I) K4 a) Q0 h4 U& w1066318 CONCEPT_HDL    CREFER           Issue with LOCATION visibility in flattened schematic
1 _) J$ |( k2 R3 K- h' X1068425 F2B            DESIGNVARI       Out of memory message in Variant Editor while 縞hange properties� command
0 m7 }2 \6 Q% P. [) h4 W8 X: t* O: Y1068966 SIP_LAYOUT     DRC_CONSTRAINTS  DRC update aborts on this design with  ERROR -3000067
1069215 CAPTURE        DATABASE         Capture Crash on usnig a TCL utltiy to correct design
1069517 SIP_LAYOUT     DIE_EDITOR       change die abstract pins tab default action from delete to modify
# u5 H' p' e6 A; O7 s0 F3 d5 O
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mengshang

真的很感谢您

topway

謝謝分享，不錯

amaryllis

眨眼之间又更新了

( {5 H& o1 J( k. x. i- Y谢谢楼主，辛苦了

wolfshiao

再下來看看..
' s( j! ?0 r  i! V2 O/ q* A感謝分享了..

大波哥

感谢分享

elm99

谢谢楼主分享！

rx_78gp02a

这次改进的相当多啊，不知道16.6的hotfix什么时候有呢

linsky2000

顶，谢谢楼主分享！

LiuY

下载起来好慢啊

littlehit

谢谢分享

zbmzy

谢谢分享

lljian

哈哈哈哈哈哈哈哈哈哈哈哈哈哈哈哈哈哈