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我建了一个电容 为什么 不能放到原理图中呢?

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1#
发表于 2013-1-4 19:52 | 只看该作者 |只看大图 回帖奖励 |倒序浏览 |阅读模式

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为什么那个C0402-RF 不能放到原理图中?  我刚刚单独建了一个元件就不让放到原理图中 点击那个图标才能放入原理图中呢?4 o2 E0 i2 e5 K1 R2 @

& m& a( c" [0 O' G; u5 a: R2 j; E4 q实在不熟悉这个软件

124.jpg (176.49 KB, 下载次数: 12)

124.jpg

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2#
发表于 2013-1-4 20:40 | 只看该作者
建工程时加入了你的库后,View→DXDataBook里找到相应元件加入

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3#
 楼主| 发表于 2013-1-4 20:56 | 只看该作者
dali618 发表于 2013-1-4 20:40
& n( ]& ^* h& j1 `建工程时加入了你的库后,View→DXDataBook里找到相应元件加入

) ?" ?5 G$ Z5 b7 U. r感谢已经添加进去了。但是没有 REF  我希望自动添加一个REF  找一个使用的REF添加上去 。例如没有C1没有使用 自动添加一个C1。这个没有REF。+ s6 B5 K" x. w3 r

! E. {+ Z5 V% R7 y" N2 b这个继续怎么办呢?

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589.jpg

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4#
发表于 2013-1-4 21:00 | 只看该作者
package操作后就有了

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5#
 楼主| 发表于 2013-1-4 22:13 | 只看该作者
本帖最后由 wanruyi 于 2013-1-4 22:40 编辑 & F3 B, j7 n& @6 @7 t5 U* r' @7 r
  [) T* w+ E4 t5 e* f* V  f
EE   
6 w$ K# S+ C0 S+ R! x+ n0 V* b3 j! q
WG  我有本的WG的书籍 对着  书操作  结果这个EE7.9.4  和书上的差异太大。! N; c1 Y/ H, T. j3 Y1 }
+ }/ R& b( w- M4 R* D, i5 T' }& V
学习进度缓慢。  这个软件难学。没有十足的信心  还是不碰为好。
3 c4 `3 W, a! n" l) N- b4 u! o# A( S) j, E% p8 n
打包 出现如下问题:# D! u# v$ P7 j6 L4 w5 R
6 N: [' K+ c3 U! t0 T) y
不知道哪里卡住。  能不能解释一下 这个新版本的打包命令。4 @8 h! q, q  Z/ }3 h) c
; L  d$ m$ D; _( |7 {2 v8 _; B7 I
网络表也生成不了。
! i( I! q1 w* E2 B# T. ?6 U. f* m! J7 r- M/ ?: ?! i6 A+ U
The Central Library is at "C:\Users\WANRUYI\Desktop\Center_Lib\Center_Lib.lmc".8 N0 l0 |: x: n+ G) ?$ X
9 N2 R+ C8 _% z, M4 X
Unable to determine the Disable Repackage status.
0 e( I0 J) O0 S3 l!Repackaging will be allowed!6 X* ^: d( J4 h

; I; l9 B) W! uThe PDBs listed in the project file will be searched to satisfy the parts& K7 }$ c; C9 W. I. j# \
requirements of the iCDB only for parts not already found in the" ~* V. P* e; S" U
Target PDB.
! s" o* f5 T8 p5 U8 @1 l( y! u: c) F6 U8 W  j8 Y8 q, I
The AllowAlphaRefDes status indicates that reference. o( F. D/ c4 e
designators containing all alpha characters should be deleted0 V9 e7 s2 \3 _* g
and the relevant symbols repackaged.- M8 \3 h- g* C4 _8 o* i

: U; Z# V" A! Y0 M! z4 @All existing reference designators and frozen properties will be ignored( M4 D$ ^% k) ^! R1 r
during packaging except for those on symbols within Reusable Blocks.
+ W" \! Y# K. c+ P1 cOnly the Room and Cluster symbol properties will be read for the purpose% l* a2 B' D( c( J7 R4 j# [
of user designated packaging. Use with the -y option if back annotation" W% k0 k3 w; s; ]% x# Z8 G/ v2 ^
to the Common DataBase is not desired.
* J6 f( T8 t2 x& h8 b: j6 I
) e' ?, a7 o& S! pThe cross mapping of symbol pin names to Part Number pin4 Z' a/ d( O5 Q% v. u& @; ]9 u  R
numbers will be checked for packaged symbols and mapped correctly
9 U' }- K! o9 Xfor unpackaged symbols.
$ x9 U" H) X4 G# G6 }3 P
' o1 W) X# j- G3 H, {! AProperties that have been checked off in the Property Definition Editor$ r3 C5 ?0 M, E" |- d" g
found at Library Manager/Common Properties will be checked for value
/ A. X* o, d; @1 Ldifferences between the PartsDB and the non-null properties on symbols.1 ~  y, Q+ }& N' U" E
Those properties checked off (other than Part Number)
  M* {8 W6 h: m, U" {0 {& xwill not be transferred from the PartsDB to symbols.
* ~2 g# F5 E' TThe following properties were checked off in the Property Definition Editor:
& I2 R+ Q9 X) Y"Pkg Group"
, L% Y, M7 m! q! [3 F& q"EPFIXEDWIDTH"; U& q7 c, i3 q% N. V
"EPFIXEDLENGTH"
8 T1 I% s3 }% t- V"Term"/ G2 N' K4 V( E1 `
"SIM_MODEL"
+ d8 u" S( i" G5 Y2 m"SIM_MODEL_FILE"
3 h, x3 U3 b$ P5 \6 u"Array Component"8 z) Q2 Z+ s% m0 p; t# `& w
"ICX_PART_MODEL"
$ `+ P& \+ z1 }: t5 K5 j* X1 v"Use Verilog"6 R- u* m3 N! S: w. R1 Q* A/ {. i
"Order"
7 }, j9 w1 Y4 [) R" ^  d"Parametric"
4 {4 V) J/ p2 w- `3 b"Value2"2 c. a3 o  O8 g! n7 E
"Tech"
  u+ h7 k0 j2 i" i: G"IBIS"+ C3 H4 O* T7 o) Y. R) K; Z/ A
"VHDL Model") f* y% p2 O$ Z9 R9 a
"Verilog Model"
, i- Y1 k! ]) Y7 P"Tolerance"6 p5 j6 c6 o5 [! K
"Value"5 o) l- Z& R6 s% ~; M1 {

. X6 @) U1 }) F4 VChecking for errors in the ICDB...
( [* }' {3 k: {; D' {9 a0 T) g
! `4 C% a* R6 D0 I- uNo errors found. Proceeding with packaging...4 ~7 O8 M( ~, }$ C* Z7 r- Q

6 H6 I% E7 D4 X$ _; {3 v" P( I3 h
! N6 l- H$ S1 v' ?$ x0 U' E8 N1 j) s, Y7 O
$ ~- b- T9 a+ D! g! f+ V
ERROR: Block page1, Page 1, Symbol $1I34:" x2 ^1 U4 Z7 O4 P# ~$ T6 ^
No part data.. u" ~* Y. [* S% f. o7 S
No Part Number, Part Name, nor Part Label has been entered.
: \. ~/ ?6 k' x2 u3 T$ QPlease enter some data to enable packaging.+ b/ p, }& c( N- u- X4 n
6 m" ?0 h9 s+ {- Q0 {' }! S! @

6 f  `/ j8 c, E ERROR: Block page1, Page 1, Symbol $1I36:
2 _- O5 r' U1 v7 `, D1 B+ u7 rNo part data.5 R' g$ y8 F$ [3 s+ P6 u  N7 h
No Part Number, Part Name, nor Part Label has been entered.
2 G0 u/ k' t4 F5 W  f0 {- CPlease enter some data to enable packaging.6 {; d9 E& s% S# x
  l  J: c$ d, F: @
; I+ y; `& U1 W* n' g
ERROR: Block page1, Page 1, Symbol $1I37:
! r' b; D# F1 w2 LNo part data.
# a  F6 {; T8 `4 P3 r& o6 u) T0 `No Part Number, Part Name, nor Part Label has been entered.
: Q6 Q( ^7 J- T3 d! qPlease enter some data to enable packaging." C2 @, }! v& |- K' A$ `

2 p6 M1 `1 J5 n2 t/ p: G8 `
* e* S' D* W0 `" k) h( }9 n ERROR: Block page1, Page 1, Symbol $1I38:. e. Z+ H9 |) k
No part data.
  |, [1 P3 u& H4 b% }9 F1 v6 ZNo Part Number, Part Name, nor Part Label has been entered.
/ y- _" b% y) p* lPlease enter some data to enable packaging.
% V" A9 E: {7 E5 r) B8 e
1 e0 H% J, R4 J+ e. r) N" b# b; W$ g  G7 p+ b8 `
ERROR: Block page1, Page 1, Symbol $1I39:; K) a/ e0 U- a6 Q# q
No part data.
% Y# k+ O% }  H  e# bNo Part Number, Part Name, nor Part Label has been entered., u( Z; L* a( F* G3 S$ z
Please enter some data to enable packaging.# z7 f6 T0 h* F+ f4 B
/ C5 f% V" P8 u# d. T5 N
Errors encountered while reading the Common Data Base.
8 f, o# i1 t5 f. A  N9 V3 r+ t
1 b4 k- c  \* o5 a3 i# x0 H! T6 ~
Testing of Packaging is being terminated with 5 errors and 0 warnings.- G% m% ~  j7 B' z
Design has NOT been packaged.
+ G& a5 s0 N9 m8 {/ x+ ^! Z- _+ Q& k+ [" S& E, n1 P
There have been 5 errors.
# u& d. |  p* p+ B# W& s7 T; j0 b# w* l4 B& B! Z' @
Copied from Log File: Integration\PartPkg.log4 P$ |) K6 N3 G$ b3 V
) }. y1 k" l* B0 R& X; [, B! N2 h

9 ?6 [( B) _7 G& k-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
  O% K7 b" Q! d. x, \6 [* O9 d) X# z  p2 @- X" C8 v) i
Finished C:\MentorGraphics\7.9.4EE\SDD_HOME\wv\win32\bin\packagerui.exe
2 Z; q! y2 T/ G* ?" n' BStarted C:\MentorGraphics\7.9.4EE\SDD_HOME\wv\win32\bin\packagerui.exe C:\Users\WANRUYI\Desktop\wg2\wg2\wg2.prj /d Board1 /nobrowse /config "C:\WDIR"
+ |( x# D+ y5 G, R8 _, A2 Z
6 F  f: z) Y8 I* ]' R3 {Packager Version: 020806.00
1 k" H; A! a& s8 K7 t' J2 C0 C+ P
5 W) g- L( Z" h2 l$ FCommandline is: "C:\MentorGraphics\7.9.4EE\SDD_HOME\wg\win32\bin\package.exe -jC:\Users\WANRUYI\Desktop\wg2\wg2\wg2.prj -nBoard1 -i -a -NoFill -Add"* }# A! S8 s" Q- E# x" |9 l  u# Q* w

1 l. m' L. g7 Q  MThe Common Database is at "C:\Users\WANRUYI\Desktop\wg2\wg2\database".+ \9 S5 G8 u( F8 Z. y; h& k! Q/ |
! W: E3 ?  F) V1 j- A8 L
The Root of this design is "page1".
  _/ B) f# a! ?) e. ]7 Z& E) u" |! O6 Z' q6 [# h
The Front End Snapshot of this design is "DxD".4 N5 ^- \! d: V; Q) H$ ^+ S

* p' M6 r' h: C; _7 D9 X/ W7 FThe Central Library is at "C:\Users\WANRUYI\Desktop\Center_Lib\Center_Lib.lmc".2 P6 j- Y- C  ?+ q2 a2 Y1 X, q* a

9 w( K+ L0 l) \0 J$ c* {$ }Unable to determine the Disable Repackage status.
3 M- W1 i! S% t!Repackaging will be allowed!  h- k4 [/ t* J, k) }2 R8 D
" z1 I0 b/ ^2 _2 @2 \8 Q  m
The PDBs listed in the project file will be searched to satisfy the parts
! K2 m- h8 `  I  |) }* orequirements of the iCDB only for parts not already found in the
8 d7 w+ _: x/ v' A$ \% zTarget PDB.  P5 F3 x# ~' `& U$ i  Z
4 u. l; r# L4 ?
The AllowAlphaRefDes status indicates that reference
, W% S2 f* M0 U; c8 o; x, U/ ]designators containing all alpha characters should be respected.  J+ z' l) e) H4 t9 G

8 t0 s5 C$ f9 p- V- x; YAll existing reference designators and frozen properties will be ignored* ^5 e) U! }0 T7 u6 e! l, I
during packaging except for those on symbols within Reusable Blocks.  W$ q9 k( s7 D. e' @$ Q: C
Only the Room and Cluster symbol properties will be read for the purpose: B- z$ D: v) a/ Y( v! F* J
of user designated packaging. Use with the -y option if back annotation
, h6 ]+ b2 a& L  x& `to the Common DataBase is not desired.( X* f* T# U1 \+ Z
! {( G0 P) F6 X7 x% Q! s
The cross mapping of symbol pin names to Part Number pin
% i; ?+ N6 m, ]1 R0 B5 Pnumbers will be checked for packaged symbols and mapped correctly" N* h7 N/ K; M' T6 k) ?
for unpackaged symbols.0 [8 P& }& E8 d2 r1 g
- S- ^+ M- W% {4 s- ]& l
Properties that have been checked off in the Property Definition Editor
2 A8 @2 O6 R* [" q% Q3 @) \found at Library Manager/Common Properties will be checked for value$ W! m& P  g, q& y! C
differences between the PartsDB and the non-null properties on symbols., o! f0 ~# Y3 h* D. U  c0 f
Those properties checked off (other than Part Number)
8 H% t9 y, P7 n+ M5 Xwill not be transferred from the PartsDB to symbols.
8 Y, Q; l& o7 u/ b+ p( k! m0 i1 X7 AThe following properties were checked off in the Property Definition Editor:
+ ?5 j, U% q/ X; D- \$ D"Pkg Group"
# w0 g2 S8 Y% E9 h- Z"EPFIXEDWIDTH"( Y4 a7 W- g* q; t! c  z* o
"EPFIXEDLENGTH"2 G5 U4 s  y' G0 a( I
"Term"7 A& g" u) R9 ?" f! Z7 q. M6 B/ \
"SIM_MODEL"& ]- x4 J5 }1 }! M+ b# U
"SIM_MODEL_FILE"3 y7 P+ F! Y1 W' R
"Array Component"* }, g+ s  S& f0 w* ?9 r- Z# I
"ICX_PART_MODEL": Z. ]4 A9 D6 d: u8 J0 ]9 C# h
"Use Verilog"
, L5 Y* m$ f6 x# I# o! d; o" E  s& }"Order"
6 _7 Y' d# w1 l8 ~! e0 V* q1 f2 w"Parametric"* n$ F( A! z3 q4 t# J
"Value2"0 `1 `' E" ^7 S! K  S" m& y: o, R
"Tech"3 M' K' e( H3 P! A) G+ J5 R4 S
"IBIS"
- v; q' h5 f  K"VHDL Model"
! k! _/ Y. Z9 f. e, U. o"Verilog Model"
1 W' o) c# a9 d; T. U) i! u"Tolerance", c( C5 u$ @6 k) G
"Value"
  `1 E9 [9 k8 V$ E
4 q' ?0 H% q. L2 n- k) R0 q2 q4 Z! S4 u( n
Testing of Packaging is being terminated with 6 errors and 0 warnings.
6 p1 w5 S5 e6 }  r) V& pDesign has NOT been packaged.9 e% K6 _$ J2 i" {" N4 ~

$ r: u5 X& u0 @/ b3 u8 _9 HWriting to Log File: Integration\PartPkg.log
7 H1 \  A/ o9 x4 P2 f6 }6 J. N; j5 ^& [% c, O; n
There have been 6 errors.
& K' b; Q5 d1 @) C( G) ^
0 k9 n( \$ J6 E  A///////////////////////////////////////////////////////////
% U4 `' W6 w, b' m5 ?! d" x  V5 W///////////////////////////////////////////////////////////6 S$ T4 o* r. U
///// The Log File will now be copied to this window. /////: h8 d( |; D& ^0 b
///// Therefore the data above will also appear below /////- [0 g7 [4 P# \, e: l
///// with more specific error and warning messages. /////: {3 w" h( Q) @) V1 j% n+ i. P: G
///////////////////////////////////////////////////////////
3 w/ z" {0 i' ^! Z. o///////////////////////////////////////////////////////////% ?  Z$ F7 F4 p8 q* B+ I
; O/ i: D' t9 h- T/ _# W+ Q
; u& j- p/ z: a
Packager1 e- ~1 Q1 h9 y3 P. ^0 @+ J2 ^
--------
) O6 @+ l3 ]. t& j0 P" K
: D8 C+ @% o3 _' _* ~! `10:26 PM Friday, January 04, 20130 e- f8 u3 s5 G3 P
Job Name: C:\Users\WANRUYI\Desktop\wg2\wg2\wg2.prj/ F2 Y' b) G6 T+ X8 R5 h* X9 u

; a0 W0 W& B3 B) S* H( I# v4 E' r, [6 \& |
Packager Version: 020806.00; W6 ?5 m0 E7 W. E  N1 s
9 a' S' f2 u, q
Commandline is: "C:\MentorGraphics\7.9.4EE\SDD_HOME\wg\win32\bin\package.exe -jC:\Users\WANRUYI\Desktop\wg2\wg2\wg2.prj -nBoard1 -i -a -NoFill -Add"
; p$ s! N9 g+ {8 G* C3 [/ y/ u; Z2 o
7 \2 O1 ^/ ~0 c  l; }The Common Database is at "C:\Users\WANRUYI\Desktop\wg2\wg2\database".( X2 w: g; Y2 k4 Y
! D$ o( @1 y0 C9 @( l- O
The Root of this design is "page1".; V' @! e/ g0 c* @- ]/ \) s; z

. J4 Z* L& \2 y1 v1 SThe Front End Snapshot of this design is "DxD"./ D7 J! m% ~- V/ E9 \& s4 e3 Y0 y

. q/ Z" n; R) l; y0 I4 |, z0 `The Central Library is at "C:\Users\WANRUYI\Desktop\Center_Lib\Center_Lib.lmc".
  h$ x" u7 @+ }7 t) U- e7 d( F# W" v8 Q6 ]2 X8 V4 K1 d& @( L
Unable to determine the Disable Repackage status.
/ ]5 }( Y9 E! ~! c6 f!Repackaging will be allowed!* K% Z8 _1 p" k2 k2 S- t7 G- j
+ h* R6 a2 j  P
The PDBs listed in the project file will be searched to satisfy the parts2 t- s- n0 Q$ O
requirements of the iCDB only for parts not already found in the: y( _, X$ [  G$ z& c" A* `
Target PDB.
0 W2 {$ l* K1 H2 Z
2 w: y8 ]" z  r9 x. NThe AllowAlphaRefDes status indicates that reference7 {( b/ \- X: a' m7 p3 D3 S
designators containing all alpha characters should be respected.
+ R% z5 s& f4 ]. d8 V+ b
7 T% Q, ]% m3 Y4 v0 `All existing reference designators and frozen properties will be ignored! i, J$ K. i& `/ q
during packaging except for those on symbols within Reusable Blocks.
( f+ c6 @2 d, W0 d+ JOnly the Room and Cluster symbol properties will be read for the purpose
( R  C, W1 y6 O5 vof user designated packaging. Use with the -y option if back annotation. D' ]. L( y* O
to the Common DataBase is not desired.
8 t6 i5 p0 h" C3 B& n6 Z1 {3 u. p$ n$ [% M- y- X# |
The cross mapping of symbol pin names to Part Number pin5 Z$ M* u0 B0 V* m  m
numbers will be checked for packaged symbols and mapped correctly
/ T) ?! D' E% d6 N5 u0 y$ Jfor unpackaged symbols.
2 o3 m  y% Y5 N
0 q7 D5 k0 @7 J% W0 F# l: v. zProperties that have been checked off in the Property Definition Editor
. Q6 `6 ]1 j+ ?( h! Kfound at Library Manager/Common Properties will be checked for value
/ t; d7 \( j0 ~# p, d8 mdifferences between the PartsDB and the non-null properties on symbols.2 u* j& C7 X% f1 ~) x, n6 u$ S: l
Those properties checked off (other than Part Number)0 L1 G7 K6 ^$ r, w4 L
will not be transferred from the PartsDB to symbols.5 A0 N2 s/ V6 s/ F1 [3 m
The following properties were checked off in the Property Definition Editor:+ Q) F0 q/ F+ K! r
"Pkg Group"
9 D7 \- N; c) B2 o8 O: R4 g"EPFIXEDWIDTH"$ v6 Z! R: t; _) k0 e' ?! ]
"EPFIXEDLENGTH"
* Z  N1 X  V3 K$ Q7 D"Term"* [0 p/ n3 n/ w' P# x6 f. m
"SIM_MODEL"7 L; m% n6 }* @& I7 ~1 @
"SIM_MODEL_FILE"$ c$ z" H& L3 j$ X3 Q
"Array Component"
7 Q. d/ k8 l7 d% i"ICX_PART_MODEL"1 r" h" p4 Q  Y2 ?4 u, W; H: f3 ]: l, [& }
"Use Verilog"- F: G3 J. s' p2 R( n  n* Y
"Order": L+ \3 P9 _5 O
"Parametric"+ a) a/ H  W$ A4 \5 |( C( U
"Value2"
5 f/ o) O5 r" Z% E5 w0 {- O6 N* W$ Q3 h"Tech"
9 F7 Y2 `% T. y( E4 z; `"IBIS"  |' K4 z8 n1 c& [
"VHDL Model"8 E7 j6 O7 N/ W& F) [2 e
"Verilog Model"
1 ^* U- r8 b3 @5 {"Tolerance". A3 \& y8 _/ o3 l8 w  M
"Value"
3 J. w  b! }3 x/ P; M# h- b5 S7 p! @" b2 p
Checking for errors in the ICDB...
2 V5 z; D" l- n* @! B6 q- y, \. n6 }' K4 h! s
No errors found. Proceeding with packaging...
; e9 g, t+ r) n  X2 z5 E6 B/ }6 f! j( V- _. l
; `" {6 y+ b+ A/ G
! B2 ]* ^& L- T9 i; p: _
4 T7 D; G$ K8 f( t) b
ERROR: Block page1, Page 1, Symbol $1I34:
. N& S2 a4 J) m/ b6 aNo part data.
/ j( I7 I4 S8 B3 ^* h. e$ f( N3 yNo Part Number, Part Name, nor Part Label has been entered.5 m3 n+ G! }( X) m4 K, h4 G
Please enter some data to enable packaging.
0 S: l) E" b! L" _. e9 {% f
0 _4 [3 w$ G' d8 d( _5 f" N5 f$ A" G
6 H; F- x" F; Z# S9 T, } ERROR: Block page1, Page 1, Symbol $1I36:' Q. p. t4 k4 r% F7 s  k" m) O! J
No part data.
/ ~% o" b* s& ]No Part Number, Part Name, nor Part Label has been entered.6 U1 J' J- R2 u6 C( H+ v+ w! e; |! I
Please enter some data to enable packaging.
8 j) d. x% p% e1 T
" C  J* X; N+ k+ @5 _& D- T2 K7 M5 R) u& w) K2 e: r
ERROR: Block page1, Page 1, Symbol $1I37:- Q1 P9 j/ \/ L* l
No part data.
% t, _  q- O; E3 S' C& `No Part Number, Part Name, nor Part Label has been entered.0 G" Y# S: y$ s8 x6 |" U
Please enter some data to enable packaging.
- ?( H, L% |6 y3 I0 u! i+ U, A0 a% C5 Y: t, g+ e6 ^( P

3 l$ J& N) E/ d3 z, r  @1 ~( c. ~ ERROR: Block page1, Page 1, Symbol $1I38:
; \8 A6 }- i0 oNo part data.1 h# R+ g7 |4 U% |- C
No Part Number, Part Name, nor Part Label has been entered.' [. l8 b9 `( K6 n" g7 E) U$ [
Please enter some data to enable packaging.
8 @+ x% W, F6 Y' z+ \, ?# E/ p4 Y/ t8 j

, c% E$ _: t# { ERROR: Block page1, Page 1, Symbol $1I39:9 N0 q7 U7 O9 I8 G; d
No part data.
) p6 ^1 n( K% i' [" m% \No Part Number, Part Name, nor Part Label has been entered.
2 |* Z% t4 N4 L: [Please enter some data to enable packaging.1 U" r# C6 p3 s/ a  O# l4 W3 ?

! u7 L$ y" Y( M# ^: G- w. l0 Q( c4 `8 R
ERROR: Block page1, Page 1, Symbol $1I42:
& Y, c) G; l4 [0 V! nNo part data.
/ a7 I: l. G) X3 U& e; i. r/ yNo Part Number, Part Name, nor Part Label has been entered.$ y6 D& C) _4 L( r1 y, T6 c
Please enter some data to enable packaging.5 d( v) N0 u3 R1 Q  _  {8 {+ [) d

1 d2 m' j' }; q( W/ q& c

4587.jpg (396.38 KB, 下载次数: 13)

4587.jpg

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6#
发表于 2013-1-5 02:21 | 只看该作者
本帖最后由 li_suny 于 2013-1-5 02:22 编辑 ; U: [  }# E# Q5 H5 m- A

; S/ N: H4 S+ C4 vMentor的工具比较讲究流程,习惯了就很好学习了。
' _8 p- T% y0 G+ M8 K6 o. K0 [, q我推荐的那本书你可以参考一下“中心库的建立及管理”、“原理图输入”等相关基础章节。  s' ^' N4 \9 o4 Q+ Y
https://www.eda365.com/thread-77797-1-1.html

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7#
发表于 2013-6-2 15:56 | 只看该作者
wanruyi 发表于 2013-1-4 22:13
) ?* F8 i" p" F0 V- t+ ~EE   
" x/ Q  \# e, E; C2 ^8 g4 M1 ^8 J; w  n- U
WG  我有本的WG的书籍 对着  书操作  结果这个EE7.9.4  和书上的差异太大。

; C; S" a5 R9 R8 e1 [楼主的问题解决没有,我也遇到同样的问题

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8#
发表于 2013-6-2 18:32 | 只看该作者
wanruyi的问题是向库中加入新器件的操作有误,我看到的5#的系统提示是:没有Part Number、Part Name、Part Label等项,我看还缺Reference Designator项。
- [2 F3 F" x) B8 H& K/ p- [/ Y
0 s( t- |2 C9 w+ M: X5 H9 V可以参考6#的书,或者这里
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