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[仿真讨论] 剧透:DesignCon2013的获奖论文

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1#
发表于 2013-1-25 04:47 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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1. A reusable generic platform for validation and characterization of high speed mixed signal designs+ ^% h" v; w" S0 ^
/ e: c" D3 M4 m  Y! ~! u
2. A rapid prototyping of FPGA-Based duobinary transmitter/receiver for high speed electrical backplane transmission* E: J3 v  f5 z' b$ x8 \+ z
, Z% K  h& B: i" E, z! `
3. channel to channel crosstalk behavior and design optimization for ddr4 memory buses
7 r- j9 f, H0 E3 |
. [. t' V; c3 f! F0 f# |% F& I4. signal and power integrity(SPI) co-analysis for high speed communication channels
/ V, r# H9 s5 t: M! R7 k0 e) v' `+ B2 K
5. innovative PDN design guidelines for practical high-layer-count pcbs
- p; l1 w- t  i$ h: e
4 M9 p  z6 f$ f. T) b; A. [6. Time domain and statistical model development,correlation,and analysis methods for high speed SerDes # r& U! w$ c2 O+ f. J
! f. `* c1 z# m8 g
7. applying microwave techiques to digital systems: a simple case study
2 i  l5 h+ p4 h1 M/ Z! Q
: [& H  A* P: O% P* u8. high throughput,hign-sensitivity measurement of power supply-induced bounded,uncorrelated jitter in time,frequency,and statistical domains; C+ @6 }& T( }

6 J* j! _& D2 L5 @4 ?  x$ O9. beyond 25Gbps:a study of NRZ and multi-level modulation in alternative backplane architectures4 y9 p3 V0 k9 {4 o/ W

* s8 r2 j( K* V* A* a7 O, J10. Memory inteRFace on-chip PDN noise Charachterization,modeling and its impact on timing% X  C: j; d: k' ]+ ?

1 O1 H' L1 w  L11. Enabling DFT logic and timing verification in mixed signal designs- A2 m8 N/ n2 y4 P
1 `+ y$ r8 d! M- X2 u3 L
12. analytic solutions for periodically loaded transmission line modeling" p' q0 J& C# X9 Y% l6 a

7 h5 E( i; E$ ]6 X13. power-signal co-integrity design for multi-Gbps low-power DDR3 mobile platforms
: O) X8 {7 w7 |9 H* X8 B
5 m1 q* u2 f& H$ M1 N$ e2 L4 S14. power/Ground bump optimization technique on early design stage+ P: a0 ^0 P8 j6 C- I4 R$ ]
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15. DDR memory channel design from passive stub eqalizer perspective + J0 h# p  v+ }" ?, Y. O- q
$ ^3 A3 I6 `0 Z* m: G( u8 N
16. using power aware IBIS v5.0 behavioral IO models to simulate simultaneous Switching Noise
3 Z2 q7 m6 D) h4 }
. _) ?2 D9 b, Q$ y, M5 e17. validating EMC simulation by measurement in  reverberation chamber
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1 P. c% u2 V& Q" S18. 3D interposer design and electrical performance study
& e' V' F" l3 Y: K7 j) [( j1 H- K: Y  |3 E% z5 e  q
19. Dramatic noise reduction using guard traces with optimized shorting vias7 A' d5 g* j/ H/ ?/ z' e

8 t9 {" m' A# n: ]6 C20. effects of ground via asymmetry on mode conversion for high speed differential signals
: `( e# p5 r4 g: V& P, t8 w6 v5 k
3 C. x8 Z4 e7 `" b2 O  ]& k1 l21. design and analysis of a high-speed parallel interface for coded differential signaling* K# J+ C& ~+ f( H$ G: M

% M3 Z! i9 v4 q0 X& \- {22. measurement-based simulation:increasing IBIS-AMI model Accuracy with Data from lab measurements& W) ~' F2 z& h4 ~: Y1 Y3 x
% M. o$ ?  E. l/ m, R& K
23. accurate receiver clock positioning in high speed parallel buses
7 c1 A* T9 [5 `. m7 d  b) ^8 a
9 [0 t4 n( ~8 i$ n24. partial response and noise predictive maximum likelihood(PRML/NPML) Equalization and Detection for high speed serial link systems
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' N$ `( R& u4 p25. Which one is better?comparing options to describe frequency dependent losses' I6 v: m; w, j4 s) U- ?* H# e

$ Y  t5 Z5 w3 @. B% [: k9 R- |  m  [26. a reverse nyquist approach to understanding the importance of low frequency information in scattering matrices
6 m5 ~7 |) R6 G) H3 K  K( F
. [9 x( D+ M% o8 v# }4 L27. Terabit/s packaging design for testing of high speed IC transceivers
# J8 s9 c3 {" X; Y+ y
( A" p% z; u! r* W2 i28. Channel operating margin(COM):evolution of channel specification for 25Gbps and beyond& X/ s3 o7 ^* S1 x- [
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(7楼继续。。。)5 w3 ]  D; i( L
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2#
发表于 2013-1-30 00:44 | 只看该作者
很好的题目  能看个详细的就好了

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3#
发表于 2013-2-1 16:19 | 只看该作者
看到这些感到学无止境啊,叹自己懂得太少

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4#
发表于 2013-2-3 21:28 | 只看该作者
如何下载这些论文?

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5#
发表于 2013-2-12 21:34 | 只看该作者
本帖最后由 Allen 于 2013-2-25 16:12 编辑
# P* x% H& N# p- w. z' F' d
* k, j2 b2 `8 U. S/ \. q5 y共享其中几篇SPI方向的文章:
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! F+ t# E* f1 Z6 o3 i4 P0 V5 o3、Channel to Channel Crosstalk Behavior and Design Optimization for DDR4 Signaling0 Q0 C/ D9 [) ~+ `$ b2 I7 M" K
4、signal and power integrity(SPI) co-analysis for high speed communication channels3 v1 y; `$ T- @# R; |$ f
5、innovative PDN design guidelines for practical high-layer-count pcbs
7 x+ F& E0 Q; @: v9 }, @" n9、beyond 25Gbps:a study of NRZ and multi-level modulation in alternative backplane architectures

6-TA2_Paper_ChannelToChannelCrosstalkBehavior.pdf

1.28 MB, 下载次数: 164, 下载积分: 威望 -5

8-TA2_Paper_SignalAndPowerIntegrityCoanalysis.pdf

4.43 MB, 下载次数: 138, 下载积分: 威望 -5

11-TA2_Paper_InnovativePDNDesignGuidelinesfor.pdf

1.7 MB, 下载次数: 139, 下载积分: 威望 -5

8-TP5_Paper_Beyond 25 Gbps A Study.pdf

2.23 MB, 下载次数: 455, 下载积分: 威望 -5

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6#
发表于 2013-2-16 11:34 | 只看该作者
非常感谢分享,那里能下载到论文,每年这个时候就期待。

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7#
 楼主| 发表于 2013-2-16 11:56 | 只看该作者

获奖论文在各公司的分布情况

本帖最后由 stupid 于 2013-2-16 14:49 编辑 7 M* J' x9 ?; Y' V! \% w
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1. A reusable generic platform for validation and characterization of high speed mixed signal designs% O& o/ n' J6 s$ \/ `

8 d: i( G5 r$ ]: yRambus 出品。
7 R" W5 e3 u. s( n+ r# D, K; G9 g, @6 O, [
2. A rapid prototyping of FPGA-Based duobinary transmitter/receiver for high speed electrical backplane transmission: Q  h( k% o7 v( z* ~' C: j* x
% \0 X2 y4 p1 V% b
宾大和Agilent联手,Agilent方面是Mike Resso.
3 R1 w  c$ ^, [3 @( `4 [7 c8 c6 ~/ I. B. F
3. channel to channel crosstalk behavior and design optimization for ddr4 memory buses
3 A( I" j. U0 C- ^: @3 _3 l- P1 x0 C; v$ }3 N! K
Intel,Xiang Li,DDR4连接器规范的制定者。
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  i& E$ O0 w  Q( x4. signal and power integrity(SPI) co-analysis for high speed communication channels8 `! }# a4 w+ A" @

0 g; l. p8 a- ]IBM美德研发中心联手。
5 H: i/ G$ \1 a; J; |/ y/ S4 B, @! ^. H6 E1 E# v. [9 W  @$ i
5. innovative PDN design guidelines for practical high-layer-count pcbs  I" n4 Z0 G" K6 e
; D1 m; f2 D- z0 n$ B3 t! X
作者主要来自密苏里理工,其中Siming Pan 和Jun Fan都来自清华,后都就读于密苏里,俩人貌似有师生之谊。/ {; D8 s* U: Q; C

. |0 R- E* Z8 |6 O, R6. Time domain and statistical model development,correlation,and analysis methods for high speed SerDes ( F* h) m# M5 ]* A' ]+ c
+ b2 n) D% B1 I$ b2 ^6 G
LSI和Agilent联合,Agilent是Fangyi  Rao。5 C% o  F4 c; I' d* O& m
7 Q( J1 l" K( F4 k5 ]
7. applying microwave techiques to digital systems: a simple case study9 s! z6 u+ X1 V
; S; l8 J- ?/ E/ N  X
Cray、SiSoft联合出品。
+ n( D' f9 g+ v, [2 C) }, k2 a# d/ K$ U9 M3 b4 E
8. high throughput,hign-sensitivity measurement of power supply-induced bounded,uncorrelated jitter in time,frequency,and statistical domains
- K7 s. G, x. \9 O
4 j% t9 X1 v9 \Altera出品,3个作者都是亚裔,其中大家熟悉的Daniel Chow,以及一位疑似华人Shishuang Sun。3 R  [5 e/ a9 ^+ m: L2 h
9 x  q8 V( q0 P' z" w& E
9. beyond 25Gbps:a study of NRZ and multi-level modulation in alternative backplane architectures+ Y6 }, V# w1 \) f9 I5 o
: I. U; S, q6 D, h. A2 P3 t2 x
LSI、TE联合出品
* p5 M; j5 u- S) Y3 v% @" J9 H' e7 q2 Y1 h% M4 ~, Z
10. Memory interface on-chip PDN noise Charachterization,modeling and its impact on timing% }% }8 ^! s. i, {* e/ O

: _3 [8 q2 F3 MAltera出品,9位作者。
5 L( t/ w5 m4 O6 p4 \9 g
  T$ `5 M8 \, P$ K+ X11. Enabling DFT logic and timing verification in mixed signal designs
, ]8 Q* _+ x0 d' L
7 Z" t* n0 m3 O4 i3 ~- _Rambus和Synopsys联合出品。" p9 _. i7 \% K5 p; t

7 O2 v( O2 e8 \4 u$ H  S- n/ S9 ^12. analytic solutions for periodically loaded transmission line modeling, F7 u) q8 o# f7 D9 B

4 R/ w1 E+ s2 v% ?; p" O* Z( EIntel 和 Ansys 联合出品。
  Z! d4 ~/ v% F/ K  l& {3 b& m* G6 H3 |
13. power-signal co-integrity design for multi-Gbps low-power DDR3 mobile platforms- g9 Y3 [; y) L# J0 f! H9 [
. [" n* V" T. U& H! ~6 k1 u" e
Samsung出品,目前似乎还没有用LPDDR3的手机,但是毫无疑问,这将会很快成为智能手机的标配。
" s1 Q9 F2 Q" [8 W* N6 J
/ H* z/ E8 L- J2 Z3 W" ?6 s4 c0 [( E- s14. power/Ground bump optimization technique on early design stage4 Q% S: U& u, p& i/ z! a

! j2 b) M8 [8 XSmasung出品。/ p$ C, Z- V9 H  o5 e

. k' B; E/ z. X. w* W15. DDR memory channel design from passive stub eqalizer perspective
) D- ~+ T5 m! j- B9 B* _9 c9 o! V4 [* a4 z
Intel,貌似1位华人 Qin Li。+ Q4 x! L$ v% U

8 D% n) ?5 y5 A' {0 ?6 b16. using power aware IBIS v5.0 behavioral IO models to simulate simultaneous Switching Noise
7 |" Y5 t; `, X0 f5 Q" O" e, Y/ _4 I3 o0 F2 d" K  I0 X! B& A! M1 D* M
Xilinx 和 Cadence出品,非常有用的SSN仿真文章。
7 S3 C! ^! \; \5 ?. B
: o: L% u4 y% M8 u4 y17. validating EMC simulation by measurement in  reverberation chamber
1 H( H" p6 d; G- p! }' ~( T* y; s# ^
* j- |* u+ P9 d来自Cisco,作者中有4位华人,3位来自思科中国研发中心,分别是Xiaoxia Zhou,Hongmei Fan,Jinghan Yu
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1 l4 U/ p4 B) ?# Q8 f18. 3D interposer design and electrical performance study9 P: ?+ I0 T# H8 b4 H/ v1 z
' b, j1 n# x. l8 g4 r; A
Rambus 联合出品。
" ^: a4 ?( l0 t5 \( \" z; @+ j( W6 }2 w# k0 s+ c
19. Dramatic noise reduction using guard traces with optimized shorting vias; A# |* W! O. G3 J) |/ {# P

7 n  W% ?. V* f. o% hEric  Bogatin和Lambert Simonovich联手
8 G% k; @' y) f( A9 W. T/ M7 u2 ^, _; L+ g8 T. E
20. effects of ground via asymmetry on mode conversion for high speed differential signals9 `5 q: y3 [5 x* t

) R( ]- g3 h: N- XIBM独家出品。
" Y, R' H/ c8 Q- q! i) r5 ]; g9 f3 L+ {8 G* K& T# N, O) o1 d
21. design and analysis of a high-speed parallel interface for 16Gbps coded differential signaling
: h5 k% l  X5 ?% t
, O, E' H+ r; x: x& f/ M% N6 YRambus、Samsung联合出品。
& @  x7 v- }8 B9 X1 ]4 }7 D" h7 E7 `+ \6 N5 ?' d
22. measurement-based simulation:increasing IBIS-AMI model Accuracy with Data from lab measurements
8 m" s) N" g+ l2 G# H# [2 f
1 P# B9 h- ^5 {# JSiSoft、Ericsson联合出品。
* {) b: I) _" u* X# z8 J
2 x. o- @; b# \* U23. accurate receiver clock positioning in high speed parallel buses
$ w4 ?6 g3 h9 X' U& ~9 N$ r( H# b
( F* [2 v( L" C: X+ s/ H$ lRambus、Altera、xilinx、Qualcomm 联合出品。
7 |4 e1 v* `' R9 K2 D! h; h: r+ X4 H( W$ p! g( D
24. partial response and noise predictive maximum likelihood(PRML/NPML) Equalization and Detection for high speed serial link systems) J% s& w# l. c" d; t

& d8 j* _4 \" t; X5 f6 B4 XLSI出品,3作者中有一个中国人,Cathy Ye Liu,1995年清华毕业,后去了美国。" D  O- i: B! O# P2 T% Z6 ~

9 y- Q4 s9 s  M5 O# G: }25. Which one is better?comparing options to describe frequency dependent losses3 o5 z# _0 u( {' w% p9 ^' [

0 p! S! `* u) X$ T; r$ u) T1 z8 L9 mEric Bogatin联合CCN,Simberian出品。
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- [. O4 R9 U+ E. m3 K3 }0 {5 M+ B26. a reverse nyquist approach to understanding the importance of low frequency information in scattering matrices
# w7 d1 I6 ]' q( P  ~1 K- O
0 c. f+ y" Y" M3 Q0 f' fAnsys出品- v/ n( h& ]& J7 V

' H: }4 ^. x- }27. Terabit/s packaging design for testing of high speed IC transceivers
+ A  }& ]3 u1 }, C& k# T; C1 M3 f1 C/ A0 c# f
出自鼎鼎大名的IBM T.J.Watson Research Center,Xiaoxiong Gu是众多作者中的一位。# d7 {# f( l8 \7 ~# L7 k

5 m& I3 @- N  ?% S( b28. Channel operating margin(COM):evolution of channel specification for 25Gbps and beyond6 f7 ^; p  x3 L% _2 L2 K
( g: ]1 z8 B% P, x8 i7 X6 @8 f
Intel、Altera联合出品,Mike Peng Li出手啦。
6 u2 |+ Z" w* s3 p; }  t1 ]
+ V; U( b+ C9 ^从今年DesignCon的获奖论文看,Rambus依然是论文大户,共有5片论文获奖,其中4篇是和别人合作。Intel 4篇,2篇与人合作。Altera 4篇。IBM独自贡献了3篇。 Samsung 3篇,一篇和Rambus联合,跟最近整个三爽的势头一样,表现的很猛。LSI 3篇。Agilent、xilinx、Sisoft都是2篇。多产的Bogatin博士,也是2篇。仿真大户Ansys这次只收获了1篇。 整机厂商,如Cisco、Cray、Ericsson则均收获了一篇。- s. ^2 U4 |3 v3 b9 N

0 @2 O. C: i" d# q7 ~, z密苏里理工表现优秀,乔治亚理工则没有收获。. W2 ~  k3 D# \9 L6 x9 W) D7 B

) f; D( \2 a' P: g4 ?5 i国内SI的领头羊,华为亦有论文宣讲,但未中奖。另外Qualcomm的有线部门开始发力,他们目前的重心应该在10G 以太网上。9 P6 B0 f: j9 V- d5 I0 N: A9 h

1 j$ a  e; Z9 ^9 O- L另外,几乎每篇获奖论文的作者都有一个华裔,从侧面反映出来中国人苦逼,到哪儿都是做民工的命,呵呵……
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8#
发表于 2013-2-16 15:39 | 只看该作者
分析的好,慢慢看吧。

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9#
发表于 2013-2-21 15:19 | 只看该作者
只能看名字,还是顶一个

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10#
发表于 2013-3-31 11:16 | 只看该作者
学习下,楼主V5

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12#
发表于 2017-3-21 05:51 | 只看该作者
想下载,不知道哪里能下到这些有用的文章

点评

本论坛就有下啊  详情 回复 发表于 2017-3-21 08:38

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13#
 楼主| 发表于 2017-3-21 08:38 | 只看该作者
chenqianwjkx 发表于 2017-3-21 05:514 h% E) ~" j# |' ]2 q5 J
想下载,不知道哪里能下到这些有用的文章

! b7 h' s: L+ j1 G本论坛就有下啊

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14#
发表于 2017-3-23 11:19 | 只看该作者
技术无止境,慢慢看
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