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本帖最后由 hzqydq 于 2013-4-9 15:11 编辑
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Hotfix_SPB16.50.041_wint_1of1.exe
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5 L7 O2 L8 [6 w% j+ ^0 E. ~2 U( x. R下载地址
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http://dl.vmall.com/c0kgf7xkaj9 W9 _9 g ?/ Q$ k; l$ r* ?8 L0 Q
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Hotfix中只需要安装最新的版本即可。- \3 q, ]. `# J; A8 h2 e, N
DATE: 04-4-2013 HOTFIX VERSION: 041
9 C2 g+ q7 H: s" q===================================================================================================================================
0 p! q7 n3 \9 ~5 K! mCCRID PRODUCT PRODUCTLEVEL2 TITLE
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835944 allegro_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
! f- v8 W! W9 G ?% d5 l988019 ALLEGRO_EDITOR PLACEMENT Allegro hangs when doing place replicate create: e" j! Z4 T1 Z4 b
1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X
% Q0 \& _4 A; r& C+ _; f! q# [1 m1073152 concept_HDL OTHER Printing Published PDF schematic has missing lines
" b+ x Z7 j1 L$ o+ A7 K& q1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device
4 |9 s5 L3 }' N6 H3 [& D1100945 SCM SCHGEN SCM generated DE-HDL has $PN placement issue
, ^9 E" V" c1 t& a* O6 I' ]1107172 CONCEPT_HDL OTHER Project Manager Packager does not report errors on missing symbol; x+ ]# C: S" d8 A, \
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die9 b' f% `4 G) `6 Q8 V
1108603 PCB_LIBRARIAN VERIFICATION PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm- t/ Y5 b1 Q$ _- H* U3 H
1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerber lines for fillet.
' R: ]" j' \; Y/ f2 M( Z1109926 CONCEPT_HDL CORE viewing a design disables console window
3 p# Q' ]3 v8 u+ X% y/ m' p3 ?. R1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
( |) M$ z0 B( Y! H1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset
|4 D/ K) v0 Y9 [5 X* x2 x1112295 APD DXF_IF padstacks offset Y cannot be caught by DXF.5 b! t" n+ ?0 A' ~# M+ L
1112395 CONCEPT_HDL CORE BASE\G for global signal is not obeyed after upreving the design to 1650.4 r7 H7 i% h( R# Q0 k, _
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan. Z# A! D3 j. t/ K% `. p
1113317 CONCEPT_HDL skill skill code to traverse design not working properly9 q6 y" E) H2 R' C& _) ~$ m$ k
1114630 CONCEPT_HDL ARCHIVER Archcore fails because the project directory on Linux has a space in the name* h- K/ k$ q4 r5 U' M
1114689 CONCEPT_HDL CORE Unknown project directive : text_editor1 f* J4 C( M9 _' f3 w5 P5 A
1114928 F2B PACKAGERXL error (SPCODD - 5) while Export Physical even after change pin from A<0> to A
6 l0 c: k8 j+ x2 e1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used., q W* e7 w1 H; B0 v
1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer. |
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发表于 2013-4-9 15:08
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