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本帖最后由 hzqydq 于 2013-4-9 15:11 编辑 " v8 c$ B; H8 `+ O
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Hotfix_SPB16.50.041_wint_1of1.exe+ w1 ^3 @* _- P+ i" S4 V. \
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下载地址& ]0 `: g% o9 x4 s$ q- P$ m& c
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$ o) p1 F% U" ?. Shttp://dl.vmall.com/c0kgf7xkaj& d4 J( a3 B( F& n5 s
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Hotfix中只需要安装最新的版本即可。
( _3 h* k; a) K' Y+ n! B' C* `DATE: 04-4-2013 HOTFIX VERSION: 041* I4 A' N; @( }8 W" f' ~! v
===================================================================================================================================
' N( \8 U2 B* KCCRID PRODUCT PRODUCTLEVEL2 TITLE8 X0 z/ p2 }0 A0 P. n! L
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* l4 `9 e v: e$ m) A# F835944 allegro_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
" T8 r! V/ G9 H( H% N% x% x( H: Y; S' q988019 ALLEGRO_EDITOR PLACEMENT Allegro hangs when doing place replicate create
/ \+ k* T7 V' h/ M9 V1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X! B3 Z8 D/ c1 `$ H* n# O5 s1 p
1073152 concept_HDL OTHER Printing Published PDF schematic has missing lines
3 ]4 F* c5 I/ J- @- U1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device
* s. L) e, s* t' U1100945 SCM SCHGEN SCM generated DE-HDL has $PN placement issue
3 U* D# z2 ]5 f# D1107172 CONCEPT_HDL OTHER Project Manager Packager does not report errors on missing symbol" v6 W. @4 d2 Y) Y: q
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die
/ n9 n* h0 L, v+ ] H& E V1108603 PCB_LIBRARIAN VERIFICATION PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm
( i B2 |( _9 j$ G y1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerber lines for fillet.9 ~" d6 ~$ s" S2 I6 G8 A' \7 `
1109926 CONCEPT_HDL CORE viewing a design disables console window
r0 r9 R' c5 e7 \; u: `1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
- ~2 _& l6 Z! u' X* i$ P' t1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset. p# B N3 o; M0 U
1112295 APD DXF_IF padstacks offset Y cannot be caught by DXF.
% B G* _ d5 M& U+ I1112395 CONCEPT_HDL CORE BASE\G for global signal is not obeyed after upreving the design to 1650.6 X |4 ?4 h7 Q8 K; R" `3 h
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan8 d6 ?$ G \2 X
1113317 CONCEPT_HDL skill skill code to traverse design not working properly
' U/ o8 H; d8 ]1114630 CONCEPT_HDL ARCHIVER Archcore fails because the project directory on Linux has a space in the name
- Q) s8 E. A7 b- | S0 X( M) T* Z1114689 CONCEPT_HDL CORE Unknown project directive : text_editor
4 V& _$ C" e: L. a4 h* r5 R1114928 F2B PACKAGERXL error (SPCODD - 5) while Export Physical even after change pin from A<0> to A! a$ p+ \, h% f, q# R' F" e: L
1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
& b% x; n/ X+ {; F+ y0 a* B+ ^1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer. |
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发表于 2013-4-9 15:08
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