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本帖最后由 hzqydq 于 2013-4-9 15:11 编辑
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8 b4 a! ~. }+ RHotfix_SPB16.50.041_wint_1of1.exe
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1 ]$ f V- }5 `4 L2 {/ _# l下载地址
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+ D5 a+ w4 N; d/ e9 w. N/ Qhttp://dl.vmall.com/c0kgf7xkaj
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* _6 l6 [# @2 w9 v3 XHotfix中只需要安装最新的版本即可。
q) @4 Q, u. x+ M2 A+ y, |: wDATE: 04-4-2013 HOTFIX VERSION: 041
& {; B* X6 r3 F R; w===================================================================================================================================. f. h3 e9 n8 {' }& D6 w
CCRID PRODUCT PRODUCTLEVEL2 TITLE5 V2 Y5 N) e) c7 q# T% F5 M1 D
===================================================================================================================================
1 _/ Y2 o' y* T6 h! t835944 allegro_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol. k0 p, r5 f( A) V
988019 ALLEGRO_EDITOR PLACEMENT Allegro hangs when doing place replicate create
/ n- _% J% r2 R0 D# g% }; c1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X! _3 ?6 x, i; A) H. q: [
1073152 concept_HDL OTHER Printing Published PDF schematic has missing lines
' |; N' R$ ` y- N0 \6 d' d8 ~# Y- F1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device, M$ i) Y( a& c, s
1100945 SCM SCHGEN SCM generated DE-HDL has $PN placement issue
/ _1 i& R6 f+ y, K% N6 o7 l. x8 [1107172 CONCEPT_HDL OTHER Project Manager Packager does not report errors on missing symbol
! [) Q# d0 b, W; }" S; z) W; W) g1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die* l( O+ G6 A; W
1108603 PCB_LIBRARIAN VERIFICATION PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm7 Q+ ~' m, M9 K7 j5 a0 i8 Z
1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerber lines for fillet.
/ v; E( D- R' U4 d# @1109926 CONCEPT_HDL CORE viewing a design disables console window( F1 X' m( a# Y' k/ {& I5 u3 g
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
0 c, Z u) \) N1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset
8 _# o9 B! V: C p/ o) T# ]1112295 APD DXF_IF padstacks offset Y cannot be caught by DXF.
( V" ?2 c+ L9 `6 H6 a1 v: d7 W' @1112395 CONCEPT_HDL CORE BASE\G for global signal is not obeyed after upreving the design to 1650.& G' N5 B. F$ Q
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan
$ [+ V3 ~ S: q# `: w1113317 CONCEPT_HDL skill skill code to traverse design not working properly
$ W y" f5 k$ C2 s1114630 CONCEPT_HDL ARCHIVER Archcore fails because the project directory on Linux has a space in the name
: S8 h- h) ]6 I* ~9 @$ I2 B1114689 CONCEPT_HDL CORE Unknown project directive : text_editor, Y, r& e& A, X; ~( L8 W2 f
1114928 F2B PACKAGERXL error (SPCODD - 5) while Export Physical even after change pin from A<0> to A# Y& w* J' F n0 d [
1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
1 {+ I' x P' t* J# W" j/ Q( Z% J1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer. |
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发表于 2013-4-9 15:08
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