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本帖最后由 stupid 于 2013-4-30 23:17 编辑
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- x0 K/ J. v' w. R, E X某一天,一个叫马克的人发起了帖子,采用了滚动刷屏的方法,4个帖子,一个内容:招人
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$ L. U; b* d4 k& t首帖Date: Mon, 7 Jan 2013 17:36:56 +0000
6 `7 S1 O2 t9 b) `" h5 ], i2贴 Date: Fri, 15 Feb 2013 00:22:29 +0000 f7 f* f% e( r& ~5 H0 P
3贴 Date: Thu, 14 Mar 2013 04:49:58 +0000
) O) u0 k$ \; P5 Q* [! M4贴Date: Thu, 25 Apr 2013 18:37:34 +0000
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/ l. }* ~. G. S0 S# ?My Team is looking for a Senior Staff Engineer(Backplane Architect)/Principle / Q+ |( n7 v) G
Engineer;
7 ]6 u+ _. P L/ y1 z) i) C* j4 |Responsibilities/Description;
1 E1 d( O; q! E) E/ i* b/ dResponsible for providing the backplane architecture and 10G+ High Speed SI4 k4 J5 S% i) R P6 {3 B x
solutions for Next Generation telecommunications equipment in the router,
, ^& X, R. I$ V1 |. x' Y) y6 Lswitch and transmission product lines to meet system design requirements.
# ]& Y& H# H8 }* _/ l# {0 rExperience in co-designing of ASIC, Package, PCB and System interconnects) F9 _2 J, l: W1 m! g8 B
desired. including:
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) X$ A1 a6 S8 a) Y! ^8 u1 C- Design and analysis of multi-gigabit serial links for Backplane and: s. h2 H( b+ D7 s9 C
chip-to-chip interfaces meeting CEI, XFI, XLAUI, SFI, 10Gbase-KR, PCIe, and
5 o$ e- I4 L+ f" Q( D& d* `0 o. j other standards.
/ `1 E7 ]' X2 L. b, p7 A$ K' }8 F- Familiar with ASIC, Hardware, interconnect teams to evaluate design2 U( x* Q; R: x: H* \ w
tradeoffs and optimize design performance / risk / cost /manufacturability.: ~' Q1 |& n4 |5 L; B
- To evaluate package designs, characterization of SerDes, and design [# `8 [: R3 Y4 y9 q( I( n
experiments to do the same.
1 {+ X, T. P3 i( E- Modeling of electromagnetic 3-D structures.' @# d6 @5 s" G6 w* e0 i0 k' m \
- Modeling and analyzing power delivery networks (PDN)." r3 }* X. j' D7 p3 @' ^1 z0 k" H
- Familiar with memory technologies such as DDR2/DDR3 is preferred.) z- W! |6 q" m
0 t* o/ g1 }( [3 vQualifications/Requirements:
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- Performing physical measurements to collect data for design1 ~4 Q2 h3 x# y* ~: ?+ x. a
validation and simulation correlations.
# H3 m( }: s ^4 f1 K- Knowledgeable in using most major SI/PI tools: HFSS, CST, HSPICE,/ g( g% ?- r4 G" a
Sigrity Tools, StatEye, ADS, Matlab, Cadence Allegro and APD, HSPICE, and2 w% f4 q6 X$ f+ V% L k7 Z- w ]
other tools.
+ J) {, {$ b' t6 S% ?3 P- Experience in correlating simulation results with lab measurements# N/ U) L0 c: u
using oscilloscopes, TDRs, VNAs, BertScope is a plus. Must be self: g i- o H% @/ ^2 L- }
motivated with strong communication and teamwork skills.
* u8 C. o3 O9 }0 R$ ]$ r: p* }- The working experience in Core router or Edge router similar product5 G% _( x: d1 ~( Q( R$ d" q/ I
in large telecomm infrastructure company.) C% `0 R# k; L
A MSEE, or a PhD is preferred, with 10years of experience.
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Some portion of time will be spent in Shenzhen working with the HQ SI team. 6 G% l; x4 O& Y8 P: \+ Z& _
Travel will be about 30-60% to China.
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4 Y, G! W" Y/ YPlease contact mark.apton@xxxxxxxxxx, f$ y0 c3 s! p2 b, X( q) B9 t
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插个广告,有符合以上条件,又愿意在深圳工作的人速速联系我 dbm@chinafastprint.com |
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