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本帖最后由 stupid 于 2013-4-30 23:17 编辑 5 x3 s% D5 q' N- g6 m& L7 M
" R. }+ L, Q5 q9 u某一天，一个叫马克的人发起了帖子，采用了滚动刷屏的方法，4个帖子，一个内容：招人
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! v* r$ Z: }6 v首帖Date: Mon, 7 Jan 2013 17:36:56 +00006 H y6 a; |, H; \# U, U3 k
2贴 Date: Fri, 15 Feb 2013 00:22:29 +00004 a' R$ e3 b8 @+ u1 u9 g' g' u
3贴 Date: Thu, 14 Mar 2013 04:49:58 +0000
8 J& ], q. ~ s( c4贴Date: Thu, 25 Apr 2013 18:37:34 +0000
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My Team is looking for a Senior Staff Engineer(Backplane Architect)/Principle " ^! m n. x; ?! ?% @
Engineer;
9 A) D, g/ T: l+ r* H$ zResponsibilities/Description;+ i" U7 x7 ^9 ^, M* G+ o# k
Responsible for providing the backplane architecture and 10G+ High Speed SI
- P$ ^& _; O% R& x' j; Ssolutions for Next Generation telecommunications equipment in the router,
# J! R6 y/ `. ~switch and transmission product lines to meet system design requirements.
/ ]9 f$ d5 O/ B, P3 VExperience in co-designing of ASIC, Package, PCB and System interconnects1 f4 g9 M `- e8 I
desired. including:( |8 M& j; o9 a3 l# e# e
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- Design and analysis of multi-gigabit serial links for Backplane and
- z! l. h2 w1 w( e. u7 o& f chip-to-chip interfaces meeting CEI, XFI, XLAUI, SFI, 10Gbase-KR, PCIe, and8 U# C( X" E/ t
other standards." c) e4 Z K4 `4 W& h" Y8 h
- Familiar with ASIC, Hardware, interconnect teams to evaluate design$ `" l8 q4 H2 t; X# e% q# O- L
tradeoffs and optimize design performance / risk / cost /manufacturability.- E, `6 X b7 B8 ]% s, C# L
- To evaluate package designs, characterization of SerDes, and design
1 e _( G2 l; W experiments to do the same.. x! N. @, }6 e5 a1 T; E
- Modeling of electromagnetic 3-D structures.0 g2 v+ w" Y) F9 g3 U
- Modeling and analyzing power delivery networks (PDN).' [: D% V2 {. r1 T) _) n( E& u
- Familiar with memory technologies such as DDR2/DDR3 is preferred.
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Qualifications/Requirements:
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! V) C: g# y* T# @! i- Performing physical measurements to collect data for design
, J* `/ H F/ r; H& ~# f validation and simulation correlations.0 L& A$ E2 e% P0 v
- Knowledgeable in using most major SI/PI tools: HFSS, CST, HSPICE,' A$ o E `: w |$ [
Sigrity Tools, StatEye, ADS, Matlab, Cadence Allegro and APD, HSPICE, and
( g+ E' Z" c& q2 v3 B: B& d/ A5 U other tools.$ t, f; G# Z X" ^4 v
- Experience in correlating simulation results with lab measurements/ K1 w" i6 e+ l) i# X: E! ?: C
using oscilloscopes, TDRs, VNAs, BertScope is a plus. Must be self; U% u) [. V" I2 t2 Z
motivated with strong communication and teamwork skills.: s2 e# y0 D% e: h
- The working experience in Core router or Edge router similar product
5 H4 W; t7 y0 p7 B in large telecomm infrastructure company.$ a0 _3 F( X0 G# \7 v. v0 l9 t
A MSEE, or a PhD is preferred, with 10years of experience.9 [$ L+ l6 q. x/ P$ a# |& T. I- o
$ i3 e/ B0 c! k [8 V( U( v7 ESome portion of time will be spent in Shenzhen working with the HQ SI team. 9 D: r- u( {& i; A7 t Y
Travel will be about 30-60% to China.
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Please contact mark.apton@xxxxxxxxxx
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插个广告，有符合以上条件，又愿意在深圳工作的人速速联系我 dbm@chinafastprint.com |
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发表于 2013-4-26 22:19
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支持！
反对！
发表于 2013-4-30 23:10