SPB:Hotfix:16.50.044~wint

penny190 · 发表于 2013-6-10 09:11

EDA365欢迎您登录！

您需要登录才可以下载或查看，没有帐号？注册

x

07 Jun 2013 SPB16.50.044, Version: SPB:Hotfix:16.50.044~wint

DATE: 06-7-2013 HOTFIX VERSION: 044
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1055338 SIP_LAYOUT    DRC_CONSTRAINTS  Soldermask to Via drcs on bondfingers
1084716 allegro_EDITOR OTHER          Getting an MPS error when updating CM from SigXplorer
1104145 ALLEGRO_EDITOR SCHEM_FTB       User defined properties do not appear in PCB
1106116 FLOWS       PROJMGR       view_pcb setting change was cleared by switching Flows in projmgr.
1106900 concept_HDL COMP_BROWSER    Component Browser peRFormance utility should honor CPM directives for include and exclude PPT
1110323 APD          DXF_IF          DXF out is offsetting square discrete pads.
1119007 CONCEPT_HDL CORE          PDF Publish of schematic creates extremely large PDF files
1121020 FSP          MODEL_EDITOR    Cut-Paste from Excel causes empty cell in Rule Editor
1121353 ALLEGRO_EDITOR INTERACTIV    Local env setting will change after saving and reopening.
1122781 CONCEPT_HDL CORE          cfg_package is generated for component cell automatically
1122909 CONCEPT_HDL CORE          changing version replicates data of first TOC on 2nd one
1123581 ALLEGRO_EDITOR MANUFACT       Dimension Line gets changed on board
1124544 CONCEPT_HDL CORE          About Search History of find with SPB16.5
1125366 CONCEPT_HDL CORE          DE-HDL craches during Import Physical if CM is open on Linux
1125628 CONCEPT_HDL CORE          Crash on doing save hierarchy
1126182 ALLEGRO_EDITOR DRC_CONSTR    Shape fillet DRC in same net thru via to thru via was removed after update DRC.
1130945 SCM          SCHGEN          SCM Export Schematic does not copy all cells in the library
1131567 CONCEPT_HDL OTHER          Lower case values for VHDL_MODE make genview use pin location to determen direction.
1131650 ALLEGRO_EDITOR PLOTTING       PDF Publisher doesnot display few component defination properties in Property parameters
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
1132457 CONCEPT_HDL CORE          The schematic never fully invokes and has connectivity errors.
1132575 CONCEPT_HDL CORE          2 pin_name were displayed and overlapped by spin command.
1132638 ALLEGRO_EDITOR DFA             'dfa_update' crashes when running the utility on the attached foder.
1133677 CONCEPT_HDL CORE          Cant delete nor reset LOCATION prop in context of top
1133791 CONCEPT_HDL CORE          Cant do text justification on a single selected NOTE in Windows mode.
1134083 CONCEPT_HDL OTHER          Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.
1134761 CONCEPT_HDL CORE          Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property
1138586 ADW          MIGRATION       design migration does not create complete ptf file for hierarchical designs
1139376 CONCEPT_HDL CORE          setting wire color to default creates new wire with higher thickness
1141300 CONCEPT_HDL CORE          DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped
1142876 ALLEGRO_EDITOR SHAPE          No DRC error when airgap between place bounds exactly zero
1142884 ALLEGRO_EDITOR OTHER          Boolean type user defined property doesn't export to the PDF
1145112 CONCEPT_HDL CORE          Warning message: Connectivity MIGHT have changed
1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP
1145253 CONCEPT_HDL CORE          Component Browser adds properties in upper case
1145284 CONCEPT_HDL CORE          Publish PDF crashes DE HDL
1145333 ALLEGRO_EDITOR SHAPE          SHAPE boundary may not cross itself. Error cannot be fixed.
1145856 ALLEGRO_EDITOR DRC_CONSTR    DRC Line to Thru Pin appear while Fillet be added
1146287 PCB_LIBRARIAN  CORE          PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps
1146728 F2B          PACKAGERXL    DCF with upper and lower case values on parts causes pxl to fail
1147326 CONCEPT_HDL CORE          HDL crashes when trying to reimport a block

DATE: 05-3-2013 HOTFIX VERSION: 043
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
876711  ALLEGRO_EDITOR GRAPHICS       Mouse wheel will only zoom out using Win7 64 bit
1103246 FSP          OTHER          New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
1105249 ALLEGRO_EDITOR OTHER          PDF out--- component user defined prop doesn't list the prop selection form
1105504 PCB_LIBRARIAN  CORE          PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running
1107132 FSP          OTHER          Altera ArriaV (5AGXMA5GF31C4) support.
1118874 ALLEGRO_EDITOR INTERFACES    Oblong pad shapes are not shown with correct orientation after DXF export from Allegro
1121540 F2B          PACKAGERXL    pxl.chg keeps deleting and adding changes on subsequent packager runs
1125201 CONCEPT_HDL CORE          Connectivity edits in NEW block not saved( lost) if block is created using block add
1130737 F2B          PACKAGERXL    Error - pxl.exe has stopped working
1131764 ALLEGRO_EDITOR EDIT_ETCH       Line segment will not slide using the New Slide.

DATE: 04-20-2013 HOTFIX VERSION: 042
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
801901  CONCEPT_HDL CORE          Concept Menus use the same key "R" for the Wire and RF-PCB menus
1076604 ALLEGRO_EDITOR SHAPE          Sliding via in pad corrupts surrounding shape and generates false DRC Errors
1077552 F2B          PACKAGERXL    Diff Pairs get removed when packing with backannotation turned on
1080386 CONCEPT_HDL CORE          Unable to highlight netclass on every schematic page using Global Navigation
1102698 SIG_INTEGRITY  ASSIGN_TOPOLOGY  ECset will map on single ended nets but fails when the two nets are define as a diff pair.
1104071 SIG_INTEGRITY  REPORTS       Shape Parasitic value changes for bottom shape for changes in top shape
1105128 CONSTRAINT_MGR DATABASE       Import dcf does not clear out user defined schedule.
1116886 CONCEPT_HDL CORE          Crefer hyperlinks do not work fine when user use double digits partitions for page Border.
1117825 CONCEPT_HDL OTHER          SHOW_CONSOLE_ON_LAUNCH throws an unrecognized directive warning in the schematic editor
1117845 FSP          DE-HDL_SCHEMATIC Schematic Generation fails without a reason
1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors
1119711 F2B          DESIGNSYNC    Design Differences show Net Differences wrongly
1120397 CONCEPT_HDL CREFER          CreferHDL attempts to create missing vlog004u.sir files
1120660 CONCEPT_HDL CORE          Save hierarchy saves pages for deleted blocks.
1120669 CONCEPT_HDL CORE          DEHDL crash on multiple replace of hier blocks
1120810 ALLEGRO_EDITOR EDIT_ETCH       Cannot slide cline segment.
1121171 CONCEPT_HDL CREFER          PNN and correct property values not annotated on the Cref flat schematic
1122449 ALLEGRO_EDITOR DRC_CONSTR    Uncoupled length DRC for diff pair shows different actual length value between show element and CM.
1123764 CONSTRAINT_MGR OTHER          Allegro crash while importing DCF file
1124183 ALLEGRO_EDITOR EXTRACT       Output from EXTRACTA gets corrupted with refdes 50

DATE: 04-4-2013 HOTFIX VERSION: 041
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
835944  ALLEGRO_EDITOR OTHER          Customer want to change for Jumper symbol by other Alt symbol.
988019  ALLEGRO_EDITOR PLACEMENT       Allegro hangs when doing place replicate create
1065641 PCB_LIBRARIAN  CORE          PDV symbol editor is crashing when deleting a group using delete or CTRL+X
1073152 CONCEPT_HDL OTHER          Printing Published PDF schematic has missing lines
1082587 FSP          FPGA_SUPPORT    Support of Xilinx's Zync device
1100945 SCM          SCHGEN          SCM generated DE-HDL has $PN placement issue
1107172 CONCEPT_HDL OTHER          Project Manager Packager does not report errors on missing symbol
1107397 SIP_LAYOUT    PLACEMENT       Place Manual-H rotates die
1108603 PCB_LIBRARIAN  VERIFICATION    PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm
1109466 ALLEGRO_EDITOR ARTWORK       Artwork create some strange gerber lines for fillet.
1109926 CONCEPT_HDL CORE          viewing a design disables console window
1110077 ALLEGRO_EDITOR DRC_CONSTR    Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
1110264 RF_PCB       FE_IFF_IMPORT IFF Import in DEHDL has component offset
1112295 APD          DXF_IF          Padstacks� offset Y cannot be caught by DXF.
1112395 CONCEPT_HDL CORE          璞BASE\G� for global signal is not obeyed after upreving the design to 1650.
1112774 GRE          CORE          Allegro GRE not able to commit plan after topological plan
1113317 CONCEPT_HDL skill          skill code to traverse design not working properly
1114630 CONCEPT_HDL ARCHIVER       Archcore fails because the project directory on Linux has a space in the name
1114689 CONCEPT_HDL CORE          Unknown project directive : text_editor
1114928 F2B          PACKAGERXL    激rror (SPCODD - 5) while Export Physical even after change pin from A<0> to A
1115625 ALLEGRO_EDITOR SKILL          Design extents corrupted when axlTrigger is used.
1115708 ALLEGRO_EDITOR INTERFACES    Export DXF is outputting corrupt data on one layer.

DATE: 03-14-2013 HOTFIX VERSION: 040
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
625821  CONCEPT_HDL CORE          publishpdf  from command line doen not work  if temp directory does not exist.
1092933 CONCEPT_HDL OTHER          PDF Publisher saves the pdf generated in the previous project folder
1096318 ALLEGRO_EDITOR INTERFACES    IDF import not removing MCAD tagged objects during import
1100449 ALLEGRO_EDITOR ARTWORK       Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork
1103631 MODEL_INTEGRIT OTHER          Model Integrity license when using orcad
1104575 CONCEPT_HDL CORE          Allign does not allign offgrid symbols correctly
1105286 FSP          DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
1105822 ALLEGRO_EDITOR SCHEM_FTB       Netrev failing with compact pin syntax
1106626 CONCEPT_HDL CORE          Concept HDL crashes when saving pages
1108032 CONCEPT_HDL CORE          'Find' option does not list all Components in the Design
1108118 ALLEGRO_EDITOR OTHER          PDF Publisher pad rotation messed up with flashed pad.
1109425 CAPTURE       STABILITY       B1: Capture crash due to Flash
1111234 ALLEGRO_EDITOR MANUFACT       Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend

DATE: 02-28-2013 HOTFIX VERSION: 039
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
868981  SCM          SETUP          SCM responds slow when trying to browse signal integrity
1086740 ALLEGRO_EDITOR mentor          mbs2brd: created shape are duplicated
1089356 SIP_LAYOUT    DIE_EDITOR    Distributed co-design : launching die editor taking more than an hour to bring up edit form
1095701 CONCEPT_HDL CORE          Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block
1097241 CONCEPT_HDL CORE          Concepthdl - zoom in to first object in Find result automatically
1099175 CONCEPT_HDL CORE          CPM directive that enables the Command Console Window in DE-HDL
1099773 CONCEPT_HDL CORE          DE HDL goes into recursive loop if a custom text locked at site level is deleted from Tools > Option
1100442 ALLEGRO_EDITOR PLACEMENT       Placement queue shows components whichs are already placed
1102798 SIP_LAYOUT    OTHER          Stream out puts offset pad in wrong position if pad is mirrored but not rotated.
1103703 F2B          DESIGNSYNC    Toolcrash with Design Differences
1104011 ALLEGRO_EDITOR DATABASE       Place replicate move group of a modules leaves traces behind
1104605 F2B          PACKAGERXL    Pins of function swapped part in block not displayed
1105066 APD          IMPORT_DATA    Import NA2 worked in 16.5 "035" but fails in 037 and 16.6

DATE: 02-15-2013 HOTFIX VERSION: 038
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
787041  FSP          DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
911292  CONCEPT_HDL CORE          Property command on editing symbol attaches property to ORIGIN immediately
995532  FSP          DE-HDL_SCHEMATIC Hierarchical block name representing FPGA does not get updated in DEHDL after refdes change in FSP.
1005812 F2B          BOM             bomhdl fails on bigger SCM Projects
1045500 CONCEPT_HDL CORE          Why Search results does not display the correct Physical Pages.
1059037 CIS          PLACE_DATABASE_P Enable Refresh symbol libs menu in CIS explorer
1065636 CONCEPT_HDL OTHER          Text not visible in published pdf
1067283 SCM          PACKAGER       ALLOW_CONN_SWAP does not work for lower level schematic parts
1073354 CONCEPT_HDL CORE          Bubble defined on symbol pin is not visible on the schematic
1077527 CONCEPT_HDL CORE          ConceptHDL net with name U cannot be found using Global navigate
1083761 CONCEPT_HDL OTHER          AGND text missing from PDF Publisher
1091335 CONCEPT_HDL OTHER          Color change cannot remain in some situation.
1093050 ALLEGRO_EDITOR DRC_CONSTR    Taper trace on diff pairs not checking to min line spacing.
1094513 CONCEPT_HDL CORE          How to display $PNN for which SIG_NAME is not visible?
1095705 CONCEPT_HDL CREFER          Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3
1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor
1095861 F2B          BOM             Using Upper-case Input produces incorrect BOM results
1096234 ALLEGRO_EDITOR DFA             Via pad connected to shape didn篙 show up after 燙uppress unconnected pads� option.
1096313 RF_PCB       LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff
1096613 ALLEGRO_EDITOR INTERACTIV    Enh-While moving parts silk ref des should remain visible
1096676 CONCEPT_HDL CORE          SPB 16.5 HF36 breaks designs that workded fine in HF35
1096913 APD          IMPORT_DATA    Import > NA2 fails to bring in the Y1 component.
1097751 ALLEGRO_EDITOR DATABASE       Import CIS netlist crashes.
1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.
1098252 ALLEGRO_EDITOR MANUFACT       Double digit drill character overlaps with figure "circle" in NC drill legend
1099151 SIG_INTEGRITY  SIMULATION    All Neighbor crosstalk numbers reported when there are no aggressors
1099998 CONCEPT_HDL CHECKPLUS       CheckPlus marker file not locating signal when signal name includes the # character.
1101009 CONCEPT_HDL CORE          Cursor stays as arrow after performing File > Save Hierarchy

DATE: 01-31-2013 HOTFIX VERSION: 037
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1067272 PCB_LIBRARIAN  CORE          Unable to retain the symbol outline changes
1070465 CONCEPT_HDL CORE          Why does ConceptHDL crash on renaming a Port Signal
1077728 APD          EXTRACT       Extracta.exe generate the incorrect result
1083934 ALLEGRO_EDITOR PAD_EDITOR    Error(SPMHUT-41): File selected is not of type Drawing.
1084711 APD          DXF_IF          Padstacks with offsets cause violations in Export > DXF
1085791 CONCEPT_HDL CORE          Publish PDF can not output Constraint Manager properties into PDF file.
1086749 ALLEGRO_EDITOR MENTOR          mbs2brd: DEFAULT_NET_TYPE rule is not translated
1086886 CAPTURE       PROPERTY_EDITOR  "Is No Connect" check box in property editor doesn't work for power pins
1088252 CONCEPT_HDL CORE          Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.
1089259 SCM          IMPORTS       Cannot import block into ASA design
1089368 SCM          OTHER          Can't do Save - cp: cannot stat ... No such file or directory
1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
1090369 SIG_INTEGRITY  LICENSING       Impedance value not updating in OrCAD PCB Designer
1091047 ALLEGRO_EDITOR REPORTS       The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas.
1091218 ADW          LRM             LRM is not worked for the block design of included project
1091347 CAPTURE       TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled
1091443 ALLEGRO_EDITOR OTHER          Crash when toggling suppress pads
1091662 CONCEPT_HDL CORE          Incorrect behavior with the SHOW_PNN_SIGNAME directive
1092426 CONCEPT_HDL CORE          Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design
1092874 CONCEPT_HDL CORE          DEHDL wire short during move not detected with check enabled
1093327 CONCEPT_HDL OTHER          Getting error SPCODD � 369 Unable to load physical part in variant editor
1093717 APD          DATABASE       Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent
1094618 CONCEPT_HDL INFRA          Unable to uprev the design in 16.5
1094788 SIP_LAYOUT    WIREBOND       Wirebond edit move command

DATE: 01-18-2013 HOTFIX VERSION: 036
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
491042  CONCEPT_HDL SECTION       Prevent PackagerXL from changing visibility on SEC attribute
945393  FSP          OTHER          group contigous pin support enhancement
1005078 CAPTURE       ANNOTATE       Copy paste operation does not fill the missing refdes
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical
1032609 FSP          IMPORT_CONSTRAIN Import qsf into FSP fails with 燕LL PLL_3 does not exist in device instance�
1071037 Pspice       SIMULATOR       Provide option to disable Index Files Time Stamp Check
1073237 SIG_INTEGRITY  GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
1076898 CONCEPT_HDL CORE          User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
1077169 APD          SHAPE          Shape > Check is producing bogus results.
1078270 SCM          UI             Physical net is not unique or not valid
1078497 ALLEGRO_EDITOR INTERFACES    Import DXF does not seem to work correctly.
1079821 CONCEPT_HDL CORE          Project Setup does not respect $TEMP variable for temp_dir and creates a  directory in project calle
1080336 CONCEPT_HDL CORE          Backannotation error message ehnancement
1080982 CONCEPT_HDL CORE          Crash of Allegro Design Entry during a copy of a note.
1081200 CONSTRAINT_MGR OTHER          In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.
1081553 CONCEPT_HDL OTHER          Model Assignment can not translate M (Milli-ohm) property value of DE HDL.
1081696 ALLEGRO_EDITOR INTERACTIV    Compose shape not working when radius is set to 1.0
1081760 FSP          CONFIG_SETTINGS  Content of 澹PGA Input/Output Onchip termination� columns resets after update csv command
1081834 CONCEPT_HDL OTHER          PDF Publisher fails crashes DEHDL
1082220 FLOWS       OTHER          Error SPCOCV-353
1082785 CONCEPT_HDL CORE          DE HDL should clean the design with non sync properties in some automated way
1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout
1083637 PCB_LIBRARIAN  CORE          Save As is not renaming the NAME in the symbol.css file
1084148 CONCEPT_HDL CHECKPLUS       The CheckPlus hasProperty predicate fails in the Physical environment.
1084285 CONCEPT_HDL INFRA          Corrupted dcf was never fixed and caused PXL error
1084441 CONCEPT_HDL CORE          Assigned net property value changes to numeric
1084542 ALLEGRO_EDITOR DRAFTING       Dimensions associated with frect doesn't rotate with the symbol.
1084736 APD          IMPORT_DATA    Import SPD2 file from UPD-L shape Pad and text issue
1085008 ALLEGRO_EDITOR INTERACTIV    Relative (from last pick) option in the Pick dialog not working for pick command
1085010 CONCEPT_HDL CREFER          Crefer crashes if the property value in the dcf file has more than 255 characters
1086576 CONCEPT_HDL CHECKPLUS       CheckPlus hangs when running Graphic rules.
1086902 CONCEPT_HDL INFRA          Problems occurred while loading design connectivity
1086905 PSPICE       SIMULATOR       PSpice crash while simulating circuit file with BREAK function
1087658 CAPTURE       PRINT/PLOT/OUTPU Lower level design pages are getting print twice
1087770 ALLEGRO_EDITOR EDIT_ETCH       Allegro crashes on a pick with the slide command.
1088231 F2B          PACKAGERXL    Design fails to package in 16.5
1090838 SIP_LAYOUT    PLATING_BAR    Can't create palting Bar

DATE: 12-7-2012 HOTFIX VERSION: 035
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
825813  CONCEPT_HDL CORE          HDL crashes when copying a property from one H block to other
871899  CONCEPT_HDL CORE          'Multiple:' column of Grid window in DE-HDL option is too wide
873917  CONCEPT_HDL CORE          Markers dialog is not refreshed
887887  CONCEPT_HDL CORE          Option to find unconnected Pins/Nets with DEHDL L License
892857  CONCEPT_HDL CORE          packager treats R? as a unique reference designator
995011  ALLEGRO_EDITOR INTERACTIV    Why Snap to option for Arc / Circle Centre is not working in this symbol file
1045863 CONCEPT_HDL INFRA          Customer had the crash several times when they run script with SPB16.51.
1061529 CONCEPT_HDL CORE          Space can be included in LOCATION value and cannot be checked by checkplus
1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.
1064035 CONCEPT_HDL COMP_BROWSER    Component Browser crashes on part number search using a library containing >23K parts
1067339 CONSTRAINT_MGR ANALYSIS       Relative Propagation Delay analysis in the Partition file seems very inconsitent.
1067400 CONCEPT_HDL CORE          ERROR(SPCOCD-171): Port exists in symbol but not in the schematic
1067451 CONSTRAINT_MGR CONCEPT_HDL    ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance
1068878 CONCEPT_HDL CORE          Rotating symbol causes the pin name to be upside down
1070007 ALLEGRO_EDITOR PLOTTING       Export IPF omits drill figure characters for backdrill holes
1071352 ALLEGRO_EDITOR UI_FORMS       Via label display option doesn't remain selected
1072067 APD          EXTRACT       When expoting using Extracta oblong pads with anyangle are abnormal
1072342 ALLEGRO_EDITOR INTERACTIV    Snap to Arc/circle center does not snap to the exact center in move command when moved about the symbol origin
1072691 CONCEPT_HDL CORE          Customer has the crash from Run Script of DE-HDL 16.51 again(#3)
1072843 ALLEGRO_EDITOR PLACEMENT       The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5
1072859 SIP_LAYOUT    DIE_EDITOR    padstack selection window crash from Die Editing: Component editing of Co-Design Die
1073745 CONCEPT_HDL CORE          Import design fails
1073852 ALLEGRO_EDITOR INTERACTIV    While doing a Copy Via use the last 'Copy Origin'
1074791 CONCEPT_HDL HDLDIRECT       User gets port exists in schematic but not on symbol message even though the port does not exist
1075151 ALLEGRO_EDITOR SHAPE          Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
1075256 ALLEGRO_EDITOR OTHER          Import > IPF in 16.5 is dropping data.
1075587 CONCEPT_HDL PAGE_MGMT       Unable to insert page in schematic
1075622 CONCEPT_HDL CORE          PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33
1075964 ALLEGRO_EDITOR SHAPE          Shape voiding is not consistent in conjunction with odd angle and arc traces
1076086 SIP_LAYOUT    IMPORT_DATA    missing wirebond after import SPD2
1076117 PSPICE       PROBE          Copy & Paste text/label in probe window changes font size and later gets invisible
1076538 CONCEPT_HDL CORE          Property visibility changes in attribute form not updated in schematic canvas.
1076566 ALLEGRO_EDITOR EDIT_ETCH       Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.
1076655 APD          DXF_IF          Dxf does not get offset value if die symbol padstack has offset value
1076909 ALLEGRO_EDITOR DRC_CONSTR    Allegro crashes while placing modules from database
1077026 CIS          LINK_DATABASE_PA fonts changes while linking db part in 16.5
1077621 CONCEPT_HDL CORE          DEHDL crashes when saving page 3
1078103 CONSTRAINT_MGR OTHER          Updating of Bus Group by Importing an Updated DCF file fails in first attempt and suceeds on second.
1078380 SCM          OTHER          Custom template works in Windows but not Linux
1078682 ALLEGRO_EDITOR DRC_CONSTR    Unaccetable slowness with Slide
1078688 F2B          PACKAGERXL    ConceptHDL crash immediately after Packaging
1078700 CONSTRAINT_MGR OTHER          The cmdiffutility is failing when comparing 2 different .dcf files.
1079068 CONCEPT_HDL CORE          DE-HDL crashes on upreved design when loading specific pages and having directive SHOW_PNN_SIGNAME '
1079400 ALLEGRO_EDITOR OTHER          desired angle vs. max angle for fillet
1079616 CONSTRAINT_MGR CONCEPT_HDL    Packager error in 16.5 which is resolved when system is re-booted
1079778 PSPICE       SIMULATOR       PSpice crash with RPC Server Unavailable Message

DATE: 11-22-2012 HOTFIX VERSION: 034
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
871886  CONCEPT_HDL CORE          Browse button in Signal Integrity window of DE-HDL option causes program crash
1030890 ALLEGRO_EDITOR DRC_CONSTR    High Speed USB Switch model
1063658 ALLEGRO_EDITOR SCHEM_FTB       Allegro Import Logic does not remove library defined diffpairs
1069915 ALLEGRO_EDITOR EDIT_ETCH       Allegro hangs with when doing spread between voids
1072791 ALLEGRO_EDITOR DATABASE       Database check cannot fix error and keep report the same issues cause artwork cannot export.
1072904 SIP_FLOW    SIP_LAYOUT    Probe pins not being mirrored in Die Editor correctly in Chip Down mode.
1073464 SCM          SCHGEN          Schgen never completes.
1074279 ADW          DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE
1076202 ALLEGRO_EDITOR EDIT_ETCH       Allegro add connect causing crash after Hotfix

DATE: 10-31-2012 HOTFIX VERSION: 033
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
103395  COBALT-COMPILE COMPILE       et3compile fails if compile for 3 boards in 32bit mode
715653  PSPICE       MODELEDITOR    Change in pin number assignment with model import for capture symbol
745682  CONCEPT_HDL CORE          Attributes window requires resizing each time DEHDL is launched
825846  CONCEPT_HDL CORE          The module_order.dat file gets corrupted
846658  CONCEPT_HDL CORE          About Change the NOTE with DE-HDL
938977  CONCEPT_HDL CORE          Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
942044  CONCEPT_HDL CORE          ConceptHDL crashes while opening the AMS project
946640  CONCEPT_HDL CORE          Import Design should inherit module order defined in the imported block
968646  ALLEGRO_EDITOR EDIT_ETCH       The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
969535  CONSTRAINT_MGR SCM             ASA retains information in the DCF file for parts/blocks that have been deleted and this causes problems.
976723  ADW          MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
981767  SCM          UI             Add series termination in ASA will crash if both output and input pins are selected.
988355  PCB_LIBRARIAN  CORE          PDV moving line-dot pinshapes left to right or visa versa places pintext wrongly
988438  CONCEPT_HDL CORE          Visible constraint disrupts MOVE command
993562  CONCEPT_HDL INFRA          After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
996577  SPECCTRA    ROUTE          Specctra not routing NET_SHORT connections
997992  CONCEPT_HDL CORE          Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
1001300 PSPICE       MODELEDITOR    BUG: Simserver crash with encryptedm model
1006400 SCM          OTHER          Incorrect warning in SCM due to way voltage value is stored in tabular and schematic blocks
1011502 CONCEPT_HDL CORE          Undo has an error on circle in DE-HDL during create a schematic symbol
1011798 ADW          LIBDISTRIBUTION  generate a differential report on parts in DB vs parts in PTF while running lib_dist
1012685 SIG_EXPLORER INTERACTIV    SigXP: traceEtchFactor value is not used.
1013656 SCM          OTHER          create diff-pair should honour diff-pair setup or ask user for positive negative leg
1013721 ALLEGRO_EDITOR EDIT_ETCH       Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
1014319 CONCEPT_HDL CORE          renaming HBlocks leads to crash
1017724 ADW          TDA             TDO update should force the schematic to re-read data from disk
1018506 ALLEGRO_EDITOR INTERACTIV    Edit copy with retain net of via will assign net to pin
1019979 SIG_INTEGRITY  LICENSING       extracta batch command result is incorrect
1020746 CONCEPT_HDL OTHER          PDF Publisher tool behavior inconsistent between OSs
1023051 SCM          UI             Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
1023057 CONCEPT_HDL CORE          Strange message when opening DE-HDL - INFO(SPCOCN-2055)
1023281 PSPICE       AA_PPLOT       Bug

spice advance analysis parARMetric plotter stops after 6000+ runs
1023702 CAPTURE       GENERAL       ORCAD Capture/CIS copy and past page to other design Issue
1023807 SPECCTRA    GUI             Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
1024890 PCB_LIBRARIAN  METADATA       con2con -metadataonly does not find footprints
1024899 PCB_LIBRARIAN  CORE          PDV symbol pins grid select all does not respect the filtering
1027147 CIS          UPDATE_PART_STAT CIS gives ERROR(ORCIS-6274) when updating Part status from Part Manager
1028237 CONCEPT_HDL HDLDIRECT       Error binding design when generating simulation netlist
1028432 SIP_LAYOUT    DIE_ABSTRACT_IF  Support pin numbers in die abstract flow
1029369 PDN_ANALYSIS EMVIEWER       EMViewer: Unit of Current Density.
1030591 CAPTURE       LIBRARY       Library Correction utiltiy locks the library and deosn't frees it even after being closed
1031474 CONCEPT_HDL ARCHIVER       Uisng Gtar as the compression utility causes the 'delete archive' to fail
1031765 PCB_LIBRARIAN  OTHER          librarian_expert feature is kept checked out for two hours
1032703 F2B          DESIGNVARI    Enhancement Replace Variant Component form needs to be resizeable
1033607 CAPTURE       NETGROUPS       Capture crash if netgroup instance name has square bracket 璟�
1033853 SIG_INTEGRITY  OTHER          netrev crashes when importing logic
1035624 CONCEPT_HDL CORE          Options pre-selected when launching base product
1036580 ALLEGRO_EDITOR MODULES       Module created from completely routed board file has lot of missing connections in it.
1037345 ALLEGRO_EDITOR INTERACTIV    Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
1038180 ALLEGRO_EDITOR DRC_CONSTR    BGA escapes not being calculated in phase tol
1038285 SCM          UI             Restore the option to launch DE-HDL after schgen.
1039147 ALLEGRO_EDITOR COLOR          Need an option to change color of Text marker and Text select in Display listing
1040257 CONCEPT_HDL INFRA          New license files causing slow tool performance
1040575 CIS          CONFIGURATION SQL database views are not visible in CIS configuration step 2.
1040678 ALLEGRO_EDITOR MANUFACT       Text spacing is inconsistant for top and bottom SM layer in xsection chart
1040869 CONCEPT_HDL INFRA          About uprev problems to SPB16.5 from 15.7
1040976 PCB_LIBRARIAN  CORE          PDV replace pinshape on Linux shows very slow performance compared to Windows
1042603 PSPICE       SLPS          About SLPS simulation interrupt
1042695 CIS          CONFIGURATION Can't see database views of an SQL database in CIS configuration
1043339 CONCEPT_HDL PAGE_MGMT       The .con and .xcon files aren't being updated.
1044029 PSPICE       ENCRYPTION    Encrypted lib not working for attached
1044222 ALLEGRO_EDITOR INTERACTIV    Capture Canvas Image changes working directory
1044264 PSPICE       SIMULATOR       Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
1045607 ALLEGRO_EDITOR OTHER          Component get placed even after Cancel IDF in form.
1045609 ALLEGRO_EDITOR PLACEMENT       Statement in the Viewlog for Update Symbol needs correction
1045694 CONCEPT_HDL INFRA          Why to package the design twice to pass the net_short property to the board?
1045734 ALLEGRO_EDITOR OTHER          Missing padstacks and layers information in cross section chart
1046929 CONSTRAINT_MGR OTHER          Unable to create physical of spacing cset after rename the default cset in design entry.
1047361 CONSTRAINT_MGR OTHER          CM fails to convert static phase tolerance value to database units.
1047756 CAPTURE       NETLISTS       Not adding user defined properties in netlist generated by orDump.dll
1047823 CONSTRAINT_MGR OTHER          acPutValue predicate text not being displayed at bottom of Constraint Manager window.
1047869 CONCEPT_HDL CORE          How do I define a custom pwr/gnd symbol for correct Verilog syntax?
1049303 CONCEPT_HDL CORE          Block rename deletes schematic data immediately in 16.5
1049317 CONCEPT_HDL OTHER          bomhdl with scm mode not working on RHEL in 16.5
1049399 SIG_INTEGRITY  OTHER          Toggling z-axis delay in CM shows the same value
1049993 ALLEGRO_EDITOR EDIT_ETCH       Loss of Y axis when adding via in manual group routing
1050483 ALLEGRO_EDITOR DRC_CONSTR    DRC has been waived but after updated DRC system generated a new DRC.
1051588 ALLEGRO_EDITOR PAD_EDITOR    Pad_Designer library drill report omits some drill holes
1052005 SIG_INTEGRITY  OTHER          Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
1052056 ALLEGRO_EDITOR PADS_IN       Pads to Allegro translator fails with error message "

ARSE ERROR: Wrong label format:Translation aborted."
1052449 CONCEPT_HDL COPY_PROJECT    Copy Project does not update all relative paths in the cpm file
1052479 PSPICE       PROBE          Cursor2 (Y2) displays the same value for all traces
1052753 ALLEGRO_EDITOR DRC_CONSTR    Allegro showing soldermask drc only when the symbol is rotated.
1052817 CONCEPT_HDL CORE          Getting packager error after renaming nets
1053319 CONCEPT_HDL INFRA          Change in property scope in windows mode is not retained
1053602 CONCEPT_HDL OTHER          Using the attached .NDX/DML files causes a lot of delay in invoking Tools > Model Assignment.
1053660 CAPTURE       PROJECT_MANAGER  Find Part Pin name or number is not working
1054010 CONCEPT_HDL CORE          MAKE_BASE
1054235 ALLEGRO_EDITOR PLACEMENT       Cannot place alt_symbols for mechanical parts.
1054846 CAPTURE       PROJECT_MANAGER  Crash on pressing Esc key
1055328 CONCEPT_HDL COPY_PROJECT    Project Manager - Project Copy
1055729 CIS          GEN_BOM       Standard CIS BOM per page is not working correctly with option  Process Selection
1056418 ALLEGRO_EDITOR OTHER          PDF exports the blank text markers whether or not the markers are visible.
1057003 ALLEGRO_EDITOR SHAPE          Z-copy to create RKI does not follow board outline
1057976 ALLEGRO_EDITOR DRC_CONSTR    No Same net Spacing DRC on attached design.
1058364 ALLEGRO_EDITOR SKILL          axlTransformObject() is moving refdes text when only symbol pin is selected for move
1058940 ALLEGRO_EDITOR INTERFACES    IDF(PTC) out command output wrong angle value
1059901 CONCEPT_HDL CORE          Global Property Change and <<OCC_DELETED>> property value.
1060428 CONCEPT_HDL CORE          ADW Flow Manager Copy Project fails to complete
1060589 F2B          PACKAGERXL    Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
1061172 CONCEPT_HDL CORE          Unable to delete Voltage
1061424 CONCEPT_HDL CORE          Customer creates <<OCC_DELETED>> property values.
1061659 ALLEGRO_EDITOR DATABASE       Unable to return drawing origin to 00
1062532 CONCEPT_HDL CONSTRAINT_MGR Our customer saw different DIFF_PAIR contentsevery time they invoke the Constraint manager.
1062558 APD          DXF_IF          If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
1064707 CONCEPT_HDL CHECKPLUS       Rules Checker core dumps on design
1065124 PCB_LIBRARIAN  SETUP          PTF properties cannot be deleted from the setup in PDV
1065745 SIP_LAYOUT    DATABASE       The logic assign net command crashes the application
1065860 ALLEGRO_EDITOR REPORTS       Design crashes when running a padstack usage report
1066051 ALLEGRO_EDITOR TESTPREP       Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
1066318 CONCEPT_HDL CREFER          Issue with LOCATION visibility in flattened schematic
1068425 F2B          DESIGNVARI    Out of memory message in Variant Editor while 盧hange properties� command
1068966 SIP_LAYOUT    DRC_CONSTRAINTS  DRC update aborts on this design with  ERROR -3000067
1069215 CAPTURE       DATABASE       Capture Crash on usnig a TCL utltiy to correct design
1069517 SIP_LAYOUT    DIE_EDITOR    change die abstract pins tab default action from delete to modify

DATE: 10-17-2012 HOTFIX VERSION: 032
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1052455 RF_PCB       DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation
1061223 CONCEPT_HDL CHECKPLUS       What determines a passthru pin?
1061817 ALLEGRO_EDITOR DRAFTING       Delete dimension vertex crash
1062982 ALLEGRO_EDITOR MODULES       Module containg partitions has been imported to the main design and cant be refreshed.
1063284 PCB_LIBRARIAN  OTHER          PDV Save As is broken
1063778 CONCEPT_HDL CHECKPLUS       The hasSynonyms CheckPlus predicate is not returning true for all global signals.

DATE: 10-5-2012 HOTFIX VERSION: 031
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1044754 SIG_INTEGRITY  SIMULATION    Incorrect waveforms when simulating with stacked die
1053631 FSP          DE-HDL_SCHEMATIC SchGen doesn't place DiffPairs together on the symbol
1054456 ALLEGRO_EDITOR MENTOR          mbs2lib incorrectly translates refdes label
1054871 CONCEPT_HDL CORE          Problem with creating schematic from block symbol
1055481 APD          SHAPE          keepout does not clear shape unless it's picked up and dropped down

DATE: 09-21-2012 HOTFIX VERSION: 030
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1008113 FSP          VIRTUAL_INTERFAC importing Altera constraints verilog to make virtual interface only small percentage of nets have IO standard
1042199 SIG_INTEGRITY  SIMULATION    Waveform list was not refreshed by switching tab.
1042348 SIP_LAYOUT    STREAM_IF       GDSII export includes the full refernce path, breaks CATS flow
1046527 ALLEGRO_EDITOR INTERACTIV    Display Segment Over Void not working correctly.
1047590 ALLEGRO_EDITOR SCHEM_FTB       Buses created in Allegro-CM are deleted by netrev in traditional flow
1047969 ALLEGRO_EDITOR NC             Some route path missed in .rou file.
1048907 ALLEGRO_EDITOR OTHER          PDF_OUT is very slow
1049262 ALLEGRO_EDITOR OTHER          APD and extracta crash owing to Wirebond.
1050408 APD          DXF_IF          Symbol has 45 degrees rotation  in mcm but DXF doesn篙.
1052045 ALLEGRO_EDITOR OTHER          Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3
1052600 ALLEGRO_EDITOR SHAPE          Adding a specific cline causing shape errors
1053065 MODEL_EDITOR GUI             The About ModelEditor form indicates an incorrect version.
1054008 CONCEPT_HDL CONSTRAINT_MGR Out of memory error while launching CM within DEHDL
1054269 ALLEGRO_EDITOR MANUFACT       Backdrill Setup and Analysis crashes on attached design
1055273 ALLEGRO_EDITOR INTERFACES    DXF exported from Allegro has an offset in pad location for Y- direction.

DATE: 09-8-2012 HOTFIX VERSION: 029
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
961420  ALLEGRO_EDITOR PLACEMENT       Regardless of the aspect ratio for room of side The QuickPlace by room command could be placed comp
1011470 FSP          GUI             Multi cell selection does not show the last cell selected
1011487 FSP          GUI             Ability to insert text directly in 激dit Group > Group Description� field
1035134 ALLEGRO_EDITOR DRAFTING       Placing mechanical symbol in a board drawing changes the dimension
1038186 ADW          LRM             CPM Option to supress the Sheet Content Mismatches during ADW _ImportSheet
1043325 CONCEPT_HDL INFRA          Incorrect bus members in CM
1043903 GRE          GLOBAL          This design crashes during planning phases in GRE.
1044230 ALLEGRO_EDITOR SHAPE          Fillets are causing spacing clearance larger than the defined value in CM
1044577 GRE          CORE          Plan > Topological either crashes or hangs GRE
1046113 CONCEPT_HDL EDIF300       EDIF creates a 0 lenght c2esch.edif file
1048291 CONCEPT_HDL CORE          Incorrect ERROR(SPCOCD-569) generated in 16.5
1048403 ALLEGRO_EDITOR SKILL          Allegro crashes opening more than 16 files with skill

DATE: 08-23-2012 HOTFIX VERSION: 028
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
320014  ALLEGRO_EDITOR EDIT_ETCH       Differential pair fail to Slide together
400672  ALLEGRO_EDITOR EDIT_ETCH       The Diffpair rule is disregarded because of the insertion of Via.
448641  ALLEGRO_EDITOR EDIT_ETCH       Diff pairs do not slide when the xnet is broken
501605  ALLEGRO_EDITOR EDIT_ETCH       Diff Pair Sliding problem
731162  ALLEGRO_EDITOR EDIT_ETCH       Slide and Delay Tune on Diff pair tunes only one net when Single trace mode is not ON.
967082  SIG_INTEGRITY  SIGNOISE       signoise command didn't use Frequency set on Net.
979958  SIP_LAYOUT    ASSY_RULE_CHECK  Running Assembly Rules Check on sip causes a crash
984604  ALLEGRO_EDITOR EDIT_ETCH       Error when trying to split via stack
988446  APD          OTHER          Beginning layer regular pad cannot change to Null.
995108  ALLEGRO_EDITOR GRAPHICS       Strange unexpected lines show across the oblong padstack
1021557 RF_PCB       DISCRETE_LIBX_2A Translator dxlib2iff lists cells alphanumerically inverted.
1021568 RF_PCB       DISCRETE_LIBX_2A translator GUI not listing library cells alphabetically in Linux/Unix
1024239 ALLEGRO_EDITOR INTERFACES    DXF pin location is moved when I execute DXF out
1039112 ALLEGRO_EDITOR ARTWORK       Antietch and Boundary layers deleted when Match Display selected
1039751 SCM          SCHGEN          SCHGEN is bunching voltage flags together to the point they're illegible
1040584 ALLEGRO_EDITOR GRAPHICS       After installing Hotfix 16.5s026  3D viewer has been impacted..
1040653 ALLEGRO_EDITOR DATABASE       Cannot update netlist data,  ERROR(SPMHDB-121): Attribute definition not found.
1041368 APD          DEGASSING       The Degas_No_Void properties assigned to Cline does not work.
1041864 ALLEGRO_EDITOR MANUFACT       Allegro crashes when opening the Backdrill setup menu
1042004 SIP_LAYOUT    DIE_STACK_EDITOR Moving die pad layer from top to bottom of package is not change the die stack side
1043777 ADW          COMPONENT_BROWSE ADW UCB must support hyperlinks in Database Mode like we do in Non-DB Mode
1043861 SIG_INTEGRITY  REPORTS       Derating values are NA in bus simulation report when derating table is not in working directory

DATE: 08-9-2012 HOTFIX VERSION: 027
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1005030 FSP          OUTPUT_GENERATIO About the CSV file of Generate PlanAhead Script command
1021870 CIS          CONFIGURATION CIS not accessing a database with table name having '&' character
1022902 RF_PCB       DISCRETE_LIBX_2A Allegro to ADS translator crashes on libraries
1035077 CONCEPT_HDL SKILL          ConceptHDL crashes during skill execution
1037325 CONCEPT_HDL COMP_BROWSER    Parse error when reading shoppingCart.xml with PTF value containing "&"
1038063 ADW          LRM             Global Property(CLASS) wasn't updated after LRM updated.

DATE: 07-27-2012 HOTFIX VERSION: 026
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
841657  FSP          DE-HDL_SCHEMATIC All ports of virtual interfaces are inout in schematic regardless of VI definitions.
868380  FSP          ALLEGRO_INTEGRAT improve error message Invalid design database encountered for ECO mode. Collaboration data was found for the following d
904790  SCM          OTHER          Update the format of the time displayed in the session log
904794  SCM          OTHER          Enhance the time displayed in the verilog file to support DST
920740  CONCEPT_HDL CORE          Detailed info about syntax error while executing "publishpdf" from Command Line.
921934  CONCEPT_HDL CORE          Clicking on Next page command would take you to the beginning of the schematic (page1)
923210  CONCEPT_HDL CORE          Search with multiple properties does not show all properties
927609  CONCEPT_HDL OTHER          CREF links bounded by rectangular box in generated PDF
957030  CAPTURE       DRC             DRC warning message for net group is not correct
957723  CONCEPT_HDL CAEVIEWS       Customer can not get DIFFERENTIAL_PAIR properties by CAEViews.
957913  CONCEPT_HDL CORE          Segmentation fault when running DE HDL from a command line with a script
966191  SIG_INTEGRITY  OTHER          Xnets to be split didn't work correctly.
970597  CONCEPT_HDL INFRA          16.5 schematic uprev fails if lib parts are missing
974361  ALLEGRO_EDITOR EDIT_ETCH       Difference in length between Show Element and CM when Z-Axis delay is enabled.
975531  CAPTURE       NETLIST_ALLEGRO  Error initializing COM property pages: Invalid pointer even after trying solution 11698280
977375  CONCEPT_HDL CORE          Unable to open the same Page of Base Schematic along with CRef Schematic Page.
981219  CONCEPT_HDL CORE          PaperSize A1 is not correctly managed by wplot_paper
981613  SCM          SCHGEN          ASA Schegen fails/crash on specific block in ASA design
981744  SCM          SCHGEN          schgen does not preserve connectivity and property related changes when done together
981809  SCM          OTHER          ASA does handle PACK_SHORT pins
982004  ALLEGRO_EDITOR GRAPHICS       Allegro crash when viewing and zoom in for subclass
982824  ALLEGRO_EDITOR OTHER          Import placement fails with a zero length log file.
989083  PCB_LIBRARIAN  CORE          PDV shows converted scalar to vector pins on symbol as Q_N<2..0> and in symbol pins as Q<2..0>_N
989518  CONCEPT_HDL CORE          DEHDL crash with Search Result tab
990582  FSP          NET_EDITING    Method to support the net names in the design to be driven by the FPGA port name
994504  PCB_LIBRARIAN  CORE          PDV adding text should respect the snap to grid grid settings and text justification
995351  ALLEGRO_EDITOR EDIT_ETCH       Enhance Allegro 16.5's slide with Vertex Action function of new Slide in SPB 16.6
995566  ALLEGRO_EDITOR REPORTS       Drill data file qty not matching drill chart
996019  PCB_LIBRARIAN  CORE          PDV having text on 2 lines having CR/LF is lost when reloading the symbol
998499  CONCEPT_HDL CORE          Attributes sticks to the component when its copied
998987  FSP          DESIGN_SETTINGS  Hyphen in project name should not be allowed while creating new project itself.
1000604 FSP          DE-HDL_SCHEMATIC Component ripping off from the board after second pass of Schgen
1000912 ALLEGRO_EDITOR DRC_CONSTR    Dynamic Phase Tuning DRC Goes Outside the Lines
1001167 SIG_INTEGRITY  GEOMETRY_EXTRACT Need warning message of DC shape check.
1001395 SIP_LAYOUT    ASSY_RULE_CHECK  Shape Minimum void check reports lots of DRCs which are not necessary to check out.
1001563 FSP          SCRIPTING_INTERF TCL command to dump the path to rules file and mapping file used by every part in a FSP project
1002462 CONCEPT_HDL CORE          Block Stretch disrupts pins
1003110 PCB_LIBRARIAN  AUTOMATION    PDV Symbol Property Outline Offset value zero wrong interpreted as -200
1003253 CAPTURE       PROPERTY_EDITOR  property is not removed from Browse Spreadsheet in H design
1003447 SIP_LAYOUT    DIE_EDITOR    Rounding errors are causing problems for shrunk dies with .001 u mfg grid
1004093 CONCEPT_HDL OTHER          Disable Default setting in Product Choice for Project manager
1004249 CONCEPT_HDL CORE          DEHDL global search crashes on a ? search
1005890 PSPICE       PROBE          Probe Window crashes when &

is added in the Probe Page Header
1006183 CIS          FOOTPRINT_VIEW Incorrect pin details in 3D Footprint Viewer.
1006336 SIG_EXPLORER OTHER          diif pair nets with shape traces cannot be extracted into sigxp
1006437 SIP_LAYOUT    BGA_EDITOR    SCM not loading the die if dies refdes and LFnames are changed
1006862 CONCEPT_HDL INFRA          Uprev process is tedious and requires lot of manual effort for a design with multiple reuse blocks
1007198 CONCEPT_HDL INFRA          Room property getting the wrong value after packaging an upreved design
1007732 CAPTURE       NETLIST_OTHER Q: Why does wirelist netlist adds an extra NODE for some connections made using POWER GROUP?
1007781 CONCEPT_HDL OTHER          Generated pdf for design upreved from 16.3 has occ_only attributes
1007904 GRE          IFP_INTERACTIVE  Setup > Design Parameters is missing the Flow Planning tab with Allegro PCB SI XL license
1007995 FSP          DE-HDL_SCHEMATIC FSP schematic generation needs abiltiy to pick power symbols just like ASA
1008112 FSP          DE-HDL_SCHEMATIC port directions set inside FSP need to be used for ports in schgen
1008451 LAYOUT       TRANSLATORS    The brd file translated using L2A Translator is loosing the diameter of the copper area attached to the pin.
1008507 PCB_LIBRARIAN  OTHER          Base Part Developer isn篙 there with the PCB Designer license of 1650.
1008608 ALLEGRO_EDITOR INTERACTIV    Add an arc/fillet with a changed radius will invert an arc at a different location
1009001 CONCEPT_HDL OTHER          Graphics Color setting form is strange on Win7.
1009077 CONCEPT_HDL CORE          unable to uprev the design
1009109 SIG_INTEGRITY  OTHER          User defined diff pair pin pairs are mixed in match group
1009557 SIG_INTEGRITY  GEOMETRY_EXTRACT Difference in Impedance and Diff Impedance calculation is not correct
1010145 ALLEGRO_EDITOR GRAPHICS       Display Issue With Oblong padstack
1010374 LAYOUT       TRANSLATORS    Layout MAX file is not getting converted to OrCAD Peformance correctly
1010512 ALLEGRO_EDITOR DRC_CONSTR    Can not check short pin in DRC
1010569 CONCEPT_HDL OTHER          Sort Old Signal Name column in paste special
1010661 PCB_LIBRARIAN  CORE          Save as the part with different in PDV changes all the property values
1011022 ALLEGRO_EDITOR OTHER          Create Fanout crashes allegro if dimension is visible
1011424 CONCEPT_HDL CREFER          Component attributes are set to invisible in the flatten schematics generated from CRefer
1011431 FSP          PROCESS       Incorrect selection of protocols under 燕rocess Options� window
1011474 FSP          OTHER          Easier way to read lengthier message which comes in no connect report (Report for Signals).
1011525 PCB_LIBRARIAN  CORE          the reload does not update sym_1 immediately
1011618 SIP_LAYOUT    DIE_ABSTRACT_IF  Add Co-design die from DIA should add any missing non-conductor subclasses for import of package shapes.
1011629 CONCEPT_HDL INFRA          RefDes change on schematic after upreving from SPB 16.3 to 16.5
1012750 CONCEPT_HDL ARCHIVER       The SI_MODEL_PATH from ARCHIVE_SI_MODEL_FILES directive of Archiver
1012942 CAPTURE       SCHEMATICS    ORCAD V16.5 open Capture DOS SDT Schematic issue
1013377 ALLEGRO_EDITOR DRAFTING       Allow edit and delete vertex in dimension environment
1013795 ALLEGRO_EDITOR MANUFACT       Tolerance value for Angular Dimension using "

lus or Minus" type is not working correctly in new Dimesnion environment
1014142 CONCEPT_HDL CORE          Customer have dump file when they run Script on DE-HDL16.5
1014243 CONSTRAINT_MGR CONCEPT_HDL    Default setting of Constraint Manager's Filter.
1014334 CONCEPT_HDL INFRA          Incorrect refdes and source after first Export Physical.
1014853 CAPTURE       NETGROUPS       Error (ORCAP-1839) Invalid Character in Netgroup name (minus sign)
1014913 ALLEGRO_EDITOR GRAPHICS       3D viewer seems to hang PCB tool.
1015256 ALLEGRO_EDITOR OTHER          Allegro Crash while working with Dimensioning Environment
1015397 SIP_LAYOUT    DIE_ABSTRACT_IF  Support bumps provided in die abstract in hierarchical blocks
1016859 SCM          REPORTS       dsreportgen exits with %errorlevel%
1016891 APD          VIA_STRUCTURE Log file does not indicate the problem or how to fix when refreshing Via Stuctures fails.
1016916 ALLEGRO_EDITOR SKILL          Cannot delete non etch shape from a symbol in the pcb editor.
1017173 ALLEGRO_EDITOR GRAPHICS       moving a via changes it's size to the NC figure
1017337 CONCEPT_HDL OTHER          DEHDL Recover adds extra page border
1018222 PDN_ANALYSIS PCB_STATICIRDROP DC-Irdrop happened crashed if GND shape did not be selected
1018348 SCM          SCHGEN          Generate schematic hangs when creating pages
1018769 SIP_LAYOUT    MANUFACTURING Deletion of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property
1019167 SIG_INTEGRITY  OTHER          Top thickness not added to the z-axis delay.
1019423 SIP_LAYOUT    DIE_ABSTRACT_IF  SiP Layout and APD should exclude characters from PinNumbers that are not valid in SPB front-end tools
1019977 CONCEPT_HDL CORE          Upver changes voltage property value
1020163 CONCEPT_HDL CREFER          missing page after running CREFER in schcref of flat design
1020666 APD          OTHER          Bug - APD option for Route >Routing Layer Assign fails with Error message
1021620 ALLEGRO_EDITOR OTHER          LINUX UNIX (AIX) numlock maps incorrectly
1021869 PCB_LIBRARIAN  CORE          SCM should not crash when using the attached design.
1022117 PCB_LIBRARIAN  CORE          Warning(SPCODD-44): File xxx/fsp.ptf not found
1023076 CONSTRAINT_MGR OTHER          ECSet Differential Pair inheritence is not working when a Physical Cset is also defined on Net Object
1023305 ALLEGRO_EDITOR PLACEMENT       ALT_SYMBOLS is not available in RMB when hover over symbol
1023715 CONCEPT_HDL OTHER          After runnign genview dashboard does not show the sym_1 view as being modified.
1023751 PDN_ANALYSIS PCB_STATICIRDROP PDN: thresholds of each padstack are not used for DC current exceed pin/via threshold report.
1023774 APD          WIREBOND       After "xml wire profile data" is imported it isn't reflected to actual wire.
1023836 ALLEGRO_EDITOR INTERACTIV    Move origin undo doesnot brings origin to original location
1024684 APD          COLOR          Layer priority not working with user defined mask layers.
1024996 SIP_LAYOUT    DIE_EDITOR    SiP Layout Edit Co-design DIE shifts the drivers, the .dia for this came from Virtuoso
1025482 CONCEPT_HDL INFRA          dcf file not getting updated
1026153 CONCEPT_HDL CORE          DE HDL crashes while saving.
1026403 ALLEGRO_EDITOR OTHER          application crashes when we attempt to change the User units form Millimeter to Mils 3
1027336 SIP_LAYOUT    DIE_EDITOR    Die editor does not allow change of pkg padstack
1028240 F2B          PACKAGERXL    plx.exe has stopped working plx.log is empty
1028544 ALLEGRO_EDITOR REPORTS       Wrong angle value of  Module Report (180->180000)
1029213 ALLEGRO_EDITOR SHOW_ELEM       Allegro crashes on Show Element when showelement_highspeed is set.
1029217 SCM          SCHGEN          Schgen creates schematics with no visable netnames.
1029596 ALLEGRO_EDITOR PADS_IN       PADS_IN dropping net name on few pins
1029606 SIP_LAYOUT    MODULES       The place manually crashes the application
1030385 ALLEGRO_EDITOR INTERFACES    Import DXF fails to import text and flag note symbols correctly
1031255 SCM          UI             SCM Replace Component form will not sort the columns.
1031324 ALLEGRO_EDITOR EDIT_ETCH       Double click to add via crashes allegro
1031676 ALLEGRO_EDITOR OTHER          Auto Rename Refdes Crashes Allegro
1031838 SIG_INTEGRITY  GUI             Auto Setup is unable to assign models which have been created by 15.7's Create Model rules.
1033291 CONCEPT_HDL INFRA          DE-HDL crashes if Search is started while the design is loading
1034699 CONSTRAINT_MGR OTHER          Constraint Manager Update DRC deletes waived DRC's comments.
1043671 ALLEGRO_EDITOR DATABASE       Dbdoctor fails on 16.5 release
320014  ALLEGRO_EDITOR EDIT_ETCH       Differential pair fail to Slide together
400672  ALLEGRO_EDITOR EDIT_ETCH       The Diffpair rule is disregarded because of the insertion of Via.
448641  ALLEGRO_EDITOR EDIT_ETCH       Diff pairs do not slide when the xnet is broken
501605  ALLEGRO_EDITOR EDIT_ETCH       Diff Pair Sliding problem
709668  ALLEGRO_EDITOR EDIT_ETCH       Diff pair can not slide together.
731162  ALLEGRO_EDITOR EDIT_ETCH       Slide and Delay Tune on Diff pair tunes only one net when Single trace mode is not ON.
790914  ALLEGRO_EDITOR EDIT_ETCH       Differential pair routing question
859855  SIG_INTEGRITY  GEOMETRY_EXTRACT OddSegParallelOffset env doesn't work if Enable CPW Extraction is checked.
966191  SIG_INTEGRITY  OTHER          Xnets to be split didn't work correctly.
967082  SIG_INTEGRITY  SIGNOISE       signoise command didn't use Frequency set on Net.
967832  CONCEPT_HDL INFRA          Back annotation process takes long time on network
969535  CONSTRAINT_MGR SCM             ASA retains information in the DCF file for parts/blocks that have been deleted and this causes problems.
974361  ALLEGRO_EDITOR EDIT_ETCH       Difference in length between Show Element and CM when Z-Axis delay is enabled.
974533  SIP_LAYOUT    OTHER          Crashes in Edit > Die Properties and obviously has a setup problem.
979958  SIP_LAYOUT    ASSY_RULE_CHECK  Running Assembly Rules Check on sip causes a crash
982004  ALLEGRO_EDITOR GRAPHICS       Allegro crash when viewing and zoom in for subclass
984604  ALLEGRO_EDITOR EDIT_ETCH       Error when trying to split via stack
988446  APD          OTHER          Beginning layer regular pad cannot change to Null.
995108  ALLEGRO_EDITOR GRAPHICS       Strange unexpected lines show across the oblong padstack
995351  ALLEGRO_EDITOR EDIT_ETCH       Enhance Allegro 16.5's slide with Vertex Action function of new Slide in SPB 16.6
996577  SPECCTRA    ROUTE          Specctra not routing NET_SHORT connections

DATE: 07-5-2012 HOTFIX VERSION: 025
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
859855  SIG_INTEGRITY  GEOMETRY_EXTRACT OddSegParallelOffset env doesn't work if Enable CPW Extraction is checked.
1014275 CONSTRAINT_MGR OTHER          F2B: DiffPair cns was not updated if DiffPair Name didn't match.
1019414 ALLEGRO_EDITOR INTERFACES    export DXF creates pin offset in 16.5
1019688 ALLEGRO_EDITOR INTERACTIV    moving dimension symbol in 16.3 crashes allegro
1022563 ALLEGRO_EDITOR INTERFACES    IDF_In do not import Arc correctly when IDF and Allegro accuracy are same.
1023892 SIG_INTEGRITY  OTHER          Need Custom Variable to control signoise.run uprev from 16.2 > 16.5 to control reading of DevLibs variables
1023939 APD          COLOR          Assigning a color to a group a second time fails after "clear net color overrides."
1025402 SIG_INTEGRITY  LICENSING       Show Element window does not display and Allegro crashes.
1025957 SIG_INTEGRITY  OTHER          Same net parallelism reports DRC errors on straight line segments
1026401 ALLEGRO_EDITOR SKILL          axlPolyExpand returns incorrect information when expand

DATE: 06-20-2012 HOTFIX VERSION: 024
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1011040 FSP          PROCESS       Feature to avoid connectivity between fixed voltage Output and variable voltage Input
1012985 ALLEGRO_EDITOR DATABASE       Allegro crashes multiple times a day
1013644 ALLEGRO_EDITOR SHAPE          Sliding trace with oops creates a duplicate shape islands
1014351 ALLEGRO_EDITOR OTHER          Whenever we open a file (brd, dra) in PCB Editor with an OrCAD PCB Designer license,we get a warning SPMH0D-34
1014893 CONSTRAINT_MGR OTHER          With CM open layout is extremely slow and Allegro crashes very frequently
1015210 ALLEGRO_EDITOR DRC_CONSTR    Deleting Via from an array casues DRC errors
1016546 CONCEPT_HDL CONSTRAINT_MGR Wrong value of NET_PYSICAL _SPACING_TYPE in Attribute form
1016932 RF_PCB       DISCRETE_LIBX_2A Incorrect Symbol Pin Numbers after import into ADS
1017332 APD          VIA_STRUCTURE Refreshing Via Structures results in shorting to power plane.
1017931 ALLEGRO_EDITOR OTHER          IPF import fails with error-IPF error : Illegal pen number
1018413 F2B          PACKAGERXL    Export Physical producing different results depending on how it is launched
1018435 APD          OTHER          Oblong pads in Sip are not displayed correctly in the Stream_out .sf file.
1018936 ALLEGRO_EDITOR OTHER          unexpexted DRC eror
1018978 ALLEGRO_EDITOR DRC_CONSTR    Update DRC changes DRC without any change in design
1019303 CONCEPT_HDL INFRA          DEHDL custom outport displays error
1019913 ALLEGRO_EDITOR DATABASE       BUG:Bottom pins are also shown in DXF export
1019955 ALLEGRO_EDITOR SKILL          axlRegionCreate and axlRegionAdd do not work in a symbol file.
1020749 ALLEGRO_EDITOR DATABASE       16.2 Parts not updating when opened in a 16.5 database
1020780 APD          COLOR          APD crash on assigning color to net using Color192
1021033 CONCEPT_HDL CONSTRAINT_MGR Cleared ecsets in 16.3 reappears as mapping errors without ecset names after uprev to 16.5

DATE: 05-30-2012 HOTFIX VERSION: 023
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
999003  LAYOUT       TRANSLATORS    L2A leaves unconnected nets and improper voids on vias
1012375 ALLEGRO_EDITOR PARTITION       Route Keepout in All subclass shape in .dpf cannot be imported back to master board.
1012522 ALLEGRO_EDITOR OTHER          Allegro crashes during Import > Logic > Deisgn HDL and creates a .SAV file.
1012765 ALLEGRO_EDITOR EDIT_ETCH       Allegro crash
1012934 CONCEPT_HDL CONSTRAINT_MGR Backannotation destroys matchgroups in replicated blocks in customer design
1012951 CONCEPT_HDL CORE          Text justification corrupted on symbol mirror
1013030 SIG_INTEGRITY  SIGNOISE       PCB SI crashes when running bus simulations
1013519 APD          GRAPHICS       The layer selection  in the Visibility Form slows down after selecting "Nets" in the Color Dialog.
1013853 CONSTRAINT_MGR OTHER          Override constraints not working
1013942 APD          COLOR          Assign color is inconsistently assigning colors to the clines but not the vias.
1014402 CONCEPT_HDL CORE          DE HDL crashes while saving some pages
1014757 SIG_INTEGRITY  GEOMETRY_EXTRACT Huge Difference in Differential Impedance values in Cross Section between Bem2d and Ems2d Field Solver.
1014956 SIP_LAYOUT    DIE_EDITOR    die editor pin move and add commands put things on the half grid and not on the grid as expected

DATE: 05-18-2012 HOTFIX VERSION: 022
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
686560  CAPTURE       BACKANNOTATE    Changing pin group property after pin swap resets pin numbers
740162  ALLEGRO_EDITOR EDIT_ETCH       Enhance Allegro PCB Editor use model when adding NULL net copper
963645  PSPICE       MODELEDITOR    Model import wizard crashes while associating IRF150 to schematic symbol.
966422  CAPTURE       PROPERTY_EDITOR  References changes, done in the property editor, lost on closing and reopening the design
968674  PSPICE       PROBE          Display Measurement evaluation does not show Measurement and its value directly.
970281  CAPTURE       ANNOTATE       Annotation assigns wrong refdes to resistor.
975497  CAPTURE       NETLIST_OTHER Capture crashes while trying to generate other format netlist
993129  CONCEPT_HDL CONSTRAINT_MGR unable to select multiple nets in schematic and highlighted them in CM
997518  PSPICE       PROBE          Mouse click on probe window is required to see Plots after simulation for multiple plots on win 7
999603  CAPTURE       NETGROUPS       Capture crashes on trying to rename a netgroup member.
1002370 ALLEGRO_EDITOR SKILL          Allegro axlMeterIsCancelled function not always returning t when Stop button is selected.
1003205 APD          DATABASE       Fillet gone after DB doctor check
1003821 ALLEGRO_EDITOR EDIT_ETCH       Diff pair routing starts from unexpacted pin for non control cline
1005793 ALLEGRO_EDITOR DRC_CONSTR    Update DRC with Multi-thread DRC changes DRC without any change in design for Win 7 OS
1005835 ALLEGRO_EDITOR OTHER          Display Status fails to show rats on missing connection point
1006701 ALLEGRO_EDITOR SHAPE          Shape to shape void incorrect spacing value in L3 layer.
1006718 CONSTRAINT_MGR OTHER          Allegro crashes while sliding nets having custom formula in CMGR
1006920 CONCEPT_HDL CORE          Global Navigate hangs schematic
1007102 CAPTURE       OTHER          Latest release on START page is not getting updated
1008585 ALLEGRO_EDITOR MANUFACT       Manufacturing X Section Chart layer is not coming up correctly in this design
1009047 F2B          PACKAGERXL    Packager crashes after installing ISR s19
1009443 ALLEGRO_EDITOR DRAFTING       Pressing TAB key in Dimension environment results error: E- (SPMHA2-65): Error -3000314.
1009562 CAPTURE       TCL_INTERFACE Library correction TCL utility is failiing to correct the corrupt libraries.
1009941 SIP_LAYOUT    DIE_ABSTRACT_IF  Distributed DIE abstract generated from Virtuoso VSiP Architect has errors on Shapes used in Area xfer
1010201 ALLEGRO_EDITOR INTERACTIV    dbdoctor on psm file returns error in open drawing
1010432 ALLEGRO_EDITOR SYMBOL          Error in placing Pin in Symbol editor, "W- (SPMHDB-226): Inconsistent rotation data."
1010611 MODEL_INTEGRIT TRANSLATION    Translation failed due to IBIS2DML errors.

DATE: 05-5-2012 HOTFIX VERSION: 021
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
642550  ALLEGRO_EDITOR EDIT_ETCH       Route connect of Diff Pairs is not honoring  the correct gap when entering a region.
921837  CONCEPT_HDL CONSTRAINT_MGR DIFFERENTIAL_PAIR property in synonymed net is deleted automatically
926776  CONCEPT_HDL CORE          Modify the newgenasym log file to convey the multi format vector information
969547  SCM          CONSTRAINT_MGR Diff Pair, Net Class objects are being "corrupted" by making logic changes in ASA involving copy & paste of signals.
976566  PCB_LIBRARIAN  VIEWERS       SCM crashes when adding a part.
984538  PCB_LIBRARIAN  CORE          PDV and con2con crash on part having illegal data into symbol view
987120  CONCEPT_HDL ARCHIVER       Customer would like to include signal models into archived project by Arciver.
988683  CONCEPT_HDL INFRA          CMGR Net extraction via DEHDL writes topology file at the CPM project level
989116  CONCEPT_HDL CORE          Warning 171: Port exist in symbol but not in schematic
990630  FSP          TERMINATIONS    Overlap of parts sig_name ctaps and refdes after schgen
992075  CONCEPT_HDL ARCHIVER       Create Single File Archive and Delete Archived Directory doesnt work if spaces are found
993084  CONCEPT_HDL CONSTRAINT_MGR Problem with bus members
994466  SCM          ECO             SCM is going out of Memory in Import ECO Netlist which is used in the BRD2ASA flow
996609  APD          EDIT_ETCH       Error (SPMHAC-31): The element from which you are connecting is not on the subclass.  Use "Add Via"
997076  CONSTRAINT_MGR OTHER          Application not checking to class to class inherited spacing Cset
997655  CONSTRAINT_MGR CONCEPT_HDL    Support Partical DCF import/Export in DEHDL
998176  SIG_INTEGRITY  OTHER          Allegro crashes when extracting net from CM
999044  ALLEGRO_EDITOR EDIT_ETCH       Routing wires is confusing because of the way DRC engine resolves spacing rules.
999218  SIG_INTEGRITY  OTHER          concept2cm has encountered a problem
1001742 ALLEGRO_EDITOR SCHEM_FTB       netrev detects an error for the part which has JEDEC_TYPE with null value.
1001897 SIG_INTEGRITY  OTHER          Packaging much longer in 16.5 s018 ISR
1001913 APD          STREAM_IF       Mirrored text is not mirrored in stream_out and stream_in
1001953 ALLEGRO_EDITOR OTHER          Allegro 16.5 database crashes when trying to downrev to 16.3
1002895 SIG_INTEGRITY  FIELD_SOLVERS Delay calculation is changed from ISR16 to ISR17 and above
1003097 APD          WIREBOND       How to change finger padstack that maintaining current finger angle
1003638 ALLEGRO_EDITOR UI_FORMS       Ability to filter and sort in IDX Flow Manager Export/Import
1004196 ALLEGRO_EDITOR DRC_CONSTR    Thermal ties creates shorts with Enable online DRC checked.
1004346 CONCEPT_HDL COMP_BROWSER    The hyper-link under the DATASHEET column breaks after sorting
1004363 ALLEGRO_EDITOR PLACEMENT       Place manual is inaccurate at pick up
1005265 CONCEPT_HDL INFRA          Uprev from 163 to 165 does not complete
1005398 SCM          SCHGEN          Crash when generating schematics when vectored pins tied to non vector signal
1005584 ALLEGRO_EDITOR MANUFACT       Variant Assembly Drawing with locked symbols creates incorrect view
1006266 ALLEGRO_EDITOR GRAPHICS       3D Viewer Crashes Allegro
1007420 ALLEGRO_EDITOR OTHER          Allegro PCB Editor crashes while doing a File > Change Editor

DATE: 04-20-2012 HOTFIX VERSION: 020
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
712448  PCB_LIBRARIAN  CORE          $PN should be grayed out if the bus is shown in un-expanded mode.
919548  ADW          COMPONENT_BROWSE After component is placed If we see the Classification of UCB that it was collapsed.
972909  SIG_INTEGRITY  SIMULATION    Bus Sim: stimulus on diff data signals were not used correctly in comprehensive sim.
974325  PSPICE       PROBE          Unable to edit and move the existing label texts.
985088  SIG_INTEGRITY  GEOMETRY_EXTRACT Extraction of the cline near the reference plane shape edge.
987311  CONCEPT_HDL CORE          ERROR (LMF-02018): License call failed for feature Allegro_TeamDesign_Auth_Option
987544  CONCEPT_HDL INFRA          Some component have $PN property annotated on the instance body
987605  APD          ASSY_RULE_CHECK  Not getting accute angle DRC's where there is a pin or via attached to the trace.
990396  SCM          OTHER          SCM Clipboard does not populate contents copied outside of SCM
990961  CONCEPT_HDL INFRA          Uprev to 16.5 causing physical net name change
993993  SIG_INTEGRITY  FIELD_SOLVERS Transmission line calculator and xsection form showing different DiffZ0 values
995086  CONCEPT_HDL INFRA          Target net is lost in the uprev process
996136  F2B          PACKAGERXL    The pstrprt.dat part entries no longer contain space after increasing PART_TYPE_LENGTH
996481  PCB_LIBRARIAN  CORE          PDV cell "file > save as" changes uppercase characters in PTF to lowercase
996816  SIP_LAYOUT    WIREBOND       The tool is down when I do the "import wirebond"
997137  CONCEPT_HDL CHECKPLUS       Why does CheckPlus report that the INUSE� property exists?
997243  CONCEPT_HDL INFRA          Save and hier_write fails on a upreved design with the message - ERROR SPCOCN-1995
997260  SIP_LAYOUT    DIE_ABSTRACT_IF  Not able to import the co-design dia file in CDNSIP with the error msg SPMHUT-110 No pin count set
997427  ALLEGRO_EDITOR PAD_EDITOR    SMD Padstack defined for Bottom placed on Top
998107  CONCEPT_HDL CONSTRAINT_MGR Error message calls for Constraint Manager Synchronization
998124  ALLEGRO_EDITOR INTERACTIV    Copy paste with snap to pin option not working correctly
998313  PCB_LIBRARIAN  CORE          PDV on linux platform to write symbol coordinates when using PDV_Symbol_Coord environment variable
999030  ALLEGRO_EDITOR SHAPE          Shape Corrupts when moving
999452  SIG_INTEGRITY  SIMULATION    HSPICE sim from probe command fail if native ibis was assigned to components.
999536  SPECCTRA    ROUTE          Allegro router crashing with memory error.
1000060 ALLEGRO_EDITOR OTHER          Board thickness in idf output is not correct
1000824 APD          WIREBOND       *Error* lessp: can't handle (14 < nil)
1000835 SIG_INTEGRITY  SIGWAVE       SigWave: can not import many simulation files at one time.
1001302 APD          WIREBOND       Add Routing channel behavior

DATE: 04-5-2012 HOTFIX VERSION: 019
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
230469  ALLEGRO_EDITOR SHAPE          Allegro improve performance of Dynamic Shapes
753867  PCB_LIBRARIAN  GRAPHICAL_EDITOR PDV crash when graphics from one symbol to another
957363  ALLEGRO_EDITOR PLACEMENT       Allegro hangs while moving reuse modules
965705  RF_PCB       DISCRETE_LIBX_2A Allegro Discrete Library to Agilent ADS Translator hangs on Windows
979872  SIP_RF       OTHER          V-SiP Arch LVL or Compare DIE abstract fails to hilite in RED a pin location move, using REF DES against IC615 Layout
983318  LAYOUT       TRANSLATORS    L2A translator for v16.5 fails with error -Subclass name TOP not valid for class Package keepin
984503  CONSTRAINT_MGR INTERACTIV    Highlighted nets/xnets in CM > Object > Filter is not working when Highlight Pattern is Solid
985091  ALLEGRO_EDITOR OTHER          Customer wants to be disabled "Allegro PCB Design L (legacy)" of the "cadence Product Choices".
985734  CONCEPT_HDL INFRA          part having a pin_name of # followed by a double digit numeric causes issues in packaging
985984  CONCEPT_HDL PAGE_MGMT       Deleting pages inside 16.5 takes to long for larger projects
986614  CONCEPT_HDL INFRA          Uprev process in 16.50 prompts Error: Exception occurred while netlisting block
987276  ALLEGRO_EDITOR MODULES       Placing module with Associative dimension crash
988088  ALLEGRO_EDITOR INTERACTIV    Edit > Move of Vias with incremental coordinates entered at the command line makes no sense in 16.5
988145  ALLEGRO_EDITOR INTERACTIV    The move command with body center selected does not behave correctly with embedded components
988822  SIG_EXPLORER SIMULATION    Incorrect hspice netlist was generated.
989010  ALLEGRO_EDITOR NC             NC Drill file for Backdrill do not include the drills without Drill Figure. Back Drill output is bad
989127  CONCEPT_HDL CONSTRAINT_MGR NET_SPACING_TYPE placeholder is not added on the net attributes on the schematic
989589  ALLEGRO_EDITOR INTERACTIV    The Options, Find and Visibility windows are deleted and we need to delete allegro.ini file for recovering them back
989593  ALLEGRO_EDITOR SCHEM_FTB       16.5 Netrev fails with the message - ERROR(SPMHNI-176) Device library error detected
989597  CONCEPT_HDL INFRA          Wrong values displayed in the canvas
989624  ALLEGRO_EDITOR COLOR          View Color file, result error "Invalid subclass specified" for Mask layers.
989734  ALLEGRO_EDITOR COLOR          Display showing shapes on a layer that is turned Off.
989882  ALLEGRO_EDITOR PADS_IN       PADS IN with runtime Error
990121  ALLEGRO_EDITOR OTHER          Tools > Derive Connectivity crashes Allegro PCB Editor
990607  ALLEGRO_EDITOR DATABASE       package symbol fails to place. Illegal line segment .. end points
990736  ALLEGRO_EDITOR MANUFACT       Stream Out crashes with customer design
990909  APD          DEGASSING       The Void to Conductor (Same Layer) option of degas does not work.
991121  APD          DATABASE       APD crash in dbdoctor drc check. Reports Illegal db pointer
991256  F2B          PACKAGERXL    What is the role of the pstdmlmodels.dat?
991404  ALLEGRO_EDITOR ARTWORK       With latest ISR of 16.5,Artwork Control Form says "Plot Completed" when it actually completed with warnings.
991459  ALLEGRO_EDITOR PLACEMENT       Rubberband between the cursor and symbol origin is missing while rotating
991965  ALLEGRO_EDITOR INTERFACES    Import IDF doesnot translate Package Keepout areas
992187  ALLEGRO_EDITOR OTHER          add connect corrupts database
992195  ALLEGRO_EDITOR OTHER          The numeric key pad on a Linux or Solaris workstation is not working in 16.5 when Num Lock is ON.
992198  CONCEPT_HDL CORE          Symbol crashes in 16.5 works in 16.3
992331  SIG_INTEGRITY  OTHER          Unbalanced diff pair is losing extra net from xnet connect - fails to update topology
992468  ALLEGRO_EDITOR PADS_IN       PADS IN with Error
992643  ALLEGRO_EDITOR INTERFACES    Problem importing DXF into Allegro. Error SPMHA1-66
992656  PCB_LIBRARIAN  CORE          PDV to store sym_cords.txt when saving cell
992659  CAPTURE       NETLIST_ALLEGRO  Improve the performance for netlisting large designs
992842  CONSTRAINT_MGR CONCEPT_HDL    Global ECSet Audit is catching errors but not updating the cmgr view to fail 'red' so hard to find errors
993535  ALLEGRO_EDITOR DRC_CONSTR    Constraint Manager not able to analyze Diff Pair Static Phase Tolerance for PCIe signals in attached database.
993554  ALLEGRO_EDITOR EDIT_ETCH       HUD for Relataive Propagation Delay turns Green eventhough the DRC is not cleared
993618  ALLEGRO_EDITOR OTHER          Viewlog for DBDoctor_ui could not find log file if ads_sdlog is defined.
993655  PCB_LIBRARIAN  CORE          PDV move other objects then pins on the non-pin grid is broken
993728  F2B          BOM             bom_ignore value is <<OCC_DELETED>>
994628  SIG_INTEGRITY  TRANSLATOR    Wrong thresholds are used in setup and hold measurements
994783  SIG_INTEGRITY  OTHER          ECSet maps to some nets but not others
994963  ALLEGRO_EDITOR INTERFACES    Mechanical Symbol has no refdes when importing IDX
995050  CONCEPT_HDL INFRA          Not able to package the design once upreved to 16.5 version
995431  CONCEPT_HDL ARCHIVER       Archiver fails in the BPc environment
995557  PCB_LIBRARIAN  VERIFICATION    con2con validating a full library often reports wrong execution time in rep file
995600  CONCEPT_HDL CHECKPLUS       Global signals appearing in the multiple_signames check under Checkplus
995699  APD          SHAPE          Shape fill is inconsistent.

DATE: 03-16-2012 HOTFIX VERSION: 018
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
758924  PDN_ANALYSIS PCB_STATICIRDROP IRDrop via current report with flag for over current
903166  PSPICE       FRONTENDPLUGIN Pspice > View netlist not working if .NET is assiciated with Capture
947680  PSPICE       FRONTENDPLUGIN Out file is not displayed with view output file option in Win 7
951483  CAPTURE       GEN_BOM       SYLK File format is not valid  in Excel
954330  CAPTURE       GEN_BOM       Corrupt BOM for attached design. How can we correct it ?
964000  CAPTURE       NETLIST_OTHER User Defined Footprint getting replaced by value in Other netlist
968261  CAPTURE       NETGROUPS       Refdes Control required with Netgroup blocks
968345  CAPTURE       NETGROUPS       Cannot tick in the Place Netgroup window
974894  CAPTURE       DATABASE       Capture crashes when updating part from database
977355  ALLEGRO_EDITOR DATABASE       Presence of fillets causing no such child error during add connect.
978007  ALLEGRO_EDITOR PCAD_IN       PCAD Translation failure
978382  CAPTURE       SCHEMATICS    Placing testpoint symbol causes extra junction
978522  SIG_INTEGRITY  LICENSING       Q- Is there a way to set via model option in Orcad PCB Designer Professional license?
979041  SIG_INTEGRITY  LIBRARY       Contents of model_pcbsi.ndx were constantly accumulated when doing the distribution on each time
979594  CONSTRAINT_MGR CONCEPT_HDL    Extra and incorrect information dumped in the alias conflicts reported generated from DE HD-CM Audit
981621  ALLEGRO_EDITOR DRC_CONSTR    Updating DRC fails to set Shape Out of Date after changing NetClass membership that affects spacing
983608  F2B          BOM             Generating all variant BOMs changes selected variant
983629  SIG_EXPLORER EXPORT          No exported cross section file created in directory with spaces
984218  CONCEPT_HDL INFRA          Uprev from 162 > 165 causes certain ECSets to be in an illegal conflict state which is false
984578  F2B          DDBPI          PDV and con2con crash on part having illegal data into ptf view
984768  APD          SHAPE          Dynamic shape finishing with strange void.
985346  SIP_LAYOUT    IMPORT_DATA    import netlist-in-wizard fails and crashes
985451  APD          DIE_GENERATOR die text in results in Invalid object type passed to GetPadstackLayer
986268  ALLEGRO_EDITOR GRAPHICS       Copy & Move graphics issue with OpenGL
986552  ALLEGRO_EDITOR EDIT_ETCH       The Cline is not avoided the "Route Keepout" by hug in 165. but it does in 16.3
986704  ALLEGRO_EDITOR EDIT_ETCH       PCB Editor crashes during add connect
986895  ALLEGRO_EDITOR NC             Any layer back drill issues
987309  SIP_LAYOUT    COMPONENT_COMPAR Component Compare with DIA file and Net Assignment fails on co-design die with net assignment done by scm
987339  CONCEPT_HDL INFRA          replace component inconsistent in .dcf file
987455  ALLEGRO_EDITOR DRC_CONSTR    Allegro wrongly reporting Mechanical Pin Antipad to Pin Spacing drc
987669  ALLEGRO_EDITOR DRC_CONSTR    multi-thread update DRC causes the application to crash
987843  SPIF          OTHER          Fanout vias on BOTTOM Layer are shown on TOP Layer in Allegro after routing and importing a session file from SPECCTRA.
988001  CONCEPT_HDL CONSTRAINT_MGR Cant assign Xnet to Electrical class at all and  CM crashes if Ecset is assigned to xnet
988133  SIG_INTEGRITY  OTHER          Extra pin pairs are created in Prop Delay worksheet when ECSet is assigned to diff pair
988609  SIP_LAYOUT    SYMB_EDIT_APPMOD When using the Symbol Applicatoin mode to edit a BGA the pin pitch settings are incorrect.
989078  ALLEGRO_EDITOR OTHER          Export IDF's  total thickness is not correct

DATE: 03-02-2012 HOTFIX VERSION: 017
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
867859  ALLEGRO_EDITOR SHAPE          Overlapping static and dynamic shape are out of date but display status shapes reports up to date
940856  PSPICE       ENVIRONMENT    Simsrvr crashes when opening "Edit simulation profile" window from Capture 2nd time
951657  FSP          DESIGN_SETTINGS  Support for new cpld with Qualcomm flow
961998  FSP          MODEL_EDITOR    Support for VRP and VRN as Target Pin Property
962132  FSP          DE-HDL_SCHEMATIC Symbol viewed in FSP has a different Pin sequence than in DEHDL Schematics
962380  FSP          OTHER          Differential pairs of group contiguous pin cannot be synthesized
963662  FSP          OTHER          PGA Port� does not match with the pecify Net name�
965353  FSP          OTHER          "This feature is not available" while printing PDF from Schematic or Files View.
967418  ALLEGRO_EDITOR INTERACTIV    Component gets mirrored when placed after using Reject
968403  ALLEGRO_EDITOR SHAPE          shape void element command does not work correctly
975184  PDN_ANALYSIS PCB_STATICIRDROP Fail to do static ID Drop Analysis
975674  CAPTURE       PART_EDITOR    Crash on saving an edited part with a different name, copied from another library
976704  CONCEPT_HDL INFRA          xcon and def files are not updated correctly although do hier_write
978649  CONCEPT_HDL OTHER          DEHDL crashes with highlight while cross-probing.
978722  ALLEGRO_EDITOR OTHER          ENH: Drafting text value should be same as given
978754  SIG_INTEGRITY  SIMULATION    OrCAD PCB SI is not using custom stimulus
978772  CONCEPT_HDL COPY_PROJECT    CopyProject is changing the library order in the cpm file when you rename the library name
979075  CONCEPT_HDL INFRA          e signoise.run and sigxp.run folders are getting created at cpm level on concepthdl in spb165
979451  SIP_RF       FTB             V-SiP Arch constraints not passing Front2Back for differential pair assignment
979458  CONCEPT_HDL CORE          Add port Genview Move pin on block - pin name disappears
980204  ALLEGRO_EDITOR SKILL          different output value before and after the execution of axlLayerCreateCrossSection skill function
980211  ALLEGRO_EDITOR MANUFACT       Empty Dimension Group Subclass on package symbol is corrupting the symbol when placed on board file.
980532  PDN_ANALYSIS PCB_STATICIRDROP PDN: PDNSIM_32BIT fail if no return path exist.
980584  ALLEGRO_EDITOR PADS_IN       mbs2brd crashes when translating the Mentor design to Allegro.
980721  SIP_LAYOUT    WIREBOND       import of wirebond xml file with malformation does not indicate any error in the file
980904  SIP_LAYOUT    WIREBOND       Why is min and max wire length in status window showing the same value which is not taken from the constraint settings
980933  PCB_LIBRARIAN  IMPORT_OTHER    License call failed for feature Capture version 16.500 and quantity of 1
981156  APD          GRAPHICS       The cline display remains while moving a finger.
981309  ALLEGRO_EDITOR OTHER          Change DFA code so a perfect square is an ambigious condition and uses the most conservative value
981345  SIP_LAYOUT    DEGASSING       Degassing causing strange voids.
981436  ALLEGRO_EDITOR OTHER          Unable to add cross section chart after deleting the chart with the delete command
981756  ALLEGRO_EDITOR OTHER          Associative Dimensioning: Change Text changes the Unit instead of Value
982272  ALLEGRO_EDITOR OTHER          Line Fattening is in incorrect license tier area
983231  ALLEGRO_EDITOR OTHER          Change Text in dimension Environment, is not working as desired
983736  CONCEPT_HDL CONSTRAINT_MGR Voltage Sync property is being removed from CMGR during Back annotation due to PXL annotate net enabled
983848  SIG_INTEGRITY  OTHER          Model names with a comma are not corrected
984120  ALLEGRO_EDITOR MANUFACT       Test prep crash Allego when using RMD on Existing Via column header
984283  ALLEGRO_EDITOR SHAPE          Allegro crashes when selecting a shape

DATE: 02-17-2012 HOTFIX VERSION: 016
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
840105  PCB_LIBRARIAN  USABILITY       PTF subtype is getting changed when Save As option is used in PDV
873075  PSPICE       PROBE          Decibel of FFT results are incorrect.
938744  ADW          COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property
943003  SCM          REPORTS       The dsreportgen command fails with network located project
961530  ALLEGRO_EDITOR INTERACTIV    The problem of Display measure command
962157  CONCEPT_HDL CORE          Where is the setting for enabling the Enable PSpice Simulator menu?
962206  CONSTRAINT_MGR CONCEPT_HDL    Import physical not passing all constraints from the board to frontend
968205  PSPICE       DEHDL_NETLISTER  Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.
968509  PCB_LIBRARIAN  METADATA       Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.
969450  LAYOUT       TRANSLATORS    OrCAD Layout to Allegro Translator crashes
969997  CONSTRAINT_MGR CONCEPT_HDL    ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~
971193  CONSTRAINT_MGR UI_FORMS       Copy and pasting a formula causes the application to crash on windows.
971601  CONSTRAINT_MGR CONCEPT_HDL    ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure
973398  CONCEPT_HDL OTHER          It should be not packaged with error while working the packaging process if the design has a ERROR
973859  PSPICE       ENCRYPTION    Pspice crashes with encrypted model
973938  PCB_LIBRARIAN  VERIFICATION    pc.db is missing
974540  CONCEPT_HDL CORE          Graphics updates are real slow
974791  F2B          DESIGNVARI    Variants are not back-annotating to schematic and turning to ?
974818  ALLEGRO_EDITOR NC             Backdrilling produces 0 plunges yet no errors reported.
974945  ALLEGRO_EDITOR SKILL          Why is axlPolyOperation is giving different result and not working
974946  MODEL_INTEGRIT TRANSLATION    ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology
975396  CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5
975633  ALLEGRO_EDITOR GRAPHICS       'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)
975720  ALLEGRO_EDITOR DRAFTING       Datum dimension lines not adjusting to text move
975745  ALLEGRO_EDITOR SKILL          cdsServIpc different 16.2 vs 16.5 when Allegro exits
976013  CONCEPT_HDL INFRA          Power pin connection of FPGA symbol is missing in netlist.
976058  CONCEPT_HDL COPY_PROJECT    SCM Copy project does not create the con and dcf files in tbl_1 views
976073  CONCEPT_HDL COPY_PROJECT    All the constraint data is lost in the SCM copied design
976160  CONCEPT_HDL CREFER          Cref fails due to some Caeviews error in the design
976204  ALLEGRO_EDITOR DRC_CONSTR    Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC
976448  F2B          PACKAGERXL    ERROR(SPCOPK-1069): Invalid POWER_GROUP property value
976521  ALLEGRO_EDITOR DRC_CONSTR    multi-thread update DRC causes the application to crash
976838  SIG_INTEGRITY  OTHER          Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.
977517  F2B          PACKAGERXL    Export physical fails after update to 16.5 from 16.3
977902  ALLEGRO_EDITOR DATABASE       generate module is crashing allegro
978652  ALLEGRO_EDITOR PADS_IN       PADS_IN fails with ERROR: Finished with errors.
978744  APD          DEGASSING       Some shapes will not DeGas on this design
979940  SIP_LAYOUT    OTHER          SiP Layout Leadframe autobonding with profile selection
981699  CAPTURE       HELP          Start Page still shows Hotfix 14 after installing Hotfix 15

DATE: 02-03-2012 HOTFIX VERSION: 015
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
871567  CONSTRAINT_MGR SCHEM_FTB       Ability to filter out Single Node Nets from Constraint Manager
921436  ALLEGRO_EDITOR MANUFACT       Change in 'decimal place' for new dimension changes the already placed dimension
941433  CONCEPT_HDL COPY_PROJECT    16.5 Copy Project should warn if trying to copy a 16.3 design
954375  ALLEGRO_EDITOR MANUFACT       Change dimension accuracy for few instaces of associative dimensioning
961646  PDN_ANALYSIS EMVIEWER       EMViewer Help > About shows wrong version
964912  CONCEPT_HDL COPY_PROJECT    ASA project crash after using copy project
967223  ALLEGRO_EDITOR MANUFACT       Bug:Oval slots orientation in one direction only
968865  SIP_LAYOUT    DIE_ABSTRACT_IF  load of die abstract fails due to differences between component and symbol
969485  ALLEGRO_EDITOR SHAPE          Shape does not update correctly in 16.5
970331  CONSTRAINT_MGR ANALYSIS       Impedance worksheet shows a zero value for impedance
970600  SIP_LAYOUT    SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins
970910  F2B          PACKAGERXL    Our customer has problem with pin color after pxl 16.5.
970970  SPECCTRA    FANOUT          Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.
970985  SIP_LAYOUT    OTHER          Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash
971757  CONCEPT_HDL INFRA          Crash while Saving/Packaging the Design
971923  ALLEGRO_EDITOR MANUFACT       Allow to change decimal accuracy for dimension instances
972568  CONSTRAINT_MGR UI_FORMS       Tools >Excel missing from CM
972821  CONSTRAINT_MGR CONCEPT_HDL    connectivity server warning: Unable to add property WEIGHT
973185  SCM          CONSTRAINT_MGR ASA2 block not seeing all instances in a package.
973211  ALLEGRO_EDITOR INTERFACES    IDX Object Type Change not recognized
973214  ALLEGRO_EDITOR INTERFACES    IDX import package keepout height value change assigns incorrect value
973384  CONCEPT_HDL CHECKPLUS       The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.
973514  SIG_INTEGRITY  OTHER          Mapping error when Ecset is updated to constraint manager from extracted net
973950  ALLEGRO_EDITOR SHAPE          Update to smooth crashes application
974533  SIP_LAYOUT    OTHER          Crashes in Edit > Die Properties and obviously has a setup problem.
974809  ALLEGRO_EDITOR SKILL          argument available for hiding a property with function axlDBCreatePropDictEntry is not working
976179  INSTALLATION ISR             Installation of ISR S014 to 16.5 on windows is breaking the documentation index

DATE: 01-20-2012 HOTFIX VERSION: 014
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
733285  PSPICE       SIMULATOR       Enhancement:In server-client installation use existing index file from server
941020  SIP_LAYOUT    OTHER          Soldermask enhancement
946407  CONSTRAINT_MGR TDD             When is it safe to open a 16.5 design in 16.3?
953067  CONCEPT_HDL OTHER          Variant Editor "Error/Warning messages" form is unusable
954818  CONCEPT_HDL COMP_BROWSER    Replace button turns to Add in component browser when a component replace is done on the schematic
956450  ALLEGRO_EDITOR DRC_CONSTR    Analysis always shows analysis failed in uncoupled length in some diffpairs
958259  F2B          DESIGNSYNC    ds.exe crashes on a big design when accessing the design from network drive
958395  ALLEGRO_EDITOR SHAPE          shape voids won't merge
959212  MODEL_INTEGRIT PARSE          Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.
959940  APD          AUTOVOID       Void all command gets result as no voids being generated.
960252  PCB_LIBRARIAN  CORE          Splash screen in PDV prevents showing error message
961634  PDN_ANALYSIS EMVIEWER       Cannot launch PDN EMViewer from withing PCB SI
961645  PDN_ANALYSIS EMVIEWER       Standalone EMViewer will crash when opening any result file in the form of *.emv file.
961700  ALLEGRO_EDITOR SHAPE          dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification
961733  ALLEGRO_EDITOR SKILL          Allegro crashes.  Appears to have a memory leak.
961758  ALLEGRO_EDITOR DRC_CONSTR    DFA check produces no DRC when the dfa bounds are not a rectangle.
961887  CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM
962552  APD          EDIT_ETCH       BUG:APD crashing when we try to slideget information but move works fine
962869  CAPTURE       STABILITY       Capture crashes after RMB click on rotated parallel wires
963232  CAPTURE       MACRO          Macros not being played in Windows7
963300  ALLEGRO_EDITOR DATABASE       Create > Module crashes in 16.5 but not in 16.3
963651  CONSTRAINT_MGR CONCEPT_HDL    ECsets are renamed after packaging on linux
963663  CONSTRAINT_MGR ANALYSIS       Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design
963715  SIG_INTEGRITY  OTHER          Application only adds the bottom conductor thickness for the via z-axis length
964068  ALLEGRO_EDITOR INTERACTIV    Allegro crash when using move alt sym mirror alt sym...
964267  CIS          PART_MANAGER    Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs
964597  ADW          LRM             Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)
966148  APD          INTERFACES    Character Limit for DIE Files (*.die) Import
966416  F2B          PACKAGERXL    Cannot package this design
966421  CONCEPT_HDL CORE          DEHDL Crash when applying property on components in duplicated blocks
966693  CONCEPT_HDL CORE          DEHDL crashes when doing model assignment if CM is open
966795  ADW          ROLLBACK       rollback utility does not honor -product option from command line
967089  SIG_INTEGRITY  OTHER          Matchgroups created by ECSet not deleted when ECset is removed from object.
967222  ALLEGRO_EDITOR OTHER          PDF export is leaving data off the drawing
967240  SIP_LAYOUT    WIREBOND       Change default bond fingers selected on multi-site leads during "bond to leads" program
967297  ALLEGRO_EDITOR OTHER          Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.
967576  CONCEPT_HDL CREFER          Occurrence location property values do not appear in flattened schematic generated by CreferHDL
968096  ALLEGRO_EDITOR DRC_CONSTR    Mechanical Pin to conductor spacing is not followed.
968222  SIP_LAYOUT    DIE_EDITOR    die pin loses IC net for a co-design die with multiple ports within IO-cell
968358  CIS          PART_MANAGER    Capture crash on removing a part from subgroup in part manager
969594  CONCEPT_HDL CORE          The dcf file is not updated with schematic changes

DATE: 12-16-2011 HOTFIX VERSION: 013
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
875695  SIG_EXPLORER INTERACTIV    Enforce Causality check box doesn't work.
927148  CAPTURE       PROJECT_MANAGER  Capture crashes on creating scehmatic folder with name which already exists in design
938013  CAPTURE       NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
941409  PSPICE       PROBE          BUG : Search accuracy wrong in new cursor window
945242  SIG_INTEGRITY  SIMULATION    Unable to select "shapes" in find filter for 'show parasitic ' command
946293  CONCEPT_HDL ARCHIVER       Archiver hangs if there is a whitespace at the end of the path of cref.dat
946770  CONCEPT_HDL CORE          iew Design� function is missing in Windows Mode after reseting the menus.
950994  CAPTURE       NETGROUPS       Problem in expanding the netgroup in Auto Connect to Bus function
953530  SIG_INTEGRITY  GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
953713  CONCEPT_HDL PAGE_MGMT       Random page replacement/duplication in block
953917  CONCEPT_HDL ARCHIVER       archcore should handle errors correctly
953971  ALLEGRO_EDITOR MANUFACT       NC Drill files not generated correctly when using the option "eparate files for plated/nonplatedholes�
954400  CAPTURE       NETGROUPS       BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.
954498  SCM          B2F             SCM crashes when importing physical
954623  ALLEGRO_EDITOR EDIT_ETCH       Unable to complete connection with Add Connect - related to soldermask to cline check?
954894  ALLEGRO_EDITOR MANUFACT       Dimensions disappear when opening database in v16.5 from v16.3
955029  CONCEPT_HDL CORE          custom text font size not recognized in symbol view
955133  SIG_INTEGRITY  FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
955290  CAPTURE       DRC             Description for UPD0014 missing in the Browse DRC markers window
955299  ALLEGRO_EDITOR DRC_CONSTR    drc text to smd pin does not work any more on this database in 16.3 S039
955338  CONCEPT_HDL CHECKPLUS       Need to change PART_NAME
955447  SIG_EXPLORER OTHER          Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL
955740  SIG_INTEGRITY  GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
955749  ALLEGRO_EDITOR MANUFACT       show element Info shows symbol dimensions on incorrect subclass
955912  ALLEGRO_EDITOR OTHER          Shapes with voids that are exported to PDF have gray filled area over the void
956129  CONCEPT_HDL INFRA          DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
956373  ALLEGRO_EDITOR NC             drawing name doesn't display in the log file
956393  CAPTURE       PROJECT_MANAGER  "GENERAL" and "TYPE" tabs are missing from "Properties" dialogue box.
956448  PSPICE       MODELEDITOR    Can not generate a DEHDL symbol from Model Editor, because no Capture license found
956456  CAPTURE       NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined
956489  ALLEGRO_EDITOR MANUFACT       dimensions lost when symbol with diemnsions attached to symbol origin placed on board
956603  CONCEPT_HDL OTHER          Part Manager "has stopped working" after changing a component
956751  ALLEGRO_EDITOR ARTWORK       Import Gerber command does not work correctly
956847  PCB_LIBRARIAN  METADATA       PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
956987  CAPTURE       OTHER          Find from "Search toolbar" doesn't gives complete results
956996  CONCEPT_HDL INFRA          Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
957009  CAPTURE       NETLIST_OTHER Problem getting database property in Mentor PADS PCB netlist
957137  APD          DXF_IF          DXF out  command dose not work correctly.
957167  APD          GRAPHICS       Highlighting for Static shape with display_nohilitefont environment variable.
957232  SIG_INTEGRITY  OTHER          Allegro crash during Model Assignment.
957267  CONCEPT_HDL INFRA          Packager Error after Import Design
957866  SIP_LAYOUT    DATABASE       Cavity outline is not getting deleted from symbol file
958010  ALLEGRO_EDITOR REPORTS       Wants the ability to extract "Batch"  reports from Partition ".dpf" files.
958252  ALLEGRO_EDITOR TESTPREP       Resequence testprep with the option - Delete probes too close crashes the design
958253  ALLEGRO_EDITOR REPORTS       Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
958433  ALLEGRO_EDITOR DRC_CONSTR    False embedded component DRCs
958753  ALLEGRO_EDITOR SHAPE          Dynamic shape is getting corrupted in 16.5
959011  ALLEGRO_EDITOR OTHER          copy problem of via and cline
959101  ALLEGRO_EDITOR EXTRACT       Using extracta with excluding Thermal reliefs
959253  CONCEPT_HDL INFRA          Design will not open
959299  APD          MODULES       Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
959884  CONCEPT_HDL INFRA          Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
959909  ALLEGRO_EDITOR SCHEM_FTB       Site level propflow.txt file is ignored property is transferred
960067  SIP_LAYOUT    PLATING_BAR    Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
960126  SIG_EXPLORER EXTRACTTOP    Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
960143  SIG_INTEGRITY  GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
961349  CONCEPT_HDL HDLDIRECT       Motorola designs have broken connectivity compared to 16.3
961816  ALLEGRO_EDITOR INTERFACES    Normal Export > DXF fails and offsets  the pins of the BGA symbol
962519  SIP_LAYOUT    WIREBOND       Align option doesn't work for wb_tackpoint fingers

DATE: 11-30-2011 HOTFIX VERSION: 012
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
959581  CAPTURE       NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats

DATE: 11-18-2011 HOTFIX VERSION: 011
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
735439  PCB_LIBRARIAN  CORE          PDV Moving line-dot pinshapes by arrow keys breaks the pinshape
894815  CONCEPT_HDL COMP_BROWSER    Why does genlibmetadata command give 'Aborted $PROG' Message?
903073  ADW          COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
909919  CONCEPT_HDL OTHER          Why is the PublishPDF UNIX command line looking for "true" script?
911561  CAPTURE       CORRUPT_DESIGN Capture crashes on trying to save the design.
919579  CAPTURE       PRINT/PLOT/OUTPU Print mode be selected based on schematic mode
921247  CONCEPT_HDL COMP_BROWSER    genlibmetadata.bat file does not have err defined
925182  CAPTURE       PROJECT_MANAGER  ENH: Feature to run update cache on all the parts in design cache at once.
926858  CONCEPT_HDL CORE          Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows
927657  CAPTURE       NETGROUPS       Enhancement: Placement of netgroup definitions under design cache list
934684  ALLEGRO_EDITOR MANUFACT       The relation between the linear dimension and the symbol breaks.
935836  SCM          SCHGEN          ASA crashes when generating Flat Document Schematic
937165  SCM          SCHGEN          Can't generate Schematic
937292  CAPTURE       GENERAL       Memory usage keeps on growing and finally gets exhausted while search
937322  CONCEPT_HDL CORE          Master.tag file alters the sequence of the files and Genview fails
939135  CONCEPT_HDL CORE          Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License
940373  CAPTURE       TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup
940547  TDA          CORE          ERROR(SPDWSD-69): highspeed cannot be checked in
940607  SIG_EXPLORER OTHER          Inconsistancy in License usage for opening sigxp -orcad
940790  F2B          PACKAGERXL    User doesn't want to display pin numbers after Export Physical 16.5.
940944  SIG_EXPLORER OTHER          Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq
941354  CAPTURE       NETGROUPS       Enhancement: Option to rename the unnamed NetGroups
941455  ALLEGRO_EDITOR MANUFACT       The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.
941863  ALLEGRO_EDITOR EDIT_ETCH       Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script
941881  CONCEPT_HDL COMP_BROWSER    How can I suppress the dialog from universalbrowser -genlibindex?
942474  CAPTURE       NETGROUPS       NetGroup member type of last added member must be remembered by Capture
942522  CAPTURE       GEN_BOM       Export in excel check mark doesn't invoked BOM in Excel
942557  PCB_LIBRARIAN  EXPORT_OTHER    PDV Export to Capture crash
942569  ALLEGRO_EDITOR MANUFACT       Dimension  move and change  text deletes leaderless balloon
942573  ALLEGRO_EDITOR MANUFACT       Balloon type parameter  has no effect on leaderless balloon.
942613  CONCEPT_HDL CORE          Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type.  .xcon not recongnised
943032  SCM          OTHER          ASA is not passing the correct reuse_module name to Allegro PCB layout.
943401  CAPTURE       NETGROUPS       Alphabetical ordering of NetGroups in Place NetGroup
944006  ALLEGRO_EDITOR EDIT_ETCH       Vias added to shapes behave differently
944367  CONCEPT_HDL OTHER          Too late to do Model Assingment in conceptHDL 16.5
944788  ALLEGRO_EDITOR GRAPHICS       Oblong Pad shows unexpected lines
945221  CONSTRAINT_MGR RETAIN_CNS    CM Conflict Resolution fails on more complex designs using ECSets and constraints
946270  ALLEGRO_EDITOR PLACEMENT       The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5
946350  F2B          DESIGNVARI    Variant Editor rename function removes all components
946380  F2B          DESIGNVARI    Some VARIANTX properties are hard some soft - why?
946419  SIG_INTEGRITY  SIMULATION    Cannot select component on BoardModel for controller in bus setup form
946458  SCM          SCHGEN          Schematic generator adding an unnecessary page
947667  ALLEGRO_EDITOR PADS_IN       Need support for PADS-POWERPCB-V9.3-BASIC
947789  ALLEGRO_EDITOR MENTOR          mbs2brd crashes during translation on the attached design.
948110  CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM
950970  ALLEGRO_EDITOR MANUFACT       Unable to generate artwork, dbdoctor fails to fix errors.
951901  ALLEGRO_EDITOR EDIT_ETCH       In 16.5 add connect to same net is shoved
951919  ALLEGRO_EDITOR OTHER          Exported package symbol soldermask and pastemask padstack locations not the same as original
951926  CONSTRAINT_MGR OTHER          What is MaestroNotifyNotSetReport.txt file?
951939  F2B          PACKAGERXL    Uprev to 16.5 is changing refdes for some pages
951983  CONCEPT_HDL INFRA          Problems converting an Allegro design from 16.3 to 16.5
952057  SCM          PACKAGER       Export Physical does not works correctly from SCM
952217  ALLEGRO_EDITOR GRAPHICS       crash when opening 3d viewer in PCB Editor
952634  CONCEPT_HDL CHECKPLUS       Checkplus logical rule fails on a design which packages fine in 16.5
953018  APD          REPORTS       Shape affects Package Report result.
953337  ALLEGRO_EDITOR OTHER          Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.
953827  ALLEGRO_EDITOR EDIT_ETCH       Snake Breakout function crashed Allegro
953918  GRE          CORE          GRE cannot route second and third row of pad in die symbol.
954055  CONCEPT_HDL CREFER          Crefer fails with UNC install path
954920  SIG_INTEGRITY  CIRCUIT_BUILDER  Each neighbor crosstalk simulation crashes or returns blank report

DATE: 11-7-2011 HOTFIX VERSION: 010
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
658866  ALLEGRO_EDITOR EDIT_ETCH       enhancement option - so that Sliding a via inside a pad does not create a cline
928624  ALLEGRO_EDITOR GRAPHICS       Layer visibility control for 3D Viewer
934991  SPECCTRA    LICENSING       Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile
938073  ALLEGRO_EDITOR PLOTTING       Plot Page size A0 and A1 with problem
938128  ALLEGRO_EDITOR DRC_CONSTR    DRC changes when do update DRC.
938648  ALLEGRO_EDITOR GRAPHICS       Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer
940518  SIP_LAYOUT    SYMB_EDIT_APPMOD Swap pins command doesn't complete
941426  CONCEPT_HDL COPY_PROJECT    Copy Project fails - Updating opf view This can't happen!
941499  ALLEGRO_EDITOR DRAFTING       BUG

imit Tolerance isnot working for Dimensioning
941814  CONCEPT_HDL CREFER          CreferHDL crashes during ScheGen
942914  SIG_INTEGRITY  OTHER          ZAxis delay calculation
943053  ALLEGRO_EDITOR SHAPE          Modifying the Board Outline shape will cause the tool to crash
945321  SIP_LAYOUT    EXPORT_DATA    generation of a xml file from cdnsip for shrunken die
945350  ALLEGRO_EDITOR SHAPE          iPick does not work on shape boundary edit.
945449  APD          SKILL          When they create a new menu entry with skill APD crashes with next menu selection.
946390  ALLEGRO_EDITOR DRAFTING       refresh_symbol crash when trying to refresh mech sym that has dimensions
946401  APD          EXPORT_DATA    stream out gdsII results in shorting of PWR/GND nets due to elongated etch
946819  SIP_LAYOUT    DEGASSING       Shape degass command
946869  ALLEGRO_EDITOR OTHER          Allegro PDF arc representation needs cleaned up
947230  ALLEGRO_EDITOR SKILL          Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3
947603  ALLEGRO_EDITOR OTHER          Component Properties (Default or User Defined) not transferred to PDF file
950995  SIG_INTEGRITY  OTHER          Netrev fatal error when importing logic
951123  ALLEGRO_EDITOR INTERFACES    IPC fails to output drill hole info in columns 33-37
951557  CONCEPT_HDL CORE          Cannot create the entity folder for old plumbing symbol

DATE: 10-26-2011 HOTFIX VERSION: 009
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
945788  CONCEPT_HDL CORE          Some component properties on the parts are incorrectly changed after Import Sheet
945789  ADW          LRM             Some component instances are not updated by LRM even though cache ptf is updated from reference

DATE: 10-21-2011 HOTFIX VERSION: 008
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
906827  ALLEGRO_EDITOR DATABASE       Logic > Parts logic does not work correctly.
923346  CONCEPT_HDL CORE          Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
926347  ADW          COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it
929348  F2B          BOM             Warning 007: Invalid output file path name
929777  CONCEPT_HDL OTHER          Component Revision Manager gives internal error
930783  CONCEPT_HDL CORE          Painting with groups with default colors
936748  ALLEGRO_EDITOR INTERACTIV    "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
938143  ALLEGRO_EDITOR CREATE_SYM    Why is this Extra Property 'ECSET_MAPPING_ERROR
938281  SIP_RF       OTHER          export_chips creating bad data when symbol is split and contains V- V+ pins
938812  ALLEGRO_EDITOR SYMBOL          Cannot create a BSM with this DRA, errors out but does not state a reason.
939075  CAPTURE       TCL_INTERFACE Texts are getting garbled in command window
939193  F2B          PACKAGERXL    ERROR(SPCODD-439): Connectivity server is unable to load the design.
939199  CONCEPT_HDL DOC             "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)
939346  ALLEGRO_EDITOR SHAPE          Shape disappears when updating with variable shape_rki_autoclip set.
939901  CONCEPT_HDL INFRA          NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.
939918  PSPICE       PROBE          Print > Preview for output file causes Pspice crash.
940217  CONCEPT_HDL COMP_BROWSER    UCB reports 'No Symbol found for the part'
940835  CONCEPT_HDL INFRA          Desing package different after uprev to 16.5 where comp instance  propeties are lost  lost
941125  ALLEGRO_EDITOR DATABASE       Performance advisor doesn't skip non plated slot padstacks
941876  SIG_INTEGRITY  OTHER          Illegal model name cause pxl fail in 16.3
942210  SCM          OTHER          Is the Project File argument is being correctly passed?
942274  CAPTURE       PROJECT_MANAGER  Crash on renaming a Design Cache part in Project Manage after doing replace cache
942839  ALLEGRO_EDITOR GRAPHICS       Graphics Issue- Pads are not visible
943055  ALLEGRO_EDITOR SKILL          axlDBCreatePropDictEntry causes application to crash

DATE: 10-21-2011 HOTFIX VERSION: 007
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
841096  APD          WIREBOND       Function required which to check wire not in die pad center.
903263  CAPTURE       SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
906692  ADW          LRM             LRM window is always in front when opening a project
912942  APD          WIREBOND       constraint driven wire bonding
912951  CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems
915178  SIP_LAYOUT    DIE_STACK_EDITOR Die Pad names changing when updating Die in a design
917887  PCB_LIBRARIAN  VERIFICATION    Part should not be released if the alt_symbols has errors
923315  SIG_INTEGRITY  GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure
927382  CONCEPT_HDL CHECKPLUS       'Verify Symbol' forces the use of 'Concept_HDL_Studio' license
927664  CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp
930152  CAPTURE       NETGROUPS       Scalar net names when being connected to net group overlap when connections are made one by one
930180  CIS          LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation
930188  CAPTURE       DATABASE       Capture 16.5 crashes in being re-invoked.
930541  CAPTURE       NETGROUPS       NETGROUP element renaming doesn' renames the associated net ?
930866  PDN_ANALYSIS SETUP          OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
930926  ALLEGRO_EDITOR GRAPHICS       Via and Holes not visible eventhough set to Visible in Color form
931274  ALLEGRO_EDITOR DRC_CONSTR    Negative Plane Islands waived DRCs reappear after performing update DRC.
932091  CONCEPT_HDL CORE          Prop attached to SIG_NAME property
932255  ALLEGRO_EDITOR GRAPHICS       Change in Zoom level makes arc segment to disappear
932292  ADW          LRM             LRM crashes during Update operation on a customer design
932639  SIG_INTEGRITY  OTHER          Add Connect command hangs for about 14 seconds and then returns.
932704  APD          DEGASSING       Shape > Degass never finishes on large GND plane
932871  APD          GRAPHICS       could not see cursor as infinite
932882  CAPTURE       SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
932969  CONCEPT_HDL CORE          ConceptHDL crashes when you save the design in 165 > hotfix #05
933024  CAPTURE       NETGROUPS       Naming restrictions for NetGroup members
933145  F2B          PACKAGERXL    Add Subdesign list is truncated in Force SubDesign Design Name pulldown
933214  APD          ARTWORK       Film area report is larger when fillets are removed
933356  CONCEPT_HDL CORE          Net prop display size become 0 if it was attached to SIG_NAME prop.
933532  ALLEGRO_EDITOR COLOR          Bad color assign and initialisation during creation of new subclass
933549  ALLEGRO_EDITOR OTHER          Chart text missing in export PDF file.
934008  ALLEGRO_EDITOR REFRESH       refresh symbol updates symbol text to some unexpected values
934031  ALLEGRO_EDITOR DRC_CONSTR    Bug : Update DRC removes Waived status for some DRCs
934087  CONCEPT_HDL CORE          Opening DEHDL and Model Assignment before design loads causes crash
934396  CAPTURE       SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.
934533  F2B          DESIGNVARI    The Variant Editor errors are not written to the variants.lst file
934811  SIP_LAYOUT    UI_FORMS       CDNSIP should not hang if contraction value in z-copy command is out-of-bound
934909  SCM          UI             Require support for running script on loading a design in SCM
935632  CAPTURE       SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.
935794  ALLEGRO_EDITOR SHAPE          BUG:Shape not filled in 16.5 but it does in 16.3
935988  ALLEGRO_EDITOR INTERFACES    When attempting to downrev this 16.5 design to 16.3 the tool will crash
936056  ALLEGRO_EDITOR DRC_CONSTR    place_manual crash while moving mirrrored symbol
936098  ALLEGRO_EDITOR SKILL          axlDBCreateCloseShape does not work correctly.
936212  ALLEGRO_EDITOR INTERFACES    DXF not created if Blocks created for Symbol and padstack
936797  CONCEPT_HDL COPY_PROJECT    Copy Project crash
936808  ALLEGRO_EDITOR DATABASE       Allegro crash replace mechanical symbol
936853  CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM
937087  CIS          DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
937173  CAPTURE       OTHER          Wrong license information "UNLICENSED" in Capture >> Help >> About
937290  APD          PLATING_BAR    Plating Bar checks does not recognize connection made through etchback through shape.
937411  ALLEGRO_EDITOR DATABASE       downrev_library  reading from one directory and writing to another hangs the command.
938235  SIP_LAYOUT    STREAM_IF       Die Orientation is not correct after importing a stream file.
938273  ALLEGRO_EDITOR OTHER          PDF export is is not opening viewer with ads_sdlog variable set

DATE: 09-16-2011 HOTFIX VERSION: 006
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
820131  CONCEPT_HDL OTHER          Moving symbols to other page will make Allegro components unplaced because logical_path changed.
863860  CONSTRAINT_MGR SCHEM_FTB       CM should display or Local Interface and Global nets to help defining low level constraints
919822  TDA          CORE          Cannot configure LDAP to only list the login name
922907  ADW          TDA             ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error
924322  ADW          COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results
924448  F2B          DESIGNVARI    Design does not complete variant annotation
925584  CONSTRAINT_MGR SCHEM_FTB       16.3 upreved Design passes the SLOT/Function Properties to PCB
927102  ALLEGRO_EDITOR OTHER          Question of Conductor Detailed Length Report
927104  F2B          DESIGNVARI    Tools > Annotate variants crashes when there are ASCII characters in the property values
927142  F2B          DESIGNVARI    Incorrect pop up asking while executing variant editor from the command line
927166  CAPTURE       NETLIST_ALLEGRO  ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets
927410  ALLEGRO_EDITOR DATABASE       ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
927475  CONCEPT_HDL CORE          About forcereset command of nconcepthdl
927498  CONCEPT_HDL CORE          Pin_Name starting with minus causes incorrect behavior for $PN display
927608  ALLEGRO_EDITOR PADS_IN       Import PADs fails with error message: Failed to close the Allegro database
927637  SCM          CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.
928429  SIG_INTEGRITY  OTHER          Request - Package Wizard to work in PCB SI.
928483  ALLEGRO_EDITOR DRC_CONSTR    Running Update DRC removes Via List DRC Error when via is actually not in the list
928738  PSPICE       PROBE          Y-axis grid settings for multiple plots
928748  PSPICE       PROBE          Cursor width settings not saved
928779  CONCEPT_HDL CORE          Error (1053) occurs on a copied part in SPB165 release
928838  CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.5
928885  SIG_EXPLORER EXTRACTTOP    PCB SI crashes when extracting a net from Probe
929284  CONCEPT_HDL ARCHIVER       archive does not create a zip file
929542  SIP_LAYOUT    DIE_ABSTRACT_IF  net issue of multiple ports of co-design die in SiP
929656  ALLEGRO_EDITOR PADS_IN       PADS translation fails with Microsoft Visual C++ Runtime Library error
930063  ALLEGRO_EDITOR TESTPREP       Test prep crash Allego when it can not create pin escape
930217  CAPTURE       NETGROUPS       Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
930355  SIP_LAYOUT    WIREBOND       about "wirebond add nonstandard" command
930607  APD          OTHER          Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.
930646  ALLEGRO_EDITOR DRAFTING       Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well
930894  CAPTURE       TCL_INTERFACE PDF export doesn't  creates property file if some symbols are used in page name/folder name
930944  ALLEGRO_EDITOR OTHER          Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked
930978  ALLEGRO_EDITOR SCHEM_FTB       3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
931248  ALLEGRO_EDITOR DRC_CONSTR    Match Group was removed if member nets became xnets.
931278  CONCEPT_HDL INFRA          $PN gets copied when upreving design from 16.2 to 16.5 version
931349  CONCEPT_HDL COMP_BROWSER    DEHDL craches and corrupts connectivity file when using Modify command extensivly.

DATE: 08-31-2011 HOTFIX VERSION: 005
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
825848  ALLEGRO_EDITOR SHAPE          Shape not filled when edges from 2 RKO shapes touch around mouting hole
837723  CAPTURE       PROPERTY_EDITOR  Occurrences of external design not related to current root should not show
891079  CONCEPT_HDL CORE          DEHDL crashes with large number of commands in Winodws mode
910908  SIG_EXPLORER OTHER          Cannot open top if Tx AMI dll name contain more than 2 dot.
914036  CAPTURE       LIBRARY       ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.
914679  ALLEGRO_EDITOR INTERACTIV    Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs
914870  MODEL_INTEGRIT OTHER          mergedml fails to merger 2 DML files from the model integrity
915645  ALLEGRO_EDITOR MANUFACT       Allow the user to place the cross-section chart at a desired location
915653  ALLEGRO_EDITOR INTERACTIV    unable to delete non-etch shape
915711  ALLEGRO_EDITOR MANUFACT       dimensioning tolerancing by limit not working
916321  CAPTURE       GEN_BOM       letter limitation in include file
916907  CAPTURE       SCHEMATICS    uto Connect to Bus� should place the wire through non-connectivity objects
920327  CONSTRAINT_MGR ANALYSIS       The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.
920753  ALLEGRO_EDITOR GRAPHICS       If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.
921097  ALLEGRO_EDITOR GRAPHICS       Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set
921226  ALLEGRO_EDITOR DRAFTING       Unable to select Package Geometry class when dimensioning in the symbol editor.
921623  ALLEGRO_EDITOR GRAPHICS       Bug : Symbol not visible when zoomed in 16.5 S002
921891  ALLEGRO_EDITOR DRAFTING       dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions
921937  ALLEGRO_EDITOR COLOR          Padstacks with shape symbol are not showing correctly
922066  CONSTRAINT_MGR ANALYSIS       Custom measurement Actual not being cleared when layout changes.
922117  PSPICE       PROBE          Label colors are not correct in Probe
922519  ALLEGRO_EDITOR SKILL          add_bviaarray command fails for some clines but not all
923224  ALLEGRO_EDITOR GRAPHICS       Thermal flash Display problem in Allegro v16.5 Hotfix S002
923286  CAPTURE       DRC             DRC markers not reported for undefined RefDes
923362  ALLEGRO_EDITOR PLOTTING       Print to Postscript file not correct in 16.5
923416  ALLEGRO_EDITOR PAD_EDITOR    Pad Designer crash on clicking on the Arrow before Soldermask_top
923507  CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)
923910  CIS          PART_MANAGER    Copy & Paste operation from Part Manager copies properties only to first section of the part.
923913  CAPTURE       PROJECT_MANAGER  Capture runs slow on attached design
923937  CONCEPT_HDL CORE          Back annotation time significantly increased with the metadata generation on
923949  ALLEGRO_EDITOR INTERFACES    Incremental DXF_IN gives 'Invalid subclass' error
924458  SCM          OTHER          Project > Export > Schematics crashes
924621  ALLEGRO_EDITOR SHAPE          Dynamic shapes are disappearing upon updating them to smooth.
925193  SIG_INTEGRITY  FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect
925195  ALLEGRO_EDITOR DRC_CONSTR    Incorrect pin to shape DRC error
925338  CONCEPT_HDL CORE          This application has requested the Runtime to terminate it in an unusual way
925435  CAPTURE       TCL_INTERFACE Capture crashes if ave design as UPPERCASE� option is disabled.
925530  SIG_INTEGRITY  OTHER          Why the single line impedance value for Top and Bottom layers are different for this design?
925864  ALLEGRO_EDITOR DRAFTING       Ability to add dimensioning to different CLASS/SUBCLASS
925976  ALLEGRO_EDITOR MENTOR          mbs2brd fails to import data
926409  SIP_LAYOUT    DRAFTING       Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.
926443  CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.
926503  CAPTURE       GENERAL       Memory leak Capture/Pspice
926553  CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet
926691  ALLEGRO_EDITOR OTHER          Crash while Importing Technology File in CM, with Overwrite Constraints.
926887  CONSTRAINT_MGR CONCEPT_HDL    Pin pairs lost after Export Physical
927159  CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''

DATE: 08-19-2011 HOTFIX VERSION: 004
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
785417  CONCEPT_HDL COPY_PROJECT    copyprojectui crashes with a Windows runtime error
851044  CAPTURE       GEN_BOM       "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.
868216  PSPICE       MODELEDITOR    Encryption of subckt names, internal nodes, comments
870247  PSPICE       SIMULATOR       Encrypt a model and simulate it, info about inside nodes being dumped in the probe file
877091  CAPTURE       SCHEMATICS    Save JPEG, GIF, PNG and other image formats in the database in its compressed form
894059  CAPTURE       OTHER          Enhancement: Adding column in edit>browse>parts window
895902  RF_PCB       OTHER          Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
895919  RF_PCB       OTHER          Round trip Allegro to ADS to Allegro requirement
903102  ALLEGRO_EDITOR OTHER          Zcopy shape command for cline seems not to work correctly.
905562  SIG_INTEGRITY  SIGWAVE       Noise margin seems not to be measured correctly with Eye Measure function.
909469  SCM          TABLE          ASA crashes when opening project
909595  APD          LOGIC          Inconsistency between export die text out and show element after pin swap
911123  CONCEPT_HDL CORE          16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152
911569  CAPTURE       EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?
915657  ALLEGRO_EDITOR OTHER          Allegro PDF Publisher  Mirror capability
915755  CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP
916062  CAPTURE       GENERAL       Auto Wire Crashes Capture
916820  F2B          OTHER          RF create netlist with problem
917967  ALLEGRO_EDITOR REFRESH       Update symbol resets refdes location for bottom side components only.
919343  ALLEGRO_EDITOR PLACEMENT       Place Manual is crashing the board file
919481  CONCEPT_HDL CHECKPLUS       CheckPlus isGlobal function is not working
919510  CONCEPT_HDL PAGE_MGMT       takes 10 min to insert page in DE HDL
919976  APD          DATABASE       Update Padstack to design crashed APD.
920418  SIP_LAYOUT    OTHER          SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition
920420  SIP_LAYOUT    LOGIC          SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run
920712  ALLEGRO_EDITOR ARTWORK       Program has encountered a problem ... error when creating artwork
920763  ALLEGRO_EDITOR ARTWORK       Soldermask gerber missing thru-hole pins
920976  ALLEGRO_EDITOR GRAPHICS       Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min
920993  ALLEGRO_EDITOR DRC_CONSTR    Minimum Metal Spacing Error is detected on Same Net
921727  ALLEGRO_EDITOR DRC_CONSTR    Pad Boundary causing P/P drc to adjacent symbol.
922579  CONCEPT_HDL CORE          Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
922592  CONCEPT_HDL CORE          DE-HDL does not report illegal connection when  Global Net  tied to  interface net using an Port symbol and named
922758  ALLEGRO_EDITOR DATABASE       Allegro crashes while placing second mechanical symbol with route keepin
922839  ALLEGRO_EDITOR DFA             The DFA drc display is unstable.
923293  ALLEGRO_EDITOR INTERFACES    File> Export> IDX is failing for this design while creating an empty error log.
924772  ADW          PCBCACHE       Import Sheet is not bringing in Parts used in the source pages into target cache ptf

DATE: 08-4-2011 HOTFIX VERSION: 003
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
787414  CAPTURE       PROPERTY_EDITOR  Part value can be moved on schematic if a part has been copied to a new design and not saved yet.
903898  PCB_LIBRARIAN  GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics
904287  ALLEGRO_EDITOR ARTWORK       some cline with arc is missed, when creating artwork.
904418  CHANNEL_ANALYS SIMULATION    channel analysis sim does not give valid result
905777  SIG_INTEGRITY  SIMULATION    User gets popup message that halts an analysis until it is acknowledged
906139  SIG_INTEGRITY  OTHER          Bus sim result were cleared at the next run even if no preference changed.
908680  SIG_INTEGRITY  OTHER          Extra prop delay due to resistance
909583  ALLEGRO_EDITOR SKILL          axlPolyOperation AND operation is not working correctly.
910315  ADW          LRM             Import Design with ADW causes partmgr and pxl errors
910689  CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5
911684  CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5
912343  APD          OTHER          APD crash on trying to modify the padstack
912384  PCB_LIBRARIAN  CORE          PDV Symbol Editor often freezes when moving groups objects by arrow keys
912853  APD          OTHER          Fillets lost when open in 16.3.
913586  ALLEGRO_EDITOR ARTWORK       Cannot create the drill figures in this design.
914009  ALLEGRO_EDITOR DRC_CONSTR    Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.
914110  CONCEPT_HDL OTHER          DEHDL 16.5  Uprev overides property values  on hierachical blocks
914264  F2B          OTHER          Cross Probing from DEHDL for global nets present inside block doesn highlight in PCB Editor.
914309  CONCEPT_HDL CORE          16.5 DEHDL crash on saving the user design
914558  ALLEGRO_EDITOR ARTWORK       Gerber6x00 output creates unpainted niche in a shape
914633  ALLEGRO_EDITOR ARTWORK       Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.
914634  ALLEGRO_EDITOR SKILL          IsThrough flag for a padstack is reset
914746  ALLEGRO_EDITOR DRC_CONSTR    DRC Update repeats takes longer on each successive pass.
914962  ALLEGRO_EDITOR SHAPE          Corruption with Shape filling
915583  CONCEPT_HDL CORE          performance issues in 16.5 compared to 16.3
915630  PCB_LIBRARIAN  OTHER          Error when running SI Model Interface Comparison using IBIS models
915742  CONCEPT_HDL HDLDIRECT       I get a newgenasym error and crash when trying to save the symbol
916154  SCM          NETLISTER       scm crashes when exporting physical database to allegro
916448  CAPTURE       NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors
916462  ALLEGRO_EDITOR DATABASE       Edit>Split_plane>create hangs Allgro PCB Editor
916469  ALLEGRO_EDITOR REPORTS       One Unrouted pin does not show in Unconnected Pins Report
916495  ALLEGRO_EDITOR INTERACTIV    Pick selects components from invisible (Off ) layer
916889  CAPTURE       NETGROUPS       How to change unnamed net group name?
917002  ALLEGRO_EDITOR OTHER          Allegro PDF Publisher creates extra circles not available on film
917434  APD          OTHER          Stream out GDSII has more pads in output data.
917739  CONCEPT_HDL INFRA          Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net
918187  CONSTRAINT_MGR OTHER          Missing acGetTotalEtchLength predicate.
918576  CAPTURE       DRC             Incorrect DRC is reported for visible power pins which are connected to power symbol

DATE: 07-24-2011 HOTFIX VERSION: 002
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
527444  ALLEGRO_EDITOR EDIT_ETCH       Slide command needs to be enhanced for same net spacings
583257  ALLEGRO_EDITOR EDIT_ETCH       Add Connect and slide command needs to be enhanced for same net spacings.
592956  ALLEGRO_EDITOR EDIT_ETCH       Same net traces will not push and/or shove each other.
745285  ALLEGRO_EDITOR EDIT_ETCH       Requesting a true "shove" in Route > Slide for Same net routing.
773503  CAPTURE       OTHER          Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.
774270  F2B          PACKAGERXL    Require to ignore space in Pattern setting to prevent duplicated Refdes.
799984  ALLEGRO_EDITOR INTERACTIV    Enhance the Fix command to select just cline segs
809008  CAPTURE       SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
810058  CAPTURE       SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
821133  ALLEGRO_EDITOR MANUFACT       Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format
831710  CAPTURE       SCHEMATIC_EDITOR Capture adds extra junctions to design by itself
842410  ALLEGRO_EDITOR EDIT_ETCH       Ability to slide with "Shove" for "Same Net" segments/vias.
854971  ALLEGRO_EDITOR INTERACTIV    Capability to add cline segment in a temp group
860772  ADW          PCBCACHE       Save Shopping Cart (pcbcache) is crashing component browser
867842  CAPTURE       PROJECT_MANAGER  Capture crash with 'Open File Location"
868306  CAPTURE       CONNECTIVITY    mirror vertically removes junction creates extra nets
882677  EMI          RULE_CHECK    bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
891439  ALLEGRO_EDITOR INTERACTIV    moving cline segments
893544  ALLEGRO_EDITOR INTERFACES    IPC-D-356A netlist issue with BB vias.
893765  ALLEGRO_EDITOR PARTITION       Mail command not sending out email on Linux platforms.
894390  SIP_LAYOUT    EXPORT_DATA    Generate all balls in the xml file for export to EDI's readPackage command
895933  APD          DATABASE       Update Symbol shifts the center of the Dynamic Fillet and creating DRCs
896598  ALLEGRO_EDITOR PLACEMENT       error message is misleading
897196  CIS          LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library
898598  ALLEGRO_EDITOR MENTOR          Negative planes from Mentor Board Station not being translated.
899556  ALLEGRO_EDITOR ARTWORK       Import artwork seems not to work correctly.
900501  ALLEGRO_EDITOR PLACEMENT       "Place Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5
901141  CIS          EXPLORER       Japanese character appear garbled in CIS explorer window.
901666  CAPTURE       OTHER          Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
902066  ALLEGRO_EDITOR DRC_CONSTR    Shape in Region not follow the constrains
902349  CAPTURE       LIBRARY       Capture crashes while closing library
902508  F2B          PACKAGERXL    SPB16.5 Packager-XL consumes much more memory than 16.3
902841  CAPTURE       GENERAL       Capture Start page does not show
902876  F2B          PACKAGERXL    Packager fails on the design upreved in 16.5
902959  CONCEPT_HDL HDLDIRECT       HDLDirect Error while saving design
903171  PSPICE       NETLISTER       Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?
903713  ALLEGRO_EDITOR PARTITION       Placement Replication do not work fine in the Design Partition
903799  SIP_LAYOUT    DIE_EDITOR    Disappear die pins after exiting co-design die editor
904021  ALLEGRO_EDITOR OTHER          Export PDF from SPB 16.5 produces a file not text searchable
904339  CONCEPT_HDL CORE          new design crashes using the attached CDS_SITE
904522  F2B          PACKAGERXL    Part will not package in 16.5  but packages in 16.3
904764  APD          OTHER          Enhance Scale Factor of Stream Out to support 4 decimal places
904771  ALLEGRO_EDITOR MANUFACT       Pin Number display issue.
904853  ALLEGRO_EDITOR GRAPHICS       Enhancement for showing Static shape as it was seen in 16.3
905144  CONSTRAINT_MGR ECS_APPLY       Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
905314  F2B          PACKAGERXL    Import physical causes csb corruption
905337  CONCEPT_HDL CORE          ConceptHDL crashes after Import Design process.
905533  ALLEGRO_EDITOR INTERACTIV    Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
905796  CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues
905811  CAPTURE       EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid
906118  CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.
906153  ALLEGRO_EDITOR SCRIPTS       Unable to run allegro script in batch mode on the attached board.
906182  APD          EXPORT_DATA    Modify Board Level Component Output format
906200  ALLEGRO_EDITOR DFA             Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element
906517  PSPICE       PROBE          PSpice new cursor window shows incorrect result.
906627  ADW          COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
906647  SIG_INTEGRITY  LIBRARY       lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run
906673  F2B          PACKAGERXL    Ignore the signal model validity check during packaging
906688  ADW          LRM             A copy of source design gets created in worklib of target design after 'Import Design'
906750  ALLEGRO_EDITOR PARTITION       Importing design partition removes the testpoint reference designation
906874  PSPICE       NETLISTER       Error less than 2 connections for unconnected hierarchical pin
907095  F2B          OTHER          Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
907424  ALLEGRO_EDITOR GRAPHICS       Allegro add option for pre 16.5 shape display
907490  CAPTURE       NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.
907884  SIP_LAYOUT    MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"
907885  SIG_INTEGRITY  OTHER          Matchgroup targets lost when importing netlist  to Allegro layout in HF31
907929  CAPTURE       TCL_SAMPLE    TCL command to delete a property from parts in a library is not working correctly
907933  SIG_INTEGRITY  OTHER          Single line impedence not working in OrCad PCB Professional
907963  CONCEPT_HDL CORE          Design uprev issue when moving from 16.2 to 16.5
908000  SIG_INTEGRITY  OTHER          Inconsistence z-axis delay reported on Tpoint when define at via location.
908057  CONCEPT_HDL CORE          DE HDL crash with the cut and paste of a signal name
908060  CONCEPT_HDL CORE          CTRL+LMB Option not working correctly in 16.3
908210  CAPTURE       CONNECTIVITY    Connection is being lost while dragging a component
908241  CAPTURE       DRC             DRC error column is blank in DRC markers window in 16.5
908339  RF_PCB       BE_IFF_IMPORT mechanical holes VIAFC are not at the right place
908534  SIP_LAYOUT    SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays
908535  F2B          DESIGNVARI    When I try to view my variant file the variant editor crashes
908595  APD          3D_VIEWER       Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b
908849  CAPTURE       ANNOTATE       Getting crash while annotating the attached design
908874  CONCEPT_HDL CORE          Part Manager - No Part Found error when using CCR# 775788 feature
909077  CONCEPT_HDL CORE          After packaging pin numbers remains invisible even when $PN
909104  ALLEGRO_EDITOR SYMBOL          Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.
909417  ALLEGRO_EDITOR REPORTS       "report -v upc" returns 'Segmentation fault' on Linux
909635  SIP_LAYOUT    DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
909749  ALLEGRO_EDITOR MANUFACT       Allegro Crash during dimensioning
909760  SIP_LAYOUT    MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
909861  F2B          PACKAGERXL    NetAssembler broken within the latest 16.30.031
910006  CONCEPT_HDL INFRA          Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.
910141  CAPTURE       NETGROUPS       Modify NetGroup definition does not update Offpage Connector
910340  ADW          LRM             Import design in schematic, only 1 page import,  the entire block is getting imported.
910678  SIG_INTEGRITY  OTHER          The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
910713  F2B          DESIGNVARI    Variant Editor crashes when you click web link under Physical Part Filter window.
910936  F2B          PACKAGERXL    ConceptHDL subdesign net name is inconsistent
911530  ALLEGRO_EDITOR SYMBOL          Package Symbol Wizard does not create symbol with the name given
911631  CONCEPT_HDL CORE          DEHDL crashes when opening a design
912001  ALLEGRO_EDITOR OTHER          option_licenses entries are made in allegro.ini even when not set as default
912459  F2B          BOM             BOMHDL crashes before getting to a menu
913359  APD          MANUFACTURING Package Report shows incorrect data

DATE: 06-24-2011 HOTFIX VERSION: 001
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
293005  ALLEGRO_EDITOR DATABASE       Allegro crash when attempting to move mech. symbol
298289  CIS          EXPLORER       CIS querry gives wrong results
366939  ALLEGRO_EDITOR OTHER          Cannot attach refdes on silk subclass with add text
432200  ALLEGRO_EDITOR MANUFACT       Fillets with an arc are required for Flexi designs
443447  APD          SHAPE          Shapes not following  the acute angle trim control setting.
473308  PSPICE       AA_SENS       Passing variables to lower level blocks using subparam
517556  PSPICE       AA_SENS       Advanced Analysis does not support variables being passed down the hierarchy
548143  ALLEGRO_EDITOR SHAPE          Dynamic shpe on Etch TOP will not void properly.
606959  ADW          COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart
616466  ALLEGRO_EDITOR SHAPE          Solid shapes are not getting filled
641358  SIP_LAYOUT    DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)
644122  SIP_LAYOUT    OTHER          SiP Layout - xsection -  ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor
645816  ALLEGRO_EDITOR SHAPE          Slide a cline all removes gnd shapes on board
725355  ALLEGRO_EDITOR SHAPE          User can not voided Logo correctly.
763569  CONCEPT_HDL CORE          Display status of Hide/Show unconnected pins icon in DE HDL UI
770021  CAPTURE       BACKANNOTATE    Changing pin group property after pin swap resets pin numbers
792126  CAPTURE       PROPERTY_EDITOR  Attempt to change display for occ prop resets
799014  CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write
803147  CIS          LINK_DATABASE_PA Link DB part should not change RefDes of multi package part
804240  PSPICE       DEHDL          Problem in simulation result for a multi-section split part.
809118  CAPTURE       NETLISTS       ENH to compare two schematic Capture designs
816568  ALLEGRO_EDITOR SHAPE          shape disappears when update to smooth.. State no etch
830053  CAPTURE       STABILITY       DXF export fails if schematic folder name as /
832108  ALLEGRO_EDITOR SHAPE          Shape void incorrectly.
833542  CONCEPT_HDL CORE          PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
835777  CIS          DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error
837640  CIS          GEN_BOM       date format of CIS BOM has broken macros of 16.2 in 16.3 version
844074  APD          SPECCTRA_IF    Export Router fails with memory errors.
851595  CONCEPT_HDL CORE          Pin numbers overlap on the pin and increase in size
852832  CAPTURE       BACKANNOTATE    Why is Capture crashing with Mentor back annotation?
855015  ALLEGRO_EDITOR OTHER          The rats are NOT connecting to the ends of the clines like they should be.
859883  CAPTURE       NETLISTS       ENH to compare two schematic Capture designs
866009  SIG_INTEGRITY  OTHER          Net with Pull-up/down should not be used for Diff-pair.
866830  SCM          REPORTS       Multiple lines added as separator between title block and report header instead of single line
866833  SCM          REPORTS       Extra indentation is left in the left side of the report when the Line Numbers are set to OFF
868618  SCM          IMPORTS       Block re-import does not update the docsch and sch view
873402  SIP_LAYOUT    LOGIC          pin swap for co-design die in SiP
874010  SIG_INTEGRITY  OTHER          PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.
874400  ALLEGRO_EDITOR INTERACTIV    Flip mode issue with move command
874966  ALLEGRO_EDITOR INTERFACES    Placed mechanical component do not get Ref Des or part number in IDF file
875709  ALLEGRO_EDITOR REPORTS       Film area report generated incorrect data at l1
876275  CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net
879361  SCM          UI             SCM crashes when opening project
879496  CONCEPT_HDL OTHER          Customer wants to have the tabulation� key as separator in HDL BOM.
879514  PSPICE       AA_MC          Monte Carlo to handle equation as comp VALUE.
881845  ALLEGRO_EDITOR SHAPE          Delete island deletes complete shape
882413  PDN_ANALYSIS PCB_PI          PDN Analysis should support routed power nets
882427  PDN_ANALYSIS PCB_PI          PDN Analysis target impedance should have a variable multiplier
882567  SIG_INTEGRITY  OTHER          PCB SI crash if boolean type prop was specified to VARIANT env.
882644  ALLEGRO_EDITOR PLACEMENT       PCB  Place Replicate Function automatically match Enhancement
883164  ALLEGRO_EDITOR INTERACTIV    Vias marked fanout moves away from position when moving component
883224  SIG_INTEGRITY  SIMULATION    crash while reflection simulation from Constraint Manager
883760  PCB_LIBRARIAN  METADATA       Incorrectly formatted revision.dat file in the metadata folder
885391  SIG_INTEGRITY  SIMULATION    RLGC data sampling algorithm and w-element interpolation.
885849  ALLEGRO_EDITOR MANUFACT       Silkscreen Audit cannot find Solder mask for the text string
885996  SIG_INTEGRITY  OTHER          The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations
886090  ALLEGRO_EDITOR INTERACTIV    Add Arc w/Radius does not snap to grid
887180  CAPTURE       SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses
887442  APD          SHAPE          Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.
887578  SCM          AUTO_UI       Component Replace pops-up the DSPANE-204 Message
887926  SIG_INTEGRITY  GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.
888414  SIG_EXPLORER OTHER          View Trace Parameter display the thickness of dielectric incorrectly.
888600  CONCEPT_HDL CREFER          Cross References not added to Schegen schematic
888679  SIP_LAYOUT    SHAPE          Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.
888804  ALLEGRO_EDITOR OTHER          Fillet will become static shape after import from partition board.
888945  CONCEPT_HDL OTHER          unplaced component after placing module
889222  ALLEGRO_EDITOR SHAPE          Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.
889365  SIG_INTEGRITY  GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3
889404  ALLEGRO_EDITOR OTHER          Incorrect pad size for Top conductor padstack written to column 59-62.
889426  CONCEPT_HDL CHECKPLUS       CheckPlus does not find single node net
889636  ALLEGRO_EDITOR MANUFACT       Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form
891235  F2B          PACKAGERXL    Packager crashes without creating a pxl.log file
891292  ALLEGRO_EDITOR SHAPE          arc routing causes weird undesireable shape fill performance
891856  ALLEGRO_EDITOR EDIT_ETCH       crash when sliding diff pairs
892375  ALLEGRO_EDITOR PLACEMENT       Place Replicate Update disband other groups, irrespective Fixed property added or not.
892455  ALLEGRO_EDITOR SYMBOL          Why the overlapping pins are not reported with DRC?
892541  SIG_EXPLORER OTHER          Export/Import layerstack through the technology file is changing the layer thickness
892766  APD          WIREBOND       Excuting Finger moving cannot push aside finger to move with together by shove all mode
892907  ALLEGRO_EDITOR DRC_CONSTR    DRC not reported for etch_turn_under_pin violations
892963  ALLEGRO_EDITOR SKILL          Bad shape boundary created after axlPolyOperation 'OR
892964  SIP_LAYOUT    LOGIC          Request that Edit Parts List use Dashes "-".
893295  APD          WIREBOND       Why move wirebond command does not shove wirebonds? This result in drcs.
893706  CONSTRAINT_MGR OTHER          On line DRC hangs on partitioned board
893743  APD          EDIT_ETCH       Route behavior when spanning pads not as expected.
893783  SIP_LAYOUT    OTHER          Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation
894456  ALLEGRO_EDITOR REPORTS       Request Net names be added to Propagation delay lines of the DRC report.
894499  SIG_INTEGRITY  LIBRARY       Tool crashes when moving a cline or selecting the Info icon with OpenGL on.
894582  APD          SHAPE          When making a dynamic xhatch Via shapes surrounding are abnormal.
895542  SIP_LAYOUT    WIREBOND       SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON
895591  ALLEGRO_EDITOR PCAD_IN       Importing PCAD file fails to get to the point where we can map layers
895757  APD          ARTWORK       Import Gerber command could not be imported Gerber data
895964  CONCEPT_HDL CHECKPLUS       The CheckPlus command getFileSubstrings is not working correctly
896428  SCM          UI             Changed Ref Des value not maintained in DEHDL block when part is replaced
896655  CAPTURE       EDIF          Import/Export Design of Hierarcy design with OrCAD Capture
896846  CAPTURE       IMPORT/EXPORT Import edif2cap and capture is crashing
897155  ALLEGRO_EDITOR REPORTS       Copper coverage in L2 and L7 looks like the same but film area report had large gap.
897654  CAPTURE       EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.
899344  RF_PCB       BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing
899629  CONSTRAINT_MGR OTHER          ECset for Total Etch Lenght is not present in OrCAD Prof
900175  CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
900481  CONCEPT_HDL CORE          Genview creates a larger symbol without taking the no. of pin in consideration
900813  ALLEGRO_EDITOR DRC_CONSTR    With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.
900905  PSPICE       STABILITY       Simsrvr crash and RPC Server unavailable error while running simulation.
901783  CONCEPT_HDL CORE          CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5
901909  APD          EXPORT_DATA    The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong
901987  CONCEPT_HDL OTHER          SPB16.5 zoom fit does not center the page while ploting the schematic page
902133  CIS          OTHER          The visible part property value are being shown very distant from part graphics on schematic
902166  SPECCTRA    ROUTE          Specctra crashes when reading in "bestsave.w" file
902170  ALLEGRO_EDITOR DATABASE       Diffpair Issues with OrCad PCB Designer Professional
902177  CONSTRAINT_MGR CONCEPT_HDL    Option to view the layer thickness in CM worksheet through worksheet customization
902463  ALLEGRO_EDITOR INTERACTIV    APD crashes when we click ( show element ) on certain components
902621  CONCEPT_HDL OTHER          Design Differences (vdd) Crashes
902909  APD          WIREBOND       die to die wirebond crash
902933  ALLEGRO_EDITOR PADS_IN       Pads_in fails while reading PADS ASCII file body
903284  PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline
903680  CONSTRAINT_MGR ECS_APPLY       Constraint Manager not passing all hiearchical member objects to a custom measurement.
904403  ALLEGRO_EDITOR DATABASE       Allegro crashes when refreshing module

jiangfux · 发表于 2015-3-25 23:23

linsky2000 发表于 2013-6-27 09:295 g J! d( }1 \0 q
https://www.eda365.com/thread-89045-1-2.html
) @% f3 X, N. @- M0 M2 }5 d' s这个贴子里有提到0 @% x" R3 L, g3 i4 `
http://dl.vmall.com/c0sfvdb4yy

嗯。能够下载，谢谢分享

mengshang · 发表于 2013-6-10 10:22

可提供下载吗

penny190 · 发表于 2013-6-10 11:14

這是原廠下載的~~自從115不提供之後~~就不知道能上傳到哪了??

killerljj · 发表于 2013-6-10 20:27

金山快盘，百度网盘都可以分享啊！

penny190 · 发表于 2013-6-11 09:59

http://pan.baidu.com/share/link? ... 3&uk=1093713990
要下載的要快喔
今天下班18:00關閉喔

amaryllis · 发表于 2013-6-11 12:28

更新了好多东西啊

wolfshiao · 发表于 2013-6-11 12:39

正在下載中,
真是太感謝大大的分享了..

mengshang · 发表于 2013-6-11 15:02

谢谢您

cxyjoe · 发表于 2013-6-15 10:55

来晚了，没有了

jinshan010 · 发表于 2013-6-15 20:32

请楼主在发一下吧，谢谢

penny190 · 发表于 2013-6-17 10:50

最後一次開放下載囉
一樣18:00 關閉喔
http://pan.baidu.com/share/link? ... 8&uk=1093713990

x68049 · 发表于 2013-6-18 00:55

沒有抓到 .. 誰可以在分享一次嗎

szcs67 · 发表于 2013-6-18 17:39

能再分享下吗?

penny190 · 发表于 2013-6-19 09:37

真的是最後一次開放下載了喔
一樣18:00 關閉喔
要下載的請盡速下載
http://pan.baidu.com/share/link? ... 1&uk=1093713990

edaman · 发表于 2013-6-19 16:35

正在下载,谢谢!

帐号		自动登录	找回密码
密码			注册

SPB:Hotfix:16.50.044~wint

EDA365欢迎您登录！

浏览过的版块

推荐内容 /1