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cadence SPB 16.5下载地址（Hotfix更新至044）5 h, ^: s" m, |7 F0 N6 v2 `
! E( K( T( [( h9 \! `% P/ MCadence最新版软件SPB 16.5及其Hotfix下载链接如下：8 l. _8 f( @6 v9 L' X+ J6 D
http://dl.vmall.com/c0sfvdb4yy3 D( ~' l) h* ~, v! j# |# c
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Hotfix中只需要安装最新的版本即可。
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8 a; M' N1 v/ P3 dDATE: 06-7-2013 HOTFIX VERSION: 044
S# P$ f" ?7 L. `% X& _2 x5 y. g& x===================================================================================================================================. `# s/ o6 \; C s
CCRID PRODUCT PRODUCTLEVEL2 TITLE
8 s& ]8 J( X) B( Y! W3 {===================================================================================================================================' |& _) x; `% F+ q. Y
1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers; f5 d/ R6 J+ N
1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
" z0 D! K& ]5 l5 }7 P1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB0 \ v+ [/ s( ~# ~
1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.4 p' [$ X* `# ?4 u
1106900 concept_HDL COMP_BROWSER Component Browser peRFormance utility should honor CPM directives for include and exclude PPT, H6 `& Y( X/ v- W4 O1 R
1110323 APD DXF_IF DXF out is offsetting square discrete pads.. G8 [2 ?) d1 x
1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files( W+ h2 @+ W, \- ^% A4 c1 p
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor: m# y7 v# ~9 e8 H- E3 H( ~* b
1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.
) t3 f1 Q5 |6 N; S9 [8 d1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically
7 J, e" c9 a' r6 @1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one
; w' Q( l( f; R1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board9 B- O" b2 @- V1 d/ O" H9 S
1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5
& @9 w8 K8 L, s( h1 r1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux
( }6 R+ S7 d. I4 [( K6 u1125628 CONCEPT_HDL CORE Crash on doing save hierarchy/ {- v9 o4 W/ @
1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.
& X2 R2 m4 u3 C/ O1130945 SCM SCHGEN SCM Export Schematic does not copy all cells in the library
# G" |, `- J& f1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.
6 ~/ d7 {9 P m F1 [. j1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters
9 Y6 R( S/ [* Q& I1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP44 x' C: \. ^9 I! o6 w8 n
1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.
3 u9 f' ~" h8 o p, D# ?- H9 `1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.
/ `$ ^1 a+ \2 ~8 C, U8 k1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.
8 a& g7 k! \; q2 H/ H1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top+ f0 b; Q% ]3 K* I* m7 w2 M
1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.
& {/ X/ e7 J7 o$ S, N4 C$ t( B1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.) t+ s1 ?% W& C* d# H0 I, k
1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property5 q9 Y L! L" a) H7 ? K1 G6 P1 r
1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs
( E- B T" S' I9 E1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness
- S$ F5 i& X4 G( r5 s& m1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped
* ]* Z8 C9 {( C# d4 W& j: @1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero1 u' _$ k1 Q4 J! \, Q
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF% t, P4 X* N8 a2 @. h
1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed
Z" f0 J# M# W. }* A" R c7 a+ g1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP H$ |; C0 q% Q5 n! B3 c+ f
1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case
% I s) h& Z9 a4 I% z1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL
! g! K$ d. j8 P1 J' a1 Y0 S" L1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.
0 i1 R* `7 }' W5 r- J1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added
3 ]) e* G2 J |2 I; f; Q6 m1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps) y9 L2 R6 J" |
1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail& @6 U# e ]0 [2 E' [
1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block |
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发表于 2013-6-17 17:16
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