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本帖最后由 dsws 于 2013-7-1 20:32 编辑
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914562 allegro_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD
# Y2 F& g8 X+ n' M8 d1120397 concept_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files6 D+ l- K4 f) k/ ~/ _
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
. |0 O" V8 I k7 x( d/ \1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.
4 L' t# B7 x! H+ C; Z' a1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line- p, j3 v2 A* u2 r; ]3 S, E! E
1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.
& E& k- k3 e& s6 h* F4 d6 N1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.2 ~6 r _2 q ^* m$ l1 k
1151458 GRE CORE GRE crashes on Plan Spatial3 E5 F. u- K* M, j; k* U) j% q
1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy
8 M) b- U! [( q# H6 O+ C1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]; H1 s+ k6 T* Q5 g ]
1152475 Pspice SIMULATOR RPC server unavailable error while simulating the attached design. z& P2 I/ |' {/ D: s3 H& x
1152737 ALLEGRO_EDITOR skill dbids are removed because highlighted objects in setting the xprobe trigger5 X q/ w0 @2 P
1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.
d( u5 j' Z# P$ ^1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places0 D8 b! k. j6 P4 w" X* Y8 N w) R
1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail& D8 o( b+ m, _
1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.( G6 v6 J9 r7 e% z" K/ ?& ~/ d
1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer
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! e- R6 k/ Z0 B' Thttp://pan.baidu.com/share/link? ... 0&uk=38260382946 v1 q0 ?+ n* t, W# e
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发表于 2013-7-1 12:00
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