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本帖最后由 dsws 于 2013-7-1 20:32 编辑 : x8 f$ w; L7 y5 P* K0 E0 d5 R' \
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! u! }( q/ A9 j; f1 D# `914562 allegro_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD
( C3 y B! W- C; G# o5 i1120397 concept_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files8 t0 R4 o1 }4 ^" w4 Q
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
. A. A6 o* t6 N7 N1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.1 l; F0 V5 d- {+ \ t0 m: g) x) o, Z
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line0 \. l/ O1 u2 ^9 @& {
1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.) E& Y& X* ]6 d) c, r; }
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.
+ B2 \& `2 B; h0 @9 O. |5 W# C1151458 GRE CORE GRE crashes on Plan Spatial2 I$ j2 C3 f8 V8 [
1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy! f. J! H9 K( I. b
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]
5 U2 x. Z/ Q7 j# v1152475 Pspice SIMULATOR RPC server unavailable error while simulating the attached design
& O/ Q, B5 y# W/ u" h1152737 ALLEGRO_EDITOR skill dbids are removed because highlighted objects in setting the xprobe trigger7 X) V; S3 G- q' C: p) X5 d
1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.
$ m8 J/ v. \% V4 x0 w2 i. i1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places+ U# @8 _% E; y# g) D( j
1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
8 J5 y5 e( A: ^ b2 I9 j8 V E1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.
9 i2 R" A& Q3 `. g1 X/ w1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer
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http://pan.baidu.com/share/link? ... 0&uk=3826038294$ U2 i' W) ~1 {& m+ d! n7 i
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发表于 2013-7-1 12:00
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