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本帖最后由 dsws 于 2013-7-1 20:32 编辑
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DATE: HOTFIX VERSION: 012
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914562 allegro_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD
* J7 E0 ]1 K0 Y% i1120397 concept_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files
* m6 F2 M" R# Z+ \2 g2 t1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display( `3 Y! z" x% [6 S6 u
1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.2 ]: U" X# O. ]: g
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line" Q3 F7 \6 y6 r7 ]# m( `
1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.
: s' k7 c! H6 l# H' z9 z1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.' u, n$ t% s: @! v& S4 W& ]
1151458 GRE CORE GRE crashes on Plan Spatial! Y' r/ Q8 y4 U
1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy( O& ~* R& [# }" j1 B/ V
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268] q( ?: i! P5 v; {# D7 H
1152475 Pspice SIMULATOR RPC server unavailable error while simulating the attached design
0 d7 o; Q& w/ K$ Y% M1 W1152737 ALLEGRO_EDITOR skill dbids are removed because highlighted objects in setting the xprobe trigger
. p7 o8 U* P% m( b1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.
2 U) Q- K5 c- f2 ?; D1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places
0 f' C. P. d; K/ ^* e" |& K1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
( O5 G" M) l5 b1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.$ |9 |% P; o+ u+ e7 D
1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer, V$ c0 F" J* \- P8 c, y$ ?
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6 k/ g; R# u! _+ t, mhttp://pan.baidu.com/share/link? ... 0&uk=38260382947 ~ W- m8 D! Y2 y- A; D* s* p
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发表于 2013-7-1 12:00
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