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本帖最后由 dsws 于 2013-7-1 20:32 编辑
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0 }: E, M0 Q) _DATE: HOTFIX VERSION: 012
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# a d# d8 `! h! NCCRID PRODUCT PRODUCTLEVEL2 TITLE: i+ {0 |( a. `6 [$ E
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914562 allegro_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD" c4 J0 G. ~# R( k# ?3 A
1120397 concept_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files$ x7 ~; [; K& \& f+ R7 c3 g
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
5 G$ v. K6 U' J1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.( {1 I! b. b% E6 `7 A+ X# E! |5 `
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line
9 k% |- ^) S5 Z- d+ L9 V1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.7 Q& ]! e. g8 Y
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.
7 \/ m2 e, p- }2 O; n n" R1151458 GRE CORE GRE crashes on Plan Spatial
4 W: M* {& j' ?# ]2 {4 p1 i6 ^1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy! y5 J; j3 O% A, s5 \+ e, e
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]
/ ?6 y+ `2 `: a& \6 `1152475 Pspice SIMULATOR RPC server unavailable error while simulating the attached design
+ N' {3 R" K2 _& m6 t1152737 ALLEGRO_EDITOR skill dbids are removed because highlighted objects in setting the xprobe trigger% w5 y0 m0 F3 F0 H4 i5 u! y
1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.
}0 Z! F! F4 _# {" ?, B1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places) b! `# D) l- f
1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
4 P- B* J/ {0 p- l2 m1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off./ \8 w) A* I8 i6 z9 u% A5 h, z
1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer
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发表于 2013-7-1 12:00
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