Hotfix_SPB16.60.013_wint_1of1

hzqydq

cadence SPB16.6下载(Hotfix013已发布)

Cadence SPB16.6已经推出，需要的朋友可以点击下面的链接下载：
/ \& B5 x4 a- ]& v' `2 o$ ]4 s# chttp://dl.vmall.com/c0ych9k8m3
$ P7 l; a& ^3 O0 Z

DATE: 07-26-2013  HOTFIX VERSION: 013
===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
% K; N* k+ W( b7 G) p. u4 C, k111368 CAPTURE        CORRUPT_DESIGN   Capture - will not produce allegro netlistwith 10.0
134439 PD-COMPILE     USERDATA         caCell terminals should be top-levelterminals
186074  CIS            EXPLORER         refresh symbols from lib requires youto close CIS
" V2 k9 Z/ z5 e7 @' Z& N583221 CAPTURE        SCHEMATIC_EDITOROption to have the Schematic Page Name as a Property in the Titleblock
591140 concept_HDL    OTHER            Scale overall output size inPublishPDF from command line
; N9 a3 J4 w/ F# g! c4 |9 F% |: l801901 CONCEPT_HDL    CORE             Concept Menus use the same key"R" for the Wire and RF-PCB menus
813614  APD            DRC_CONSTRAINTS  With Fillets present the "cline toshape" spacing is wrong.
881796 ALLEGRO_EDITOR GRAPHICS        Enhancement request for Panning with Middle Mouse Button
" w) ?+ l5 f+ ~( N  t$ `887191 CONCEPT_HDL    CORE             Cannot add/edit the locked property
911292 CONCEPT_HDL    CORE             Property command on editing symbolattaches property to ORIGIN immediately
6 q& r2 c- Q. y9 g987766  APD            SHAPE            Void all command gets result as novoids being generated on specific env.
* i, v; ^* o( i( u! {3 ^3 m1001395 SIP_LAYOUT    ASSY_RULE_CHECK  Shape Minimumvoid check reports lots of DRCs which are not necessary to check out.
1030696 ALLEGRO_EDITOR INTERACTIV       Enh - Allow another behavior of PANmovement using middle mouse in Allegro
$ b1 L" v: X4 X9 A1 ]0 x* A1043856 ADW           TDA              Diff between TDOand DE-HDL Hierarchy Viewer is confusing to the user
1046440 ADW           PCBCACHE         ADW: ImportSheetis not caching libraries under flatlib/model_sym when the source design is notan ADW project
1 m' I- v, d* p! X( X  X1077552 F2B           PACKAGERXL       Diff Pairs get removed when packing withbackannotation turned on
( B1 d4 @" F9 Q9 K1079538 F2B           PACKAGERXL       Ability to blockall 縮ingle noded nets� to the board while packaging.
9 S% B- Z. I3 X1 A1086362 ALLEGRO_EDITOR SHAPE            Enhancement request to autovoid a viaif shape cannot cover the center of the via.
2 {, o1 M& g6 I# _9 E1087958 Pspice        MODELEDITOR      Is there anylimitation for pin name definition?
1087967 CIS           UPDATE_PART_STAT Update part status window shows incorrect differences
1090693 ADW           LRM              LRMauto_load_instances does not gray out Load instances Button
' a- H, g+ \& s# P1 n. }" q1097246 CONCEPT_HDL   CORE             ConceptHDL -assign hotkeys to alpha-numerical keys
. L) {  {$ E( m1099773 CONCEPT_HDL   CORE             DE HDL goes intorecursive loop if a custom text locked at site level is deleted from Tools >Option
  ]+ ^- T7 C% s* B1100945 SCM           SCHGEN           SCM generatedDE-HDL has $PN placement issue
% R1 b8 o& e& z* T1100951 PSPICE        SIMULATOR        Increasing theresolution of fourier transform results in out file
: Q* K8 D$ e2 i) y% N" B1103117 RF_PCB        FE_IFF_IMPORT    Enh- Allow theAllegro_Discrete_Library_to_ADS_Library_Translator to output in its originalunit
1105473 PSPICE        PROBE            Getting errormessages while running bias point analysis.
( f0 `4 Z9 d4 g1106116 FLOWS         PROJMGR          view_pcb settingchange was cleared by switching Flows in projmgr.
1106298 ALLEGRO_EDITOR INTERACTIV       Copy Shape uses last menu pick locationas origin and not the Symbol Origin as specified in Options.
1106626 CONCEPT_HDL   CORE             Concept HDL crashes when saving pages
1107086 ALLEGRO_EDITOR INTERACTIV       manual void with arc's goes in wrongdirection during arc creation
1107172 CONCEPT_HDL   OTHER            Project ManagerPackager does not report errors on missing symbol
1108193 CONCEPT_HDL   CORE             Using theleft/right keys do not move the cursor within the text you're editing
  A3 S. X6 T6 m! K, T1108603 PCB_LIBRARIAN VERIFICATION     PDV ToolsVerification > View Verification (CheckPlus) leaves<project>.cpm_tmp.cpm
1109024 CIS            OTHER            orcad performance issue from Asus.
1109109 CAPTURE       NETLIST_ALLEGRO  B1: Netlistmissing pins when Pack_short property pins connected
4 ~0 `  L. K0 S7 K4 m0 ~1 P1109466 ALLEGRO_EDITOR ARTWORK          Artwork create some strange gerberlines for fillet.
1109647 SIP_LAYOUT    DEGASSING        Shape degassingcommand enhancement - control over what layers are counted in even/odd layersets.
! G5 j. |$ f8 M" y9 e  L. o$ A* G8 g1109926 CONCEPT_HDL   CORE             viewing a designdisables console window
1110194 SIP_LAYOUT    WIREBOND         If OpenGL settings for display ofdynamic net names is enabled, should be visible while push/shove wirebonds.
1112357 SIP_LAYOUT    WIREBOND         wirebond commandcrashes the application
6 ^" v+ F; O4 G4 R' J8 y3 Z1112395 CONCEPT_HDL   CORE             縗BASE\G� for global signal is not obeyedafter upreving the design to 1650.
+ Y. b& S- F7 c0 w! L9 p1112658 CAPTURE       PROPERTY_EDITOR  Changing Part 縂raphic� value from property EditorChanges Occ refdes values to instance
1112662 CAPTURE       PROJECT_MANAGER  Capture crashesafter moving the library file and then doing Edit> Cut
/ U5 ^# _) \1 c2 M7 X1113177 PCB_LIBRARIAN CORE             Pin Shapes arenot getting imported properly
  [3 j, Q" z  ^( T0 T1113380 ALLEGRO_EDITOR INTERACTIV       Change layer to - option for packagetype .dra is not available in 16.6 release
1113656 SIP_LAYOUT    WIREBOND         Enable Changecharacteristic to work without unfixing its Tack point.
1113838 SIP_LAYOUT    DIE_ABSTRACT_IF  probe pinsdefined in XDA die abstract file are added with wrong location
* w: M# {: G3 |1113991 CAPTURE       GENERAL          Save Project Asis not working if destination is a linux machine
1114073 APD           DRC_CONSTRAINTS  Shape voidingdifferently if there are Fillets present in the design.
1114241 CAPTURE       SCHEMATIC_EDITOR Port not retaining assigned color, when moved on theschematic
1114442 PSPICE        PROBE            Getting Internalerror - Overflow Convert with marching waveform on
' \* Q  o3 G8 {1 Z1114630 CONCEPT_HDL   ARCHIVER         Archcore failsbecause the project directory on Linux has a space in the name
" T7 X; x+ h+ y- X4 E( @. M* k1114689 CONCEPT_HDL   CORE             Unknown projectdirective : text_editor
8 R, ~6 e( Q+ u7 |9 g- n' z1114928 F2B           PACKAGERXL       縀rror (SPCODD - 5) while Export Physical even afterchange pin from A<0> to A
/ S6 |: u: L" }1116886 CONCEPT_HDL   CORE             Crefer hyperlinksdo not work fine when user use double digits partitions for page Border.
: i6 V5 Z2 `( u# N; x& _1118088 ALLEGRO_EDITOR EDIT_ETCH        Should Plan accurate and Optimize beremoved in 16.6?
, s0 U! h$ @4 T' z6 K1118734 APD           EDIT_ETCH        Multiline routingwith Clines on Null Net cannot route in downward direction
1118756 ALLEGRO_EDITOR SHAPE            Shape clearance parameter oversizevalues getting applied to Keepouts
1119606 CONCEPT_HDL   MARKERS          Filtering two ormore words in Filter dialog box
% w' J) r( ~9 a' f1119707 CONCEPT_HDL   CORE             Genview does not use site colors when gen schfrom block symbol
% P5 I7 q+ f# H4 X0 c" `1119711 F2B           DESIGNSYNC       DesignDifferences show Net Differences wrongly
1120659 CAPTURE       PROJECT_MANAGER  "Saveproject as" does not support some of Nordic characters.
2 ~$ ^) F  G( i1120660 CONCEPT_HDL   CORE             Save hierarchysaves pages for deleted blocks.
2 ^# l, o0 ^! A+ y1120817 SIP_LAYOUT    SYMB_EDIT_APPMOD Rotate pads commands not working while in the SymbolEdit App. mode
1120985 PSPICE        MODELEDITOR      Unable to importattached IBIS model
- V% M9 G+ k/ ~1121171 CONCEPT_HDL   CREFER           PNN and correctproperty values not annotated on the Cref flat schematic
4 X+ |' w2 J/ e: k: T1121353 ALLEGRO_EDITOR INTERACTIV       Local env setting will change aftersaving and reopening.
1121382 ALLEGRO_EDITOR INTERACTIV       Undo command is limited to two for thisdesign
1 s" \) O+ H: _* y; i1121540 F2B           PACKAGERXL       pxl.chg keepsdeleting and adding changes on subsequent packager runs
: H4 x$ l& X9 |8 p+ v. h# ]! H1121558 ALLEGRO_EDITOR MODULES          Unrouted net and unrouted connectionwhen module is placed of completely routed board file.
1121585 ALLEGRO_EDITOR OTHER            Drill Hole to Shape Same NetSpacing with Dynamic Shapes shows wrong result.
+ \6 T0 S) ^- ^( b! {: C! J* m1121651 CAPTURE       SCHEMATIC_EDITOR "PCB editor select" menu option is missing
1122136 SIP_LAYOUT    PLACEMENT        Moving acomponent results in the components outline going to bottom side of the design.
1122340 CAPTURE       NETLIST_ALLEGRO  Cross probe ofnet within a bus makes Capture to hang.
9 `  f4 r7 H- G. f1 c4 N1 o) H( \& Q1122489 CONCEPT_HDL   OTHER            Save _Hierarchycausing baseline to brd files
1122781 CONCEPT_HDL   CORE             cfg_package isgenerated for component cell automatically
5 r* d+ Z; K5 I; x3 k8 c1122909 CONCEPT_HDL   CORE             changing versionreplicates data of first TOC on 2nd one
1123150 CONCEPT_HDL   CORE             property on yaxis in symbol view was moved by visibility change to None.
( L7 l3 j! X: ^" i& p0 N3 X1123176 ALLEGRO_EDITOR UI_FORMS         Negative values for pop-up location isnot retained with multiple monitors (more than 2)
" l$ d4 a( A8 E* @4 ]/ S8 ~1123815 ALLEGRO_EDITOR GRAPHICS         Embedded netname changes to a differentnetname
# U, `/ t9 L1 ~; R. s9 Y: |1124369 ALLEGRO_EDITOR INTERACTIV       Sliding a shape using iy coordinate doesnot work indepedent of grid.
# P" c! F9 V1 n6 K; T$ U+ @1124544 CONCEPT_HDL   CORE             About SearchHistory of find with SPB16.5
1124570 APD           IMPORT_DATA      When importingStream adding the option to change the point
1125201 CONCEPT_HDL   CORE             Connectivityedits in NEW block not saved( lost) if block is created using block add
1125314 ALLEGRO_EDITOR INTERACTIV       Enved crash during setting of library paths inuser preference
( ]7 J" C% g3 {7 l) \0 y% s' E8 H1125366 CONCEPT_HDL   CORE             DE-HDL crachESDuring Import Physical if CM is open on Linux
1125628 CONCEPT_HDL   CORE             Crash on doingsave hierarchy
+ v; j1 X2 M1 E1130555 APD           WIREBOND         Wirebond Import should connect to pinsof the die specified on the UI.
' T4 h. f5 H% E, w7 ~- q! U: ~  U1131030 PSPICE        ENVIRONMENT      Unregistered iconof Simulation setting in taskbar
) W' ~+ W$ t7 d/ ~' D  F1131083 ALLEGRO_EDITOR INTERACTIV       Bug: 16.6 crash in changing the mode inFind filter window
$ N; s* V  f- u, V1131226 ALLEGRO_EDITOR PLACEMENT        When Angle is set in design parameterswhile placement component is rotated but outline is not.
1131567 CONCEPT_HDL   OTHER            Lower case valuesfor VHDL_MODE make genview use pin location to determen direction.
: q! `7 z0 n5 ^" T' Q1131699 PSPICE        PROBE            Probe windowcrash on trying to view simulation message
8 Z: s5 C# D3 M  N( y/ I1132457 CONCEPT_HDL   CORE             The schematicnever fully invokes and has connectivity errors.
1132575 CONCEPT_HDL   CORE             2 pin_name weredisplayed and overlapped by spin command.
1132698 ALLEGRO_EDITOR EDIT_ETCH        Slide Via with Segment option with newSlide command
1132964 ALLEGRO_EDITOR SHAPE            Same net "B&B via toshape" errors created when adding shape
1133677 CONCEPT_HDL   CORE             Cant delete norreset LOCATION prop in context of top
. J/ R# G( F8 K) u/ P1133791 CONCEPT_HDL   CORE             Cant do textjustification on a single selected NOTE in Windows mode.
1134761 CONCEPT_HDL   CORE             Why does MousePointer/Tooltip display LOCATION instead of $LOCATION property
8 Q# k, y, K( B& c* U4 ]- k  w) R1135118 ALLEGRO_EDITOR INTERACTIV       Mirror and other editing commands aremissing for testpoint label text in general edit mode.
1136420 CAPTURE       GENERAL          Registrationissue when CDSROOT has a space in its path
; u+ r+ Q. \+ F1136808 PSPICE        STABILITY        Pspice crashmarker server has quite unexpectedly
1136840 CAPTURE       SCHEMATICS       Enh: Alignment oftext placed on schematic page
  X( m# d; s3 W: n- _1138586 ADW           MIGRATION        design migrationdoes not create complete ptf file for hierarchical designs
1139376 CONCEPT_HDL   CORE             setting wirecolor to default creates new wire with higher thickness
0 t5 b* B* q* w& k- q1140819 APD           GRAPHICS         Bbvia does notretain temp highlight color on all layers when selected.
, \, o4 P: r) r3 K% A6 u1141300 CONCEPT_HDL   CORE             DE HDL hier_writesave hierarchy log reports summarizes Successfully saved block x while blockwas skipped
1141723 ADW           PURGE            purge commandcrashes with an MFC application failure message
1143448 CAPTURE       GENERAL          About copy &paste to Powerpoint from CIS
/ ^+ r, \5 w8 y; w) ]; F1143670 SIP_LAYOUT    OTHER            Cross Probingbetween SiP and DEHDL not working in 16.6 release
1143902 ALLEGRO_EDITOR DATABASE         when the shape is rotated 45 degreesthe void is moved.
) M+ y4 o  f$ C6 b$ u% z8 n1144990 PCB_LIBRARIAN CORE             PDV expand &collapse vector pins resizes symbol outline to maximum height
. `# o. D8 R& ^1145112 CONCEPT_HDL   CORE             Warning message:Connectivity MIGHT have changed
1145253 CONCEPT_HDL   CORE             Component Browseradds properties in upper case
, u& [7 e4 H" N$ W' _1146386 ALLEGRO_EDITOR INTERACTIV       Place Replicate Create add Static shapewith Fillet shape
1146728 F2B           PACKAGERXL       DCF with upperand lower case values on parts causes pxl to fail
& [6 K& q* w8 s8 o+ l- b1 k1146783 ALLEGRO_EDITOR INTERFACES       Highlighted component is missing fromexported IPF file.
1147326 CONCEPT_HDL   CORE             HDL crashes whentrying to reimport a block
3 ~' o5 o' ]% q8 I! b+ B8 h1148337 CAPTURE       ANNOTATE         Checking "refdes control" isnot giving the proper annotation result
2 n# M: B$ ^. j( S6 B1148633 SIP_LAYOUT    INTERACTIVE      Add "%"to the optical shrink option in the co-design die and compose symbol placementforms
1149778 CAPTURE       SCHEMATICS       Rotation of pspice marker before placementis not appropriate
1149987 PCB_LIBRARIAN PTF_EDITOR       Save As pushingthe part name suffix into vendor_part_number value
1151748 ALLEGRO_EDITOR OTHER            If the pad and cline are the samewidth don't report a missing Dynamic Fillet.
8 E1 H# T" h; b3 b, ]& \6 P1152206 CONCEPT_HDL   CORE             ROOM Propertyvalue changes when saving another Page
3 m2 x2 R% B$ S+ |1152755 CONCEPT_HDL   COPY_PROJECT     Copy projecthangs if library or design name has an underscore
6 e: T; P( D9 r8 R8 ?5 P0 Y1152769 PSPICE        ENCRYPTION       Unable to simulate Encrypted Models in16.6
1153308 ALLEGRO_EDITOR DRC_CONSTR       Creating Artwork Getting Warning"DRC is out of Date" even when DRC is up to date
1153893 F2B           DESIGNVARI       16.6 VariantEditor not supporting - in name
) V' v! h  J2 g1154185 SIG_INTEGRITY SIGNOISE         Signoise didn'tdo the Rise edge time adjustment.
1154860 ALLEGRO_EDITOR MANUFACT         Double digit drill character overlapswith figures triangle, hexagon and octagon in NC drill legend
1155167 ALLEGRO_EDITOR EDIT_ETCH        Via structure placed in Create Fanouthas incorrect rotation.
, \6 Q' c$ F; y2 j5 m3 M3 f- ?1155728 CONCEPT_HDL   CORE             Unable to uprevpackaged 16.3 design in 16.5 due to memory
! |: h3 x# @& o, B8 ~- d1 T6 L" a8 l1155855 SCM           SCHGEN           A newlyuser-defined net property is not transferred from SCM to DEHDL in PreservedMode
8 p- T# o! \6 K0 V6 V) m1156274 ALLEGRO_EDITOR INTERFACES       Exported Step file from Allegro is wrong
" {. z, m9 U; }1 a1156316 CONSTRAINT_MGR OTHER            Break in functionality whilecreation of pin-pairs under Xnet in Constraint Manager
1156351 CONCEPT_HDL   CONSTRAINT_MGR   Loose members inPhysical Net Class between DEHDL and Allegro
0 N. C5 L* m; S$ r7 q" ^1156547 ALLEGRO_EDITOR DRC_CONSTR       Etch Turn under SMD pin rule checkthrough pin Etch makes confused.
+ d, k7 G4 M0 |" V1156779 CONSTRAINT_MGR OTHER            Electrical Cset References in CM notworking correctly
# Y3 x# t1 u, ^  @1157167 ALLEGRO_EDITOR skill            axlPolyFromDB with ?line2poly isbroken
$ g! \4 i* |. K8 j5 L/ S! Z1158042 ALLEGRO_EDITOR DFA              DFA_DLG writes the dra file namein uppercase.
1158718 CONCEPT_HDL   CHECKPLUS        Customer couldnot get $PN property values on logical rule of CheckPlus16.6.
: N8 n  X# {' o1158970 ALLEGRO_EDITOR SCHEM_FTB        Changing LOCATION to $LOCATION in DEHDLdoes not update the .brd file
  l' E  l* J/ _6 o+ X1158989 ALLEGRO_EDITOR INTERFACES       pdf_out -l creates a PDF
1159285 APD           DXF_IF           DXF_OUT fails;some figures are not exported
+ U; _0 }4 y2 t  B3 m& Q" k9 |1159432 ALLEGRO_EDITOR SHOW_ELEM        http:// in the Show Element in 166 donot have HTML link to open the Website
! c8 ?) Q5 B  u1 ~+ v1159483 PCB_LIBRARIAN SETUP            part developercrashing with
' V! Q: P! A$ r6 U1159516 ALLEGRO_EDITOR EDIT_ETCH        Unable to slide cline segment with newslide.
1159959 ALLEGRO_EDITOR GRAPHICS         3D viewer displays clines arcsincorrectly
; h  B" a# Z# T: o2 g1160004 SCM           UI               The RMB->Pastedoes not insert signal names.
1160410 ALLEGRO_EDITOR DATABASE         Lock databse with View Lock option ismisleading
1160529 SCM           SCHGEN           Schematicgeneration stopped because the tool was unable to create an appropriateinternal symbol structure
' `: x- k/ x' c6 h1160537 SPIF          OTHER            Cannot start PCBRouter
5 P, H6 ]! S( H6 q. a) O) G" v1161363 ALLEGRO_EDITOR SYMBOL           Getting error SPMHGE-73 when tryingto mirror symbol
1161781 CONSTRAINT_MGR CONCEPT_HDL      SigXp crash when selecting ECset indesign
5 p& B# e/ B) f; i/ n1 z6 [% ~; C1161896 ALLEGRO_EDITOR DRAFTING         Tolerance value added for Dimensionsis not working correctly (HF11-12)
& K; h3 B& Z  S) X# w; @  E3 J1162193 SIP_LAYOUT    DIE_ABSTRACT_IF  shapes in diafile not linked to the die after edit co-design die
! G- T$ j/ \& ^1162754 APD           VIA_STRUCTURE    Replace Via Structurecommand selecting dummy nets.