Hotfix_SPB16.60.013_wint_1of1

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cadence SPB16.6下载(Hotfix013已发布)

Cadence SPB16.6已经推出，需要的朋友可以点击下面的链接下载：
7 z- q7 n6 N) |9 P% Phttp://dl.vmall.com/c0ych9k8m3

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' P% O( Y% g# |5 t! I" zDATE: 07-26-2013  HOTFIX VERSION: 013
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CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
, W1 c. m7 k$ x" o' n2 Q===================================================================================================================================
' Y8 B1 D1 D5 Y8 t* @+ o. Z8 [111368 CAPTURE        CORRUPT_DESIGN   Capture - will not produce allegro netlistwith 10.0
' z4 O; ^9 ?* u# q4 n% Q/ x134439 PD-COMPILE     USERDATA         caCell terminals should be top-levelterminals
# Q) }( R) i3 V  x# K$ h2 K186074  CIS            EXPLORER         refresh symbols from lib requires youto close CIS
, i* \1 F. R& u583221 CAPTURE        SCHEMATIC_EDITOROption to have the Schematic Page Name as a Property in the Titleblock
0 M7 G9 O5 T- I* V591140 concept_HDL    OTHER            Scale overall output size inPublishPDF from command line
% A) O; `( ^! v801901 CONCEPT_HDL    CORE             Concept Menus use the same key"R" for the Wire and RF-PCB menus
6 M" Y& S4 r1 ]' S5 C3 O. e813614  APD            DRC_CONSTRAINTS  With Fillets present the "cline toshape" spacing is wrong.
881796 ALLEGRO_EDITOR GRAPHICS        Enhancement request for Panning with Middle Mouse Button
* G) Q4 C6 g! ~7 }887191 CONCEPT_HDL    CORE             Cannot add/edit the locked property
911292 CONCEPT_HDL    CORE             Property command on editing symbolattaches property to ORIGIN immediately
987766  APD            SHAPE            Void all command gets result as novoids being generated on specific env.
4 {5 c) X9 ^7 O% w4 [2 V1001395 SIP_LAYOUT    ASSY_RULE_CHECK  Shape Minimumvoid check reports lots of DRCs which are not necessary to check out.
1030696 ALLEGRO_EDITOR INTERACTIV       Enh - Allow another behavior of PANmovement using middle mouse in Allegro
1043856 ADW           TDA              Diff between TDOand DE-HDL Hierarchy Viewer is confusing to the user
1046440 ADW           PCBCACHE         ADW: ImportSheetis not caching libraries under flatlib/model_sym when the source design is notan ADW project
$ y0 y: H6 F3 }4 @4 D1 I1077552 F2B           PACKAGERXL       Diff Pairs get removed when packing withbackannotation turned on
1079538 F2B           PACKAGERXL       Ability to blockall 縮ingle noded nets� to the board while packaging.
- k6 m) J" G9 u5 ?  Y1086362 ALLEGRO_EDITOR SHAPE            Enhancement request to autovoid a viaif shape cannot cover the center of the via.
1087958 Pspice        MODELEDITOR      Is there anylimitation for pin name definition?
1087967 CIS           UPDATE_PART_STAT Update part status window shows incorrect differences
- n, Q! }) t3 M0 M7 @+ U* O1090693 ADW           LRM              LRMauto_load_instances does not gray out Load instances Button
) \& s+ ?0 L4 j1097246 CONCEPT_HDL   CORE             ConceptHDL -assign hotkeys to alpha-numerical keys
1099773 CONCEPT_HDL   CORE             DE HDL goes intorecursive loop if a custom text locked at site level is deleted from Tools >Option
1100945 SCM           SCHGEN           SCM generatedDE-HDL has $PN placement issue
  c1 @# F. v* i  S& E1100951 PSPICE        SIMULATOR        Increasing theresolution of fourier transform results in out file
1103117 RF_PCB        FE_IFF_IMPORT    Enh- Allow theAllegro_Discrete_Library_to_ADS_Library_Translator to output in its originalunit
1105473 PSPICE        PROBE            Getting errormessages while running bias point analysis.
1106116 FLOWS         PROJMGR          view_pcb settingchange was cleared by switching Flows in projmgr.
9 T- Q% p/ I- X1 [6 x/ f/ }1 U, Z/ k9 o: i1106298 ALLEGRO_EDITOR INTERACTIV       Copy Shape uses last menu pick locationas origin and not the Symbol Origin as specified in Options.
" p, z+ h5 P+ \* o# x1106626 CONCEPT_HDL   CORE             Concept HDL crashes when saving pages
1107086 ALLEGRO_EDITOR INTERACTIV       manual void with arc's goes in wrongdirection during arc creation
1107172 CONCEPT_HDL   OTHER            Project ManagerPackager does not report errors on missing symbol
; Z6 G  |0 n9 d: U+ T8 Y) X" A1108193 CONCEPT_HDL   CORE             Using theleft/right keys do not move the cursor within the text you're editing
1108603 PCB_LIBRARIAN VERIFICATION     PDV ToolsVerification > View Verification (CheckPlus) leaves<project>.cpm_tmp.cpm
1109024 CIS            OTHER            orcad performance issue from Asus.
- C5 w4 {- J  a& D6 Z' }( `! R" M1109109 CAPTURE       NETLIST_ALLEGRO  B1: Netlistmissing pins when Pack_short property pins connected
- j/ ]0 G! v+ `1109466 ALLEGRO_EDITOR ARTWORK          Artwork create some strange gerberlines for fillet.
% w; }% r+ {* A8 D% b1109647 SIP_LAYOUT    DEGASSING        Shape degassingcommand enhancement - control over what layers are counted in even/odd layersets.
1109926 CONCEPT_HDL   CORE             viewing a designdisables console window
1110194 SIP_LAYOUT    WIREBOND         If OpenGL settings for display ofdynamic net names is enabled, should be visible while push/shove wirebonds.
1112357 SIP_LAYOUT    WIREBOND         wirebond commandcrashes the application
) K2 t7 t& p9 v% ]' F1112395 CONCEPT_HDL   CORE             縗BASE\G� for global signal is not obeyedafter upreving the design to 1650.
4 n  |1 d; k0 W6 |8 S( R* V7 L! D0 X1112658 CAPTURE       PROPERTY_EDITOR  Changing Part 縂raphic� value from property EditorChanges Occ refdes values to instance
7 {1 ?1 R. L% Y) [% i1112662 CAPTURE       PROJECT_MANAGER  Capture crashesafter moving the library file and then doing Edit> Cut
8 C9 Z; K) [! \  k3 P1 [1 k' f1113177 PCB_LIBRARIAN CORE             Pin Shapes arenot getting imported properly
9 v+ I* |$ E" v9 m( e1113380 ALLEGRO_EDITOR INTERACTIV       Change layer to - option for packagetype .dra is not available in 16.6 release
1113656 SIP_LAYOUT    WIREBOND         Enable Changecharacteristic to work without unfixing its Tack point.
$ I" Z4 t, l$ j/ v2 d# g1113838 SIP_LAYOUT    DIE_ABSTRACT_IF  probe pinsdefined in XDA die abstract file are added with wrong location
2 M9 {4 }5 s7 E6 O, g7 V1113991 CAPTURE       GENERAL          Save Project Asis not working if destination is a linux machine
1114073 APD           DRC_CONSTRAINTS  Shape voidingdifferently if there are Fillets present in the design.
; o& G7 c. `6 K- D: |1114241 CAPTURE       SCHEMATIC_EDITOR Port not retaining assigned color, when moved on theschematic
; I5 u' `6 g; Z1114442 PSPICE        PROBE            Getting Internalerror - Overflow Convert with marching waveform on
9 a  W6 g9 s8 F# x1114630 CONCEPT_HDL   ARCHIVER         Archcore failsbecause the project directory on Linux has a space in the name
. d. h: |$ D) N7 j/ l2 X7 o1114689 CONCEPT_HDL   CORE             Unknown projectdirective : text_editor
; @& |& b$ s" L9 Q2 y1114928 F2B           PACKAGERXL       縀rror (SPCODD - 5) while Export Physical even afterchange pin from A<0> to A
% m  Z5 t2 \; l. S& A1116886 CONCEPT_HDL   CORE             Crefer hyperlinksdo not work fine when user use double digits partitions for page Border.
1118088 ALLEGRO_EDITOR EDIT_ETCH        Should Plan accurate and Optimize beremoved in 16.6?
1118734 APD           EDIT_ETCH        Multiline routingwith Clines on Null Net cannot route in downward direction
) Y, s& x/ M2 K& i+ b+ S1118756 ALLEGRO_EDITOR SHAPE            Shape clearance parameter oversizevalues getting applied to Keepouts
+ G+ Q; {! q6 j8 |- k/ ]* Y1119606 CONCEPT_HDL   MARKERS          Filtering two ormore words in Filter dialog box
1119707 CONCEPT_HDL   CORE             Genview does not use site colors when gen schfrom block symbol
# l7 ^6 V' i1 y8 y* t6 E: J: W1119711 F2B           DESIGNSYNC       DesignDifferences show Net Differences wrongly
  o, i4 T) @9 C5 i; w5 W1120659 CAPTURE       PROJECT_MANAGER  "Saveproject as" does not support some of Nordic characters.
7 ^& W% n9 m& I. j+ D1120660 CONCEPT_HDL   CORE             Save hierarchysaves pages for deleted blocks.
- o7 h" _$ T) B6 `5 @( q! B: P" U1120817 SIP_LAYOUT    SYMB_EDIT_APPMOD Rotate pads commands not working while in the SymbolEdit App. mode
7 ?1 ~" w: D8 J8 M/ i" h- f1120985 PSPICE        MODELEDITOR      Unable to importattached IBIS model
* w6 e/ ^, s) m" J0 O* `1121171 CONCEPT_HDL   CREFER           PNN and correctproperty values not annotated on the Cref flat schematic
) a2 |# @3 C" N! B0 e2 T, f3 z1121353 ALLEGRO_EDITOR INTERACTIV       Local env setting will change aftersaving and reopening.
1121382 ALLEGRO_EDITOR INTERACTIV       Undo command is limited to two for thisdesign
, u- X) V, z- {: E& E6 o1121540 F2B           PACKAGERXL       pxl.chg keepsdeleting and adding changes on subsequent packager runs
1121558 ALLEGRO_EDITOR MODULES          Unrouted net and unrouted connectionwhen module is placed of completely routed board file.
5 _# S6 `9 G* q+ _# z1121585 ALLEGRO_EDITOR OTHER            Drill Hole to Shape Same NetSpacing with Dynamic Shapes shows wrong result.
7 B: |; N3 @$ h. u9 @1121651 CAPTURE       SCHEMATIC_EDITOR "PCB editor select" menu option is missing
& u  m$ X' p8 F1122136 SIP_LAYOUT    PLACEMENT        Moving acomponent results in the components outline going to bottom side of the design.
: z# B( N1 m# K* G2 ~# ^1122340 CAPTURE       NETLIST_ALLEGRO  Cross probe ofnet within a bus makes Capture to hang.
# [" c" D5 S( P1122489 CONCEPT_HDL   OTHER            Save _Hierarchycausing baseline to brd files
( H, m' H7 Q. H1122781 CONCEPT_HDL   CORE             cfg_package isgenerated for component cell automatically
6 J, [2 }# z# F$ z8 z1122909 CONCEPT_HDL   CORE             changing versionreplicates data of first TOC on 2nd one
  B  e4 c: G) r! i1123150 CONCEPT_HDL   CORE             property on yaxis in symbol view was moved by visibility change to None.
# S+ S) X4 ~; d) Q& `9 g1123176 ALLEGRO_EDITOR UI_FORMS         Negative values for pop-up location isnot retained with multiple monitors (more than 2)
" f. @: ?0 Q# _# @' W! F1123815 ALLEGRO_EDITOR GRAPHICS         Embedded netname changes to a differentnetname
1124369 ALLEGRO_EDITOR INTERACTIV       Sliding a shape using iy coordinate doesnot work indepedent of grid.
1124544 CONCEPT_HDL   CORE             About SearchHistory of find with SPB16.5
1124570 APD           IMPORT_DATA      When importingStream adding the option to change the point
5 T4 Y' q# x! f9 Q1125201 CONCEPT_HDL   CORE             Connectivityedits in NEW block not saved( lost) if block is created using block add
1125314 ALLEGRO_EDITOR INTERACTIV       Enved crash during setting of library paths inuser preference
1125366 CONCEPT_HDL   CORE             DE-HDL crachESDuring Import Physical if CM is open on Linux
1125628 CONCEPT_HDL   CORE             Crash on doingsave hierarchy
; U- D) d7 z  Q3 {7 B1130555 APD           WIREBOND         Wirebond Import should connect to pinsof the die specified on the UI.
1131030 PSPICE        ENVIRONMENT      Unregistered iconof Simulation setting in taskbar
* o( {1 X! v! [* i1131083 ALLEGRO_EDITOR INTERACTIV       Bug: 16.6 crash in changing the mode inFind filter window
1 j+ |2 O2 U8 {# c/ _/ b* V1131226 ALLEGRO_EDITOR PLACEMENT        When Angle is set in design parameterswhile placement component is rotated but outline is not.
4 ]2 J/ a/ _7 t1 p) p# [1131567 CONCEPT_HDL   OTHER            Lower case valuesfor VHDL_MODE make genview use pin location to determen direction.
1131699 PSPICE        PROBE            Probe windowcrash on trying to view simulation message
1132457 CONCEPT_HDL   CORE             The schematicnever fully invokes and has connectivity errors.
. C; Z9 K2 |/ r( Y" \1132575 CONCEPT_HDL   CORE             2 pin_name weredisplayed and overlapped by spin command.
1132698 ALLEGRO_EDITOR EDIT_ETCH        Slide Via with Segment option with newSlide command
1132964 ALLEGRO_EDITOR SHAPE            Same net "B&B via toshape" errors created when adding shape
1133677 CONCEPT_HDL   CORE             Cant delete norreset LOCATION prop in context of top
! ~& t3 {: _2 F9 N3 }1133791 CONCEPT_HDL   CORE             Cant do textjustification on a single selected NOTE in Windows mode.
1134761 CONCEPT_HDL   CORE             Why does MousePointer/Tooltip display LOCATION instead of $LOCATION property
# D! b% @0 T5 N) C* q; I& Q, ^3 ~1135118 ALLEGRO_EDITOR INTERACTIV       Mirror and other editing commands aremissing for testpoint label text in general edit mode.
1136420 CAPTURE       GENERAL          Registrationissue when CDSROOT has a space in its path
1136808 PSPICE        STABILITY        Pspice crashmarker server has quite unexpectedly
1136840 CAPTURE       SCHEMATICS       Enh: Alignment oftext placed on schematic page
' X# i1 u' z% O. M8 j- m3 L1138586 ADW           MIGRATION        design migrationdoes not create complete ptf file for hierarchical designs
1139376 CONCEPT_HDL   CORE             setting wirecolor to default creates new wire with higher thickness
1140819 APD           GRAPHICS         Bbvia does notretain temp highlight color on all layers when selected.
1141300 CONCEPT_HDL   CORE             DE HDL hier_writesave hierarchy log reports summarizes Successfully saved block x while blockwas skipped
1141723 ADW           PURGE            purge commandcrashes with an MFC application failure message
1143448 CAPTURE       GENERAL          About copy &paste to Powerpoint from CIS
; `( Y8 h( q# D1 M$ @  h1143670 SIP_LAYOUT    OTHER            Cross Probingbetween SiP and DEHDL not working in 16.6 release
1143902 ALLEGRO_EDITOR DATABASE         when the shape is rotated 45 degreesthe void is moved.
1144990 PCB_LIBRARIAN CORE             PDV expand &collapse vector pins resizes symbol outline to maximum height
1145112 CONCEPT_HDL   CORE             Warning message:Connectivity MIGHT have changed
1145253 CONCEPT_HDL   CORE             Component Browseradds properties in upper case
. q& `4 X& ^, h6 |1146386 ALLEGRO_EDITOR INTERACTIV       Place Replicate Create add Static shapewith Fillet shape
* T$ U9 x! [% R$ Y1146728 F2B           PACKAGERXL       DCF with upperand lower case values on parts causes pxl to fail
1146783 ALLEGRO_EDITOR INTERFACES       Highlighted component is missing fromexported IPF file.
& V; {( @% O9 ]6 [# C7 ?1147326 CONCEPT_HDL   CORE             HDL crashes whentrying to reimport a block
1148337 CAPTURE       ANNOTATE         Checking "refdes control" isnot giving the proper annotation result
/ W6 Z0 L6 z' G% i; y: ?# h+ G1148633 SIP_LAYOUT    INTERACTIVE      Add "%"to the optical shrink option in the co-design die and compose symbol placementforms
1149778 CAPTURE       SCHEMATICS       Rotation of pspice marker before placementis not appropriate
1149987 PCB_LIBRARIAN PTF_EDITOR       Save As pushingthe part name suffix into vendor_part_number value
" F3 t% _2 x* H% c, G  W1151748 ALLEGRO_EDITOR OTHER            If the pad and cline are the samewidth don't report a missing Dynamic Fillet.
1152206 CONCEPT_HDL   CORE             ROOM Propertyvalue changes when saving another Page
" R3 q; {8 ?# \2 p2 s# M$ g) U1152755 CONCEPT_HDL   COPY_PROJECT     Copy projecthangs if library or design name has an underscore
1152769 PSPICE        ENCRYPTION       Unable to simulate Encrypted Models in16.6
1153308 ALLEGRO_EDITOR DRC_CONSTR       Creating Artwork Getting Warning"DRC is out of Date" even when DRC is up to date
1153893 F2B           DESIGNVARI       16.6 VariantEditor not supporting - in name
1154185 SIG_INTEGRITY SIGNOISE         Signoise didn'tdo the Rise edge time adjustment.
1154860 ALLEGRO_EDITOR MANUFACT         Double digit drill character overlapswith figures triangle, hexagon and octagon in NC drill legend
1155167 ALLEGRO_EDITOR EDIT_ETCH        Via structure placed in Create Fanouthas incorrect rotation.
- w- j0 j/ ~' y$ ]5 z4 @! }1155728 CONCEPT_HDL   CORE             Unable to uprevpackaged 16.3 design in 16.5 due to memory
1155855 SCM           SCHGEN           A newlyuser-defined net property is not transferred from SCM to DEHDL in PreservedMode
1156274 ALLEGRO_EDITOR INTERFACES       Exported Step file from Allegro is wrong
1156316 CONSTRAINT_MGR OTHER            Break in functionality whilecreation of pin-pairs under Xnet in Constraint Manager
0 G& }9 K& Z' Z; x; I% l1156351 CONCEPT_HDL   CONSTRAINT_MGR   Loose members inPhysical Net Class between DEHDL and Allegro
& m: k- c; O1 M$ d! i1156547 ALLEGRO_EDITOR DRC_CONSTR       Etch Turn under SMD pin rule checkthrough pin Etch makes confused.
2 \" q9 D( o2 Z9 A6 L: i& @* Y1156779 CONSTRAINT_MGR OTHER            Electrical Cset References in CM notworking correctly
1157167 ALLEGRO_EDITOR skill            axlPolyFromDB with ?line2poly isbroken
6 Q- ~7 l8 ?/ ~1158042 ALLEGRO_EDITOR DFA              DFA_DLG writes the dra file namein uppercase.
. R- ~: {/ L" o# n. g4 Z1 z  u1158718 CONCEPT_HDL   CHECKPLUS        Customer couldnot get $PN property values on logical rule of CheckPlus16.6.
0 k. W# L$ e7 P1 y1158970 ALLEGRO_EDITOR SCHEM_FTB        Changing LOCATION to $LOCATION in DEHDLdoes not update the .brd file
) z4 ?. N, \; g* k) b1158989 ALLEGRO_EDITOR INTERFACES       pdf_out -l creates a PDF
5 F1 a8 l3 ]4 j" M1 K# e- I1159285 APD           DXF_IF           DXF_OUT fails;some figures are not exported
9 l/ W+ c9 }( F+ i& c1159432 ALLEGRO_EDITOR SHOW_ELEM        http:// in the Show Element in 166 donot have HTML link to open the Website
2 |0 I) D. c; k; k) X$ _. J1159483 PCB_LIBRARIAN SETUP            part developercrashing with
1159516 ALLEGRO_EDITOR EDIT_ETCH        Unable to slide cline segment with newslide.
5 n4 T& k) _2 l/ J/ n& l1159959 ALLEGRO_EDITOR GRAPHICS         3D viewer displays clines arcsincorrectly
1160004 SCM           UI               The RMB->Pastedoes not insert signal names.
4 d6 Z& {, P2 X2 V# K" Q( n: L1160410 ALLEGRO_EDITOR DATABASE         Lock databse with View Lock option ismisleading
. E* T- g! }: S# d/ v! |1160529 SCM           SCHGEN           Schematicgeneration stopped because the tool was unable to create an appropriateinternal symbol structure
  u2 q$ p" ^4 A+ v1 s1160537 SPIF          OTHER            Cannot start PCBRouter
1161363 ALLEGRO_EDITOR SYMBOL           Getting error SPMHGE-73 when tryingto mirror symbol
2 |2 R+ c1 L' q# r) E9 d1161781 CONSTRAINT_MGR CONCEPT_HDL      SigXp crash when selecting ECset indesign
( R7 Y; C- c1 q3 K* c$ G1161896 ALLEGRO_EDITOR DRAFTING         Tolerance value added for Dimensionsis not working correctly (HF11-12)
* _6 t# b4 h. L9 c% W" ]0 k1162193 SIP_LAYOUT    DIE_ABSTRACT_IF  shapes in diafile not linked to the die after edit co-design die
1162754 APD           VIA_STRUCTURE    Replace Via Structurecommand selecting dummy nets.