Hotfix_SPB16.60.013_wint_1of1

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cadence SPB16.6下载(Hotfix013已发布)

Cadence SPB16.6已经推出，需要的朋友可以点击下面的链接下载：
$ e  j+ ^% }3 z1 qhttp://dl.vmall.com/c0ych9k8m3


) k" o3 {& W* ~1 B4 C: J! i& ADATE: 07-26-2013  HOTFIX VERSION: 013
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CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
* }, L* X+ b8 O111368 CAPTURE        CORRUPT_DESIGN   Capture - will not produce allegro netlistwith 10.0
134439 PD-COMPILE     USERDATA         caCell terminals should be top-levelterminals
9 W: N! P% B5 r3 O186074  CIS            EXPLORER         refresh symbols from lib requires youto close CIS
) h3 a' t4 j- d5 H/ A0 P" q583221 CAPTURE        SCHEMATIC_EDITOROption to have the Schematic Page Name as a Property in the Titleblock
+ @- }! J$ Q6 x/ f+ }! _591140 concept_HDL    OTHER            Scale overall output size inPublishPDF from command line
) E3 j  G) b2 r6 t+ Y) M$ {6 {801901 CONCEPT_HDL    CORE             Concept Menus use the same key"R" for the Wire and RF-PCB menus
813614  APD            DRC_CONSTRAINTS  With Fillets present the "cline toshape" spacing is wrong.
881796 ALLEGRO_EDITOR GRAPHICS        Enhancement request for Panning with Middle Mouse Button
. M8 Z' p9 |3 I7 X887191 CONCEPT_HDL    CORE             Cannot add/edit the locked property
3 ?9 G4 v; B* x( `2 A( f& S911292 CONCEPT_HDL    CORE             Property command on editing symbolattaches property to ORIGIN immediately
) `: ^0 W, G# ~3 T/ H987766  APD            SHAPE            Void all command gets result as novoids being generated on specific env.
3 z$ C2 ~& ^1 k0 F$ o1001395 SIP_LAYOUT    ASSY_RULE_CHECK  Shape Minimumvoid check reports lots of DRCs which are not necessary to check out.
1030696 ALLEGRO_EDITOR INTERACTIV       Enh - Allow another behavior of PANmovement using middle mouse in Allegro
! J9 E: c' `3 J* d; T; I8 L1043856 ADW           TDA              Diff between TDOand DE-HDL Hierarchy Viewer is confusing to the user
1046440 ADW           PCBCACHE         ADW: ImportSheetis not caching libraries under flatlib/model_sym when the source design is notan ADW project
1077552 F2B           PACKAGERXL       Diff Pairs get removed when packing withbackannotation turned on
1079538 F2B           PACKAGERXL       Ability to blockall 縮ingle noded nets� to the board while packaging.
5 q* I; P6 k$ t& _7 `1086362 ALLEGRO_EDITOR SHAPE            Enhancement request to autovoid a viaif shape cannot cover the center of the via.
1087958 Pspice        MODELEDITOR      Is there anylimitation for pin name definition?
1087967 CIS           UPDATE_PART_STAT Update part status window shows incorrect differences
1090693 ADW           LRM              LRMauto_load_instances does not gray out Load instances Button
- W  v& E$ B6 q7 p- i# j1097246 CONCEPT_HDL   CORE             ConceptHDL -assign hotkeys to alpha-numerical keys
8 L' X5 {( ^7 C/ u1 g4 M, Q+ u1099773 CONCEPT_HDL   CORE             DE HDL goes intorecursive loop if a custom text locked at site level is deleted from Tools >Option
1100945 SCM           SCHGEN           SCM generatedDE-HDL has $PN placement issue
" d5 p: S' i/ U; _8 D% [8 r! B1100951 PSPICE        SIMULATOR        Increasing theresolution of fourier transform results in out file
1103117 RF_PCB        FE_IFF_IMPORT    Enh- Allow theAllegro_Discrete_Library_to_ADS_Library_Translator to output in its originalunit
1105473 PSPICE        PROBE            Getting errormessages while running bias point analysis.
1106116 FLOWS         PROJMGR          view_pcb settingchange was cleared by switching Flows in projmgr.
9 T, U5 k0 _( l! P$ \% g5 v1106298 ALLEGRO_EDITOR INTERACTIV       Copy Shape uses last menu pick locationas origin and not the Symbol Origin as specified in Options.
: h& H" i0 Y3 Y8 P1106626 CONCEPT_HDL   CORE             Concept HDL crashes when saving pages
* y. z# {( g& B$ t8 s1107086 ALLEGRO_EDITOR INTERACTIV       manual void with arc's goes in wrongdirection during arc creation
1107172 CONCEPT_HDL   OTHER            Project ManagerPackager does not report errors on missing symbol
! @- B! h- ^9 ?7 o* Z" \1108193 CONCEPT_HDL   CORE             Using theleft/right keys do not move the cursor within the text you're editing
5 t; L/ T$ J  \& |2 Q- x1108603 PCB_LIBRARIAN VERIFICATION     PDV ToolsVerification > View Verification (CheckPlus) leaves<project>.cpm_tmp.cpm
1109024 CIS            OTHER            orcad performance issue from Asus.
! k$ o- g2 L" s% E1109109 CAPTURE       NETLIST_ALLEGRO  B1: Netlistmissing pins when Pack_short property pins connected
' _) ]) S+ U" }7 j2 E1109466 ALLEGRO_EDITOR ARTWORK          Artwork create some strange gerberlines for fillet.
1109647 SIP_LAYOUT    DEGASSING        Shape degassingcommand enhancement - control over what layers are counted in even/odd layersets.
% b$ Q+ l! W; P4 l( [  s: ^1 w1109926 CONCEPT_HDL   CORE             viewing a designdisables console window
1110194 SIP_LAYOUT    WIREBOND         If OpenGL settings for display ofdynamic net names is enabled, should be visible while push/shove wirebonds.
+ j+ P3 o- s' D1112357 SIP_LAYOUT    WIREBOND         wirebond commandcrashes the application
1112395 CONCEPT_HDL   CORE             縗BASE\G� for global signal is not obeyedafter upreving the design to 1650.
- i* K! h) o7 |; c5 e& }/ G1112658 CAPTURE       PROPERTY_EDITOR  Changing Part 縂raphic� value from property EditorChanges Occ refdes values to instance
1 e/ F, q6 G' l% X& g& {1 a1112662 CAPTURE       PROJECT_MANAGER  Capture crashesafter moving the library file and then doing Edit> Cut
: Z* ?: Q/ `/ f: b3 n( L1113177 PCB_LIBRARIAN CORE             Pin Shapes arenot getting imported properly
3 \5 {2 d0 v+ a1113380 ALLEGRO_EDITOR INTERACTIV       Change layer to - option for packagetype .dra is not available in 16.6 release
( k& |0 z% T, y0 P) L( ]- }1113656 SIP_LAYOUT    WIREBOND         Enable Changecharacteristic to work without unfixing its Tack point.
; }9 \; f$ r3 H5 \4 A1113838 SIP_LAYOUT    DIE_ABSTRACT_IF  probe pinsdefined in XDA die abstract file are added with wrong location
6 Z/ A# b- @1 R1113991 CAPTURE       GENERAL          Save Project Asis not working if destination is a linux machine
) T3 Y- r/ U1 s, p" f4 c1114073 APD           DRC_CONSTRAINTS  Shape voidingdifferently if there are Fillets present in the design.
/ e+ }: H$ L- y4 f& p- E" j1114241 CAPTURE       SCHEMATIC_EDITOR Port not retaining assigned color, when moved on theschematic
1114442 PSPICE        PROBE            Getting Internalerror - Overflow Convert with marching waveform on
% c- w5 r3 ?" X, p% O4 O1114630 CONCEPT_HDL   ARCHIVER         Archcore failsbecause the project directory on Linux has a space in the name
1114689 CONCEPT_HDL   CORE             Unknown projectdirective : text_editor
1114928 F2B           PACKAGERXL       縀rror (SPCODD - 5) while Export Physical even afterchange pin from A<0> to A
1116886 CONCEPT_HDL   CORE             Crefer hyperlinksdo not work fine when user use double digits partitions for page Border.
: l+ M  Z  f3 E8 `# Z2 ?1118088 ALLEGRO_EDITOR EDIT_ETCH        Should Plan accurate and Optimize beremoved in 16.6?
1118734 APD           EDIT_ETCH        Multiline routingwith Clines on Null Net cannot route in downward direction
1118756 ALLEGRO_EDITOR SHAPE            Shape clearance parameter oversizevalues getting applied to Keepouts
1119606 CONCEPT_HDL   MARKERS          Filtering two ormore words in Filter dialog box
1119707 CONCEPT_HDL   CORE             Genview does not use site colors when gen schfrom block symbol
1119711 F2B           DESIGNSYNC       DesignDifferences show Net Differences wrongly
1120659 CAPTURE       PROJECT_MANAGER  "Saveproject as" does not support some of Nordic characters.
7 W7 Q7 @% F8 H1120660 CONCEPT_HDL   CORE             Save hierarchysaves pages for deleted blocks.
1120817 SIP_LAYOUT    SYMB_EDIT_APPMOD Rotate pads commands not working while in the SymbolEdit App. mode
- Q4 j# j1 f  z/ I5 w; z0 v/ h1 Q  K8 J1120985 PSPICE        MODELEDITOR      Unable to importattached IBIS model
& T8 }- C. v2 G! w1 G+ v1121171 CONCEPT_HDL   CREFER           PNN and correctproperty values not annotated on the Cref flat schematic
4 I+ |" \; \- q5 L% Q( [1121353 ALLEGRO_EDITOR INTERACTIV       Local env setting will change aftersaving and reopening.
1121382 ALLEGRO_EDITOR INTERACTIV       Undo command is limited to two for thisdesign
' L2 `/ {- p1 H; i* g1121540 F2B           PACKAGERXL       pxl.chg keepsdeleting and adding changes on subsequent packager runs
1121558 ALLEGRO_EDITOR MODULES          Unrouted net and unrouted connectionwhen module is placed of completely routed board file.
1121585 ALLEGRO_EDITOR OTHER            Drill Hole to Shape Same NetSpacing with Dynamic Shapes shows wrong result.
1121651 CAPTURE       SCHEMATIC_EDITOR "PCB editor select" menu option is missing
% C# S* t: b8 t" Z' \1122136 SIP_LAYOUT    PLACEMENT        Moving acomponent results in the components outline going to bottom side of the design.
( B) _2 B, _8 c* I! Q5 ?1122340 CAPTURE       NETLIST_ALLEGRO  Cross probe ofnet within a bus makes Capture to hang.
1122489 CONCEPT_HDL   OTHER            Save _Hierarchycausing baseline to brd files
8 N4 e' j1 X  e( R1122781 CONCEPT_HDL   CORE             cfg_package isgenerated for component cell automatically
1122909 CONCEPT_HDL   CORE             changing versionreplicates data of first TOC on 2nd one
1123150 CONCEPT_HDL   CORE             property on yaxis in symbol view was moved by visibility change to None.
1123176 ALLEGRO_EDITOR UI_FORMS         Negative values for pop-up location isnot retained with multiple monitors (more than 2)
1123815 ALLEGRO_EDITOR GRAPHICS         Embedded netname changes to a differentnetname
' o- W. Z5 `' X- I9 {) S* E1124369 ALLEGRO_EDITOR INTERACTIV       Sliding a shape using iy coordinate doesnot work indepedent of grid.
1124544 CONCEPT_HDL   CORE             About SearchHistory of find with SPB16.5
6 Z, ^1 G  g) |0 ^1124570 APD           IMPORT_DATA      When importingStream adding the option to change the point
1125201 CONCEPT_HDL   CORE             Connectivityedits in NEW block not saved( lost) if block is created using block add
1125314 ALLEGRO_EDITOR INTERACTIV       Enved crash during setting of library paths inuser preference
* i9 g8 T4 p8 ?1125366 CONCEPT_HDL   CORE             DE-HDL crachESDuring Import Physical if CM is open on Linux
+ O9 g# H# A# h: d& D/ t5 o/ W1125628 CONCEPT_HDL   CORE             Crash on doingsave hierarchy
& Z& j% Q& [: J$ p- Y7 G% \" k6 _6 B1130555 APD           WIREBOND         Wirebond Import should connect to pinsof the die specified on the UI.
1131030 PSPICE        ENVIRONMENT      Unregistered iconof Simulation setting in taskbar
5 z! i0 g8 c% O) v1131083 ALLEGRO_EDITOR INTERACTIV       Bug: 16.6 crash in changing the mode inFind filter window
. x0 Z1 w; U* o7 I1131226 ALLEGRO_EDITOR PLACEMENT        When Angle is set in design parameterswhile placement component is rotated but outline is not.
2 z* M/ B8 |; R8 V+ ?1131567 CONCEPT_HDL   OTHER            Lower case valuesfor VHDL_MODE make genview use pin location to determen direction.
1131699 PSPICE        PROBE            Probe windowcrash on trying to view simulation message
/ w; y. s& l$ t8 W0 e1132457 CONCEPT_HDL   CORE             The schematicnever fully invokes and has connectivity errors.
% h# t+ E7 a$ H1132575 CONCEPT_HDL   CORE             2 pin_name weredisplayed and overlapped by spin command.
1132698 ALLEGRO_EDITOR EDIT_ETCH        Slide Via with Segment option with newSlide command
1132964 ALLEGRO_EDITOR SHAPE            Same net "B&B via toshape" errors created when adding shape
1133677 CONCEPT_HDL   CORE             Cant delete norreset LOCATION prop in context of top
1133791 CONCEPT_HDL   CORE             Cant do textjustification on a single selected NOTE in Windows mode.
* }' Y) n) Z* q3 a6 L6 p/ t3 [1134761 CONCEPT_HDL   CORE             Why does MousePointer/Tooltip display LOCATION instead of $LOCATION property
9 Q7 q0 S. e  b- I, Q7 T# S1135118 ALLEGRO_EDITOR INTERACTIV       Mirror and other editing commands aremissing for testpoint label text in general edit mode.
% E  w/ Y5 a& {% X1136420 CAPTURE       GENERAL          Registrationissue when CDSROOT has a space in its path
* ^; Z, X' x0 J% S; K2 T1136808 PSPICE        STABILITY        Pspice crashmarker server has quite unexpectedly
1136840 CAPTURE       SCHEMATICS       Enh: Alignment oftext placed on schematic page
1138586 ADW           MIGRATION        design migrationdoes not create complete ptf file for hierarchical designs
3 Q6 Y. C' p7 h& J: h$ V% J- I1139376 CONCEPT_HDL   CORE             setting wirecolor to default creates new wire with higher thickness
; p3 H  W' f1 H2 p1140819 APD           GRAPHICS         Bbvia does notretain temp highlight color on all layers when selected.
1141300 CONCEPT_HDL   CORE             DE HDL hier_writesave hierarchy log reports summarizes Successfully saved block x while blockwas skipped
1141723 ADW           PURGE            purge commandcrashes with an MFC application failure message
1143448 CAPTURE       GENERAL          About copy &paste to Powerpoint from CIS
8 P0 V  P7 v3 @/ A4 l  u' }/ j1143670 SIP_LAYOUT    OTHER            Cross Probingbetween SiP and DEHDL not working in 16.6 release
3 g5 [& s+ Q9 R: _1143902 ALLEGRO_EDITOR DATABASE         when the shape is rotated 45 degreesthe void is moved.
) m: c# n) N+ K( C: A+ I1144990 PCB_LIBRARIAN CORE             PDV expand &collapse vector pins resizes symbol outline to maximum height
1145112 CONCEPT_HDL   CORE             Warning message:Connectivity MIGHT have changed
5 U0 k2 d* M. `- z2 c0 V1145253 CONCEPT_HDL   CORE             Component Browseradds properties in upper case
1146386 ALLEGRO_EDITOR INTERACTIV       Place Replicate Create add Static shapewith Fillet shape
1146728 F2B           PACKAGERXL       DCF with upperand lower case values on parts causes pxl to fail
1146783 ALLEGRO_EDITOR INTERFACES       Highlighted component is missing fromexported IPF file.
1147326 CONCEPT_HDL   CORE             HDL crashes whentrying to reimport a block
1148337 CAPTURE       ANNOTATE         Checking "refdes control" isnot giving the proper annotation result
1148633 SIP_LAYOUT    INTERACTIVE      Add "%"to the optical shrink option in the co-design die and compose symbol placementforms
1149778 CAPTURE       SCHEMATICS       Rotation of pspice marker before placementis not appropriate
1149987 PCB_LIBRARIAN PTF_EDITOR       Save As pushingthe part name suffix into vendor_part_number value
7 g+ V2 m. F6 O- |1151748 ALLEGRO_EDITOR OTHER            If the pad and cline are the samewidth don't report a missing Dynamic Fillet.
1152206 CONCEPT_HDL   CORE             ROOM Propertyvalue changes when saving another Page
1152755 CONCEPT_HDL   COPY_PROJECT     Copy projecthangs if library or design name has an underscore
1152769 PSPICE        ENCRYPTION       Unable to simulate Encrypted Models in16.6
1153308 ALLEGRO_EDITOR DRC_CONSTR       Creating Artwork Getting Warning"DRC is out of Date" even when DRC is up to date
1153893 F2B           DESIGNVARI       16.6 VariantEditor not supporting - in name
% p6 r# ]% c; r7 v4 s1154185 SIG_INTEGRITY SIGNOISE         Signoise didn'tdo the Rise edge time adjustment.
1154860 ALLEGRO_EDITOR MANUFACT         Double digit drill character overlapswith figures triangle, hexagon and octagon in NC drill legend
+ E, q- D4 h2 T! v4 U) I) c1155167 ALLEGRO_EDITOR EDIT_ETCH        Via structure placed in Create Fanouthas incorrect rotation.
( r/ y) y2 F+ H8 _  p# _1155728 CONCEPT_HDL   CORE             Unable to uprevpackaged 16.3 design in 16.5 due to memory
1155855 SCM           SCHGEN           A newlyuser-defined net property is not transferred from SCM to DEHDL in PreservedMode
1156274 ALLEGRO_EDITOR INTERFACES       Exported Step file from Allegro is wrong
+ y# b$ k  |& U1156316 CONSTRAINT_MGR OTHER            Break in functionality whilecreation of pin-pairs under Xnet in Constraint Manager
9 t& g& I5 v: n0 R1 K: \# Z& `1156351 CONCEPT_HDL   CONSTRAINT_MGR   Loose members inPhysical Net Class between DEHDL and Allegro
1156547 ALLEGRO_EDITOR DRC_CONSTR       Etch Turn under SMD pin rule checkthrough pin Etch makes confused.
6 j$ T. g2 ]' S" h' n7 U, P1156779 CONSTRAINT_MGR OTHER            Electrical Cset References in CM notworking correctly
1157167 ALLEGRO_EDITOR skill            axlPolyFromDB with ?line2poly isbroken
1158042 ALLEGRO_EDITOR DFA              DFA_DLG writes the dra file namein uppercase.
1158718 CONCEPT_HDL   CHECKPLUS        Customer couldnot get $PN property values on logical rule of CheckPlus16.6.
- ?6 W- M) N8 [. B1158970 ALLEGRO_EDITOR SCHEM_FTB        Changing LOCATION to $LOCATION in DEHDLdoes not update the .brd file
. W8 m1 M2 U9 g1158989 ALLEGRO_EDITOR INTERFACES       pdf_out -l creates a PDF
1159285 APD           DXF_IF           DXF_OUT fails;some figures are not exported
, d& |1 m/ Z6 M% r0 {+ f1159432 ALLEGRO_EDITOR SHOW_ELEM        http:// in the Show Element in 166 donot have HTML link to open the Website
1159483 PCB_LIBRARIAN SETUP            part developercrashing with
1159516 ALLEGRO_EDITOR EDIT_ETCH        Unable to slide cline segment with newslide.
1159959 ALLEGRO_EDITOR GRAPHICS         3D viewer displays clines arcsincorrectly
2 T6 {5 m& U( g6 ?4 c# s3 ?1160004 SCM           UI               The RMB->Pastedoes not insert signal names.
" }* Q% e, |' f' w( d# Z1160410 ALLEGRO_EDITOR DATABASE         Lock databse with View Lock option ismisleading
1160529 SCM           SCHGEN           Schematicgeneration stopped because the tool was unable to create an appropriateinternal symbol structure
1160537 SPIF          OTHER            Cannot start PCBRouter
1161363 ALLEGRO_EDITOR SYMBOL           Getting error SPMHGE-73 when tryingto mirror symbol
: c9 E* S; }4 U" e  d1161781 CONSTRAINT_MGR CONCEPT_HDL      SigXp crash when selecting ECset indesign
1161896 ALLEGRO_EDITOR DRAFTING         Tolerance value added for Dimensionsis not working correctly (HF11-12)
, F* v* B# n/ Q1 F# Y, X" N" B1162193 SIP_LAYOUT    DIE_ABSTRACT_IF  shapes in diafile not linked to the die after edit co-design die
, O$ f8 p' j5 |9 h$ `1162754 APD           VIA_STRUCTURE    Replace Via Structurecommand selecting dummy nets.