|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 pzt648485640 于 2013-10-16 22:11 编辑
' n8 b. c4 v& C8 p3 E ^! X* U6 [1 M
下载地址：http://pan.baidu.com/s/1kmHkL
! Q: e4 l9 q( d" ?" f* p" i
# n# f- O- D' N" S百度网盘 在hotfix附录里
4 T$ ~9 t( w3 E9 r0 |6 v. \) \, t% i$ R' n; y. O
+ h1 T* n3 z5 R( Y- t& \
$ S: H. ~3 s& z9 I* a0 kDATE: 10-10-2013 HOTFIX VERSION: 017* Y/ O( U# \- b# o5 U2 P1 R* N8 f
" q# Q; y: Y) e4 G+ Z
===================================================================================================================================
: Z2 [1 w6 A6 B G& e* ^
* R' q' U. g. x l' b7 G6 k& WCCRID PRODUCT PRODUCTLEVEL2 TITLE
3 d3 g4 Y9 g6 N0 E0 ]/ O
' H. {, ? h( \6 z! T5 Y===================================================================================================================================9 ^* M& H% Y9 ~7 _: Q" ~- n, i
# I) `; Z+ G+ ~+ K) j/ J# w# P1 J* O5 s: E735992 ADW LIB_FLOW Create Test Schematic does not use the correct package type1 N( W L* E0 q& y2 g2 B
e3 ?" v( E8 M% t& j. ?; @) M4 u
1121403 FSP PROCESS "Assign to Pin" not getting obeyed by Synthesis.
. ]1 A3 p9 `6 K( A3 T9 v- w% y7 L; ~6 o2 I5 C+ ^2 a0 B$ h( _
1141844 RF_PCB DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing* @; m& Q" W3 H3 {( B' w& @
; r* n" p$ f5 B! x1 @, m1169269 allegro_EDITOR DRAFTING Dimension placed on package symbol moves to different place when it is placed on brd file., u; n: n1 `& c7 o* q# A# l
' G* J) ~: c1 u# E$ [8 [4 q1170488 ALLEGRO_EDITOR MANUFACT Dimension text(on .psm) move to different position, when it is placed on .brd.
4 Q% u5 D& r+ P! w0 j- V. z a3 o: w6 E# q5 C1 G8 f
1173345 CIS CRYSTAL_REPORTS Crystal Report - Display Parameter dialog for export option' {3 v9 m. t3 Q7 \
W8 D# c& x- e( B8 B: ^, X1181759 SCM LVS SCM Crash when doing update all that executing import physical command.
- u% C# `4 Q9 j) I; v; w n9 b T; I7 S$ C* S' G2 e5 O# }& M
1182499 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks (all pins and via) drill.
% j' X4 }* w8 |9 [ J, Q" X( L. N0 ~6 R6 R1 I) Q/ V+ P* E
1184682 concept_HDL CONSTRAINT_MGR Net Constraint not transferring to layout from schematic" q- L% E Q3 o+ h" T
& V# d2 b) R2 s0 ?; I3 k" k
1185524 F2B PACKAGERXL Enhancement User would like notification of pack_short in pxl.log
! q7 |% z; y8 P1 q$ j' T! f# [+ Y0 B, J/ ]' m) u
1185902 ALLEGRO_EDITOR SHAPE Update shapes dont clear some diffpairs in HF15; b" W+ K7 p+ s9 B# `
. q8 b( A0 Q8 H) M( B
1186152 ADW LRM Part Status for Deleted Part in LRM is distinguished with other part status
. a$ v# o6 n* t# |0 C6 D$ {2 {0 ?7 C
1186387 ALLEGRO_EDITOR OTHER DXF cannot catch offset value in s047 hotfix.
- I. w' f b' ]( J" Z* b/ A' b1 n+ a# `( U
1186805 ALLEGRO_EDITOR OTHER Exported STEP file missing multiple components placed on board
" ? P& T# s6 f4 F. T# Y# [& F1 c+ l: d7 [/ A; H+ k
1186818 ALLEGRO_EDITOR COLOR Custom color not retained during dehilight
. B4 `! c+ n" Q3 O; y3 Z) b6 u6 v* `' u2 F0 P% s
1187196 CONCEPT_HDL CORE TOC not populating (page 1): O7 ?) S1 { M4 A
" s; c0 E8 }, h1187667 F2B PACKAGERXL Existing hard LOCATION property in drawing was left unchanged; B! {* w2 g3 Y4 s8 G0 ^4 B4 r0 A
4 Z- e h7 ?( {% T1188264 ALLEGRO_EDITOR MODULES Some fillets not regenerated in module created from a board file./ t; O. v4 ~; s9 a0 b0 a
" \3 p, h6 T% k, C9 R( |' d1190144 ALLEGRO_EDITOR OTHER Fillet shape is not genrated around cline
2 _. w9 {5 d& m
( X; a1 H3 w2 t0 Z( C" y" [1190210 F2B BOM The bomhdl.exe fails - MFC Application has Stopped Working
! N% g" ~. o: a' {& \: p2 h$ C9 u
8 G6 }5 c: M0 x' j) R1 b+ w0 e1190618 ALLEGRO_EDITOR GRAPHICS Enhancement for Visible grid3 {8 U6 N4 l* C& K/ X
( _& S$ N% @+ q4 Z- {! M9 D& o+ z1190813 ALLEGRO_EDITOR INTERFACES 3rd party netlist file in TEL format fails syntax check but imports successfully
' b/ }7 `, H* R. c, E% c7 I z7 ^" x; z, y3 v: h* w
1190895 ALLEGRO_EDITOR EDIT_ETCH Route delay meter displays violation when sliding diff pair
/ @% n1 M7 ?8 Y+ E
+ \* M2 f! Q- S' j5 c1190908 F2B OTHER DE-HDL aborts if dummy net is being cross-probed from PCB Editor
0 G7 q# i5 p3 c7 g C C" w4 E
, L" U, g1 O9 Z1190990 CONCEPT_HDL CORE Mismatch in .csa and .csb files
0 X- R M0 Q( W8 n% @$ x
4 {8 l( L G+ B1 S$ {1191008 CONCEPT_HDL CORE Remove Binary File feature doesn't work
. I A) Z; ^* a! x; u5 S
6 P5 x$ Q9 @% m9 T8 B1191514 SCM PACKAGER Packaging error PKG-1001 X+ Z, M) l) g- o6 T: D1 ?' _
/ T. C2 R( w) s. l# x
1191517 ALLEGRO_EDITOR DRAFTING Metric +tolerance when using dual dimensions is not displayed correctly
' K ]2 D0 ^8 C+ b' D# k# U3 q
/ f+ c4 |8 y. r% S* F0 `0 V1192561 ALLEGRO_EDITOR GRAPHICS Padstack with offset is not showing correctly in the 3D Viewer." w% k! T" I$ E+ k% ]
* Q, c% J* L8 s3 _
1192916 ALLEGRO_EDITOR EDIT_ETCH Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.
; ]$ N4 f/ i$ E5 m
( F7 l9 [! H. _% q/ S, {1194197 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks.
1 Z$ ~+ E- x8 X: ?4 W7 a6 f1 d3 A/ t$ q
1194239 Pspice DEHDL Associate Model does not launch from DE-HDL* Y# m0 @/ S3 c# q
1 j0 ~. g/ h- T6 L( Q1194736 PSPICE SIMULATOR Design causes RPC failure when run consectively
5 p( Q9 t# G' K1 e
+ f& M1 c+ o V2 q/ {1195139 ALLEGRO_EDITOR PLACEMENT Components disappears from board file once they moved1 a' \& T% d2 k* d$ u
|
|
/1 
发表于 2013-10-15 10:33
收藏
淘帖
支持！
反对！
