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本帖最后由 pzt648485640 于 2013-10-16 22:11 编辑 5 h& k# V* `3 E3 H2 Z7 m
( G0 I9 T& j3 o* D h; ^下载地址：http://pan.baidu.com/s/1kmHkL
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$ y4 }: p( F8 k0 N: n百度网盘 在hotfix附录里 h& ^: R1 O u: p- M* X3 R5 y' ~2 G6 q
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2 G+ r9 Y2 _# H4 E/ ]DATE: 10-10-2013 HOTFIX VERSION: 0174 \' }9 h. E M6 @5 O* X {+ O
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+ ?2 m1 ~( \9 r: R% {735992 ADW LIB_FLOW Create Test Schematic does not use the correct package type% M; Q# ]8 b" h1 Y8 h8 V
1 w) d5 @' j2 P1121403 FSP PROCESS "Assign to Pin" not getting obeyed by Synthesis.
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1141844 RF_PCB DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing
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1169269 allegro_EDITOR DRAFTING Dimension placed on package symbol moves to different place when it is placed on brd file.
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' |" [$ d. X# P. ] N& M' y5 ? y1170488 ALLEGRO_EDITOR MANUFACT Dimension text(on .psm) move to different position, when it is placed on .brd.. W% f3 l1 O' c
# n; U! B- g* H# D0 w' d" O1173345 CIS CRYSTAL_REPORTS Crystal Report - Display Parameter dialog for export option
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( a2 E6 q3 V" |1181759 SCM LVS SCM Crash when doing update all that executing import physical command.
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& J3 H- V W9 H# ^. q: [, c/ l: M1182499 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks (all pins and via) drill.
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( T# g3 _1 {3 p- u" H+ Y1184682 concept_HDL CONSTRAINT_MGR Net Constraint not transferring to layout from schematic) ?9 f' S! j r
" G: k; p+ G Q; p: R) U1185524 F2B PACKAGERXL Enhancement User would like notification of pack_short in pxl.log- q# X: z; k9 P& N
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1185902 ALLEGRO_EDITOR SHAPE Update shapes dont clear some diffpairs in HF15
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: j- r" N4 j1 S }, V1 G) J1186152 ADW LRM Part Status for Deleted Part in LRM is distinguished with other part status
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/ Y" y9 e5 U: }' {! n F, M9 ]! I1186387 ALLEGRO_EDITOR OTHER DXF cannot catch offset value in s047 hotfix.5 }) n, c, j" p3 G" ~9 J/ f
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1186805 ALLEGRO_EDITOR OTHER Exported STEP file missing multiple components placed on board
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1186818 ALLEGRO_EDITOR COLOR Custom color not retained during dehilight: v3 `1 O0 \$ e5 j2 E
) r) f- A$ Q% W1187196 CONCEPT_HDL CORE TOC not populating (page 1)
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1187667 F2B PACKAGERXL Existing hard LOCATION property in drawing was left unchanged
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1188264 ALLEGRO_EDITOR MODULES Some fillets not regenerated in module created from a board file.0 X( _+ t' x/ `& r8 l e2 Q* k
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1190144 ALLEGRO_EDITOR OTHER Fillet shape is not genrated around cline" H9 t2 B3 \& k; v- M* F( c
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1190210 F2B BOM The bomhdl.exe fails - MFC Application has Stopped Working- o1 U6 o" a, A9 c
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1190618 ALLEGRO_EDITOR GRAPHICS Enhancement for Visible grid
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" `/ i! f0 q0 @1 G7 l. @/ q+ \0 `1190813 ALLEGRO_EDITOR INTERFACES 3rd party netlist file in TEL format fails syntax check but imports successfully% M: i- f) |8 K# N* m
) M& [2 t( X" C! P, v1190895 ALLEGRO_EDITOR EDIT_ETCH Route delay meter displays violation when sliding diff pair; Q' c- @7 ^$ p
$ C5 H6 j. K8 w3 m# b/ m1190908 F2B OTHER DE-HDL aborts if dummy net is being cross-probed from PCB Editor
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1190990 CONCEPT_HDL CORE Mismatch in .csa and .csb files6 w' |( b) R% g$ J
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1191008 CONCEPT_HDL CORE Remove Binary File feature doesn't work
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1191514 SCM PACKAGER Packaging error PKG-100( p7 t, L; Y+ W1 p! d
. _1 ^, @1 L6 [3 l1191517 ALLEGRO_EDITOR DRAFTING Metric +tolerance when using dual dimensions is not displayed correctly% L2 [( w9 Q/ D' F: O# K
9 R* y0 C& o7 Z# s( R3 D1192561 ALLEGRO_EDITOR GRAPHICS Padstack with offset is not showing correctly in the 3D Viewer.7 N5 |2 ?; k4 `
/ ^0 ]. T- D+ z& \0 L1192916 ALLEGRO_EDITOR EDIT_ETCH Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.
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: Q. [8 Q* a+ p, K e8 `1194197 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks.
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6 ?5 ~, f9 _1 {3 E1194239 Pspice DEHDL Associate Model does not launch from DE-HDL8 p& U. s8 D6 \2 ^5 N9 [ F
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1194736 PSPICE SIMULATOR Design causes RPC failure when run consectively
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4 ^; Y. a3 E( |5 X* h. K- u _1195139 ALLEGRO_EDITOR PLACEMENT Components disappears from board file once they moved: F+ t3 y* X+ y' {3 `6 U
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发表于 2013-10-15 10:33
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