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本帖最后由 pzt648485640 于 2013-10-16 22:11 编辑
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: k; G" s/ C2 f6 f X8 f O4 {9 g下载地址：http://pan.baidu.com/s/1kmHkL0 `7 D' f3 I4 l
% v" s V3 H% A+ r4 g# I1 U百度网盘 在hotfix附录里% T6 J# C6 v2 P, P3 t; i( n' I; X
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DATE: 10-10-2013 HOTFIX VERSION: 017; [' x, y7 q6 v N
7 H! ]+ `3 W9 r) G* b; z===================================================================================================================================) ]' g' a- V& k
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CCRID PRODUCT PRODUCTLEVEL2 TITLE% A( Y) Q# s9 q3 ]
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===================================================================================================================================
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735992 ADW LIB_FLOW Create Test Schematic does not use the correct package type
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7 l/ ^% q# j) r0 a# m6 a. C1121403 FSP PROCESS "Assign to Pin" not getting obeyed by Synthesis.
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1141844 RF_PCB DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing
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: U$ [& Y( s8 R7 g8 Z' h1169269 allegro_EDITOR DRAFTING Dimension placed on package symbol moves to different place when it is placed on brd file.- X% J8 c+ i( |8 i/ M
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1170488 ALLEGRO_EDITOR MANUFACT Dimension text(on .psm) move to different position, when it is placed on .brd.4 z" x7 r' D i$ |0 y
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1173345 CIS CRYSTAL_REPORTS Crystal Report - Display Parameter dialog for export option
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; ] g; `4 m v: U# ?2 o1 Q2 }1181759 SCM LVS SCM Crash when doing update all that executing import physical command.# R$ I# {' V0 ^9 o; ]+ u, O; |
& s; h/ Z6 l6 _2 v8 `4 i5 R1182499 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks (all pins and via) drill.
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1 }5 a* s3 q6 M- ?/ Y1184682 concept_HDL CONSTRAINT_MGR Net Constraint not transferring to layout from schematic: I; E. \# o2 i" P
" S( r% ^4 P) d# k \) O7 `. D1185524 F2B PACKAGERXL Enhancement User would like notification of pack_short in pxl.log
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1185902 ALLEGRO_EDITOR SHAPE Update shapes dont clear some diffpairs in HF15& G8 l6 }8 w$ J1 `" j
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1186152 ADW LRM Part Status for Deleted Part in LRM is distinguished with other part status+ D. ^: | E- j" N; L, o% R& H, v
0 O5 _0 M/ z% R1 S+ m+ r" s8 ^1 ~- {1186387 ALLEGRO_EDITOR OTHER DXF cannot catch offset value in s047 hotfix. f" M) y; q! b( J
/ ?. v) O% A6 @! Z9 m- C1186805 ALLEGRO_EDITOR OTHER Exported STEP file missing multiple components placed on board- @0 d8 K% b4 ~' a! c* Y3 Q& u7 V
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1186818 ALLEGRO_EDITOR COLOR Custom color not retained during dehilight
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0 J2 S0 X5 d1 X8 |4 I9 K1187196 CONCEPT_HDL CORE TOC not populating (page 1)
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1187667 F2B PACKAGERXL Existing hard LOCATION property in drawing was left unchanged# c- Z; [! y" a6 g
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1188264 ALLEGRO_EDITOR MODULES Some fillets not regenerated in module created from a board file.' Q1 M) x- |2 B' S* v# k/ y
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1190144 ALLEGRO_EDITOR OTHER Fillet shape is not genrated around cline7 b) W7 U) Z! b
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1190210 F2B BOM The bomhdl.exe fails - MFC Application has Stopped Working! I$ g% D# L# j, U& h% y/ d
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1190618 ALLEGRO_EDITOR GRAPHICS Enhancement for Visible grid# ]" B9 H J+ X2 Y
9 H0 {9 [5 o0 y/ \1190813 ALLEGRO_EDITOR INTERFACES 3rd party netlist file in TEL format fails syntax check but imports successfully0 t% X. `, i" k0 R3 r/ Y
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1190895 ALLEGRO_EDITOR EDIT_ETCH Route delay meter displays violation when sliding diff pair
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1190908 F2B OTHER DE-HDL aborts if dummy net is being cross-probed from PCB Editor- X! u; [! T$ o/ \: u! h/ q) c
' Q% W, x6 R1 D& `% V1190990 CONCEPT_HDL CORE Mismatch in .csa and .csb files
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1191008 CONCEPT_HDL CORE Remove Binary File feature doesn't work' M C+ X% w: G6 F+ F
2 G% J D3 A. h' j- Z, q0 G1191514 SCM PACKAGER Packaging error PKG-100
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; b+ P1 L9 r& U3 _' {1191517 ALLEGRO_EDITOR DRAFTING Metric +tolerance when using dual dimensions is not displayed correctly
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- U$ A; f" E( @1192561 ALLEGRO_EDITOR GRAPHICS Padstack with offset is not showing correctly in the 3D Viewer.
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+ X" T6 k- j: f: `. f# {1192916 ALLEGRO_EDITOR EDIT_ETCH Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.
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1194197 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks.0 @! j* ~; S1 I9 L3 l( Z% a
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1194239 Pspice DEHDL Associate Model does not launch from DE-HDL7 D! r0 a% o) u: {# E' C
: X9 o% r ]/ [6 F) G1194736 PSPICE SIMULATOR Design causes RPC failure when run consectively
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1195139 ALLEGRO_EDITOR PLACEMENT Components disappears from board file once they moved2 u9 T0 N. I& p* I5 V
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发表于 2013-10-15 10:33
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