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Hotfix_SPB16.60.017_wint_1of1.exe

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1#
发表于 2013-10-15 10:33 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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本帖最后由 pzt648485640 于 2013-10-16 22:11 编辑
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下载地址:http://pan.baidu.com/s/1kmHkL
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# n# f- O- D' N" S百度网盘 在hotfix附录里
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$ S: H. ~3 s& z9 I* a0 kDATE: 10-10-2013   HOTFIX VERSION: 017* Y/ O( U# \- b# o5 U2 P1 R* N8 f
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===================================================================================================================================
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* R' q' U. g. x  l' b7 G6 k& WCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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' H. {, ?  h( \6 z! T5 Y===================================================================================================================================9 ^* M& H% Y9 ~7 _: Q" ~- n, i

# I) `; Z+ G+ ~+ K) j/ J# w# P1 J* O5 s: E735992  ADW            LIB_FLOW         Create Test Schematic does not use the correct package type1 N( W  L* E0 q& y2 g2 B
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1121403 FSP            PROCESS          "Assign to Pin" not getting obeyed by Synthesis.
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1141844 RF_PCB         DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing* @; m& Q" W3 H3 {( B' w& @

; r* n" p$ f5 B! x1 @, m1169269 allegro_EDITOR DRAFTING         Dimension placed on package symbol moves to different place when it is placed on brd file., u; n: n1 `& c7 o* q# A# l

' G* J) ~: c1 u# E$ [8 [4 q1170488 ALLEGRO_EDITOR MANUFACT         Dimension text(on .psm) move to different position, when it is placed on .brd.
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1173345 CIS            CRYSTAL_REPORTS  Crystal Report - Display Parameter dialog for export option' {3 v9 m. t3 Q7 \

  W8 D# c& x- e( B8 B: ^, X1181759 SCM            LVS              SCM Crash when doing update all that executing import physical command.
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1182499 ALLEGRO_EDITOR OTHER            Step export to include through hole padstacks (all pins and via) drill.
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1184682 concept_HDL    CONSTRAINT_MGR   Net Constraint not transferring to layout from schematic" q- L% E  Q3 o+ h" T
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1185524 F2B            PACKAGERXL       Enhancement User would like notification of pack_short in pxl.log
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1185902 ALLEGRO_EDITOR SHAPE            Update shapes dont clear some diffpairs in HF15; b" W+ K7 p+ s9 B# `
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1186152 ADW            LRM              Part Status for Deleted Part in LRM is distinguished with other part status
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1186387 ALLEGRO_EDITOR OTHER            DXF cannot catch offset value in s047 hotfix.
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1186805 ALLEGRO_EDITOR OTHER            Exported STEP file missing multiple components placed on board
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1186818 ALLEGRO_EDITOR COLOR            Custom color not retained during dehilight
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1187196 CONCEPT_HDL    CORE             TOC not populating (page 1): O7 ?) S1 {  M4 A

" s; c0 E8 }, h1187667 F2B            PACKAGERXL       Existing hard LOCATION property in drawing was left unchanged; B! {* w2 g3 Y4 s8 G0 ^4 B4 r0 A

4 Z- e  h7 ?( {% T1188264 ALLEGRO_EDITOR MODULES          Some fillets not regenerated in module created from a board file./ t; O. v4 ~; s9 a0 b0 a

" \3 p, h6 T% k, C9 R( |' d1190144 ALLEGRO_EDITOR OTHER            Fillet shape is not genrated around cline
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( X; a1 H3 w2 t0 Z( C" y" [1190210 F2B            BOM              The bomhdl.exe fails - MFC Application has Stopped Working
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8 G6 }5 c: M0 x' j) R1 b+ w0 e1190618 ALLEGRO_EDITOR GRAPHICS         Enhancement for Visible grid3 {8 U6 N4 l* C& K/ X

( _& S$ N% @+ q4 Z- {! M9 D& o+ z1190813 ALLEGRO_EDITOR INTERFACES       3rd party netlist file in TEL format fails syntax check but imports successfully
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1190895 ALLEGRO_EDITOR EDIT_ETCH        Route delay meter displays violation when sliding diff pair
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+ \* M2 f! Q- S' j5 c1190908 F2B            OTHER            DE-HDL aborts if dummy net is being cross-probed from PCB Editor
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, L" U, g1 O9 Z1190990 CONCEPT_HDL    CORE             Mismatch in .csa and .csb files
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4 {8 l( L  G+ B1 S$ {1191008 CONCEPT_HDL    CORE             Remove Binary File feature doesn't work
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6 P5 x$ Q9 @% m9 T8 B1191514 SCM            PACKAGER         Packaging error PKG-1001 X+ Z, M) l) g- o6 T: D1 ?' _
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1191517 ALLEGRO_EDITOR DRAFTING         Metric +tolerance when using dual dimensions is not displayed correctly
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/ f+ c4 |8 y. r% S* F0 `0 V1192561 ALLEGRO_EDITOR GRAPHICS         Padstack with offset is not showing correctly in the 3D Viewer." w% k! T" I$ E+ k% ]
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1192916 ALLEGRO_EDITOR EDIT_ETCH        Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.
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( F7 l9 [! H. _% q/ S, {1194197 ALLEGRO_EDITOR OTHER            Step export to include through hole padstacks.
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1194239 Pspice         DEHDL            Associate Model does not launch from DE-HDL* Y# m0 @/ S3 c# q

1 j0 ~. g/ h- T6 L( Q1194736 PSPICE         SIMULATOR        Design causes RPC failure when run consectively
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+ f& M1 c+ o  V2 q/ {1195139 ALLEGRO_EDITOR PLACEMENT        Components disappears from board file once they moved1 a' \& T% d2 k* d$ u
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    [LV.4]偶尔看看III

    5#
    发表于 2013-10-20 22:19 | 只看该作者
    刚装上还没用过

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    6#
    发表于 2013-10-21 16:00 | 只看该作者
    cadence当之无愧的补丁王。

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    7#
    发表于 2013-10-23 11:50 | 只看该作者
    补丁王
    : _* U& t$ h7 V坐等某天科通的START PAGE刷出S018
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