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DATE: 02-07-2014 HOTFIX VERSION: 022
# X) a; o& j' ^( b( I/ N===================================================================================================================================/ k* l! s. \$ y4 ^' q6 _
CCRID PRODUCT PRODUCTLEVEL2 TITLE
, O3 h$ T0 A; L) f" @9 ^===================================================================================================================================, p# g* c: v7 x& \
192358 ALLEGRO_EDITOR PADS_IN Pad_in does not translate some copper shapes
8 A0 m8 A' s. j% t+ z222141 ALLEGRO_EDITOR PADS_IN PADS_IN: Extra shapes are created whenimporting PADS design
; S% K7 h6 c. ]/ W1 O274314 ALLEGRO_EDITOR PADS_IN PAD_in boundary defined for flooded area be translated DYN
, d# Q. g/ Y4 y8 s- ?413919 ALLEGRO_EDITOR PADS_IN pads_in cannot import width of refdes.! H2 B2 J4 @" t' ?% L, q
609053 ALLEGRO_EDITOR PADS_IN "Mils to oversize" of "pads in" did not workcorrectly for MM data.1 _/ B: f2 }8 y2 J9 s9 h
666214 CONCEPT_HDL OTHER Option to increase Line thicknessin publishpdf utility
% R2 q4 @- O2 w/ }0 [0 v2 x738482 ALLEGRO_EDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphicscard7 {, C2 ?/ ?1 W; e9 `
982950 CONCEPT_HDL OTHER change the mouse button for thestroke to have same function with in pcb editor- L# V; k* G4 [) X
1020886 SIP_LAYOUT LEFDEF_IF a quicker way to promote die pins (byimporting macro_pin list), x+ {& Z3 @9 \( p9 V: u- O7 e* C
1032678 CIS VIEW_DATABASE_PA View Database Partgives incorrect result in complex design with variants.
7 w) G; v+ E5 l# L! t8 O1033864 ALLEGRO_EDITOR PADS_IN pads_in doesnot translates teardropspresent in design
4 e2 T, B, W: |1054862 CONCEPT_HDL OTHER Option to increase Linethickness in publishpdf utility; r# Q( Y. t3 L2 K
1055252 FSP PROCESS Add a synthesis option to target agroup to contiguous or consecutive banks) r/ L# Y& c' v( w1 M' Z
1100772 CONSTRAINT_MGR OTHER In Constraint Manager > DRC >Spacing the Show Element DRC totals are wrong.
7 @! |" T i" Q* V2 O1135020 CIS DESIGN_VARIANT Variant list is showing wrong results forhierarchical designs
4 }1 e- I* D! A- m1138951 SIP_LAYOUT DIE_ABSTRACT_IF Fix die abstract r/w to properly supportpinnumbers on ports7 X7 P, x, l( Y# |3 S+ ~" i; Q
1140042 CONSTRAINT_MGR OTHER Diff_Pair lengths and analysis arelost after closing and opening Constraint Manager.
+ d1 j& C$ }( v0 i* j1143662 ALLEGRO_EDITOR INTERACTIV Enhancement Request for RMB - Snap Pickto options increased to include Pin edge7 a0 M& i3 E. m) _+ h
1147961 PSPICE SIMULATOR Simulation produces no output data
" u. n% v! I, w( ]! q/ K4 S1150874 ALLEGRO_EDITOR PADS_IN Dimensions in PADS are not translatedcorrectly during pads_in translation- B7 ~$ ?( V/ S; x9 Z. t
1154184 CONSTRAINT_MGR CONCEPT_HDL Difference in the way topology isextracted in 16.3 versus 16.63 [! j4 o! X, N1 e; |$ e! z A# {
1154770 CAPTURE PROPERTY_EDITOR Variant Name property doesn't show value inVariant View mode f& L, `" n& f& P# O
1158350 CONCEPT_HDL CORE Need a warning Message whileimporting a 16.3 sub-design in a 16.6 Design
9 x4 w. a$ [) F w3 ]1162347 ALLEGRO_EDITOR EDIT_ETCH Enh- Allow new option in Move commandsuch that it allows stretching etch using only 45/90 degree segments directly7 h/ C1 X2 ~4 U7 T* U/ Y
1165553 ALLEGRO_EDITOR INTERACTIV Subclass list invoked from the statuswindow does not represent correct colors.# @' I3 e% {, w% P- o$ Z
1168079 FSP MODEL_EDITOR Clicking OK or Save As in rules editorallows user to overwrite the master with no warning' a% p" R: F# Z
1172043 SCM OTHER : in pin name causes SCM to crash+ H; S- e9 o3 Y. `& ^9 f0 q4 W. d
1172207 CAPTURE STABILITY Capture crash while adding new partfrom Spreadsheet
6 x: I# o5 ]& [8 o2 q. k s- q1172743 ADW TDA Allowed character set for thecheck-in comments is too limited
5 L( N7 u5 S e: f1174099 SIP_LAYOUT WIREBOND Option to reconnect wire based on 縫in name� in the Wire Bond Replace. x) _: q- a& q: ^+ q
1177672 APD IMPORT_DATA Netlist-in wizard didn縯 provide detail information about whatcolumns have been ignored by import process
5 Q3 A4 [! m% d7 f# K1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATIONproperty can not be set to invisible
% d! j8 X' n8 j$ |$ F1177820 CONSTRAINT_MGR INTERACTIV Done the Allegro command when attemptingto launch CM
2 @: g8 Y+ O7 W8 N1178586 ALLEGRO_EDITOR EDIT_SHAPE Number of digits displayed after thedecimal point of Shape Creation function does not match the Accuracy of BRD
$ T% p. X2 o6 e6 F5 n! Z5 l4 i1179688 PSPICE STABILITY pspice crash for particular HOMEvariable vlaue0 s+ v$ |8 F( @9 T! x
1179827 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to Symbolexport - enable field to add Keywords for data fields to excell cells/ ]& D9 v, y; e) f- Y& z. W
1179879 SIP_LAYOUT STREAM_IF Data file corrupt when exporting Streamdata from SiP database.
! E$ \1 K( E* X) g. J% k% g1180164 F2B BOM BOM csv data format converts toexcel formats
V" X$ y0 \7 a. n& @1180477 ALLEGRO_EDITOR INTERFACES IPC-356 output is listing a duplicatelocation in the comment section- l4 H: r& ~+ p ^, y
1180932 SIP_LAYOUT OTHER SiP Layout - Symbol to Spreadsheetadd option for writing to existing spreadsheet
5 v3 x: D4 P! {9 N" o1181377 ALLEGRO_EDITOR INTERACTIV Pick Releative does not work correctlywith RMB-Move Vertex$ k) Z6 i: Q, M
1181516 ALLEGRO_EDITOR DRC_CONSTR Getting a "Thru Pin to RouteKeepout Spacing" when there should not be one.
/ i% k7 x `: A- r1181739 GRE CORE Running Plan > Spatial crashesGRE
& c+ w" M/ ]1 V3 ^7 o1181935 ALLEGRO_EDITOR DATABASE Enh. Property that allows internal C-CDRC errors6 O% r" t- P/ S8 E3 {! h% t
1182185 SIP_LAYOUT OTHER SiP Layout - Import symbolspreadsheet - suppress Family for the font in the XML spreadsheet
7 q2 M" U: }5 i. B1182566 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to symbol- Enhance ability of spreadsheet exchange to allow for a portion of a full pinmap: d2 z7 y! p! q$ c$ Y3 F
1182599 CONSTRAINT_MGR DATABASE CM Prop Delay Actuals do not updateafter Z Axis option is turned ON or OFF and Analyze is run., H' D, F3 O: x' J. o+ l
1182892 CAPTURE SCHEMATIC_EDITOR Pspice marker rotationbefore placement% p" n* z7 y4 n
1183682 ALLEGRO_EDITOR DRC_CONSTR Implement Nodrc_Sym_Pin_Soldermask &Nodrc_Sym_Pin_Pastemask to symbol level
) X2 _. u1 I5 C, j! g1185445 SIP_LAYOUT DIE_ABSTRACT_IF Die abstract export needs to be able toselect xda file type when browsing8 C6 G* n: ^# k- k
1185932 ALLEGRO_EDITOR SHAPE Soldermask in solder mask void DRC
3 S+ j: [8 U; o4 b1 x @, p1185946 CONCEPT_HDL CORE Ericsson perfomance testing report5 sept 2013
7 d- O. V2 F( @/ L# w; j1187213 FLOWS PROJMGR Unable to lock the directive:backannotate_forward
- p6 }2 c! @' r# \* W1187444 ALLEGRO_EDITOR DRC_CONSTR With this design Database check promptserror "SPMHGE-47: Error in call to batch DRC"
* P$ @4 O0 M7 q8 ~) P& L' m1187597 ALLEGRO_EDITOR DRC_CONSTR No Package to Package Spacing DRC error,when symbol overlap sideways at 45 degree.2 M' ?8 ^) b: x
1187723 FSP PROCESS Synthesis can fail depending on componentplacement
. m2 @! q" r. w* U- d1188164 SIP_LAYOUT OTHER SiP Layout - Spreadsheet interfacesImport Export and Add Component - include Keyword for NET_GROUP+ E6 a6 ?( c" N" w, I
1188245 CONCEPT_HDL CORE INFO(SPCOCN-2055): You cannot runthe CHANGE command in a read only schematic
- F. C! d- B2 H) {+ s9 g2 [1190927 CONCEPT_HDL CORE Check sheet does not reportshorted signal/power nets if power symbol is connected to a pin
G+ ?4 R- s- t# q$ O1191497 ALLEGRO_EDITOR INTERACTIV ENH: Adding names to the text blockparameters numbers
( B/ v j: M; Q1192005 SIP_LAYOUT IMPORT_DATA Import SPD2 is missing 1 smart metalshape from file
( z. c: n* O: ^3 _& ~6 h1192204 ALLEGRO_EDITOR EXTRACT Need ability to extract vias that arelabeled as microvia
1 R6 t: m: }. t1 i: `1193063 ALLEGRO_EDITOR MANUFACT TestPrep log displays "Pin is notaccessible from bottom". The component is through hole.1 ]5 `& |( c4 U2 V
1193418 ALLEGRO_EDITOR GRAPHICS 3D Viewer can`t export image in both SPB166S015 and SPB165S047
, n2 M# r8 y1 }) b3 b: \1194305 SIP_LAYOUT EXPORT_DATA export package overlay creates file withno package info. W, e* n2 E4 `2 K, F: d
1194418 APD IMPORT_DATA issue when doFile->import->netlist-in wizard# Z6 { i( a& }" U3 ]
1195279 F2B PACKAGERXL Ptf files are not being read whenpackaging with Cache: G- z2 u; ]% J& `8 L1 C: s# a
1195374 ALLEGRO_EDITOR INTERACTIV Modules are not showing up in Tools >Module reports
3 G3 G7 N4 }* m* G1196603 SIP_LAYOUT EXPORT_DATA Change form for "Write PackageOverlay..." to better support longer lists of routing layers6 ~/ v: W0 X: j
1197302 CONSTRAINT_MGR UI_FORMS Inconsistancy in selection of objectfor Spacing Constraint Worksheet* b& i8 z6 [8 f7 a# D5 Z
1197399 CAPTURE OTHER Draw toolbar disappears when usingPrint Preview0 S. o/ p0 m, J0 s& z& V" v
1197543 ADW TDA TDO does not correctly showdeleted pages0 W# J) r4 R! ]3 C" X$ E
1198033 CONCEPT_HDL CORE Signals do not get highlightedwhen Show Physical Net Name is option enabled
0 N% K4 j' g0 V: @* `$ h1198468 ALLEGRO_EDITOR GRAPHICS 3D_step model does not show thecorrect view in 3D_Viewer when symbols have multiple place_bounds.6 }6 ?9 A2 s+ G
1198617 CIS GEN_BOM Mech parts are showing with Partreference in CIS BOM
3 g9 c2 M- n1 K# k3 w" }& K, I0 Y. e1199764 ALLEGRO_EDITOR SHAPE Allegro crashes when trying todelete small island on POWER layer.
: Y' X+ W8 V+ v5 g1200232 ALLEGRO_EDITOR INTERACTIV Moving all items including board outlinewhich is made of lines does not move the board outline in General Edit Mode.6 |" ]* e5 s9 L- O F
1200748 ALLEGRO_EDITOR INTERACTIV Additional pin edge vertex object tosnap pick
2 v8 z% J8 @$ x' Q1201056 ALLEGRO_EDITOR DATABASE Unsupported functionality strip designcreates a .SAV file& Y7 Q' D! J' m! f
1201638 CIS PART_MANAGER Part retains previous linking inside thesubgroup
: J. t" B) B6 Z2 C. y+ v1201834 ALLEGRO_EDITOR PLOTTING Bug: Import Logo command changesresulting imported object9 V, {- q; E9 B* j
1202406 SIP_LAYOUT OTHER enable the dynamic display of componentpin names for co-design dies in Sip Layout
1 d% Y2 G0 W3 S( H9 u1202431 CONCEPT_HDL PDF The publishpdf -variant optionshould have a "no graphics" option/ G( C3 @5 M+ ~- \* E
1202717 ALLEGRO_EDITOR DATABASE About Warning(SPMHA1-108):Illegal linesegment ... end points.
4 n) }) \" {! l4 s7 G) \+ d1203459 CONSTRAINT_MGR INTERACTIV Object Report has no mechanism to outputinformation for a specific design.
$ y' r7 l" |/ n5 q1204544 F2B DESIGNVARI Variant Editor does not warn on save ifno write permissions are on the file
$ W6 B* |" y- {4 |1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDLsyntax: K- j' O3 L& t
1205952 ALLEGRO_EDITOR GRAPHICS Step Model for Mechanical Part isvisible in 3D viewer only when Etch Top Subclass is enabled
: V9 |9 a, x3 R e2 W1206103 SIP_LAYOUT IC_IO_EDITING add port name property to pins, and addSkill access I/O driver cell data
I& V+ E t( \8 S& Q+ ]: E1206546 CAPTURE ANNOTATE User assigned refdes are resettingwhen 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�+ ^' [: Y( Z* _! V/ G4 k
1206561 ALLEGRO_EDITOR GRAPHICS Not all mechanical symbols made with Stepfiles are displayed in the 3D View
$ J2 {% g1 k: ]+ M+ _2 [1207125 SIG_INTEGRITY ASSIGN_TOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus: I& m3 r# Z* U4 k) u3 {4 c; v
1207386 CAPTURE GENERATE_PART Altera pin file not generating the partproperly" s8 Z- j+ q; P0 H0 ?
1207629 CAPTURE TCL_INTERFACE Bug: GetMACAddresses tcl command notworking/ B1 ?7 a2 v6 O* X+ \' X. e
1207994 CAPTURE TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pinswith black color
" C: L( I+ ?% Y' }* r1208017 F2B DESIGNVARI sch name is not same when updatingSchematic View while backannotating Variant, K1 E" F* h0 n4 v8 M: c
1209363 ALLEGRO_EDITOR INTERFACES When placing pins using the polarcommand the tool returns 4500.00 for 45 degrees.
* m' ~! S$ G/ b/ B# q, U$ J1209769 CONCEPT_HDL CORE Top DCF gate information missing3 ]% Z+ z$ N+ C/ ~3 S
1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box
; ]8 U' ]7 s& L) a- G1210442 CONCEPT_HDL INFRA Save design givesERROR(SPCOCN-1995): Non synchronized constraint property found in schematicpage
' k8 B0 i$ O6 ?8 x4 A( s6 x1210685 ASI_PI GUI User can't edit padstack inPowerDC-lite( u9 r" x- K- t$ |* Y1 d8 ^$ C
1210744 SIG_INTEGRITY SIGWAVE SigWave: FFT Mode Display unit seemsnot to be correct
\% E" r/ x( S5 k/ U! ~1210829 CAPTURE NETLIST_VERILOG Shorted port is missing from verilog file, S3 C$ v4 \) S2 j- Y
1210850 CONCEPT_HDL CORE DE-HDL backannotation crashingafter instantiating specific cell from Ericsson BPc Library" { v( E: ~" |3 @4 Q9 |# f2 V; S
1211620 ADW COMPONENT_BROWSE Component BrowserPerformance3 E; B5 c, x4 _ u6 G3 t+ ]1 I
1212102 ALLEGRO_EDITOR INTERACTIV Shape edit boundary adds arc mirrored tothe highlighted preview.
$ k1 t& N9 S% ?, ]* I% z( @% ~, X0 B1213294 CONCEPT_HDL SECTION DE-HDL windows mode multiple section fails tosection first contactor pin from column of individual pins4 E9 ~# [8 |1 i9 G
1213402 APD DATABASE The old "ix 0 0" fix is now causing the features to lose netsentirely.* p/ q: r: U0 b0 ?3 b
1213694 ALLEGRO_EDITOR PARTITION Via connected to Dummy Net pin in Partitiongets connected to shape on the board after importing partition7 U2 h! V. v( P) g0 d
1214247 CONSTRAINT_MGR UI_FORMS Selecting the "All" folderin Spacing Constraints in CM does not automatically select the first column forediting( R. V2 n+ W2 j: p$ t
1214320 SIG_INTEGRITY SIGNOISE signoise command with -L and -k option
; t6 U, t$ e$ O' ~1214433 CONCEPT_HDL CORE Genview does not update sym_1 withports added to the schematic/ ]8 P5 @% o: \! Z
1214909 ALLEGRO_EDITOR NC NC Drill Legend show extra rowsfor drills
( c' e! p0 n3 t& Y4 l2 i1214916 SIP_LAYOUT OTHER package design integrity check forvia-pin alignment with fix enabled hangs
. l5 D+ I5 E4 z# T; E- [/ Y% [/ C3 ^1215954 SIG_INTEGRITY SIMULATION Cycle.msm does not exist error whensimulating extracted net
7 o/ ~. H: |/ M( t1216328 CAPTURE STABILITY Capture crash2 k9 g: s: O: K6 V5 D+ y
1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.0496 O4 G& e( W7 w2 O
1217450 F2B BOM ERROR 233: Output file path doesnot exist" V; Y4 `7 N* P
1217612 ALLEGRO_EDITOR INTERACTIV Replace padstack will not replacepadstacks that have multiple alphabetic characters in the pin name - AB21-AB37
5 S6 {- N4 M4 |1 ?' R0 L* b* \( O1217823 ALLEGRO_EDITOR INTERACTIV Compose shape fails with SPMHIS-473* @+ x" P3 B. m- }* r* x6 I( Z) c
1217887 ALLEGRO_EDITOR INTERFACES An undo option to be made available inthe STEP Package Mapping window
6 | I% [- B3 p. e1218665 ALLEGRO_EDITOR INTERFACES In step viewer, the bottom side partsare placed above the pcb board surface3 u" d4 _# c6 |/ i; F/ p3 K
1219053 PSPICE PROBE PSpice crash with the attachedDesign
# }- {8 e" F' d* E! E1219067 ALLEGRO_EDITOR EDIT_ETCH dynamic fillets behavior is unstable& @7 C; ^8 \# U* B% N7 B% I
1219095 ALLEGRO_EDITOR MANUFACT Design Cross section chart is taperedfor two layer board4 L0 k9 T8 f% L% F( A
1219126 ALLEGRO_EDITOR SKILL Skill issue with axlRefreshSymbol()6 f5 ~) O# E. t8 k( g% N- F* ?
1220701 ALLEGRO_EDITOR INTERACTIV View > Windows > Worldview(showhide view command) fails with command not found# I" \, A! _) @% ~# m
1221057 ALLEGRO_EDITOR REPORTS Units in Cross section report forspacing is not synced with the design% G1 \ g& W9 Y1 d' q- |" Q
1221139 ALLEGRO_EDITOR EDIT_ETCH Delay tune is not tuning differentialpair% u7 O' f3 Z; H% g5 z& X. N. K
1221157 SIP_LAYOUT IMPORT_DATA import spd2/na2 file is not importingdata correctly into sip
: j: r+ ]# V* ~* O# ?# b0 G; c1221163 SIG_INTEGRITY GEOMETRY_EXTRACT Simulation aborts withsevere convergence issue when coupled vias is enabled.' Y/ r3 U& @ K+ ^
1221416 ALLEGRO_EDITOR DATABASE strip design for function type; L5 B- y' F6 K1 j8 X
1221931 ALLEGRO_EDITOR DATABASE Fatal software error when embeddingcomponent
# ^/ u% }. m( p3 {1222105 CONCEPT_HDL CORE Moving Pins around the edge of aBlock causes the text of the pin to change its text size.( O$ _# c1 U% d9 I* v3 r1 T/ ~: F$ X7 u
1222124 APD DATABASE Same Net DRC's exhibiting inconsistentbehavior.4 L t$ h8 a: O+ [6 z
1222272 SIG_EXPLORER EXTRACTTOP Cannot extract net or open SigXplorerafter selecting a netgroup% [, g2 |: Q* }7 ]0 t4 n
1222329 ALLEGRO_EDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top
$ z6 ]3 g& x [" r$ h& S1223183 SIP_LAYOUT BGA_GENERATOR Getting an incorrect error message whenusing the BGA generator with a long BGA name.4 L8 d" ~) q4 A1 Y
1223662 ALLEGRO_EDITOR REFRESH Allegro crashes when trying torefresh symbol1 U; H1 b& K2 o; J% l# b0 ]
1223932 CONCEPT_HDL CORE DEHDL block desend does not find1st page if its not page1& T* j7 V9 v/ S# F% J
1223940 CONSTRAINT_MGR UI_FORMS Unable to change CLOCK name inSetup/Hold Worksheet under Timing in CM.
+ C0 ~- L9 F4 ^- L0 T6 s1224127 SIG_INTEGRITY IRDROP Is the old static IRDrop in 16.6officially supported?
; a2 w3 E2 h5 f+ g! F5 ^/ M1 v1225492 PCB_LIBRARIAN CORE PDV expand vector pins resizessymbol outline to maximum height again/ ^! [/ d+ R2 X; w% ], S1 F
1225546 CONSTRAINT_MGR ECS_APPLY nets where the referenced ECS mapscorrectly in constraints manager for front end but not in back end
+ u1 p8 ?0 M. |; d) d" \1226405 ALLEGRO_EDITOR INTERFACES File > Export > IDF ask for filterconfig file eventhough it is created in same session and stored in parent folder, V. w S0 u9 @0 j: Z
1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDNAnalysis with XL and GXL
# G. w$ r7 V* v# @/ W% R1228721 SIP_LAYOUT OTHER File Export Netlist Spreadsheetenhance sort to be a natural method per Jedec according to customer |
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发表于 2014-2-10 15:09
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