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. I8 u4 |+ L+ I& u$ y* m5 ]DATE: 02-07-2014 HOTFIX VERSION: 0222 Z& z1 O8 f8 m$ q
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- p D5 e8 H |8 |192358 ALLEGRO_EDITOR PADS_IN Pad_in does not translate some copper shapes
9 {7 l; o% D4 S; w- ]222141 ALLEGRO_EDITOR PADS_IN PADS_IN: Extra shapes are created whenimporting PADS design* R5 j; c1 H8 j3 ?; d8 Q2 q. G) i3 k
274314 ALLEGRO_EDITOR PADS_IN PAD_in boundary defined for flooded area be translated DYN9 G$ V( U+ W2 K( m) k$ w7 T; C
413919 ALLEGRO_EDITOR PADS_IN pads_in cannot import width of refdes.
* ^4 W4 m6 S: m7 G* ~5 l609053 ALLEGRO_EDITOR PADS_IN "Mils to oversize" of "pads in" did not workcorrectly for MM data.
" t$ g+ k5 r& q) Z" V5 [666214 CONCEPT_HDL OTHER Option to increase Line thicknessin publishpdf utility! d7 A8 b& W- d
738482 ALLEGRO_EDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphicscard
& A$ w# L) D) f% R. K/ j7 S. n982950 CONCEPT_HDL OTHER change the mouse button for thestroke to have same function with in pcb editor# G2 M+ m+ C$ |" F
1020886 SIP_LAYOUT LEFDEF_IF a quicker way to promote die pins (byimporting macro_pin list): l# L5 L% @- z; P
1032678 CIS VIEW_DATABASE_PA View Database Partgives incorrect result in complex design with variants.$ d7 ?9 v6 y- g% [4 w: a% ^0 O+ P- r) z- o
1033864 ALLEGRO_EDITOR PADS_IN pads_in doesnot translates teardropspresent in design2 ?# w$ h0 w4 p3 {( e
1054862 CONCEPT_HDL OTHER Option to increase Linethickness in publishpdf utility
5 C4 D7 d3 M* M; U- \3 q2 s: G1055252 FSP PROCESS Add a synthesis option to target agroup to contiguous or consecutive banks
4 x+ {3 r) ] \+ \+ z' E$ F8 n1100772 CONSTRAINT_MGR OTHER In Constraint Manager > DRC >Spacing the Show Element DRC totals are wrong./ V2 \2 \9 c2 ?
1135020 CIS DESIGN_VARIANT Variant list is showing wrong results forhierarchical designs% U+ p& ^% ]2 p* W! F
1138951 SIP_LAYOUT DIE_ABSTRACT_IF Fix die abstract r/w to properly supportpinnumbers on ports
! v R* y1 ?; U' |" D1140042 CONSTRAINT_MGR OTHER Diff_Pair lengths and analysis arelost after closing and opening Constraint Manager.) F; R, x: h" ?- a% f! H; b2 @
1143662 ALLEGRO_EDITOR INTERACTIV Enhancement Request for RMB - Snap Pickto options increased to include Pin edge5 [! s( V. _. \7 h) {. Z( d* q% ~
1147961 PSPICE SIMULATOR Simulation produces no output data
" q; H. \7 V- a9 T% B3 k x1150874 ALLEGRO_EDITOR PADS_IN Dimensions in PADS are not translatedcorrectly during pads_in translation: U) v) k& d6 i$ y: R& }8 A
1154184 CONSTRAINT_MGR CONCEPT_HDL Difference in the way topology isextracted in 16.3 versus 16.6* Q& C5 X% Q4 V6 x8 F* g) Z
1154770 CAPTURE PROPERTY_EDITOR Variant Name property doesn't show value inVariant View mode* ?! C; b, f4 D3 K0 n% s
1158350 CONCEPT_HDL CORE Need a warning Message whileimporting a 16.3 sub-design in a 16.6 Design
) t$ f- Q# p9 [0 H1162347 ALLEGRO_EDITOR EDIT_ETCH Enh- Allow new option in Move commandsuch that it allows stretching etch using only 45/90 degree segments directly
8 k& a$ r1 B$ c$ X( J# b7 {1165553 ALLEGRO_EDITOR INTERACTIV Subclass list invoked from the statuswindow does not represent correct colors.
8 m9 |: G$ `* m/ [6 z: N1168079 FSP MODEL_EDITOR Clicking OK or Save As in rules editorallows user to overwrite the master with no warning6 \6 O8 W2 I( ~3 K6 X
1172043 SCM OTHER : in pin name causes SCM to crash
! w, D$ c" H9 @3 u5 q5 w1172207 CAPTURE STABILITY Capture crash while adding new partfrom Spreadsheet
) ]+ O4 I% x' h8 a' I1172743 ADW TDA Allowed character set for thecheck-in comments is too limited+ ^5 g9 a9 s/ n* k- T
1174099 SIP_LAYOUT WIREBOND Option to reconnect wire based on 縫in name� in the Wire Bond Replace1 y" h. |- A9 o
1177672 APD IMPORT_DATA Netlist-in wizard didn縯 provide detail information about whatcolumns have been ignored by import process
o9 {$ |) i! I1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATIONproperty can not be set to invisible2 _4 W2 |9 v. P) g) v
1177820 CONSTRAINT_MGR INTERACTIV Done the Allegro command when attemptingto launch CM
0 y+ J# [5 Q/ ?" w' `1178586 ALLEGRO_EDITOR EDIT_SHAPE Number of digits displayed after thedecimal point of Shape Creation function does not match the Accuracy of BRD
/ Q% w- L& z4 l' j+ a1179688 PSPICE STABILITY pspice crash for particular HOMEvariable vlaue
! w; R. S, E$ |' ^# T. F8 l" @8 P1179827 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to Symbolexport - enable field to add Keywords for data fields to excell cells1 V P2 C8 f1 d
1179879 SIP_LAYOUT STREAM_IF Data file corrupt when exporting Streamdata from SiP database.! j6 }2 _+ m3 I5 @
1180164 F2B BOM BOM csv data format converts toexcel formats
0 V% @. @) s& \9 ~7 \3 v1180477 ALLEGRO_EDITOR INTERFACES IPC-356 output is listing a duplicatelocation in the comment section& P- ?4 j# l/ W
1180932 SIP_LAYOUT OTHER SiP Layout - Symbol to Spreadsheetadd option for writing to existing spreadsheet' s) e8 g8 u9 G/ }
1181377 ALLEGRO_EDITOR INTERACTIV Pick Releative does not work correctlywith RMB-Move Vertex
, z' H8 X7 L5 d- c; V5 d1181516 ALLEGRO_EDITOR DRC_CONSTR Getting a "Thru Pin to RouteKeepout Spacing" when there should not be one.
9 @2 J; B) C$ d1 V$ }7 U1181739 GRE CORE Running Plan > Spatial crashesGRE) L- n; C2 z( h8 u
1181935 ALLEGRO_EDITOR DATABASE Enh. Property that allows internal C-CDRC errors" ^4 g0 s: w8 B; t5 I: @' l/ ?4 i/ s
1182185 SIP_LAYOUT OTHER SiP Layout - Import symbolspreadsheet - suppress Family for the font in the XML spreadsheet
1 y$ Z. r, F. F% w1182566 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to symbol- Enhance ability of spreadsheet exchange to allow for a portion of a full pinmap% i0 n$ h6 Q3 _2 | S! r
1182599 CONSTRAINT_MGR DATABASE CM Prop Delay Actuals do not updateafter Z Axis option is turned ON or OFF and Analyze is run.1 ~/ a7 ]# s! K" T- D
1182892 CAPTURE SCHEMATIC_EDITOR Pspice marker rotationbefore placement
7 t' z* a7 I- n* ~1183682 ALLEGRO_EDITOR DRC_CONSTR Implement Nodrc_Sym_Pin_Soldermask &Nodrc_Sym_Pin_Pastemask to symbol level
% Z! b* z# R* q% Z1185445 SIP_LAYOUT DIE_ABSTRACT_IF Die abstract export needs to be able toselect xda file type when browsing
; @1 p* a" f3 v4 i4 Q3 `! k6 u1185932 ALLEGRO_EDITOR SHAPE Soldermask in solder mask void DRC
9 U, q0 W' [: P; p W1185946 CONCEPT_HDL CORE Ericsson perfomance testing report5 sept 2013
6 i4 u4 B. y, z0 T6 ?( n: D6 q1187213 FLOWS PROJMGR Unable to lock the directive:backannotate_forward2 v, h F" G! R4 o' m7 K! a
1187444 ALLEGRO_EDITOR DRC_CONSTR With this design Database check promptserror "SPMHGE-47: Error in call to batch DRC"
9 f* _/ V- w9 d+ d: F1187597 ALLEGRO_EDITOR DRC_CONSTR No Package to Package Spacing DRC error,when symbol overlap sideways at 45 degree.9 `- ], r' H, E0 {/ J. k' F* x& K
1187723 FSP PROCESS Synthesis can fail depending on componentplacement0 B. d: \4 {( @! k9 O; ?1 r# S! ]& `
1188164 SIP_LAYOUT OTHER SiP Layout - Spreadsheet interfacesImport Export and Add Component - include Keyword for NET_GROUP& x' S) D# t4 `! i4 z
1188245 CONCEPT_HDL CORE INFO(SPCOCN-2055): You cannot runthe CHANGE command in a read only schematic
! h( d) Q6 Y& y: F* C1190927 CONCEPT_HDL CORE Check sheet does not reportshorted signal/power nets if power symbol is connected to a pin
) Q Q7 v# P/ p6 n' j, V) @1191497 ALLEGRO_EDITOR INTERACTIV ENH: Adding names to the text blockparameters numbers
- l- ]* \; G9 ~% f- ^; Q# O; E1192005 SIP_LAYOUT IMPORT_DATA Import SPD2 is missing 1 smart metalshape from file5 h$ _; f' j9 e6 \, U
1192204 ALLEGRO_EDITOR EXTRACT Need ability to extract vias that arelabeled as microvia
7 W4 S! {6 \0 o4 i& `1193063 ALLEGRO_EDITOR MANUFACT TestPrep log displays "Pin is notaccessible from bottom". The component is through hole.
1 I) Y/ _/ g6 O" R, _# @: [: f$ m1193418 ALLEGRO_EDITOR GRAPHICS 3D Viewer can`t export image in both SPB166S015 and SPB165S0478 Q. w; Y2 ]! {0 y5 {8 _0 Y
1194305 SIP_LAYOUT EXPORT_DATA export package overlay creates file withno package info1 l4 Y7 G8 a! {& E2 ?7 S0 L3 g
1194418 APD IMPORT_DATA issue when doFile->import->netlist-in wizard+ e5 j9 l+ p( P: ?+ h+ ~
1195279 F2B PACKAGERXL Ptf files are not being read whenpackaging with Cache0 G; |+ g9 G+ k& C8 |0 q
1195374 ALLEGRO_EDITOR INTERACTIV Modules are not showing up in Tools >Module reports
& i8 B; R2 q# l+ N: [7 a& q: D) F1196603 SIP_LAYOUT EXPORT_DATA Change form for "Write PackageOverlay..." to better support longer lists of routing layers% C' z. t, o4 n
1197302 CONSTRAINT_MGR UI_FORMS Inconsistancy in selection of objectfor Spacing Constraint Worksheet, X) S0 u/ c9 ~2 x+ t
1197399 CAPTURE OTHER Draw toolbar disappears when usingPrint Preview1 F' I& b' ], Q, U
1197543 ADW TDA TDO does not correctly showdeleted pages0 I/ z/ w% V, j$ {
1198033 CONCEPT_HDL CORE Signals do not get highlightedwhen Show Physical Net Name is option enabled& v/ c, Q: [% I% L7 J& _
1198468 ALLEGRO_EDITOR GRAPHICS 3D_step model does not show thecorrect view in 3D_Viewer when symbols have multiple place_bounds.
0 l; H4 ?! S& F, P" r3 n8 B! E1198617 CIS GEN_BOM Mech parts are showing with Partreference in CIS BOM, ^$ y( \4 r1 r$ L0 v& T
1199764 ALLEGRO_EDITOR SHAPE Allegro crashes when trying todelete small island on POWER layer.# C: B, o) `& i9 _
1200232 ALLEGRO_EDITOR INTERACTIV Moving all items including board outlinewhich is made of lines does not move the board outline in General Edit Mode.9 F- \! i3 j; R c# O
1200748 ALLEGRO_EDITOR INTERACTIV Additional pin edge vertex object tosnap pick! l8 @) U6 @# I4 D1 u
1201056 ALLEGRO_EDITOR DATABASE Unsupported functionality strip designcreates a .SAV file5 Z/ i& x7 j! d+ x2 S
1201638 CIS PART_MANAGER Part retains previous linking inside thesubgroup( r" A) G& u2 |+ r. A6 ^' J
1201834 ALLEGRO_EDITOR PLOTTING Bug: Import Logo command changesresulting imported object7 l2 R8 O" H; |& w
1202406 SIP_LAYOUT OTHER enable the dynamic display of componentpin names for co-design dies in Sip Layout
% K+ @! h! i, M7 v! z1202431 CONCEPT_HDL PDF The publishpdf -variant optionshould have a "no graphics" option8 e8 g. y7 k7 d+ U% T( m& A
1202717 ALLEGRO_EDITOR DATABASE About Warning(SPMHA1-108):Illegal linesegment ... end points.
. D% k; g- k7 w. g# }1203459 CONSTRAINT_MGR INTERACTIV Object Report has no mechanism to outputinformation for a specific design.
. Z9 G( S6 K9 A5 L5 I. I+ l ~1204544 F2B DESIGNVARI Variant Editor does not warn on save ifno write permissions are on the file
* n9 Y9 l6 `8 A0 \- B( e- E1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDLsyntax( H9 b9 Q( M! d) _, U7 [3 }
1205952 ALLEGRO_EDITOR GRAPHICS Step Model for Mechanical Part isvisible in 3D viewer only when Etch Top Subclass is enabled
- m: F0 w4 C+ Z- Y0 }$ X7 ]1206103 SIP_LAYOUT IC_IO_EDITING add port name property to pins, and addSkill access I/O driver cell data6 v7 }2 h* [# }: a
1206546 CAPTURE ANNOTATE User assigned refdes are resettingwhen 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�9 [* R2 A0 T% {
1206561 ALLEGRO_EDITOR GRAPHICS Not all mechanical symbols made with Stepfiles are displayed in the 3D View& g/ Z" \' H, M) H
1207125 SIG_INTEGRITY ASSIGN_TOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus
' d. Z, D; K* |4 f+ e" Q g1207386 CAPTURE GENERATE_PART Altera pin file not generating the partproperly0 Y( ^. u' B' ^" q8 e/ T" Z5 C
1207629 CAPTURE TCL_INTERFACE Bug: GetMACAddresses tcl command notworking- t9 p- p. q4 t" t7 u
1207994 CAPTURE TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pinswith black color
. Z J( e' u1 M$ ~7 X2 F1208017 F2B DESIGNVARI sch name is not same when updatingSchematic View while backannotating Variant Y- {7 |- ]8 T% Z6 ?
1209363 ALLEGRO_EDITOR INTERFACES When placing pins using the polarcommand the tool returns 4500.00 for 45 degrees.
) Q! G7 v6 B" h* Y Z1209769 CONCEPT_HDL CORE Top DCF gate information missing
# G: A$ P4 ~* C& T; e1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box
" B5 p( e; N' M1210442 CONCEPT_HDL INFRA Save design givesERROR(SPCOCN-1995): Non synchronized constraint property found in schematicpage
: n& A) J( U2 b1 d: T1210685 ASI_PI GUI User can't edit padstack inPowerDC-lite
* _% b- ?. S8 U1210744 SIG_INTEGRITY SIGWAVE SigWave: FFT Mode Display unit seemsnot to be correct( o% Q! A) R( Q9 c; A
1210829 CAPTURE NETLIST_VERILOG Shorted port is missing from verilog file
+ N$ N) P( {0 p4 K1210850 CONCEPT_HDL CORE DE-HDL backannotation crashingafter instantiating specific cell from Ericsson BPc Library8 E: K- v) M4 o+ r, N1 S4 }
1211620 ADW COMPONENT_BROWSE Component BrowserPerformance+ z3 Y, n) U7 x. Z( X- m. e
1212102 ALLEGRO_EDITOR INTERACTIV Shape edit boundary adds arc mirrored tothe highlighted preview.! S/ f# p$ }, y( }/ m* D/ E
1213294 CONCEPT_HDL SECTION DE-HDL windows mode multiple section fails tosection first contactor pin from column of individual pins
5 r4 v9 }' n$ q( E1213402 APD DATABASE The old "ix 0 0" fix is now causing the features to lose netsentirely.3 w' v; N1 s- D; e X
1213694 ALLEGRO_EDITOR PARTITION Via connected to Dummy Net pin in Partitiongets connected to shape on the board after importing partition) Y# `9 D2 m+ M( Q C: K# o3 N
1214247 CONSTRAINT_MGR UI_FORMS Selecting the "All" folderin Spacing Constraints in CM does not automatically select the first column forediting
8 l+ s2 ]" R- r! `4 ` h+ W1214320 SIG_INTEGRITY SIGNOISE signoise command with -L and -k option
! C9 T/ ~- A; Y7 U; ^1214433 CONCEPT_HDL CORE Genview does not update sym_1 withports added to the schematic7 Z' I. J5 T; g! ?
1214909 ALLEGRO_EDITOR NC NC Drill Legend show extra rowsfor drills
# l2 f& A/ |8 r1 e1214916 SIP_LAYOUT OTHER package design integrity check forvia-pin alignment with fix enabled hangs, H- G" F7 |; V1 L/ Q
1215954 SIG_INTEGRITY SIMULATION Cycle.msm does not exist error whensimulating extracted net1 R' v7 g+ M4 B h' T T
1216328 CAPTURE STABILITY Capture crash
( }8 w2 O8 O& m$ `6 D' ^3 y, h7 j3 y1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.049! i* `, ~) l( X; G* k Z
1217450 F2B BOM ERROR 233: Output file path doesnot exist8 U% ?0 w3 ~# o2 }, F6 Y
1217612 ALLEGRO_EDITOR INTERACTIV Replace padstack will not replacepadstacks that have multiple alphabetic characters in the pin name - AB21-AB37/ g2 Q3 F1 e/ S4 T% o
1217823 ALLEGRO_EDITOR INTERACTIV Compose shape fails with SPMHIS-473
7 m- |0 h }2 [0 m" W& I% u1217887 ALLEGRO_EDITOR INTERFACES An undo option to be made available inthe STEP Package Mapping window
4 f9 a% V L- R/ U1218665 ALLEGRO_EDITOR INTERFACES In step viewer, the bottom side partsare placed above the pcb board surface3 `0 [0 l5 s8 s5 w
1219053 PSPICE PROBE PSpice crash with the attachedDesign
- T! d% ^% D: ?8 Y$ m3 S# v6 k+ b1219067 ALLEGRO_EDITOR EDIT_ETCH dynamic fillets behavior is unstable8 P0 a; V8 \# J% P
1219095 ALLEGRO_EDITOR MANUFACT Design Cross section chart is taperedfor two layer board
" r5 {! p. `2 ^9 V! y, I1219126 ALLEGRO_EDITOR SKILL Skill issue with axlRefreshSymbol()% d5 ~6 i+ m$ _' [/ }, R5 W6 g
1220701 ALLEGRO_EDITOR INTERACTIV View > Windows > Worldview(showhide view command) fails with command not found
, q) D/ m) E* k/ k0 F# s3 k1221057 ALLEGRO_EDITOR REPORTS Units in Cross section report forspacing is not synced with the design
& Q0 x& l$ Z" x1 a1221139 ALLEGRO_EDITOR EDIT_ETCH Delay tune is not tuning differentialpair! w1 [. i0 X% ^
1221157 SIP_LAYOUT IMPORT_DATA import spd2/na2 file is not importingdata correctly into sip7 x6 L! ~: x( k- R
1221163 SIG_INTEGRITY GEOMETRY_EXTRACT Simulation aborts withsevere convergence issue when coupled vias is enabled.2 h- q; A. V2 M6 K
1221416 ALLEGRO_EDITOR DATABASE strip design for function type% b8 Q6 |% B, h
1221931 ALLEGRO_EDITOR DATABASE Fatal software error when embeddingcomponent
w2 X6 h( g) h( V; p1222105 CONCEPT_HDL CORE Moving Pins around the edge of aBlock causes the text of the pin to change its text size.. k4 z9 i& l1 o8 F" D
1222124 APD DATABASE Same Net DRC's exhibiting inconsistentbehavior.& _2 r' ^; e( C1 H/ V
1222272 SIG_EXPLORER EXTRACTTOP Cannot extract net or open SigXplorerafter selecting a netgroup% o' s! v1 p& F4 O6 q2 q
1222329 ALLEGRO_EDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top
+ x% l8 n! L `: }, }9 M1223183 SIP_LAYOUT BGA_GENERATOR Getting an incorrect error message whenusing the BGA generator with a long BGA name.8 B, \+ t8 D0 v1 I* @1 q6 K) y' L
1223662 ALLEGRO_EDITOR REFRESH Allegro crashes when trying torefresh symbol
5 x6 M; _) l/ w4 B1223932 CONCEPT_HDL CORE DEHDL block desend does not find1st page if its not page1
9 P" D# p0 I5 i6 G6 u( x- l1223940 CONSTRAINT_MGR UI_FORMS Unable to change CLOCK name inSetup/Hold Worksheet under Timing in CM.
/ ]7 p T' g! p) j1224127 SIG_INTEGRITY IRDROP Is the old static IRDrop in 16.6officially supported?* j* K. D' K0 N ~$ b, r% V
1225492 PCB_LIBRARIAN CORE PDV expand vector pins resizessymbol outline to maximum height again3 ]' W. V$ k' ]% C. k
1225546 CONSTRAINT_MGR ECS_APPLY nets where the referenced ECS mapscorrectly in constraints manager for front end but not in back end
, J7 M) y0 H+ c1226405 ALLEGRO_EDITOR INTERFACES File > Export > IDF ask for filterconfig file eventhough it is created in same session and stored in parent folder9 Q! f u: H* c# T3 F
1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDNAnalysis with XL and GXL
$ B$ R( |/ m; C4 ~1228721 SIP_LAYOUT OTHER File Export Netlist Spreadsheetenhance sort to be a natural method per Jedec according to customer |
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发表于 2014-2-10 15:09
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