Hotfix_SPB16.60.023_wint_1of1

steven.ning

http://pan.baidu.com/s/1eQl7md8
: t8 p4 A8 S# ]$ A$ |0 s5 QDATE: 02-14-2014   HOTFIX VERSION: 023
# c, `3 V! w  T9 H  _- e3 r===================================================================================================================================
: u  c5 f/ I3 M! ~% H9 v( H3 `CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
, {) j( g4 w) h  J+ i+ m===================================================================================================================================
! G2 R% l" V* A# A1120183 F2B            DESIGNVARI       Variant Editor Filter returns incorrect results.
! g/ A/ p# ]! q0 \1202715 SPIF           OTHER            Objects loose module group attribute after Specctra
1203443 ADW            LRM              LRM takes a long time to launch for the first time
1 c1 _9 E& M  F; E& D1207204 concept_HDL    CORE             schematic tool crashed during save all
8 M9 n4 n9 v9 P2 J1222101 CONCEPT_HDL    CORE             Pins are shorted on a block by the Block's title delimiter
$ W0 p, x, M9 |4 r3 ]1223709 FSP            FPGA_SUPPORT     Need FSP model of Altera 5AGZME3E3H29C4 FPGA
1224025 allegro_EDITOR INTERFACES       The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
1225591 F2B            PACKAGERXL       Aliased net signals starting with equals sign are not resolved correctly in cmgr
1226480 ALLEGRO_EDITOR EDIT_ETCH        Routing time is took to double increase when using the Add Connect because DRC is Allowed.
1229234 FLOWS          PROJMGR          Can't open the part table file from Project Setup
1229555 ALLEGRO_EDITOR ARTWORK          IPC-2581 not recognizing pin offsets correctly.
/ e7 g) V* e: o2 n1229610 FSP            FPGA_SUPPORT     New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
1229664 ALLEGRO_EDITOR SHAPE            Shape not voiding different net pins causing shorts with no DRC's
1232601 ALLEGRO_EDITOR MANUFACT         Cannot add test point to via on trace.
2 U, Z; `* G$ c" W- M$ u1232772 ALLEGRO_EDITOR DATABASE         When applying a place replicate module Allegro crashes
( K9 I! p5 h. r. i8 C# e& L1233216 SIP_LAYOUT     DIE_ABSTRACT_IF  Allow more than 2 decimal places for the shrink facor in the add codesign form
9 l# {% ^6 b$ C, F$ m0 L1233690 PDN_ANALYSIS   PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
1233977 ALLEGRO_EDITOR INTERFACES       single shape copied and rotated fails to create when importing IDX
1234357 SIP_LAYOUT     SCHEMATIC_FTB    DSMAIN-335: Dia file(s) error has occurred.
1234450 ALLEGRO_EDITOR INTERFACES       clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
1235587 Pspice         MODELEDITOR      PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
9 _5 _/ X4 _$ G1236571 ALLEGRO_EDITOR GRAPHICS         Allegro display lock up and panning issues
3 n& A- E2 U; K1237415 ALLEGRO_EDITOR INTERFACES       Multidrill pad is exported with single Drill in the STEP File
1237807 ALLEGRO_EDITOR SCHEM_FTB        The line feed code of netview.dat

larryfarn

Thanks a lot.

mengshang

点赞，谢谢分享啊

wolfshiao

昨天才重灌16.60.022說,結果進了StartPage頁,就看到有.023出了,
; ~* n( U8 B! E真是暈倒!!!!
太感謝steven.ning大大提供這網速快的百度網盤的資料下載了...

yuankai

感谢楼主分享

ziyu

更新太快了。。。

x68049

可以提供另一種下載方式嗎?

steven.ning

  U5 {( J8 x0 o. Chttp://dl.vmall.com/c0fu1auqa8

linsky2000

楼主给力，两种网盘都上传了！