|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
http://pan.baidu.com/s/1eQl7md8
+ x9 _+ p9 A* _/ V7 ]3 UDATE: 02-14-2014 HOTFIX VERSION: 0234 L4 z% U, h; Z. `+ f& @
===================================================================================================================================
: \2 Q3 T+ Z! \' \. tCCRID PRODUCT PRODUCTLEVEL2 TITLE( j4 `/ F' R0 {$ m- O
===================================================================================================================================+ O8 |) c9 _7 q% [& U# E- r( \; B( f) ?( o
1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
- i1 k. u2 s6 A2 ]9 {) t* Q1202715 SPIF OTHER Objects loose module group attribute after Specctra
* {2 B2 v$ v" }) z7 q1203443 ADW LRM LRM takes a long time to launch for the first time
$ j! u1 O2 n1 W, f }1207204 concept_HDL CORE schematic tool crashed during save all8 ^ r: G$ {2 Y+ i
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter$ c$ a3 s5 B5 I* r+ i) b
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA/ { d0 P& \. k$ i! ^8 Y/ p% v* w
1224025 allegro_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side0 T1 F2 b2 x" w. e2 _' \$ ~) e
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
5 i4 }/ m0 m0 V$ }5 M1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.1 h9 v/ u2 }0 v( s: X
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
2 `7 q& d- V+ B0 y9 u9 I% D1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.# {5 q& M6 i# D: s4 _, B3 O
1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7 o9 A/ {5 B( \ ?! A- u
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's; F3 B% `! {( W) [/ t1 _1 \
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.: `' s/ R0 @1 h, p7 J8 m
1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes. e, q" W6 N# X0 {% i/ _: L: f
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form
2 ~: v. Q f/ K$ y, F1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.' J/ m; ~" [3 L' C
1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
) \( d/ y) e% g. u! r1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
3 A7 ]7 Z4 M# H7 M1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
* a& ^2 a" q& T1235587 Pspice MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
$ j8 j1 }, q$ Y! ~. n' j1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
! i% F8 k; T% O1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File3 J3 \# i, p) p" ~/ ^
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
|
/1 
发表于 2014-2-18 18:04
收藏
淘帖
支持！
反对！
楼主