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: t8 p4 A8 S# ]$ A$ |0 s5 QDATE: 02-14-2014 HOTFIX VERSION: 023
# c, `3 V! w T9 H _- e3 r===================================================================================================================================
: u c5 f/ I3 M! ~% H9 v( H3 `CCRID PRODUCT PRODUCTLEVEL2 TITLE
, {) j( g4 w) h J+ i+ m===================================================================================================================================
! G2 R% l" V* A# A1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
! g/ A/ p# ]! q0 \1202715 SPIF OTHER Objects loose module group attribute after Specctra+ G6 u# q3 V' \8 x3 B
1203443 ADW LRM LRM takes a long time to launch for the first time
1 c1 _9 E& M F; E& D1207204 concept_HDL CORE schematic tool crashed during save all
8 M9 n4 n9 v9 P2 J1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter
$ W0 p, x, M9 |4 r3 ]1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA" N K! L8 @4 J' x8 Y' }
1224025 allegro_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side3 z c5 J; ]9 C* `# k' _0 s
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr( n& U) m. F: [/ J; G8 |
1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.' q' f/ c) f4 Y4 S
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup$ D& c W% S0 q1 W
1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
/ e7 g) V* e: o2 n1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7) U0 \3 C4 K; ^2 B
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's) x6 ^5 S3 c- |- t
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
2 U, Z; `* G$ c" W- M$ u1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes
( K9 I! p5 h. r. i8 C# e& L1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form
9 l# {% ^6 b$ C, F$ m0 L1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.5 w! W, @3 i0 L
1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX0 z$ v" b6 n0 E( ^. N- T
1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.6 h# m- U# ?7 E& M
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.) u1 b4 t% A. V6 p2 O3 I4 j k" l
1235587 Pspice MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
9 _5 _/ X4 _$ G1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
3 n& A- E2 U; K1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File* w5 ?, y5 p ~0 M
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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