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DATE: 02-14-2014 HOTFIX VERSION: 023/ @2 S/ O3 ?% u0 D$ R* l o
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CCRID PRODUCT PRODUCTLEVEL2 TITLE, s3 r8 |+ V; t. p$ k: X7 c
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~" u, T2 Y1 W1 i+ q1 C1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results. g8 g ^. X( x, z* p4 Y
1202715 SPIF OTHER Objects loose module group attribute after Specctra5 a+ }# D* ^4 I) M y
1203443 ADW LRM LRM takes a long time to launch for the first time
& \# U- f# e# o( N1207204 concept_HDL CORE schematic tool crashed during save all
5 n* J6 g) B4 m1 T* F8 Y1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter9 b' }7 Y1 I( [1 L8 x
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA- z" c2 ]6 \6 i
1224025 allegro_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side9 P8 q% i p3 S, j" G# U. j
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr: V" S) \) p/ e$ T$ D( |, n" k
1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.
* R4 f- A4 o( J* s. A1229234 FLOWS PROJMGR Can't open the part table file from Project Setup+ N1 H. J: W) d2 Z0 i. q& ]
1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.; R1 i- b$ u1 ~, P
1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
2 |3 m7 z& ]6 | c7 m* k. N( d" p1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's
! |% Z* K, _5 P, j4 }1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
" ^, }! M. k3 G$ m, f7 O1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes
* I. ^4 s: H3 j( O& j! v2 I1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form
; U- @" ~& C6 C% K1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
) G- P; {3 e1 V2 O1 e1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
5 n* m+ i* ^& a, L1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
0 Y( a4 z; n4 k8 [1 G1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
; x" V+ v' K$ C, \1 Q1235587 Pspice MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol8 z- l+ W& \4 |; j& A- P" G
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues$ r) X: w1 j- o3 c) |- t1 ~1 i
1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File+ v7 D( Y; q$ A4 h
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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