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http://pan.baidu.com/s/1eQl7md8+ M' \1 a0 ]9 \+ a
DATE: 02-14-2014 HOTFIX VERSION: 023; `$ q$ I5 n4 v5 M
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
: k) R2 P/ m" K1 X* ^* s0 X1202715 SPIF OTHER Objects loose module group attribute after Specctra8 N: l1 B9 U0 P7 r6 s. p+ I) \' T
1203443 ADW LRM LRM takes a long time to launch for the first time7 z2 G; P+ x! i; g
1207204 concept_HDL CORE schematic tool crashed during save all; M/ o- y" ?. F. S* i
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter1 v# Y% u$ U& c2 x/ E; ^6 ?( A7 |
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA
6 f) Y& @7 B4 O3 `& Z) I1224025 allegro_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side" e5 g! x. G. H' o+ A
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr1 `1 W- S% i* ?+ {9 i5 w" I
1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.% j4 h$ i/ e u
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup$ { f9 @; U6 D$ E B1 [
1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
9 g+ r; b& O, {: n3 r% [4 b2 g0 a1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7, U* b3 a d! r/ p X: q
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's* [( Y7 I7 g0 J2 @
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
- Q: c; P; Q6 _% a( R7 n, {1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes
/ M5 \8 {4 k( J1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form
/ x; I |+ m, T) `4 y1 d8 M: l1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
; {3 ~. ^2 n6 }, N/ r1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX5 y; x6 F# s2 p; g( M, d" v
1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.2 F) A1 E6 o1 I' G% F
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.- L& ~4 J, {% {0 Y+ A2 f, I) U
1235587 Pspice MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
" N, d# m$ `$ T- K# Q4 F( C) I1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
% Y. _: |5 F* o. C' s1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File8 _" N, k: b. v. F
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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