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本帖最后由 dsws 于 2014-4-28 12:56 编辑 6 i" D/ p0 T* g
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链接: http://pan.baidu.com/s/1dD9XLPB 密码: ujuq
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) H6 d2 r% G3 V& w# Z/ k# EDATE: 04-25-2014 HOTFIX VERSION: 027" c9 `/ K/ L) }8 v$ M; i3 T+ j$ c; z
===================================================================================================================================$ k3 K8 f( V* U3 l6 \; v
CCRID PRODUCT PRODUCTLEVEL2 TITLE# P% L; O% k4 V$ L; b4 p
===================================================================================================================================, A( U& m6 i# m
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM
2 U8 a" v; N) b r481674 allegro_EDITOR pads_IN No board file saved from PADS_in/ E7 r- g; x5 t
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
/ E$ W4 r( o/ |6 X {* u; q. S1012783 FSP OTHER Need Undo Command in FSP
" e- P s- X$ V4 ~: W1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.
* n" U: R1 l7 w/ ?5 x1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
. Y" u& k" K* T! T! |* }9 W7 B1073231 concept_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.- U. N9 d9 P1 p7 X+ o, d- [
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups
8 B; A, g% \& _* \0 A+ R1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
, ?3 Z6 ]6 v% u# Q' _1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
3 A+ C5 n: w- N, g$ ^1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
0 C0 v! `" u, P, k4 }2 U; ]1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present ] W+ ?# ]( a7 p3 v9 u; c6 k6 Y6 R! X
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
* J J9 \ y7 D5 u9 a: T2 p) @1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings
8 {& ^# f% }2 D) a, N1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
# S* e3 R; h2 S( ?) v1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV- { Q7 B' L x/ Q* W5 t
1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.+ M2 a& w3 l; o( H$ }7 P2 J
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
9 x1 f/ ~ k& t1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime
) W% l4 L& R4 J0 `1208478 Pspice PROBE Attached project gives overflow error with marching ON.
& v3 |# g! L' r1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol! u+ ~& N! z5 k% x& c' M% d
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed# \( H0 u6 ~. h6 E* ]7 `) _. D
1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
- I" d- f$ U2 J1 H8 m0 R1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers
9 E1 R& G2 Y5 X0 c" t+ @, o1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?" S: B: a( n7 U4 ]) T7 H/ }
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.' ?. c, v, B) z6 n3 L7 V& F. e. w
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values5 J8 N- K$ V8 G! V% W6 U
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging6 s( N' A* h% B H& y, _& G- u, A6 Y
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
! n& _( Y$ Y& L& B9 n6 i3 g1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added0 Y, j S2 N' W: N5 I% k
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
! @+ Z& _* b% g. t q0 ]: J: ]* q1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
6 ~3 R: u$ N; K1 t1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux. ?8 b3 ^8 G5 {1 [9 h: D' @
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
2 s4 e% z0 l2 p8 f! h% d5 i1221182 ADW TDA Team Design with SAMBA
% |& C3 r w+ V1 E& d y1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair! v: V% }# F7 _! E( }5 y& V+ Q
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened7 J3 g* k" ^" ~/ n e: ^
1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?: H' U$ d* i- h8 T9 Q
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
) ~0 ^' h" W/ |* s) K# b1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms8 P6 H- U1 D5 I* V7 r
1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
3 z# G; j+ z8 f& u1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor. ?5 C4 X- |6 i
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.! K0 |3 Y9 D$ p
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path3 q3 `: F0 @! Z' O* U3 Q6 P* E
1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin; C* _! \' `5 @1 D8 }5 i6 T% N
1225494 CAPTURE DRC Different DRC results for Entire design and selection) [- T4 I/ M1 M1 P& f& v
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property
) ?7 @/ i0 Q8 T" D% ?' x. y1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet, A0 S% z' j# H) ~. Z
1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
$ g1 ?! C8 m7 I1 b1 R, [) [5 b5 g1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal- D. G. W d/ r. d1 R
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file3 T5 R9 F. S! K) I0 z/ O2 S+ y
1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors/ C( M& T+ [# m1 j
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,84 t0 t* x, `7 k0 D1 m, c C
1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration
7 s7 ~+ {% [6 f* B$ q1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part9 L7 Q5 E) K- T
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case) f/ Q8 i* F4 r3 P" i& `) b
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins L: Q$ ]8 W1 u( l: X% N5 q
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
9 t; c0 v3 |0 n: U. P- i) T% e1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
5 O7 W, l1 w0 H! l! ?; n1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.* H5 k. d" J! z% y
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).6 @7 W, C1 N5 H# n7 a* A% R/ R
1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM# N c' p# G% b7 ]; ^
1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined- g: v. }3 B9 e) ^$ \" I
1230432 CONCEPT_HDL CORE No Description information in BOM6 i$ H% V6 m* m3 t! o
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes/ F) j$ [# p. l% p" U0 N
1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files
8 I% p8 V' L* ]( ^) W1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands7 E7 L; x& G7 ~# K5 }! j
1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets; k6 Z! H6 `- U6 A) N$ E
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.1 S) a0 @8 d- S/ N7 y
1232100 CONCEPT_HDL skill Unable to execute the SKILL commands in viewer mode1 e3 R& \: ?: k
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical
1 Z3 t9 N5 Z' { C( m( b1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode' m- y" F4 c+ `, e6 S* z; S. ]
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files8 e3 ^; S E( ~$ E4 I2 v
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy* I& e: M3 F& i' T0 e
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
1 g6 R/ g1 W2 @$ f1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect$ v+ N3 F8 Y5 @& u0 w
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set% Y4 ~4 q. ?8 k( v2 H* k
1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
Z1 w) x2 V6 i# j1236161 CONCEPT_HDL CORE Import Design shows the current project pages9 ]7 `5 h8 @: \, Q
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.
& f- W1 ]; ]7 h) m7 y, H2 c9 {1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion* O( H: X1 H6 `$ `9 \
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file4 C; }) ` d3 y4 E2 P
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape; e, X9 ^5 y* b5 B4 g
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming
4 p) v; H, D8 @3 p2 `9 ~1236781 F2B PACKAGERXL Export Physical produces empty files8 {$ d/ B8 `7 b" J6 i" W) n# w
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
. S& L- X# Z+ M* m. q8 r4 y1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command6 s, v5 c/ N, g8 ~* p
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
3 m$ A ^1 ^- Y5 i( Z+ ?' G/ u1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
- A) P$ X& k' T5 p+ ?1238852 CAPTURE GENERAL signal list not updated for buses1 Q6 r. z5 \+ O6 N( |4 K
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes0 J) [) y3 T/ `' |- c5 D3 h4 O
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack., m7 Z* o0 @0 [! S% T
1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE' n$ Q3 E* X3 e1 d1 _+ s
1239763 PSPICE PROBE Cannot modify text label if right y axis is active" |; }) V5 R$ V5 }6 `) `9 |
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images
- [4 O% g: S/ U, d: A1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
' } t& A9 T+ {! `1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
2 B% K$ G: E/ i0 s9 g& p0 B1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file8 g7 z+ O: e- B) q
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable
4 p! N0 w6 `& k1 }& g% D1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy
& V- z& K) T2 U1 n( Y2 i3 ]6 R1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
9 m5 d0 [) l) o1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working5 ]5 D d- }% d+ y/ o, `
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
/ C# n1 Z: D6 w* V7 Z. a5 C5 t; k2 T1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
) N. T0 ^6 f( o( F1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
q: \1 Z! w% s c5 {7 X# ?1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side. J2 D" M# \" a k5 z9 X
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer
; l9 P( u+ m- L4 z# |1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results* K* x3 u l2 y% i/ q+ ?6 D# {" c
1243609 CONCEPT_HDL CORE autoprop for occurrence properties% @ x5 D0 {( e7 J" l6 {( n
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
' ^6 V0 P" w* D4 K4 E4 H1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
( e7 `2 h. J7 f5 H8 R C1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
# s5 N: _/ S Y1 |/ P2 { H0 v1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
2 G) q1 l* ~" `7 n) n0 W& P1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is$ x2 e/ z% R8 h; K4 @3 ~
1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design3 m( c9 z @0 \- Y% K+ L! v
1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?
( ]: {* u3 y$ G* V1 G* ?' d1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
' T' c0 N1 r* y5 Q* G9 [. |1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters
5 Q5 e' D4 Q! o! A' e7 f$ d5 N/ a; \; J1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown" U9 T9 v, b. L1 i5 \ {
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
5 Q8 z Z* s) |1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL H1 M1 K) k) _2 A& B; _6 ]" I3 H2 ]- w
1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained
, G4 r, j/ i" h/ q! |6 l5 }( h1247462 CONCEPT_HDL CORE Text issue while moving with bounding box
9 g: }' G" u' d+ h. }" d7 B1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered2 @2 b5 u' d% i, O6 d8 E, t
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
- ^, @+ s% L1 g* V% m3 G; W+ V: x% N- P1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts7 n/ O T; i3 @$ i" Z
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
; S$ v; w* Z& @$ w1 D* W1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint' }! N7 ^1 u0 Q& e3 O# \
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly4 i+ F- D9 Q: z$ T# n, X
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
3 |6 ^; Z. A5 y/ x# }& E: Z1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies" p- r4 K7 L9 ~% h- j/ z
1253424 SCM SCHGEN Export Schematics Crashes System Architect
& G+ N8 ^2 N# I* d, C( R1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled9 d. f' \3 r5 p$ @& t* I
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
9 Z0 h) X* f- H* w7 s" E* q1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
% \6 P, c& S# t) m/ q; O1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error5 T7 ~& H9 Z' R0 L
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
# A, i }+ \1 M/ o) G1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation
6 x0 V; {# n+ a9 |1 Q& I& Y1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects- ~1 _. p6 [' H& E% G' Y9 H
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
5 f9 ~$ [5 ~9 Y9 ^, Z1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
9 \" t4 F' R7 A: D. l1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
3 b# m; H9 i5 L5 U' b3 e2 g8 Z( l1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
: s$ p, k; n, W; O7 b: K1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design/ y& z- c, e; T! ~
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library
' D1 s4 M* }3 i1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
. _8 y/ W' L) I& j1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash+ k3 v! F. ~+ v* q
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time1 W) \, Y( \3 @0 G/ `
1258029 APD WIREBOND The bondwire lost after import the wire information; g$ ]1 ]5 h" R4 t
1258979 APD NC NC Drill: There is difference of number of drills.2 u6 S1 F! r# g" a4 F$ k. W! B2 O
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement
5 F: R0 ^1 h9 {# i* g% q s1 c1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
/ y6 f) D* c7 j6 }% G8 v4 o. l+ j1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"
& X& a% S+ o( A2 N4 E6 t1 M1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines
8 o. I" q3 ~/ g# }1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void
1 z8 Z( M' v7 @; N1 r" [1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss3 k7 d. e) o. X: G) v7 ~
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发表于 2014-4-26 15:14
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