SPB_16.6 27号补丁下载链接--Hotfix_SPB16.60.027_wint_1of1.exe

Csec

http://sw.cadence.com/P/download ... e4d05&file=.exe
更新百度网盘下载链接！
- S  ~2 u/ |+ S; [http://pan.baidu.com/s/1mgwSsPy
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DATE: 04-25-2014   HOTFIX VERSION: 027
, s) ^6 f  S; h% R0 T# q8 r  v+ U===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
% c% \' U. h1 O8 X" C: Z% _===================================================================================================================================
- c& K" j! N! N308701  CONSTRAINT_MGR OTHER            Needs to delete user defined schedule in CM
2 g& D* n& D( H" N# K. b481674  allegro_EDITOR pads_IN          No board file saved from PADS_in
982929  ALLEGRO_EDITOR EDIT_ETCH        can't route on NC pin and other that are not pin.
4 N. G. V  M0 j/ o% b( b- f# X1012783 FSP            OTHER            Need Undo Command in FSP
1017381 ALLEGRO_EDITOR DRC_CONSTR       Need Dynamic Phase to be able to measure back to the Drive Pins.
% G5 ?2 t" j- \# ~2 S1072673 PCB_LIBRARIAN  GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
. H7 H4 W# z+ x1 R4 M! }) |1073231 concept_HDL    CORE             Copy-paste of signal names goes off-grid in Windows mode.
8 A7 n" z. }6 H# Q1105371 CONCEPT_HDL    INTERFACE_DESIGN Strange behavior when shorting two Net groups
' R9 E: \$ m% L" c! x) Z# C1116498 CIS            LINK_DATABASE_PA link database with modified part results in Capture crash
1118632 ALLEGRO_EDITOR GRAPHICS         Text display refresh issue while in Edit > text command
! z" ^0 i: j$ k; h. ~1155821 SIG_INTEGRITY  LIBRARY          Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
8 ?2 {* P1 i3 t9 O8 @8 f1157372 ALLEGRO_EDITOR DRC_CONSTR       Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
% n4 O7 ?' e! ?) B- R1171951 ALLEGRO_EDITOR CREATE_SYM       Jumper has a limited of count when it add to list.
1180871 CAPTURE        LIBRARY_EDITOR   Copied parts don't retain pin name and pin number settings
1185575 SIP_LAYOUT     DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
  \9 N- T0 d: O9 V: P1185772 PCB_LIBRARIAN  CORE             VALID_PACK_TYPE warning when cell was opened in PDV
1192377 CAPTURE        SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
( o- t, E, x0 I3 |' @7 P% _% V1202654 ALLEGRO_EDITOR GRAPHICS         Zoom using mouse wheel shall maintain the center co-ordinates
8 a4 H; {( ]( R2 q1208031 ALLEGRO_EDITOR INTERACTIV       Snap to Pin for via during Copy command do not snap to connect point everytime
1208478 Pspice         PROBE            Attached project gives overflow error with marching ON.
7 _% Z" _8 r% W' v: l6 Z1210015 CONCEPT_HDL    CORE             The value of $PN should be not turned on spin or rotate symbol
7 Z, w4 M7 l, Q0 }) k* h( ]* K; M  M1210425 CONCEPT_HDL    CORE             When moving a circuit tool reports that connectivity has changed
1215858 ALLEGRO_EDITOR SHAPE            Force update does not void cline with the shape
0 N! {5 {8 {# D% @3 Q6 M9 l2 i1215906 ALLEGRO_EDITOR SHAPE            Dynamic shape fill smooth failed when copying to other layers
4 M' Y$ a1 d3 ^1216358 CONCEPT_HDL    CORE             Can we improve our export BOM function to check if user did export physical function before exporting BOM?
1217364 CONCEPT_HDL    OTHER            Netlist reports fail because error: GScald failed.
1217529 CONCEPT_HDL    CORE             ADW checks do not catch single quotes in PTF values
1217556 F2B            PACKAGERXL       signal name change not sent to Allegro after packaging
1219283 ALLEGRO_EDITOR DRC_CONSTR       Show constraint is inconsistent when displaying region information
9 C( S# h0 m- H1220078 F2B            PACKAGERXL       Export Physical crashes when ALL the part pins are added
1220393 CONSTRAINT_MGR CONCEPT_HDL      HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
1220540 ALLEGRO_EDITOR GRAPHICS         Need an option to see the pads inside the internal plane shapes
* v3 H5 W. A& q! j0 w3 F/ p. N7 G' q% p1220936 CONCEPT_HDL    CORE             About crash by vpadd/vpdelete command on Linux
1221059 ALLEGRO_EDITOR DRC_CONSTR       Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
0 a, J6 z) m: ?; t1 F1221182 ADW            TDA              Team Design with SAMBA
1 f8 T. V! Z" s' B1222442 CONSTRAINT_MGR UI_FORMS         Duplicate pin pairs appear in DiffPair
3 t( {. p( A# U# N, d+ ^, i1223175 CONCEPT_HDL    CONSTRAINT_MGR   Schematic crashes when opened
1223533 ALLEGRO_EDITOR GRAPHICS         Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
7 d% p8 g& v5 r- D" y1223680 CONSTRAINT_MGR ECS_APPLY        Improve ECSet mapping by allowing user to address ambiguity of Parts
1224156 SIG_INTEGRITY  SIGWAVE          Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
1224417 ALLEGRO_EDITOR PLOTTING         Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
1224704 F2B            DESIGNVARI       There is no lock for the variant.dat file - multiple users can open the editor
/ k$ f. D* ?: }& P3 u# ^  R: ?6 s  M  i1224968 ALLEGRO_EDITOR INTERACTIV       Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.
7 P/ |1 Z" [' P4 x7 \1224982 CONCEPT_HDL    PDF              commandline publishpdf does not work when there are spaces in the path
1225114 CAPTURE        GENERAL          H-pins added after netgroup pin get color as of netgroup pin
1225494 CAPTURE        DRC              Different DRC results for Entire design and selection
* a2 d7 O2 I4 d% |1226153 ALLEGRO_EDITOR INTERFACES       Export STEP should include PART_NUMBER property
1226235 ALLEGRO_EDITOR EDIT_ETCH        Enhancement to include Pin_delay of descrete forming Xnet
1226372 CAPTURE        GENERATE_PART    ENH: Functionality to add pin spacing in New Part From Spreadsheet
: X2 K$ y: b' j2 U& ^" {- ~1226477 CONCEPT_HDL    CORE             DE HDL縮 `Allowed Global Shorts?  function is inconvenient for Global Signal
3 |8 \# a8 a" |4 K; C9 i1 Q3 j% c7 R( f1226813 SIP_LAYOUT     LEFDEF_IF        ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
3 J9 ]" h1 V6 T9 `) h1227453 ALLEGRO_EDITOR SHAPE            Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
8 j  J- `" R; r/ X/ _1227461 ALLEGRO_EDITOR SHAPE            Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
1227469 CIS            DBC_CFG_WIZARD   Oracle Views not visible on Step2 of CIS Configuration
1227780 CAPTURE        ANNOTATE         Inconsistent behaviour when annotating heterogeneous part
2 c5 a0 M- Z4 [7 n1227831 CONCEPT_HDL    CORE             Pin text and H-block name in upper case
1227954 CONCEPT_HDL    OTHER            supress check for global signals when wires are unconnected to pins
1228190 ALLEGRO_EDITOR OTHER            Unable to close the 'usage' window during license selection
1228899 CONSTRAINT_MGR INTERACTIV       Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
) v& I! C% G7 e/ L1228934 ALLEGRO_EDITOR EDIT_ETCH        The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
1229316 ALLEGRO_EDITOR EDIT_ETCH        When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
1229545 CONSTRAINT_MGR OTHER            Allegro indicate bundle scheduled nets in CM
/ R: A* I; _/ m# y1230056 ALLEGRO_EDITOR GRAPHICS         Bug: 3D View of Mechanical Symbol with the drill hole defined
4 u+ A6 n" W4 N2 C1230432 CONCEPT_HDL    CORE             No Description information in BOM
1231148 F2B            DESIGNVARI       The variant.dat file is not updated with library PTF changes
! `9 e$ [  O/ M% [, G1231625 F2B            DESIGNSYNC       VDD at command line needs to support sch2sch and test variable to write out report files
1231697 CONCEPT_HDL    CORE             If any locked files exist force a pop-up dialog restricting certain commands
1231767 CONCEPT_HDL    OTHER            Unable to find under the search options single bit vector nets
; X: O! I- Z0 C) l) P8 h1231961 ALLEGRO_EDITOR SHAPE            Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
1232100 CONCEPT_HDL    skill            Unable to execute the SKILL commands in viewer mode
% l8 i0 [$ _* A' ~1232336 CONSTRAINT_MGR CONCEPT_HDL      cmFeedback takes 5hrs to complete during Import Physical
8 B& a; n' ^+ x9 r; a1232710 F2B            DESIGNVARI       Dehdl crash while moving component in variant viewer mode
0 J) ?$ l, u5 e) P1 Z: g1 t1233894 F2B            PACKAGERXL       The page data is missing in the pst* and PCB files
1235785 CONCEPT_HDL    CREFER           cref_from_list custom text is not subsitituted in complex hierarchy
1 G+ e( \8 S/ m0 u( |1235928 CAPTURE        SCHEMATIC_EDITOR OleObject modifications not saved
1 y  n8 t% i0 R$ `) N1236065 CAPTURE        PART_EDITOR      Mirrored part after being edited get pin name locations incorrect
1236071 ALLEGRO_EDITOR SHAPE            Airgap for Octagonal Pads ignores DRC Value when Thermal set
1236072 CONCEPT_HDL    CORE             Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
% f" S  q& X4 _$ Y8 |% R1236161 CONCEPT_HDL    CORE             Import Design shows the current project pages
1236432 ALLEGRO_EDITOR PADS_IN          pads_in doesnot translate via and shape in some instances.
/ p: z- o9 Z8 B  g7 c  ]1236557 CONCEPT_HDL    PDF              Running Publish PDF on command line in linux doesn't output progress until completion
7 G8 M* r" T! [5 q& i( \1236589 CONCEPT_HDL    PDF              Enhancement license failure error should appear in pdfpuplisher  log file
1236644 ALLEGRO_EDITOR EDIT_ETCH        create fanout deletes shape
& q+ r) o; W6 ]1236689 ALLEGRO_EDITOR GRAPHICS         Graphics displays extraneous lines when panning or zooming
1236781 F2B            PACKAGERXL       Export Physical produces empty files
2 p* N9 r7 ~; H. F9 H1237331 PSPICE         ENVIRONMENT      pspice.exe <cir file name> - hangs when run
, y3 r" Y) ~! z% ]9 }1237400 CIS            EXPLORER         Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
1237437 CONCEPT_HDL    CONSTRAINT_MGR   CM Crash when saving after restore from definition
) x/ b: H6 P* D" W1237862 CONSTRAINT_MGR OTHER            A way to remove the RAVEL markers from the Constraint Manager.
7 }; N0 w6 k' z) ?. A1238852 CAPTURE        GENERAL          signal list not updated for buses
1 [9 H. W7 z/ m1238856 FSP            DE-HDL_SCHEMATIC FSP schematic generation crashes
/ _' b, o. N1 w1239079 ALLEGRO_EDITOR INTERACTIV       The 16.6 Padstack > Replace function leaves old padstack.
, L. s/ A! u7 m1239706 CONSTRAINT_MGR ANALYSIS         The reflection result on a differential signal in the CM when Measurement location is DIE
1239763 PSPICE         PROBE            Cannot modify text label if right y axis is active
: z  Y; j' h2 |$ d9 \1240276 ALLEGRO_EDITOR GRAPHICS         Printing to PDF from SigXp is giving unreadable images
1240356 CAPTURE        IMPORT/EXPORT    Can縯 import SDT schematic to Capture.
5 s" u: T$ R/ i; M  f1 D1240502 F2B            PACKAGERXL       Corrupt cfg_package does not stop PackagerXL from completing
1240607 ALLEGRO_EDITOR OTHER            Footprint of screw hole got shift in DXF file
1240670 ALLEGRO_EDITOR PLACEMENT        Select multiple parts and Rotate makes them immovable
1240773 CAPTURE        DRC              DRC check reports error for duplicate NetGroup Reference in complex hierarchy
1240845 SIG_EXPLORER   EXTRACTTOP       Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
1241634 ALLEGRO_EDITOR OTHER            Netshort for pad-pad connect not working
/ j, A$ N" A4 G. @3 u1241776 CONCEPT_HDL    CORE             In hierarchal design not all pages are getting printed.
+ F. W" m6 M/ E: |, j2 y7 ~1241788 CONSTRAINT_MGR CONCEPT_HDL      Issues with changing focus in Constraint manager using keys on keyboard
1242683 ALLEGRO_EDITOR INTERACTIV       Color View Save replaces file without warning
1242818 ALLEGRO_EDITOR PLACEMENT        Placement edit mirror option places component on wrong side
9 J- Z! ]5 M" l% C% @+ @. d1242847 ALLEGRO_EDITOR GRAPHICS         Need an option to suppress Via Holes in 3D Viewer
4 l- `( H) q1 J, O1242923 ADW            COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
/ {) ^3 b" H9 p! e) f- T1243609 CONCEPT_HDL    CORE             autoprop for occurrence properties
8 z5 l' O  h. d" r( v# L! I; Z0 s1243682 F2B            DESIGNVARI       after undocking variant icon cannot be redocked back to GUI
! y/ V4 A! E# K& [( T* e1243686 ALLEGRO_EDITOR GRAPHICS         Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
! B: X3 S) B* e' ~* {1243715 CAPTURE        PART_EDITOR      Pin name positioning get changed after rotating or mirroring
1244945 CONCEPT_HDL    PDF              PDF Publisher does not include image when file is not located in the root folder
1245568 CONCEPT_HDL    CORE             Dual unselect needed for wires attached to other net/source and property is not deselected when component is
1245819 F2B            PACKAGERXL       wrong injected properties information passed during packaging of the design
1245916 SCM            CONCEPT_IMPORT   Where does the folder location reside for DEHDL imported blocks?
' M" H) S0 W6 s$ \2 \0 C& b4 K) m1246347 CONSTRAINT_MGR CONCEPT_HDL      DEHDL crash if environment variable path has trailing backslash character
5 }8 D( Y" E  k1246896 ALLEGRO_EDITOR DFA              DFA_UPDATE on Linux reports err message if the path has Upper case characters
1247019 SIP_LAYOUT     DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
1247037 CAPTURE        LIBRARY_EDITOR   Copy & Paste of library parts resets pin name and number
. u  r: V; U/ l+ k7 e$ t1247089 CONCEPT_HDL    CORE             Group Align or Distribute > Left/Center/Right crashes DEHDL
# e5 j# I+ J; l. [$ B, u4 M( P1247163 CONCEPT_HDL    PDF              Physical Net Names in PDF not maintained
# H/ H9 V* J6 a+ T5 c1247462 CONCEPT_HDL    CORE             Text issue while moving with bounding box
6 v' W) ~) G) g# S: q/ S. |1247464 ALLEGRO_EDITOR UI_FORMS         When using the define B/B via UI the end layer dropdown arrow is partially covered
1249063 CONCEPT_HDL    CONSTRAINT_MGR   CM and SigXP doesn縯 respect PACK_IGNORE at components
1250270 CONCEPT_HDL    CORE             Part Manager Update places wrong parts
: \; S# j; K! M; s2 Q8 b% Y1251206 ALLEGRO_EDITOR ARTWORK          Aperture command cannot create appropriate aperture automatically from design.
1251356 ALLEGRO_EDITOR INTERFACES       Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
' B" v0 g1 @" G" V$ ~" X( K0 w0 o% y1251845 ALLEGRO_EDITOR EXTRACT          Crosshatch arcs do not extract correctly
1252143 APD            OTHER            When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
& ^: M- S* @, ^1252737 SIP_LAYOUT     OTHER            SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
1253424 SCM            SCHGEN           Export Schematics Crashes System Architect
$ M0 ]  A9 K9 ^* S3 I, ~1253508 ALLEGRO_EDITOR INTERFACES       Bug - Export IPC2581 exports Crosshatch shapes as filled
1253554 SIP_LAYOUT     OTHER            SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
% R$ h8 m$ |  D3 ]; E2 i6 B6 U1254578 SPIF           OTHER            Specctra crash with Error -1073741819 for Auto router
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK   adding nets to a net group causes constraint assignment error
1254676 GRE            IFP_INTERACTIVE  Rake Lines disappear when Auto-Interactive Breakout is enabled.
1255067 SIG_INTEGRITY  REPORTS          Allegro hangs on Net Parasitc Report generation
* I* q+ [5 m8 `) U& J9 m" U4 e+ M1255267 ALLEGRO_EDITOR SKILL            axlDBGetPropDictEntry does not return a list of all objects
9 L: h  B# ~2 V- S1255383 SIP_LAYOUT     IC_IO_EDITING    cant move bumps or driver in app mode
$ q" |/ C& W$ [) S- p4 @6 q1255703 ALLEGRO_EDITOR SKILL            axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
1255759 ALLEGRO_EDITOR INTERFACES       Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
  R0 x, I+ b1 d: g! H( _- g1256457 CONCEPT_HDL    CONSTRAINT_MGR   Extracting a XNet from CM crashes the tool
- ?% h! l& K4 O$ k9 ~9 H2 l' m1256597 GRE            CORE             Allegro GRE crashes while running Plan Spatial, on a particular design
/ O% H; m" L* g2 N, x2 T# a$ J1256650 ASI_PI         GUI              PFE - Cannot generate model file error when using company decap library
' K0 s7 Y! @( p* b6 k1256837 SIP_LAYOUT     DIE_EDITOR       Open and close of die editor takes too long
) z# m0 a/ [& d% |% R2 I1257732 CONSTRAINT_MGR OTHER            Bug - Export Analysis Results in CM makes Allegro crash
1257755 ALLEGRO_EDITOR OTHER            Editing time in Display > Status seems to be logging wrong time
1258029 APD            WIREBOND         The bondwire lost after import the wire information
1258979 APD            NC               NC Drill: There is difference of number of drills.
1259484 SIP_LAYOUT     OTHER            SiP - calc min airgap calculate minimum airgap beta feature improvement
7 x6 H) c3 k, R4 s7 s8 W* o, D! k1259677 CONCEPT_HDL    CORE             hier_write -forcereset cause component prop change.
* b* U3 c7 {7 }1 C7 s. O1259913 ALLEGRO_EDITOR UI_FORMS         Unable to save setting of "use secondary step models in 3D viewer"
1261758 ALLEGRO_EDITOR EDIT_ETCH        Auto Interactive Delay tune (AiDT) is deleting clines
% e% c2 z" |2 d0 `9 h5 d" s1262543 ALLEGRO_EDITOR MANUFACT         merge shape results in moved void
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK   XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
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wqnet

myexpma 发表于 2014-4-29 23:51
安装时前面有几个图片出现crc错误，忽略过去了，但是后面有exe文件也有crc错误，因此中止了更新，希望版主 ...

6 a, `( _) m  z/ x应该是百度客户端的问题，一旦断线，重新开始的东西就不对了！遇到过好多次。文件本身应该没有问题，刚下载，数字签名没问题。

wu5163

finezhang 发表于 2014-4-26 17:09
0 v) p9 S: q; }. |  N9 o好像不能下载

谢谢楼主的分享            好像不能下载

pzt648485640

谢谢楼主的分享

finezhang

好像不能下载

mengshang

我用迅雷下载，速度比较慢啊

zhongwaiting

& S0 X1 v9 l4 f! F; j  c: c/ D7 a0 R2 l5 C
6 K, `1 U4 B! f: x- k! a7 Z& X请哪位大虾给一个百度网盘链接！
4 i7 ~) u. l( L7 d  {5 Y# b网络的下载速度跟不上软件的更新！

Vegeta

请问怎么打补丁？需要重新安装Candence么？

rufeng888

16.5补丁出到多少啦？

mengshang

现在Download失败了

rainbowII

链接无法打开，请放置在百度网盘

wangerfeng

链接无效，不能下载，鉴定完毕。

amote

谢谢楼主分享，请问有转存baidu盘的么，这个链接下载不了

zeiss

谢谢啊，要是有其它网盘的下载地址就更好了，cadence下载有点慢
不过还是要十分感谢分享

tubegong

下不了