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本帖最后由 Csec 于 2014-4-28 11:04 编辑
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, M7 ^) ~6 B5 N5 Ohttp://sw.cadence.com/P/download ... e4d05&file=.exe+ B" _6 B5 S, e/ {
更新百度网盘下载链接！
& a+ M( Q0 p" I. J/ E$ D3 l( i7 vhttp://pan.baidu.com/s/1mgwSsPy& ]( ]; `1 ~9 b# r& W
$ K2 Q* i. A# W* M) s7 F5 l, V
DATE: 04-25-2014 HOTFIX VERSION: 027; a( c- ]9 Y/ ^# X
===================================================================================================================================
- R$ V* M# h2 u E W9 K Q7 l- h+ ICCRID PRODUCT PRODUCTLEVEL2 TITLE
* }. s# a0 W' x! n===================================================================================================================================
% D4 p, ?1 b3 F! U, H% h" H6 F308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM# q7 l% S; C8 M
481674 allegro_EDITOR pads_IN No board file saved from PADS_in9 p+ L" o# I7 Z& k Z1 c4 u
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
0 `- I$ c0 h! C6 M# X1012783 FSP OTHER Need Undo Command in FSP
) @0 `" @" C+ }, u. N7 X1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.! o5 { c5 _3 Y6 K" _; V
1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved4 e" O5 u, L/ D K) @
1073231 concept_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
* V/ k5 S, [. O0 l+ v ~4 f1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups! O* U) a! H/ S P
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
4 y/ M w& x' ?2 y; U$ H2 o8 S+ {1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
' t/ h7 E6 L5 B! W4 {& ?) {; n7 Q1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
( B% H/ m- [! b# |$ ]1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present$ H. J5 w8 |8 F0 D9 N4 U+ M# I9 P
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
% n6 z& n h" d1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings. V: j r" _" j1 F- \
1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
8 e7 ?) m' f5 ~( b8 c$ |1 o5 c2 s1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
" I# K" @) j0 H' J$ p3 n1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
9 _' r8 H( n q) [" q1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
, L7 Z& B+ |0 _5 o, D1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime
" |; j! a; N% D* o* F# n1208478 Pspice PROBE Attached project gives overflow error with marching ON.
6 [4 S; ]8 C- b9 A4 d- ^; G0 O1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol% [# j, N0 N$ C: R
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed+ [* T8 [" j3 w; E5 M- e
1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
7 k9 s: x8 m: P- L. O1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers
* F' @4 _; H7 w8 E: A; n1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?% a+ I% Q% D( u, P7 \
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.
! ^/ r2 M2 y6 Z1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values1 w# `% ?2 k. c' @5 L
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging# O; h3 u8 C" S6 @! h0 d
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
( [1 F' g- ~' K1 a( ]1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added$ e% z; _: B# n- ]4 E1 s4 G$ D+ J
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.0 g2 p3 o- S$ Y' G0 }/ F
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
H% }3 o# ?* D+ Z5 I: B1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux0 P; k7 Y5 ]: v8 J; ^% _
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
" ?* N8 s# {4 P1221182 ADW TDA Team Design with SAMBA
3 r9 |. E/ ~8 c0 Z. b9 ]1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair4 ^) b1 S0 F+ l; ^
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened3 ^2 t" G. ]- b
1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?/ N3 r3 B9 x1 T1 u
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
/ W% h* M) L+ p! ]) ^1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms6 k$ X, Y, c# r" z
1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.' W# N3 Y; y# S7 W( y5 M! h* [
1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor
' x/ q" z3 T' _1 A# y6 r1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.3 F& v7 o# B: Q' j; s( S. K; E
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
6 \6 s, K) j- e1 f: y1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin9 j$ E2 ?! i% r" _
1225494 CAPTURE DRC Different DRC results for Entire design and selection
* d- d$ `$ }* v( f( Q1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property
/ ]; N0 i5 g& p& F$ M/ h1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet. k. x3 w+ l/ z" C( ]; u0 z
1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet6 Y* p9 N, P4 |; q6 h3 ]( b6 |
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal
, b) [1 x3 {) E/ y1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
* q9 b& ]: M, X! Z1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors; n( k* ]: Z5 W5 ~6 K
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
7 r, A0 a3 R# k: I* ]+ T: |% @# T1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration
' \+ t9 p5 l! L2 D: J; G& c/ S1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part
6 d+ c2 f0 W; H8 o6 r1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case: ?: J: v2 x: y5 g s3 H, ~9 ]
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins0 v7 J* J/ W/ U) ^2 }* U) l
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
% B0 b$ v& x" H2 ?7 g5 t B* g1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
8 Q2 @8 d1 Y% D4 x! G1 w1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
. H3 \' z, b6 T9 j0 [6 M+ s6 S: }! z1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
" ^: `' T7 N0 L) Y1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
* [9 u1 w: A/ r% @7 T7 L }" ?0 R1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined; e7 h/ A8 ^4 D! Y
1230432 CONCEPT_HDL CORE No Description information in BOM% v9 j# I4 y* t1 n6 D# ~5 A3 ~
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
# z0 P' u T+ B t$ ~# u+ u1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files( ~ v/ o* I# L" T
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
. V, V( k: }' b q8 r) `1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets
# H6 E! o: f, m- J- S1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.9 Z9 b* P2 L- b5 I: w
1232100 CONCEPT_HDL skill Unable to execute the SKILL commands in viewer mode$ m, P( c7 L V1 Q
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical
5 e! W: F. |7 k1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode
4 @% S/ c; P) t' l+ y" B. P, i1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files4 P0 M' B- O- F* x
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy
( |4 E" A% [9 b% w1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved7 N$ }7 d* ]( c# s6 t
1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect( F$ |, ~3 y A8 `
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set( C/ W ?4 a5 g. q8 B1 l' H" s
1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
/ t/ t; S7 g/ Y# M0 h1236161 CONCEPT_HDL CORE Import Design shows the current project pages
* d! G% K m0 K6 H1 O1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.8 }/ m: y0 {) H
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
) \1 E: p3 \; U5 O. s3 d, w, D1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file3 `$ M. c6 e. l [, k5 |) P
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape7 c* O' _" a/ N! U3 y
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming1 W9 C1 d* f: @. j! F* h
1236781 F2B PACKAGERXL Export Physical produces empty files% e! N3 ? s3 ]& S
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
, c; H) f3 b" Y1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
" j$ I- D7 T# V+ h6 j: [1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
, M+ S" @3 }5 [9 P) |. h1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
4 `7 X& o$ }4 s! M/ Y7 b1 ?8 Y1238852 CAPTURE GENERAL signal list not updated for buses) O# v: U2 R# b
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes
6 j1 @! V! Q: A3 E1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
# G2 J0 A9 G" e& q1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE
6 t8 Q) ~- N; b1239763 PSPICE PROBE Cannot modify text label if right y axis is active
U# r) ^* S, J/ v/ p0 E1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images0 r/ k( `2 ^9 a* F" a! o: x# V
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
6 f* v: I# @5 V, v, `8 V$ B9 p1 l1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
" \% u1 \7 Q3 j9 M) M& O) e6 x. |1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file
$ j g1 W- L/ L7 g: L2 d8 }1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable8 a" n' {8 K& K5 M4 R, B
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy3 o+ k1 E& c7 X
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms, N5 s! g; a0 b
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working* l+ Y& `; o* s t3 n. V
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.% n5 m: _; _- S; ~) ^8 N/ X8 i
1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
; T) g/ r! X1 ?8 V/ M- j& z1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
# q* q* ?4 |& Y' k3 \3 b! o6 Z1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side9 D/ M+ \: C. K0 Q8 H3 k
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer' l; B7 s- y8 ~6 J6 O+ J* e/ W
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results( b6 x, E' k+ ?) t) R$ [
1243609 CONCEPT_HDL CORE autoprop for occurrence properties- y% p/ m3 S# F$ j6 f( A/ E# ~
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI. U; m0 _, R& n. Y$ f& `: V
1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.; X' ]% R- Y0 L& z! K
1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
% W) a1 k) H, ]0 U1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
/ `# v" F) f" n1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
5 `. R; P8 M/ ]$ D5 _ d1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
+ W2 W+ k7 W; ^ O$ S# b1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?) q' U* {3 ?+ [! F
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character! l# ~ u8 H* c, T2 [ S, R
1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters( _! t* W& d; @* E6 y6 F$ x7 L
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown1 G: t9 s& I5 O$ i
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
' B4 A6 w3 S& P" e0 V3 h& S) u1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL) j3 p; x4 }, h
1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained9 I. P: u" Q2 X6 |" t
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box
& W" j2 v7 I) B1 G1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered
* L. L- Q( v& c8 n' j3 w1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components; J2 @: j6 ~! Y% L* N& ^: r! P) Y
1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts
; v& P" ]- M7 ^* U! {1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.0 b( }5 \- a. k6 k
1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint& B' O* y$ g$ P5 J
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly
6 S4 H- [% H; e, z" S1 ?0 T1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
% y Y7 \, G# X% ~0 q6 A1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies" @' s3 B+ e8 ]4 i, N M4 |, d0 o
1253424 SCM SCHGEN Export Schematics Crashes System Architect8 I% V6 B) ?: O2 j: g {8 k
1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled3 W& B, F( }+ p) t* j) }" a
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
5 P' x4 x( ~4 R5 o1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router( v9 d0 U4 D Q4 M9 w
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error
$ Y9 O- \% ^/ h0 o) \% l8 i1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
* G' t& i9 ~' k% w7 ?% I1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation
8 p, P6 h4 `" d! z( _: a8 R# l1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects$ U# v* Y9 R* l4 R
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode# b6 Y2 b# f) J+ B* q) H
1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
# l* i+ c G |+ U1 }! K7 D3 Q1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE; n' `: `" C' ]& Y( S
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
$ D( ^4 j8 ?. h7 D# |- i1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design( M9 A h1 T$ l
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library
- C4 l; l$ w% `. O3 b1 i- n1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
$ P% Z% y3 D# l+ f4 f- B1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash6 C2 ]" @% N% U- J- s( o* b; A- O
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time/ m, ?% b3 H( T
1258029 APD WIREBOND The bondwire lost after import the wire information
9 p+ J1 P3 s1 c( q; @# N1258979 APD NC NC Drill: There is difference of number of drills.
$ M9 \6 Q `* V9 S1 a0 }# [1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement
. e0 u" e8 \# T- M# o1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
$ R; ?% F! R; m9 k1 y2 E1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer" N) E* v8 Z& F2 {* O
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines) S5 g+ M# G t6 Y& H' v4 }8 v- H! L1 d
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void9 i4 |& u" N. f2 v* ~- G; E4 o' h
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss: H) s+ _$ z$ w, t
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发表于 2014-4-26 15:15
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发表于 2014-4-27 21:59
