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DATE: 05-23-2014 HOTFIX VERSION: 029
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1209461 FSP DE-HDL_SCHEMATIC Hierarchical BlockSize not automatically adjusting to text needs
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1217832 SIG_EXPLORER SIMULATION S-param generated by SigXP doesn't matchwith HSPICE/ADS.
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2 k/ Z2 |) m3 c1263575 concept_HDL CORE Copy-Pate makes ComponentsOff-Grid% L4 B4 b3 y, `/ z* s
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1267602 SPIF OTHER Route Automatic hangs
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9 {' F6 P; g. Z I' x1268022 FSP PROCESS FSP is not respecting the use banks forattached design.
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% z0 y9 D+ g# C- N$ r1 I# M/ n1268587 allegro_EDITOR INTERFACES Enh. Preserve relation between hole andpadstack in IPC-2581( W! T7 S% `- m9 n; x. }
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1268918 SIP_LAYOUT DIE_ABSTRACT_IF SiP - DIE export from co-design object to XDAresults in missing data
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1269232 CONCEPT_HDL INFRA While Pspice uprev the designcrashes
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1269825 SIG_INTEGRITY SIGNOISE PCB SI hangs when running crosstalksimulations
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1270963 ALLEGRO_EDITOR GRAPHICS Add Circle lint font hidden/Phantom hasresolution problem
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1270990 ALLEGRO_EDITOR GRAPHICS Allegro response is slow when addedcircle7 ~( q) k! a& ?) f1 x1 T. f6 k
k G8 d8 k8 g1 p- G* u( F b1271655 ALLEGRO_EDITOR MANUFACT Dimension option causes a genericcrash, reproducible in any design
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; E2 O9 z' l4 R" y% L1 }1272495 ALLEGRO_EDITOR MANUFACT Filtered Part numbers in IPC-2581still pass actual part number for references onutide of BOMItem
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W9 N; C5 Y. M& Q+ V$ {! _( v1272839 ALLEGRO_EDITOR MANUFACT Kindly explain the drill legendbehavior when padstack rotation is 45 degrees and mirrored ?
: w5 t# v U8 m: H: t1274518 ALLEGRO_EDITOR ARTWORK Artwork does not create voidcorrectly. |
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发表于 2014-5-31 18:29
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