找回密码
 注册
关于网站域名变更的通知
查看: 2937|回复: 14
打印 上一主题 下一主题

Hotfix_SPB16.60.032_wint_1of1

[复制链接]

该用户从未签到

跳转到指定楼层
1#
发表于 2014-7-30 15:35 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

EDA365欢迎您登录!

您需要 登录 才可以下载或查看,没有帐号?注册

x
http://pan.baidu.com/s/1kToiYV1
! J( C7 M9 N' }  T
# M+ r* z& l9 P! o$ I" ~% F6 p% I7 R. r% r3 p4 _
DATE: 07-25-2014   HOTFIX VERSION: 032. w- ~8 F2 {  f
===================================================================================================================================
+ }/ ?- N$ h+ LCCRID  PRODUCT        PRODUCTLEVEL2   TITLE
& h1 }% B6 C# }1 f# P===================================================================================================================================9 f% B) S5 }8 m0 q; U$ h
381127 SPECCTRA       CROSSTALK        Specctra xtalk reports aren't correct; h" f9 t  h& Y/ T" {: V  k7 v
616770 allegro_EDITOR COLOR           Remove the APPLY button in the Color Dialog window.
/ E3 l9 v8 t8 _! z, d9 K, k& p8 j982944 ALLEGRO_EDITOR COLOR           seperate the Etch to the Shape and the the Cline in the visibilitywindow! \# b9 n2 o9 [0 R2 B4 t
982995 ALLEGRO_EDITOR INTERACTIV      Shown infomation for the selected physical symbols6 ~3 _& R) y( W: P8 \9 U
1024832 Pspice         PROBE            Shows wrong data & header whenexporting trace to .txt  {$ t3 I: i6 Y4 n
1063258 PSPICE         AA_OPT           curve fit fails with error  same data works in 16.5 Simulation error: outof range of data
& |! z4 T; u  b8 X8 ]! Q1 R1112360 PSPICE         AA_OPT           Advacne analysis gives runtime error whileusing Optimizer in attached design: _! a, A; g2 v  g/ {3 y
1154323 PCB_LIBRARIAN  VERIFICATION     Con2con is choosing incorrect Primitivefrom Chips file and failing FTB Checks' N; [5 [- b+ x
1184690 concept_HDL    CORE             Weird behavior of genview forsplit hierarchical blocks
% P! s: [' t( R8 n# ?2 k! O6 a6 I1212577 PSPICE         MODELEDITOR      IBIS translation fails without anyinformation in log file/ V- q6 r5 p, P1 P
1213204 ALLEGRO_EDITOR PLACEMENT        Place Manually with existing fixed netbehaving incorrectly4 K9 g; C, F- W% _7 U+ \1 W5 a; g
1213837 ALLEGRO_EDITOR INTERACTIV       When copying a stacked via the temphighlight does not display on the last layer of the stack.
8 n: E8 \; z7 _. Q) g0 j1 V1216519 SPECCTRA       ROUTE            Autorouter will not add BB viabetween uvia within the BGA area- Z! ]$ r) d: P% d8 l
1220655 PSPICE         DEHDL_NETLISTER  Support for automatic addition for Powersource and Ground Node for Globals  inDEHDL PSpice netlisting- i* Y2 e" m: y% m- m$ N/ h$ T
1223018 CAPTURE        OTHER            Diff pair Auto Setup not workingfor the buses.
0 r0 u& h2 o2 y3 ?2 a% A% v1225689 PSPICE         AA_SMOKE         Smoke analysis crashes with attachedtestcase' u; C* a7 w) K' m/ b- m
1232124 CONCEPT_HDL    COMP_BROWSER     unable to generate ppt_options.dat file infirst go2 k1 Q4 k5 T, }9 n: ~# |3 ^& L" p
1235059 PCB_LIBRARIAN  IMPORT_CSV       pin_delays not being imported into PDV
6 t  j2 O& O% M: K) n' e* K9 S0 X1238815 CAPTURE        OTHER            Capture doesn?t retain more than191 library in add part/capture.ini under part selector configured libraries1 I& N+ x1 Q. k/ i3 P
1239241 ALLEGRO_EDITOR INTERACTIV       Via replacement doesn't replace withcorrect via but right padstack name.
6 y$ I6 l( @  P# E! o( h1240201 ALLEGRO_EDITOR EDIT_ETCH        RPD DRC unresolved evenif HUD turnsGreen
8 C' W/ w1 c9 I  d2 u1240314 PSPICE         SIMULATOR        Getting internal error,oveRFlow for thesecond run) ?* ^/ ~/ u' q; \. d
1242805 ALLEGRO_EDITOR DRC_CONSTR       no_drc_progress_meter variable hangsallegro after running update drc1 s, @- m; z( U
1243267 ADW            TDA              URL to TDO-SharePoint should bedefined in CPM File
( x9 p# O# P& M  e7 J; J& y1244857 ADW            TDA              Policy File Variables not workingcorrectly in policy file
) |# i0 F0 }2 w; _/ j1245779 CONCEPT_HDL    CONSTRAINT_MGR   Obsolete objects in DEHDL CM$ o+ a9 S5 W" @
1246811 CIS            EXPLORER         Option to keep the part type tree inCIS explorer expanded on every invoke5 {! f" L3 k* Q
1246964 PSPICE         PROBE            Simulation Crashes in 16.6 butrunning successfully in 16.5& q# M$ ]' z5 B, A3 u6 ^
1248782 CONCEPT_HDL    CORE             Display winning physical bus names(occurrence mode) in the the lower block of an Hierarchical design1 L; U2 R+ i3 i% }6 Y! P
1249238 CONCEPT_HDL    CORE             Uprev from 16.3 splatters textaround sch page. c5 E' ^% G. T' |1 [: f% W! `
1249692 ALLEGRO_EDITOR GRAPHICS         3D Viewer is wrong when resizing itswindow.7 J5 H9 D7 D+ @5 y$ J; e' w
1249850 ALLEGRO_EDITOR SHAPE            With shape_rki_autoclip RouteKeepin to Shape DRC is created
# V9 T2 c( X- I2 O, x4 e3 v1250683 ALLEGRO_EDITOR INTERACTIV       devpath corrupts if edited from userpreferences.9 f4 G1 ^" X) Y) u
1252059 ALLEGRO_EDITOR INTERACTIV       Preference Editor is unable to delete aprevious path entry for library paths7 B& A6 N# W* h; w- ]1 q
1253563 SIP_LAYOUT     DEGASSING        Not getting degassing voids when closeto shape in center of design
6 }; k% D: `6 A- d8 }* Q- T1254319 ALLEGRO_EDITOR GRAPHICS         ENH: Functionality to change the 3DModel color for more realistic view
: ?4 z" l' |2 a8 w1254562 ALLEGRO_EDITOR DATABASE         Unable to delete a subclass that existonly on classes Package Keepout, Package Keepin and Route Keepin.2 z' o( k  _  K4 R
1255169 CONCEPT_HDL    OTHER            ADW (BPc) Packager should reportthe specific corrupt directive in the .cpm file. X- L; V% i) S# r& i
1255573 ALLEGRO_EDITOR DRC_CONSTR       Need soldermask DRC checks when same netvia and smd pad overlaps2 j2 e" L/ Q* i) t) q
1257950 CONSTRAINT_MGR SCHEM_FTB        Changing xnet name on Allegro CM., x  }, j  V2 [! H
1258165 F2B            DESIGNVARI       changing visibility of Probe_number invariant schematic changes it to $Porbe_number
. j+ l: D6 A7 ~5 j/ P, N1258274 PCB_LIBRARIAN  VERIFICATION     con2con crash with no notification orerror message+ t; y, j7 n* u" h. |& t
1258860 CAPTURE        PROJECT_MANAGER  Bug: Text Editor (File> New> VHDL File)filters characters from Text/ Q2 ], j8 ^# C# h4 D" v
1258872 CONCEPT_HDL    CORE             Objects are copied (instead ofmoved) when moved from sheet to sheet! ?) Z9 w( _9 {" }
1259284 CONCEPT_HDL    PDF              HDL_POWER ( global) net does notget transferred to the published pdf
% y3 B8 l* x$ E/ \! N  X6 p$ E$ d1259375 CONCEPT_HDL    CORE             Help link to cdnUsers.org needs tobe changed8 F3 p: g' G0 n. w* k
1259860 ALLEGRO_EDITOR INTERACTIV       Edit > Mirror does not displayasymmetrical pad correctly when the footprint is attached to cursor.
9 }9 |1 m* l2 r* z: u/ u' W1260002 ALLEGRO_EDITOR INTERACTIV       Alt sym hard is not obeyed when usingEdit > Move > Mirror
3 V& S' ]0 o$ ^( \" m( @/ }! q1260006 ALLEGRO_EDITOR PLACEMENT        funckey r iange 90 rotation issue0 o! m, b$ p  R' y
1260667 ALLEGRO_EDITOR EDIT_ETCH        Allegro crashes when running AICCcommand on few Diff Pair traces.
, P' L6 s' X" L4 x1 w% l1260763 CONCEPT_HDL    CORE             Export Physical fails with $TEMPentry in Setup-Tools1 S$ F& v0 e7 T8 |. j2 {0 X
1260847 SIP_LAYOUT     SYMB_EDIT_APPMOD Border texts seen astriangles.* ~2 v" O9 l* f( n
1260948 ALLEGRO_EDITOR SHAPE            Dynamic ground shape is shorting tovia of a different net at layer 4 & 5 in this design
- L- Q( o- |$ V1262011 ALLEGRO_EDITOR PLACEMENT        Key Properties on Component Instance/Definition on available to use with Quickplace by Property
& O2 x; \. S1 K: [1262322 ALLEGRO_EDITOR PADS_IN          Pads_in can not translate routekeepout which specified for the all layers." c, m% t5 U1 k. [" }  N
1262626 CONCEPT_HDL    CORE             PROBE NUMBER attributes lost fromthe nets after upreving the design
3 h) K0 ^1 @4 X6 S$ K* z1263592 PCB_LIBRARIAN  VERIFICATION     Unable to check in Schematic Model due topc.db file
  g& k( z, n5 V/ S, w1263685 ALLEGRO_EDITOR INTERACTIV       Editing Photo Width value from non zero tozero allegro gives warning- Value must be greater or greater to zero# H' _' D/ T9 f' j! I
1263704 ALLEGRO_EDITOR EDIT_ETCH        Bug - AiTR wrongly deletes blind viasand do reroutes.
3 a9 f4 M: k! e. f' U& Y! o6 G1265120 ALLEGRO_EDITOR SHAPE            Require voids in dynamic shapes touse pad value; ^* @8 l" T/ k" u: z: E
1265275 ALLEGRO_EDITOR DRC_TIMING_CHK   When XNETS are dissolved by removing theModels all Physical and Spacing NetClass associations are lost
/ _, u* T. m6 ?; a  o1265633 PSPICE         SIMULATOR        Bias point result is different inconsecutive simulation run of the attached project! K9 b6 d5 ]5 E& c
1266349 ALLEGRO_EDITOR PLACEMENT        Rotating symbol while placement showwrong angle of rotation than the placed angle when Angle is set in DesignParameter
1 d# t7 X" T) s1267541 PSPICE         PROBE            pspice.exe does not exit when runfrom command line
8 g4 h/ Q5 [8 W8 r# v# V: |1267707 ALLEGRO_EDITOR PLACEMENT        Mirror Command - preselect/postselectbug with general edit mode
3 z2 S  a7 e+ U+ f% N1268299 PSPICE         STABILITY        Pspice crash on attached design" G% F* Z3 X& y7 _; |/ n
1270879 ALLEGRO_EDITOR COLOR            Color view save creates .color fileusing older extension( v8 _4 G3 B) k, E# `
1271295 SIP_LAYOUT     DIE_STACK_EDITOR Die stack editor supportneeded for large variant combination designs.- J. M# O- [7 g% M- i
1271385 CONCEPT_HDL    CORE             Locked property can still be added& x0 t( [5 X' k; U4 z
1271853 APD            OTHER            When using the beta "shape tocline" command, add improved messages and partial completion of individualsegs in error.$ z% B: }# h8 R2 U0 z
1272197 CONCEPT_HDL    CORE             concepthdl_menu.txt containsinvalid Variants menu/ s) p& b. X6 q8 D% t0 d
1272318 CAPTURE        GEN_BOM          BOM_IGNORE not working for CaptureBOM on hierarchical designs.( O4 U# h& ~6 D5 R
1272743 ALLEGRO_EDITOR PADS_IN          PADS Library Translator does not openthe Options dialog window.6 N: k# O8 a  W' ?0 Y+ N, b2 S
1273517 F2B            PACKAGERXL       Netrev error - ERROR(40) Object notfound in database
  v! d2 z" N; ?2 S: z3 H1274000 ALLEGRO_EDITOR DATABASE         PCB layer can't be removed
' Z% {0 }  W7 G/ e- c0 ?# c! e0 ?1274530 ALLEGRO_EDITOR INTERACTIV       Add Circle radius value changes nexttime using this command
0 Z9 S7 U8 s$ u" ]6 i/ T% B1274697 PSPICE         AA_MC            pspiceaa crashes when runningAdvanced analysis monte carlo for the attached design
% W$ l# s7 X0 {5 ~2 G1275154 CONCEPT_HDL    CORE             Hierarchical Blocks lose refdesignators when moved to another page! |; _' B7 q7 e$ u! e
1275724 GRE            CORE             AiDT delete another clines0 s$ K& v3 V) g; Y- w$ Y- ?. u
1275831 ALLEGRO_EDITOR DRC_CONSTR       Waived DRCs return when usingmulti-thread DRC check4 t0 |( t  w; N" F# L( N
1275834 CONCEPT_HDL    CORE             ERROR (SPCOCD-569) on global bus, q! i. e: V/ [0 D* M' R/ k; q
1276334 ALLEGRO_EDITOR PADS_IN          PADS Library Import problem withoutlines' L1 Y0 t$ g; I1 Z, c8 H
1277062 ALLEGRO_EDITOR PLACEMENT        Swapping parts from top to bottomOrientation changes) @& J5 N( U# h$ n' P* E
1278746 ALLEGRO_EDITOR DRC_CONSTR       Package to package DRC allowsplace_bound_top in 0 spacing has drc in 16.6 version.
+ R; _5 ~9 ~1 f! g( r1278804 CONCEPT_HDL    COPY_PROJECT     Copy project crashes
- f4 C7 U' p& I; r: y( g1279362 ALLEGRO_EDITOR INTERACTIV       User skill file makes Allegro Icons goneaway
& ]. U$ L3 c. Y" T1279619 ALLEGRO_EDITOR DRC_CONSTR       Netgroup in a Netclass doesn't inheritSpacing Cset! @  P5 j( ^$ G( Z3 i) i' \) y  J
1279815 CONCEPT_HDL    CORE             Text > Change and RMB Editordoes not allow multiple text edits0 f, A8 o' i% Q; L$ m# v. F
1279876 ALLEGRO_EDITOR DATABASE         Using the Curved option in Filletsresults in a pad to shape DRC* z% U9 G: Q+ @1 O+ v3 {7 V7 C& X7 O, u% {
1280435 F2B            BOM              BOMHDL with variant repeats thePART_NUMBER value
! }1 p; L* |7 c& U1281669 CONCEPT_HDL    COMP_BROWSER     Match Any radio button in ComponentBrowser didn't work.- |5 {) r1 P- A7 B# ~/ V4 Y
1282001 ALLEGRO_EDITOR DRC_CONSTR       Updating the DRCs on this design causethe DRC count to change on every update8 k8 t* J& i) S( l
1282480 SIP_LAYOUT     WIREBOND         Info on the Wire Count property needsto be updated indicating that it is a User Defined Property. m% Y0 Y! G: d4 ^  r0 l
1283952 ALLEGRO_EDITOR PLOTTING         Published pdf does not show dotted orphantom lines
6 F# q* n3 Z; f8 E  ]9 l1283957 ALLEGRO_EDITOR INTERACTIV       Replace padstack in "Single ViaReplace Mode" is changing netname of the vias with the latest hotfix ofAllegro 16.6+ X  @9 G, F( \( E9 F
1285588 ALLEGRO_EDITOR DRC_CONSTR       Dynamic phase control has wrong analysisresult when add rectangle test bead in Clines.0 J$ d1 D$ p: [6 n- z2 ^; Q' q
1286743 ALLEGRO_EDITOR SHAPE            Getting copper islands in thedesign after running the Delete Plating Bar command
+ N( P- D2 N# G1287215 ALLEGRO_VIEWER OTHER            Allegro viewer plus does notsupport constraint regions
7 n0 t3 N( r) H  ~1288808 APD            LOGIC            Derive Assignment stalls out orwon?t finish and appears to run out of database room.% H7 j: h' N6 J2 A7 ^
1289251 ALLEGRO_EDITOR SCHEM_FTB        Pin escapes (clines and vias) notinheriting new net name from a pin with a new net name.& n; D( {5 N  S# C
1289293 F2B            DESIGNVARI       Warning 04: Cannot merge the variantproperties on variant instance C119 component with same canonical path notpresent; o3 M, v4 x, v% g
1289809 SCM            VERILOG_IMPORT   User not able to import a verilog netlistinto SCM
' F9 n4 q; W# |. Y1290696 CONCEPT_HDL    CORE             Copying a net name repeatedlycauses it to go off grid
; g' M6 u; f3 l) u5 \; Z9 j/ I/ X1291162 CONCEPT_HDL    CREFER           crefer crashes when selectinggenerate cross refernece for all nets selected
2 U: l: @8 {2 p  x# o- d1291285 SIP_LAYOUT     IMPORT_DATA      Replacing a Die with the Die Text inWizard causes some Clines to Shift, creating new DRCs.; Y  D( q; I3 ?  d" T9 p
1291658 ALLEGRO_EDITOR INTERACTIV       Cannot add Frectangle to Group
/ g. S4 i1 U5 h/ t$ @1292180 ALLEGRO_EDITOR SKILL            Allegro Crash while performingquery contents of "Maximum_Cavity_Size" with the skill command'axlDBGetPropDictEntry'
' R' b( I# c4 b/ Z! p3 G1292210 CONCEPT_HDL    CORE            DEHDL crash if design wasopened with -nonetlistuprev option.
  w! C$ z1 U/ T+ ]1 F1292278 SIP_LAYOUT     WIREBOND         When creating Wirebonds by Importing aWirebond File, (wbt) the wirebonds are not on the correct Die layer, J5 m$ \! H! U, ]2 s
1292282 SIP_LAYOUT     INTERACTIVE      Getting Multiple GUIs when the WirebondImport is open and we select outside the command GUI.& _& I/ N8 h3 }$ W; k; F
1293381 SIP_LAYOUT     IMPORT_DATA      Import SPD2 error
1 J5 ]+ Y' O+ n/ j7 J( Z1293889 CONCEPT_HDL    PAGE_MGMT        page name regression result deleted bynetassembler2 K4 Q4 |9 l# {( D
1294124 ALLEGRO_EDITOR INTERACTIV       Samsung Mobile division wants todisappear the grids in the display window when zoom-out function executes inthe allegr! N- K7 I! t! E# a7 g" ?! I" A: G. t
1294749 ALLEGRO_EDITOR ARTWORK          Null pad is flagged as an error thatbreak Thales automatic tape out
4 l1 c$ u2 G& e1294777 ALLEGRO_EDITOR SYMBOL           Mechanical symbols missed on STEPresult

该用户从未签到

2#
发表于 2014-7-30 20:53 | 只看该作者
我说这么长时间没有更新,原来cadence在憋大招了。

该用户从未签到

3#
发表于 2014-7-30 23:39 | 只看该作者
win7下安装破解后,allegro 很难运行起来啊,很卡。:Q:Q
  • TA的每日心情
    擦汗
    2019-12-12 15:00
  • 签到天数: 13 天

    [LV.3]偶尔看看II

    4#
    发表于 2014-7-31 10:19 | 只看该作者
    感謝大大的分享囉!!!

    该用户从未签到

    5#
    发表于 2014-8-4 18:20 | 只看该作者
    orcad的是什么?

    该用户从未签到

    7#
    发表于 2014-8-6 11:09 | 只看该作者
    ORCAD viewer挺不错的。另外一个不知道是升级补丁吗?

    该用户从未签到

    8#
    发表于 2014-8-6 23:40 | 只看该作者
    这个补丁主要是修复哪些方面的问题呢

    该用户从未签到

    10#
    发表于 2014-8-12 14:38 | 只看该作者
    麻烦再分享下,谢谢!
    * n; G- |3 X* `

    该用户从未签到

    11#
     楼主| 发表于 2014-8-12 15:24 | 只看该作者
    defir 发表于 2014-8-12 14:38  z. n1 [& Z' h$ C+ d8 {
    麻烦再分享下,谢谢!
    * F3 ~# r/ @8 I) {0 C
    33号补丁已经出了;还没上传上去

    该用户从未签到

    12#
    发表于 2014-8-12 15:35 | 只看该作者
    pzt648485640 发表于 2014-8-12 15:24
    - W$ l4 {8 q7 O: m' V33号补丁已经出了;还没上传上去

    ; ^3 ?1 @: m1 T! v# c太好了,现在用20号,生成XNET有问题,看论坛上有人说30号补丁对这个还没改善,不知道32有解决没。
    4 {; B) K* z( g" i9 I7 K' r2 t3 h7 F麻烦上传后给个链接,谢谢!

    该用户从未签到

    13#
     楼主| 发表于 2014-8-12 17:56 | 只看该作者
    defir 发表于 2014-8-12 15:35# W- _. R4 x1 i- U: v
    太好了,现在用20号,生成XNET有问题,看论坛上有人说30号补丁对这个还没改善,不知道32有解决没。, a7 `: Q, ^' W( @& M
    麻烦 ...
    / ?0 R$ Z" u$ ]+ i
    33号补丁已上传OK; D, T( `( l) o9 q, o4 O

    ! e2 _% G, M# U  i- ^& [比27到32号补丁好多了;不过出钻孔文件还是有点小问题的的。- n2 z$ }7 \7 r

    , _4 T6 d7 }" d8 }8 ^: x钻孔文件增加了CAM350支持选项去除项目英文

    该用户从未签到

    15#
    发表于 2014-8-22 14:46 | 只看该作者
    没看见有链接下载
    您需要登录后才可以回帖 登录 | 注册

    本版积分规则

    关闭

    推荐内容上一条 /1 下一条

    EDA365公众号

    关于我们|手机版|EDA365电子论坛网 ( 粤ICP备18020198号-1 )

    GMT+8, 2025-8-24 08:27 , Processed in 0.171875 second(s), 23 queries , Gzip On.

    深圳市墨知创新科技有限公司

    地址:深圳市南山区科技生态园2栋A座805 电话:19926409050

    快速回复 返回顶部 返回列表