这段文字如何理解呢？为何会进入亚稳态？

mengzhuhao

这段文字如何理解呢？为何会进入亚稳态？
5 T. u/ V- q! w
If the asynchronous reset is released at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.

mengzhuhao

The biggest problem with asynchronous resets is that they are asynchronous, both at the
4 Y3 c7 m: _$ p) _assertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the
) e- Y* x9 j0 h* k& h/ Tissue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the
! u/ \& N' b6 ]9 Noutput of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.
Another problem that an asynchronous reset can have, depending on its source, is spurious resets
% W5 w9 U) ]: D6 j, L! Qdue to noise or glitches on the board or system reset. See section 8.0 for a possible solution to
reset glitches. If this is a real problem in a system, then one might think that using synchronous
/ _0 u( j. y. y+ _" c  Hresets is the solution. A different but similar problem exists for synchronous resets if these
spurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is
2 F- Y9 m, q1 G! ]' strue of any data input that violates setup requirements).