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发表于 2014-11-16 10:34
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DATE: 11-14-2014 HOTFIX VERSION: 039$ H7 G& f7 S" g6 ?, c5 B
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
4 C: N( J: q( ^ @4 Z===================================================================================================================================
% Y) b& a$ M9 q' R3 \1213239 FLOWS PROJMGR SPI_ERROR: Missing closing quote at line 41 in""0 C3 ?' N" J% L2 B5 m
1301262 SPIF OTHER When creating .dsn file for designs containing netclasses with net groups, PCB Editor stops responding.
/ E+ h1 Y/ N [- ?1301469 CONCEPT_HDL CORE DE-HDL Import Design - Need a directive to enable the "Retain Hard Packaging Information" option by default3 U3 B" _2 r6 t( ~% |
1309535 SYSTEMSI ENG_PBA PA5700: Cannot print, save, or post process SI analysis reports
7 Z1 u3 I+ S% q0 Y1 N1317019 SIG_INTEGRITY LIBRARY Buffer model for pins not changing correctly when multiple DML files are present in working directory.
7 p4 s- S t3 Q8 c! E, P9 K/ L( r1318452 ALLEGRO_EDITOR DATABASE Derive Connectivity does not update connections; DRC errors thrown
- R! A7 g: b% a6 A) j) L' U* z1318610 CONCEPT_HDL CORE DE-HDL does not re-validate/re-read DML files on disk upon launching Constraint Manager
7 p9 q3 Q8 n% q- E/ M- m1320997 CAPTURE SCHEMATIC_EDITOR Copy paste of multiple images are stacked in same place.
- n3 z: |9 G( X# c, h. s1321377 FSP GUI FSP crashes while performing copy-paste operations between different arrays in the Rule text editor$ E; {4 i) c: b' k" n
1321513 ALLEGRO_EDITOR SYMBOL Preview not available for DRA3 E" `9 W# H- G1 l5 m6 {. Y
1324479 ALLEGRO_EDITOR OTHER Option specified in license_packages_allegro.txt file but missing in license server causes Segmentation fault on LINUX
8 M# I7 s* Z& k4 U1327962 FSP MODEL_EDITOR Need ability to select multiple pins in the Preview area of Rule Editor6 }1 c# d5 F) a: ~; p1 x
1328633 CONCEPT_HDL CORE On running Save All, changes were partially saved before DE-HDL crashed. N8 _9 _ g% e; v1 i7 p
1328921 ALLEGRO_EDITOR DATABASE Running Derive Connectivity followed by Database Check throws SPMHUT-17 error
& R7 {0 O9 s1 @7 ?$ S1330029 CONCEPT_HDL CORE PIN_TYPE and PINUSE attributes not updated consistently in DE-HDL design
/ n- r2 q- |2 {$ [4 \- `% V1330580 SIP_LAYOUT SYMB_EDIT_APPMOD When adding a pin using the Symbol Editor the Pin Name is being changed if duplicated
" ~# {& d0 R9 _' E1331028 CONCEPT_HDL CHECKPLUS Rules Checker fails on DE-HDL component.
. E# m& H/ v( W7 k1331051 ALLEGRO_EDITOR INTERFACES Soldermask layer is mapped to both Soldermask solderPaste and Miscellaneous Image Layers columns using IPC-2581B2 e$ U) j! i! S7 B% s
1333127 CONCEPT_HDL CORE Sheet number in the new window is only the block-level number and not the design-level number
2 G' {0 d9 J$ |( R1333591 SIP_LAYOUT SKILL Difference in behavior for padstack replace using axlPadstackReplace and command Replace Padstack; t7 d( a. f1 L$ G: _( n0 _2 `
1333896 ASI_SI OTHER signoise -f and -k options don't work for net names with consecutive underscores.
* k( `5 P" j; s: r) y1333982 ALLEGRO_EDITOR ARTWORK ARTWORK: Coordinates of the hole get shifted by the "Draw holes only" option.2 D* f$ G+ d$ V S, [
1334302 CONSTRAINT_MGR SCHEM_FTB Import Logic - Import changes only or Overwrite current constraints fails to update signal models.
. V+ ]/ f" i ?7 R1335276 CONCEPT_HDL OTHER On selecting objects near the schematic page border, the border is also selected+ O0 H% B: a0 ]3 d' ?
1336322 CONCEPT_HDL CORE DE-HDL does not open with maximized window.
* U+ C5 z/ q y) f1336783 PCB_LIBRARIAN IMPORT_EXPORT con2cap fails to export the part to OrCAD Capture format |
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发表于 2014-11-16 10:30
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发表于 2014-11-16 23:52
