Hotfix_SPB16.60.040_wint_1of1.exe 更新

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SPB16.60稍后跟链接           链接：http://pan.baidu.com/s/1o69LWDk 密码：v1l5
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% d3 q- s. I' xDATE: 12-12-2014   HOTFIX VERSION: 040
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CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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, d6 A0 w! n2 v, m9 |' f8 U577694  allegro_EDITOR OTHER            Need to retain padstack edits during "Refresh Symbols"
" D9 B! X6 V6 R2 f9 F" @) x1 F1105280 FSP            MODEL_EDITOR     Negative Voltage leads to 'Internal error. Invalid voltage value -12 specified for pin'
! i0 ~  c$ E  X) L: l3 t+ b! F1198148 FSP            OTHER            In the Symbol Setup form instances instantiated multiple times must be customized individually
1200015 concept_HDL    CORE             module_order.dat is generated for sym_n view automatically
1275209 Pspice         NETLISTER        PSpice is not considering 3K9 as 3.9K if inside a condition in PSpice template
1297335 SPECCTRA       FANOUT           Wrong fanout created in PCB Editor on using the Route Automatic option.
$ B# L. B: h7 [1316637 CONCEPT_HDL    PDF              PublishPDF does not set arc lines to the defined line width setting
1320581 ALLEGRO_EDITOR OTHER            Dangling line listed in Dangling Line report but no line exists.
, `) s' m" H- X5 W9 b5 }+ C1326104 CONCEPT_HDL    CORE             Pin dots, pin text do not stay on grid in symbol editor on moving/copying.
7 W0 U  J1 @2 {; C# g5 n1329848 CONSTRAINT_MGR CONCEPT_HDL      Export Excel from DE-HDL CM displays 'Server busy' message.
% \- B! h/ z2 l7 h1 ]$ H' R) P4 r- t1330044 CONSTRAINT_MGR OTHER            Need command line equivalent of cmDiffUtility to save reports as HTML
0 D) ^" A/ @/ W7 P1 `/ N1330122 SIP_LAYOUT     PLACEMENT        When placing IC type symbols in SiP they are being placed as Wire Bond instead of Flip Chip.
1330930 CONCEPT_HDL    CORE             Hyperlink in attributes window not working.
1336086 SIP_LAYOUT     MANUFACTURING    If a design has bondfingers at a certain angle/position the tool does not create a soldermask opening
1338610 MODEL_INTEGRIT TRANSLATION      IBIS to DML failed with incorrect error message.
1338925 ALLEGRO_EDITOR MANUFACT         Need a 16.5 route file option in SPB 16.6.
1339672 CONCEPT_HDL    CORE             Editing a symbol in PDV results in error (SPCOCN-1731)
6 Q- |: i, _8 H  I/ o& _1339987 ALLEGRO_EDITOR skill            axlFormCreate embeddedForm is not working as expected
1339989 PCB_LIBRARIAN  LIBUTIL          Con2con exits if Global section of PTF file has NC_PINS
1 s- ?) p6 l% r6 m% z1340342 F2B            DESIGNVARI       DE-HDL crashes when trying to use Variant commands
. R' ?" e0 }7 ^5 f4 F) ^2 a1340360 ALLEGRO_EDITOR EDIT_ETCH        On running the AiDT command, if Total Etch Length is defined directly on an XNet, PCB Editor crashes.
1340854 CONSTRAINT_MGR CONCEPT_HDL      Component properties are lost during backannotation
9 l& v7 X5 _) S) [6 G, C1341096 SIP_LAYOUT     ASSY_RULE_CHECK  ADRC rule 'Wire to Pad Optical Short' gives wrong results
1341330 ALLEGRO_EDITOR DRC_CONSTR       Spacing rules not followed if bond_pad is set to bond_finger
1342705 ALLEGRO_EDITOR INTERFACES       IDX incremental bend areas need delete processed first before adds
" P# t, r5 V$ }" O" R' H& d' p! X1342910 FSP            SETTINGS         Unable to remove "Don't Use Banks" setting.
1343076 SIG_INTEGRITY  OTHER            'orcad PCB Professional' tier should not allow Differential Pair extraction
: N9 q- h. X& A2 e8 X2 [$ ]1343239 PCB_LIBRARIAN  VERIFICATION     Con2con reporting errors against the wrong primitive
1 Z# C6 R) e% F8 W! J1343257 SCM            SETUP            In SCM, unable to add termination to design.
1343403 CONCEPT_HDL    CORE             Return code in Search_History prevents DE-HDL launch.
1343749 CONCEPT_HDL    CORE             Global Navigate does not always respond
1343870 ALLEGRO_EDITOR DATABASE         Import Logic changes VIA net names to GND
1343949 FSP            IMPORT_ALLEGRO   Import Instances from PCB Editor does not import FPGA model
6 L; J. i$ ?: q( ?0 ~1344265 CONCEPT_HDL    CORE             DE-HDL crashes on viewing page search
' K/ B  r$ @9 E- W1344413 SIP_LAYOUT     DIE_GENERATOR    When composing a die From Geometry the die pads are shifting.
2 r6 n5 B& S/ m1 }2 g% ]* d1344745 ALLEGRO_EDITOR EXTRACT          Need information about the changes in the format of the report generated using axlExtractToFile()
1346277 SIP_LAYOUT     DIE_ABSTRACT_IF  Shape cannot be read when sip_symed_codesign is set.
1346318 CONSTRAINT_MGR OTHER            cmDiffUtility shows "unrelease_unrelease.." message and stops
9 W/ s9 d% N# T) }; ~1346621 ASI_PI         GUI              Sigrity tools shown in PI Base Analyze menu regardless of option selected
1347103 ALLEGRO_EDITOR INTERFACES       Step mapping - 3D view for mechanical symbol

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