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本帖最后由 zgyzgy 于 2015-6-29 19:30 编辑 1 I/ w" o$ ?0 k& v3 x) v
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这次出大招了更新好多。官网显示是52，DATE里面介绍是51：
( _' x3 P2 z% Y. S- P8 ADATE: 06-26-2015 HOTFIX VERSION: 051
: { i0 {8 m4 [$ V: V3 k ` n: q5 M===================================================================================================================================
$ ^+ ~$ r# b4 H: e+ N" T- WCCRID PRODUCT PRODUCTLEVEL2 TITLE
_ P+ q: L# ?( [6 m9 A3 G===================================================================================================================================
" R$ R# H* b7 o) H; d7 L295747 allegro_EDITOR PLACEMENT Place manual form takes a long time to open) g9 j |/ v9 H2 w. L. k5 f
713130 CAPTURE GENERAL Bias points get displaced when schematic is copied/pasted in MS Word/ R$ F9 O9 E. I/ V; I
832170 SIG_INTEGRITY SIMULATION IBIS buffer results with two TV curves do not correlate with HyperLnx or MATLAB results
# x% A5 C9 b- ~2 y. @926138 SIG_INTEGRITY SIMULATION IBIS buffer results with two TV curves do not correlate with HyperLnx or MATLAB results ]# x8 L5 T9 y0 B
1056824 ALLEGRO_EDITOR INTERACTIV Need a way to repeat the 'Snap pick to' selection
' @+ G- W+ D* u7 c0 M1131613 concept_HDL COMP_BROWSER DE-HDL: inconsistent display of hyperlinks in Component Browser
7 S6 e7 N9 K# D* }% I7 Z1156766 ALLEGRO_EDITOR INTERACTIV Retain selected options (lasso, polygon, or path)
0 e y; K% v% s3 }1224882 CONCEPT_HDL CORE Unable to modify the port position on the sym view if the signal names have double underscores
) F1 r9 d5 ~! b$ @, I/ i+ U, [1225998 CAPTURE NETGROUPS Bug: Normal scalar hierarchical pin is getting changed to netgroup pin# P% O- Z @ p/ ]
1281668 ALLEGRO_EDITOR EDIT_ETCH Arc bump of AiPT
9 e' k2 W2 x$ _3 D/ i* D" _1286749 FSP PROCESS FSP not allowing group swap across inteRFaces in same_vccaux_io region( O5 A% P0 o. L7 r, H6 P
1306988 SIG_INTEGRITY SIMULATION Support needed for the multiple VI and VT waveforms for the buffer with TLSIM) |$ T$ g7 z* x$ }
1311177 CONCEPT_HDL CORE Save Hierarchy for read-only blocks should not produce ERROR(SPCOCN-2123)7 [" K* H" Y, g3 \( P
1315888 SIP_LAYOUT ASSY_RULE_CHECK "Dummy" DRC violations with xhatched shapes filled with "crosshatch void fill" function
+ ]+ ^! }; }- V, Y; R1319663 PCB_LIBRARIAN VERIFICATION con2con always reports the first part name when problems are reported for 2nd or 3rd part name from same primitive6 [+ A4 @( f: U* f7 J
1321192 APD VIA_STRUCTURE When atttempting to delete a layer we get the warning messages stating its a symbol when its a Via Structure issue.8 ~1 T/ }- \- Q, {
1324280 ALLEGRO_EDITOR COLOR Layer Priority for user-defined Ref Des Layers7 k1 l- F( g" u- u# p: ^) Y- F2 p2 D
1327949 CONCEPT_HDL CORE not able to add placeholder for VOLTAGE to bodies
. r" |7 s. {& e! R1 j+ t1332123 APD INTERACTIVE Snap to pin is snapping to via.( v, n- |' U* G: o! p9 k
1333113 F2B PACKAGERXL A hard LOCATION9 }8 V( F! [/ O7 S, A: x
1335908 CIS RELATIONAL_DB Relational data fields order do not appear correctly in CIS BOM.% k7 o8 o% D& y% W4 t, g% r# C0 }
1336970 ADW LRM Replaced by report does not show the replacement part) g( N9 u E) v R
1337197 ADW LRM DE-HDL crashes and corrupts design during LRM update* g! m' u, \1 _. v6 q
1337548 CONCEPT_HDL COMP_BROWSER Component Browser in the cached mode crashes when doing a search' v- t0 E3 d; p
1341177 ALLEGRO_EDITOR PLACEMENT Need the ability to resize the Place Replicate Unmatched Component Interface window, f6 ^; J9 ?& f. d
1341940 APD OTHER WIRE_COUNT check doesn't work for diepad to diepad bond1 y! V8 D8 N" {
1341947 SIG_EXPLORER OTHER Sigxplorer hangs when the Wizard_Template_Path variable is set
! K. t4 o. n. J8 `! {( Q8 O1343981 SIP_LAYOUT MANUFACTURING add an option (Refdes) for Display Pin Text
' K: b) A9 I3 d, m8 T2 ]4 k& R1345577 TDA CORE TDO crashes when attempting to check-out block" R- A( s$ x; ], _5 \
1345601 TDA CORE Error message when attempting to change to ECO mode2 W" p* a3 N) U9 a
1345629 ADW LRM LRM deletes worklib contents when updating schematic design. u* x, B a+ }5 K6 x7 Q% K
1346088 ADW DSN_MIGRATION Parts missing in part_table.ptf after design migration6 m6 O9 a! b* ]5 L% `. l" _# b {
1346925 APD STREAM_IF Need ability to have same class/subclass mapped to more than one stream layer3 ]# `1 d( ^. E' l
1347102 CIS GEN_BOM MDB file is shown wrong variant name
- y( {$ U( ~) [ Y1347145 CAPTURE INTERFACES Capture crash while editing comapre test bench settings for Pspice design
* ]4 D. G K: f- p$ _8 D% l1348619 ADW LRM LRM does not update symbol and its attributes in the schematic7 l P. Y( s% E
1351123 CONCEPT_HDL CORE Changing Net Name in Attribute or using Text > Change deletes constraints
3 t) @' r) H; @1351700 ADW LRM LRM Crashes while loading design, k6 Z# b; r( p, y% e3 E, L
1353844 ALLEGRO_EDITOR SHAPE When creating a copper shape on the M2 layer a void is created running top to the bottom.) c: v' v7 Y1 {, c. }
1354049 SIP_LAYOUT ASSY_RULE_CHECK Exclude fillet shapes from the Continuous Solder Mask Coverage ADRC check
% o" K9 W' K9 s$ c& N1354790 CONCEPT_HDL COMP_BROWSER Remove limit of 2500 for Component Browser search results
+ x9 U3 w- L7 }6 I1355258 ALLEGRO_EDITOR DATABASE Matched Groups generating wrong pin pairs
6 c, ^& \4 L' ^% Q% {. }1355882 ADW TDA ERROR(SPDWSD-58): Unable to copy file ... to folder ... /.sdm/tarballs& `# C3 r+ d" t4 f" q/ L
1357624 CONCEPT_HDL CORE DEHDL fails to recognize PTF header changes resolved by LRM
" g# P# W2 Q, X6 _5 P; G# K1357760 CONCEPT_HDL OTHER What arguments to use when starting DE-HDL with options?5 @, Y& C8 g5 g q; w. ?/ o3 \
1358018 CONCEPT_HDL CORE PinPosition from template.tsg located at $CDS_SITE is not honoured for split hier block symbol generation3 e8 W& x! }' q/ }7 |( {- j& `
1358053 TDA CORE TDO and VarEdit: Check out variant_cbc.dat separately1 [$ G) ]! H5 |) H/ W2 s5 d
1358511 ALLEGRO_EDITOR INTERACTIV Replace padstack error message unclear& {& `; J( I. ^2 [
1359168 CAPTURE TCL_INTERFACE Bug: CIS "Place database part check" tcl command not working% l" b' \' `' A& ~) r1 F
1359357 CONCEPT_HDL OTHER HF039 BOM_IGNORE for complex hierarchy is not working normally" d. @! e$ H- F, \) l
1360071 CONCEPT_HDL CORE The Change Properties dialog does not show a cursor when selecting5 ]6 G& ?" V: g) \$ i/ n, X
1360554 ALLEGRO_EDITOR DRC_CONSTR Same net DRC disappeared after update DRC.
- c3 P+ \: A* Y' i* K1360653 CONCEPT_HDL CORE CUSTOM_TXT_CDS not working for defprop in template.tsg2 f" M$ v& v/ o' x( R& U8 Y
1360772 SIP_LAYOUT INTERACTIVE Cannot change Clines to a different layer.) O* G8 t2 U5 U. s( k9 _
1361281 ALLEGRO_EDITOR INTERACTIV Unlike stacked vias, moving non-stacked vias requires an additional step of choosing a pick point
/ G0 ^5 a/ M, M% z/ H1 r1362156 ALLEGRO_EDITOR PCAD_IN PCAD import to PCB Editor fails with message "ERROR: netname not NULL for non-etch class"; S! n: a' O) x
1363298 ADW PCBCACHE Part Manager Error when replacing a part with a4 S+ w. |6 I$ t$ `
1365794 ALLEGRO_EDITOR PCAD_IN PCAD to Allegro translation does not generate the translated board file and also does not give any error message.+ ^& B- i& I- v! M5 r0 D% x0 ?. Q9 d3 d
1366525 ALLEGRO_EDITOR INTERACTIV The "replace via structure" command of APD and SiP is also required in Allegro PCB Editor
P: L! t! V8 `9 O& o P1366976 APD EDIT_ETCH Interactive edit etch slide command not working as expected.
9 g+ E8 J/ y$ j1367224 ALLEGRO_EDITOR INTERACTIV merge 'shape edit mode' into 16.69.
, c8 ^2 y: S- J5 o. X1367314 CONCEPT_HDL OTHER Setting lock of Reference schematic.# A- e2 A* Q, S: \5 q
1367609 F2B DESIGNVARI Variant overlay shows the ALT_SYMBOLS attribute for modified inductors% R' m/ V1 B n. I9 _4 x/ t
1368091 ALLEGRO_EDITOR INTERACTIV A filled rectangle should be treated as a shape to use the "snap pick to" function with the "Shape Center" option E' N' Y5 m/ G5 ]1 K0 | t, G; ~
1368159 CONCEPT_HDL CONSTRAINT_MGR Make CM_DEFAULT_PRECISION a site.cpm directive
. a! U% z* d- Y- k2 A. C1370186 SIP_LAYOUT EDIT_ETCH Cannot add a via to the selected layer
R! m5 a/ ^8 Z4 r! _! w1371015 CAPTURE OTHER Tools > Update properties displays Error (ORCAP-1579)# s. t, E7 p) P' E: V+ y% v! i
1371807 CAPTURE SCHEMATIC_EDITOR Button Status for 'drag connected objects' hard to see
- J& y+ n9 I9 V p! K1372282 TDA CORE Integrator utility to refresh policy' c. l- h) {% d8 E/ C# S
1372351 CAPTURE DRC Browse DRC marker and search of DRC marker are giving different results.& l3 B8 c4 [5 y/ N) g; X
1373118 CONCEPT_HDL CORE Only generate $HOME/cdssetup/concept files when changes are made
# }+ v) W% H; [3 P1 d1373412 ALLEGRO_EDITOR GRAPHICS SigXP Print Canvas: Via model is filled by a black via box* e( d9 |+ r5 f3 S
1373575 CONCEPT_HDL INTERFACE_DESIGN Net Group name clash Pin Name0 w* V! ]. j/ }" O9 J Z7 r8 @
1374703 ALLEGRO_EDITOR SHAPE Inconsistent behavior on shape voiding j& Q5 `# ]4 z( m( }
1375127 ALLEGRO_EDITOR INTERACTIV The errset skill command with axlSpreadsheetRead crashes the tool
/ i& C% S0 ^ r% @1375940 PCB_LIBRARIAN PTF_EDITOR PTF Editor error messages are truncated.$ s A" m. u4 a
1375974 ASI_SI GUI want to use SigWave on SI Base2 O! ]2 e3 J' Y* [
1376591 ALLEGRO_EDITOR COLOR Dehighlight command with "Dehighlight All" option does not remove the color marker swatches from Constraint Manager
. F/ J) M3 O: p+ u2 @1376634 ALLEGRO_EDITOR INTERACTIV Snap pick to symbol center not working in symbol editor3 I4 \+ e% l, v2 C
1376765 CONSTRAINT_MGR ANALYSIS Setup/Hold spreadsheet lists only one pin pair6 N" x% n3 J8 M
1376851 CONSTRAINT_MGR UI_FORMS CM workbooks change after simulating
. t6 J, I2 v* y# p: P$ L1377555 ALLEGRO_EDITOR DRC_CONSTR The "Line to SMD Pin Same Net Spacing" DRC appears and disappears each time Force Update is run for Dynamic Shapes
: m7 \" i- T8 h0 A0 d1377606 APD REPORTS APD16.6 Missing Fillets Report ?4 G' q. h) w0 s- A! |9 B
1378094 CAPTURE EE_INTERSHEET_RE intersheet References are wrong) t# w0 M4 B6 j
1378625 ALLEGRO_EDITOR FSP_PINSWAP FSP crashes while synchronizing design
% @& }* f9 C# z) C) J1378703 CAPTURE DRC different DRC results even design and options not changed% ] {, _, M# ]8 _$ M7 D9 }4 B
1382541 PCB_LIBRARIAN CORE Show Pin Numbers in Global Rename Pin dialog for better understanding# K- B% p1 q! d4 X
1394552 CONCEPT_HDL OTHER The link function enhancement.
! G9 f; Q4 A( v# m. V& _# e1395007 CONCEPT_HDL INTERFACE_DESIGN Issue with NET_SPACING_TYPE and NET_PHYSICAL_TYPE properties depending on visibility0 |) V t' H" \' p, R1 i2 J2 ~
1395033 CAPTURE HELP Project opens as text file if the directory or project or project name has .v in it.; a8 o( c6 N1 o5 k, a
1395356 SIP_LAYOUT SHAPE When merging shapes, a certain void in one of the shapes changes location and is resized
+ f! u o$ n8 r$ a% S$ j4 K- l; |& b1397564 CONCEPT_HDL CORE Design Entry HDL crashes when opening from Part Developer: f5 z" E. I6 [2 D; C* s
1398919 CONCEPT_HDL INTERFACE_DESIGN NG buss error
5 m/ ` j$ M0 G! u1399924 CAPTURE OTHER Error message location always shows in inches
0 M: e* g3 J/ p0 u7 F1400086 CONCEPT_HDL CORE Option to retain the distance between Pin number and wire/pin while moving a pin number.3 u4 b& @" e7 Q* a4 O/ y
1400691 CONCEPT_HDL INTERFACE_DESIGN Rename of netgroups is a must
4 y7 N" Q( U2 A6 C7 B, t9 p/ N1400755 ALLEGRO_EDITOR SHAPE Updating shapes on design causes a short to a pad2 {) k: W, V! G& m# Y5 Y8 m6 ]
1401320 ADW COMPONENT_BROWSE Issues with filtering in Component Browser, c+ o) Y7 \( @5 y: L$ O: N
1401900 ALLEGRO_EDITOR MANUFACT Drill chart resized from V16.5 to V16.6) k. K6 M# `) y, L+ x4 ?
1402317 ADW DSN_MIGRATION Design Migration hangs in the final stage "saving the design"9 `* b/ L$ K) q1 z4 L& K0 D
1403716 SIP_LAYOUT SYMB_EDIT_APPMOD SiP layout - Dynamic ability to applying expansion/compression of symbol using app mode! w. A- D5 ^9 @
1404071 SCM ERROR_WINDOW About Violations window messages and Export Physical
1 q9 |! e6 m- ~# M* k: u0 J1404754 TDA CORE setPermissions client API needs to be changed to pass only changed permissions
5 \& q) o: y9 \- f: a$ a: f9 Z" B1404993 ALLEGRO_EDITOR DATABASE dbdoctor falsely reports Illegal rectangle size error has been fixed.
8 T' f- C7 h4 J1405018 ADW COMPONENT_BROWSE Need a way to move the Attributes tab first, but make the Properties tab open by default6 z$ \6 F* N s. c/ n
1405201 CONCEPT_HDL INTERFACE_DESIGN Provide mechanism to sort the Net Groups created in the Interface Browser" }; T4 B L& _, q. M5 y* P! v
1405896 CIS PLACE_DATABASE_P If FPLIST field is set to transfer to design in DBC, Capture CIS crashes
( K. o) {% j* ?3 S1406554 CONCEPT_HDL INTERFACE_DESIGN When trying to map a port group all members cant be selected
) c- n1 m+ ?# b, H1406780 CONSTRAINT_MGR OTHER Deleting cline segments when Constraint Manager is open on net properties bundle crashes PCB Editor
: \+ y8 E/ G- i8 ]0 `5 x1407817 CONCEPT_HDL INTERFACE_DESIGN Port group mapping issues on saving design when using non-high speed license
2 f6 \+ q# k L z1408001 ADW COMPONENT_BROWSE Searchable only properties are missing from a shopping list in UCB
& R4 L0 z7 t' J5 @1408414 ALLEGRO_EDITOR DRC_CONSTR Waived DRC does not move with the elements it is associated) [. J: j$ b2 m; L: d% S
1409474 CONCEPT_HDL GLOBALCHANGE Global Replace does not retain refdes values
2 \" v" E( }- u- z: c0 d% G1 w Q1410333 CONSTRAINT_MGR DATABASE Unrouted net length does not match total Manhattan length/ R# F- `) n* O4 F
1410857 ALLEGRO_EDITOR DRC_CONSTR Diff Pair Uncoupled length DRC gives different results in SPB16.3, SPB16.5, and SPB16.6.
4 `* X) G9 W! G2 X- }% _1411936 CONCEPT_HDL CORE Font support for $PN is inconsistent
$ I9 w2 X* y5 g$ B" ^* R1412878 ADW COMPONENT_BROWSE Shopping cart tooltip for PPL error has a bad character
1 F5 v* j6 R8 c: ?! J; D! u1413243 F2B PACKAGERXL Backannotation warnings about $PN not deleted from Property file (dcf)
2 U v* N' B ~) @6 s: i k4 }4 X/ A1413699 F2B DESIGNVARI Provide an option to create variant-specific schematics without any variant specific color overwrites
8 P; [& s; n r( X1414672 ALLEGRO_EDITOR PAD_EDITOR Padstack designer Lock mechanisim fails to lock padstack when it's reopened.2 V: b2 |7 n" C! P- h
1415863 CONSTRAINT_MGR OTHER DCF import ignores Voltage property values
, o. ~, n. H O3 I8 {( J1416561 F2B DESIGNVARI When using the Replace Component command in DE-HDL, Component Browser takes a long time to load+ b. a( Q4 ^/ C0 ^7 A f. d
1416704 ALLEGRO_EDITOR EDIT_ETCH AiDT Turning Pattern Corner type option to Arc1 ~! R; t+ @! Q' |, F$ h
1417283 CONCEPT_HDL INTERFACE_DESIGN Provide an option to flatten a block when adding it from Component Browser! x( G8 K! ]$ @
1417802 CONCEPT_HDL CORE Multiple ghost images while copying group or objects5 O& f0 `/ B( S# _1 B, Z
1418134 CONCEPT_HDL CORE Some objects are removed from the group on using the group move command in Linux& Y: F [# w) l0 M6 e
1418484 SIG_INTEGRITY SIMULATION Estimated Xtalk and Simulated Xtalk results do not match in 16.6 ISR0445 u3 a# s+ i* |( @ R2 X# O/ k) n! S
1419474 CONCEPT_HDL CORE CheckPlus, PDF Publisher, should detect invalid view files/ A. l8 k/ G- v- I
1419560 ADW COMPONENT_BROWSE Removing a value from the search criteria, removes the field from the displayed results
+ x$ D' n) R3 V! p* h1419954 SIP_LAYOUT DIE_ABSTRACT_IF add abstract show ic details to the place codesign die abstract form
" r% b" s5 [( f1 V4 \: ]) @6 P& `- x1420459 CAPTURE STABILITY Capture crashes when library has pages with parts where pin names or numbers have been moved
8 U2 A4 Z7 N. Z1420482 ADW LRM LRM deleting symbol properties during the UPDATE process4 n& F5 I/ s: q5 E
1420580 CONSTRAINT_MGR INTERACTIV Constraint Manager crashes when displaying the Relative Propagation Delay worksheet8 r$ c! f. t0 U- P2 y/ [3 j
1420623 CONCEPT_HDL CREFER creferhdl fails with message std::bad_alloc on Windows and Linux
. T4 M; l& \# ?5 ^1421106 ALLEGRO_EDITOR DATABASE Get message "E- (SPMHDB-183): 'SHAPE' object may not exist on layer 'ETCH/WIRE'" when updating dyanmic shape.: h V' s0 p9 Q6 [6 g$ H
1421352 ALLEGRO_EDITOR EDIT_ETCH Application crashes when Create Fanout is executed with a blank end layer.
$ M4 |- f" f1 i1421769 ALLEGRO_EDITOR MANUFACT NC Drill legend behavior changed from S040 to S048
) }3 y! m3 k0 e% {" G7 ~% Q1422131 APD DXF_IF dxf error) K: \. z8 a# c/ g: k
1422153 CONSTRAINT_MGR OTHER The display in cmDiffUtility is corrupted after a Match Group is removed2 t: w6 U. d- I: E$ n
1422372 CONCEPT_HDL PDF Publish PDF-generated file: Unable to click links or copy in Javascript window: @* a3 A# t2 u6 _) z8 ~
1422993 SIP_LAYOUT DIE_STACK_EDITOR Diestack Editor graphics depicts die stack incorrectly. The complete stack isn't shown
& \ x2 n1 L3 k1423268 SIP_LAYOUT SYMB_EDIT_APPMOD Update Die Extents causes Die layer change
. u* c( f6 {& s! \; C1 T8 `) z1423539 ALLEGRO_EDITOR EDIT_ETCH Timing Vision crashes for board., G% [9 {2 G& e: y8 h3 G4 D
1423988 ASI_SI GUI DesignLink system configuration file is not set automatically on SI-Base/ L* y' D5 S7 V% }3 B
1424053 SIP_LAYOUT ASSY_RULE_CHECK DRC info of "Acute Angle Merged Metal Check" reports the same via object to itself5 @' D: o8 S$ C: p/ F% n
1424415 GRE CORE 2 bundles are misbehaving during plan spatial.
0 Y1 q8 F1 q0 D! {' w# D2 t* Q1424773 CONCEPT_HDL OTHER How to delete schematic-defined netgroups with locked members in the top-level block
% `/ q/ V8 N% e u" ?1425060 RF_PCB DISCRETE_LIBX_2A Miscellaneous enhancements requested for discrete library translator
+ k1 J' Z) P! i1425592 F2B BOM Generating BOM in CSV format changes the value format
3 y+ f+ n8 Q! N1426286 ALLEGRO_EDITOR EXTRACT Slotted hole within a footprint supported in STEP file; g6 w' m9 ^* M7 @& D, [
1426593 CAPTURE DRC orcad Capture crashes on replaying DRC command.# L4 W7 U8 k, ~
1426939 CONCEPT_HDL CORE Error message SPCOCN-2208 can be misinterpreted* t( p; q, P- f3 g
1427364 F2B PACKAGERXL Board does not backannotate and generates this message: ERROR (SPCOPF-2069): COMP_DEVICE_TYPE$ Z' f' k# v; \( R
1427690 CONCEPT_HDL PDF PDF Publisher on remote display hangs if run on a design with a missing component7 h% ^" l: I: z9 _( u8 s" B7 w
1427721 CONCEPT_HDL CORE The copy paste command on text doesn't preserve the text size& `- y8 H$ e0 b2 ~
1428130 CONCEPT_HDL CORE LRM reports additional parts on schematic which were already synchronized with the cache ptf
( X" R9 N6 W5 N/ Z8 h3 Z/ o1 P1428925 CONCEPT_HDL CORE Global signal is not selected as base if it is synonymed to local signal with ase suffix.
# @' `5 E6 t) `- W5 S$ v1 m, g2 V5 [1429526 ALLEGRO_EDITOR INTERFACES Export PDF is blank if lanscape mode is selected.
% f9 U7 {) F* I1 D$ ^: G2 `! W" }1429840 SIP_LAYOUT SYMB_EDIT_APPMOD pin numbers are not applied if I have used library manager6 x$ X" S5 B+ x5 }" a" F c
1430098 ORBITIO ALLEGRO_SIP_IF The Die Pads and Vias around Die are missing when the SiP database is imported in ORbitIO- L! Y7 B$ h9 x
1430564 ALLEGRO_EDITOR PLACEMENT moving group separates Place Bound from group 不好意下载上传都比较慢让大家久等了。下载链接 ：http://pan.baidu.com/s/1qWwYnNI2 L N- g9 d' D
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发表于 2015-6-28 20:56
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