Hotfix_SPB16.60.052

zgyzgy

) z% Z! J; G9 u0 A5 s) H" V9 [这次出大招了更新好多。官网显示是52，DATE里面介绍是51：
DATE: 06-26-2015   HOTFIX VERSION: 051
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CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
  `/ v; M) j( U2 v4 S===================================================================================================================================
* m* U4 p* x2 B% d7 N3 L7 o295747  allegro_EDITOR PLACEMENT        Place manual form takes a long time to open
5 q2 X, n7 ?3 n- z. v. t9 P713130  CAPTURE        GENERAL          Bias points get displaced when schematic is copied/pasted in MS Word
. I- \( ?" L7 x3 B( f& O832170  SIG_INTEGRITY  SIMULATION       IBIS buffer results with two TV curves do not correlate with HyperLnx or MATLAB results
) H' Q7 H+ n4 W926138  SIG_INTEGRITY  SIMULATION       IBIS buffer results with two TV curves do not correlate with HyperLnx or MATLAB results
1056824 ALLEGRO_EDITOR INTERACTIV       Need a way to repeat the 'Snap pick to' selection
! T3 R5 Z2 q/ O% O% b: P1131613 concept_HDL    COMP_BROWSER     DE-HDL: inconsistent display of hyperlinks in Component Browser
1156766 ALLEGRO_EDITOR INTERACTIV       Retain selected options (lasso, polygon, or path)
+ _6 E# a! Y& h% S0 A0 ~1224882 CONCEPT_HDL    CORE             Unable to modify the port position on the sym view if the signal names have double underscores
. j- l. m  g1 K( f. r8 S, z, D1225998 CAPTURE        NETGROUPS        Bug: Normal scalar hierarchical pin is getting changed to netgroup pin
/ S  c/ g0 r" L/ p# W) v( @1 y1281668 ALLEGRO_EDITOR EDIT_ETCH        Arc bump of AiPT
( B  o; y" d7 Q+ N1286749 FSP            PROCESS          FSP not allowing group swap across inteRFaces in same_vccaux_io region
. ~- ~: @& E. a. ^1306988 SIG_INTEGRITY  SIMULATION       Support needed for the multiple VI and VT waveforms for the buffer with TLSIM
1311177 CONCEPT_HDL    CORE             Save Hierarchy for read-only blocks should not produce ERROR(SPCOCN-2123)
1315888 SIP_LAYOUT     ASSY_RULE_CHECK  "Dummy" DRC violations with xhatched shapes filled with "crosshatch void fill" function
1319663 PCB_LIBRARIAN  VERIFICATION     con2con always reports the first part name when problems are reported for 2nd or 3rd part name from same primitive
7 ?& b9 n; l  y/ Z1321192 APD            VIA_STRUCTURE    When atttempting to delete a layer we get the warning messages stating its a symbol when its a Via Structure issue.
1324280 ALLEGRO_EDITOR COLOR            Layer Priority for user-defined Ref Des Layers
4 F& Z: R' ^! N# c1327949 CONCEPT_HDL    CORE             not able to add placeholder for VOLTAGE to bodies
1332123 APD            INTERACTIVE      Snap to pin is snapping to via.
: D, m9 \0 P: K0 ~5 i- Z  c) n1333113 F2B            PACKAGERXL       A hard LOCATION
5 |: ^9 l5 d3 `" m1335908 CIS            RELATIONAL_DB    Relational data fields order do not appear correctly in CIS BOM.
1336970 ADW            LRM              Replaced by report does not show the replacement part
1337197 ADW            LRM              DE-HDL crashes and corrupts design during LRM update
4 U/ \" ?: i! e$ v1337548 CONCEPT_HDL    COMP_BROWSER     Component Browser in the cached mode crashes when doing a search
. x' R* e1 Z0 m7 }; v; u7 V1341177 ALLEGRO_EDITOR PLACEMENT        Need the ability to resize the Place Replicate Unmatched Component Interface window
! q8 G" r  ^- W' P! I, j4 q1341940 APD            OTHER            WIRE_COUNT check doesn't work for diepad to diepad bond
# Z" x1 {% L4 ~. ^/ v1 Q% h' f2 A1341947 SIG_EXPLORER   OTHER            Sigxplorer hangs when the Wizard_Template_Path variable is set
* @' }: Z0 C+ B$ w1343981 SIP_LAYOUT     MANUFACTURING    add an option (Refdes) for Display Pin Text
& g: H% z) R5 ]1345577 TDA            CORE             TDO crashes when attempting to check-out block
% ]8 p! M& }. m0 P3 }1345601 TDA            CORE             Error message when attempting to change to ECO mode
1345629 ADW            LRM              LRM deletes worklib contents when updating schematic design
1346088 ADW            DSN_MIGRATION    Parts missing in part_table.ptf after design migration
3 {: d$ K5 H% S$ D6 D9 e, W4 Y1346925 APD            STREAM_IF        Need ability to have same class/subclass mapped to more than one stream layer
( j+ N* a, y. }' D4 w* z, [# U1347102 CIS            GEN_BOM          MDB file is shown wrong variant name
1347145 CAPTURE        INTERFACES       Capture crash while editing comapre test bench settings for Pspice design
8 B5 f( h# J- H. S1348619 ADW            LRM              LRM does not update symbol and its attributes in the schematic
1351123 CONCEPT_HDL    CORE             Changing Net Name in Attribute or using Text > Change deletes constraints
0 q: z( f) v, @" A1351700 ADW            LRM              LRM Crashes while loading design
1353844 ALLEGRO_EDITOR SHAPE            When creating a copper shape on the M2 layer a void is created running top to the bottom.
' T. Y  `" h( w0 L  |' d- Q1354049 SIP_LAYOUT     ASSY_RULE_CHECK  Exclude fillet shapes from the Continuous Solder Mask Coverage ADRC check
- i* D; I. V* U/ r  `; i- L1354790 CONCEPT_HDL    COMP_BROWSER     Remove limit of 2500 for Component Browser search results
1355258 ALLEGRO_EDITOR DATABASE         Matched Groups generating wrong pin pairs
/ n9 g/ A0 ]) ^7 {! }$ H/ w, |1355882 ADW            TDA              ERROR(SPDWSD-58): Unable to copy file ... to folder ... /.sdm/tarballs
1357624 CONCEPT_HDL    CORE             DEHDL fails to recognize PTF header changes resolved by LRM
" q1 ]& h- v, L3 U, o3 u1357760 CONCEPT_HDL    OTHER            What arguments to use when starting DE-HDL with options?
$ b! @: B3 v! W1358018 CONCEPT_HDL    CORE             PinPosition from template.tsg located at $CDS_SITE is not honoured for split hier block symbol generation
% o1 U  D7 u. c* T" E1358053 TDA            CORE             TDO and VarEdit: Check out variant_cbc.dat separately
1358511 ALLEGRO_EDITOR INTERACTIV       Replace padstack error message unclear
1359168 CAPTURE        TCL_INTERFACE    Bug: CIS "Place database part check" tcl command not working
1359357 CONCEPT_HDL    OTHER            HF039 BOM_IGNORE for complex hierarchy is not working normally
1360071 CONCEPT_HDL    CORE             The Change Properties dialog does not show a cursor when selecting
2 l0 X6 d( @2 j3 n: C1360554 ALLEGRO_EDITOR DRC_CONSTR       Same net DRC disappeared after update DRC.
1360653 CONCEPT_HDL    CORE             CUSTOM_TXT_CDS not working for defprop in template.tsg
1360772 SIP_LAYOUT     INTERACTIVE      Cannot change Clines to a different layer.
1361281 ALLEGRO_EDITOR INTERACTIV       Unlike stacked vias, moving non-stacked vias requires an additional step of choosing a pick point
! n8 z1 K4 }% t2 C* h5 ~2 d: T1362156 ALLEGRO_EDITOR PCAD_IN          PCAD import to PCB Editor fails with message "ERROR: netname not NULL for non-etch class"
, g. c* X# M5 D/ ^1363298 ADW            PCBCACHE         Part Manager Error when replacing a part with a
/ Y$ I! z7 ]1 e2 h1365794 ALLEGRO_EDITOR PCAD_IN          PCAD to Allegro translation does not generate the translated board file and also does not give any error message.
9 b8 q$ z8 n0 j4 p/ Q8 k0 N1366525 ALLEGRO_EDITOR INTERACTIV       The "replace via structure" command of APD and SiP is also required in Allegro PCB Editor
1366976 APD            EDIT_ETCH        Interactive edit etch slide command not working as expected.
1367224 ALLEGRO_EDITOR INTERACTIV       merge 'shape edit mode' into 16.69.
1367314 CONCEPT_HDL    OTHER            Setting lock of Reference schematic.
1367609 F2B            DESIGNVARI       Variant overlay shows the ALT_SYMBOLS attribute for modified inductors
' @* k  c; v6 K% u% r6 l1368091 ALLEGRO_EDITOR INTERACTIV       A filled rectangle should be treated as a shape to use the "snap pick to" function with the "Shape Center" option
1368159 CONCEPT_HDL    CONSTRAINT_MGR   Make CM_DEFAULT_PRECISION a site.cpm directive
7 ~# x9 z5 c4 z# T  I. [/ S1370186 SIP_LAYOUT     EDIT_ETCH        Cannot add a via to the selected layer
; g$ {. T9 T$ `  W/ Y7 Q9 k* S1371015 CAPTURE        OTHER            Tools > Update properties displays Error (ORCAP-1579)
0 m2 ]4 R7 r1 u; `7 w5 h1371807 CAPTURE        SCHEMATIC_EDITOR Button Status for 'drag connected objects' hard to see
1372282 TDA            CORE             Integrator utility to refresh policy
1372351 CAPTURE        DRC              Browse DRC marker and search of DRC marker are giving different results.
1373118 CONCEPT_HDL    CORE             Only generate $HOME/cdssetup/concept files when changes are made
9 K* M$ Q& U1 S+ m2 W# p1373412 ALLEGRO_EDITOR GRAPHICS         SigXP Print Canvas: Via model is filled by a black via box
1373575 CONCEPT_HDL    INTERFACE_DESIGN Net Group name clash Pin Name
1374703 ALLEGRO_EDITOR SHAPE            Inconsistent behavior on shape voiding
& O) N9 A# W; l  @  c1375127 ALLEGRO_EDITOR INTERACTIV       The errset skill command with axlSpreadsheetRead crashes the tool
6 Y- X! L% U4 K1 S; B1375940 PCB_LIBRARIAN  PTF_EDITOR       PTF Editor error messages are truncated.
5 R8 h- T0 f7 H4 A, N1375974 ASI_SI         GUI              want to use SigWave on SI Base
1376591 ALLEGRO_EDITOR COLOR            Dehighlight command with "Dehighlight All" option does not remove the color marker swatches from Constraint Manager
1376634 ALLEGRO_EDITOR INTERACTIV       Snap pick to symbol center not working in symbol editor
" |4 L8 c# r" T  a$ @1376765 CONSTRAINT_MGR ANALYSIS         Setup/Hold spreadsheet lists only one pin pair
% j: g4 q2 n& x, m% J4 P1376851 CONSTRAINT_MGR UI_FORMS         CM workbooks change after simulating
' k8 q, ]4 q; P0 t1377555 ALLEGRO_EDITOR DRC_CONSTR       The "Line to SMD Pin Same Net Spacing" DRC appears and disappears each time Force Update is run for Dynamic Shapes
4 O( ^0 y9 O: T0 O$ w# S+ x  u) Y& w1 x1377606 APD            REPORTS          APD16.6  Missing Fillets Report ?
1378094 CAPTURE        EE_INTERSHEET_RE intersheet References are wrong
3 V2 }3 R' _- @1378625 ALLEGRO_EDITOR FSP_PINSWAP      FSP crashes while synchronizing design
1378703 CAPTURE        DRC              different DRC results even design and options not changed
4 k* t) i- G6 g9 C* l4 r% J1382541 PCB_LIBRARIAN  CORE             Show Pin Numbers in Global Rename Pin dialog for better understanding
$ c7 X: B  h9 |6 G& ^& B" D1394552 CONCEPT_HDL    OTHER            The link function enhancement.
1395007 CONCEPT_HDL    INTERFACE_DESIGN Issue with NET_SPACING_TYPE and NET_PHYSICAL_TYPE properties depending on visibility
1395033 CAPTURE        HELP             Project opens as text file if the directory or project or project name has .v in it.
1395356 SIP_LAYOUT     SHAPE            When merging shapes, a certain void in one of the shapes changes location and is resized
- Z$ I: h7 o# ], H1 f9 X7 q1397564 CONCEPT_HDL    CORE             Design Entry HDL crashes when opening from Part Developer
* }! a$ D& ]+ A! R! x- i8 V1398919 CONCEPT_HDL    INTERFACE_DESIGN NG buss error
  ^  Q$ Y! [; W! ?* P" w1399924 CAPTURE        OTHER            Error message location always shows in inches
0 i- `: l  _3 w3 q8 H1400086 CONCEPT_HDL    CORE             Option to retain the distance between Pin number and wire/pin while moving a pin number.
2 i' H; K6 V- O9 p. p* ~& S1400691 CONCEPT_HDL    INTERFACE_DESIGN Rename of netgroups is a must
$ t' x4 s/ @9 U" {5 c1400755 ALLEGRO_EDITOR SHAPE            Updating shapes on design causes a short to a pad
/ D1 G5 r7 U. M5 K1401320 ADW            COMPONENT_BROWSE Issues with filtering in Component Browser
1401900 ALLEGRO_EDITOR MANUFACT         Drill chart resized from V16.5 to V16.6
1 ?  M6 y. s8 C) t1402317 ADW            DSN_MIGRATION    Design Migration hangs in the final stage  "saving the design"
+ V7 x# ?% t, d: q0 r1403716 SIP_LAYOUT     SYMB_EDIT_APPMOD SiP layout - Dynamic ability to applying expansion/compression of symbol using app mode
# w7 V4 g1 F9 G. Z  |6 z8 ]1404071 SCM            ERROR_WINDOW     About Violations window messages and Export Physical
1404754 TDA            CORE             setPermissions client API needs to be changed to pass only changed permissions
2 l7 x: b/ ]5 Q4 ~4 k6 D1404993 ALLEGRO_EDITOR DATABASE         dbdoctor falsely reports Illegal rectangle size error has been fixed.
1405018 ADW            COMPONENT_BROWSE Need a way to move the Attributes tab first, but make the Properties tab open by default
1405201 CONCEPT_HDL    INTERFACE_DESIGN Provide mechanism to sort the Net Groups created in the Interface Browser
1405896 CIS            PLACE_DATABASE_P If FPLIST field is set to transfer to design in DBC, Capture CIS crashes
9 N4 t* t9 o5 N% F+ J- u" A: M1406554 CONCEPT_HDL    INTERFACE_DESIGN When trying to map a port group all members cant be selected
1406780 CONSTRAINT_MGR OTHER            Deleting cline segments when Constraint Manager is open on net properties bundle crashes PCB Editor
* m2 C5 K& N1 q1 @+ z; }$ ?& Q$ g1407817 CONCEPT_HDL    INTERFACE_DESIGN Port group mapping issues on saving design when using non-high speed license
( B! K( ], X2 u& [" t2 p1408001 ADW            COMPONENT_BROWSE Searchable only properties are missing from a shopping list in UCB
1408414 ALLEGRO_EDITOR DRC_CONSTR       Waived DRC does not move with the elements it is associated
1409474 CONCEPT_HDL    GLOBALCHANGE     Global Replace does not retain refdes values
3 f2 Y: q3 F' G" y1410333 CONSTRAINT_MGR DATABASE         Unrouted net length does not match total Manhattan length
, u) c; X% w: b" G0 ?) R1 R1410857 ALLEGRO_EDITOR DRC_CONSTR       Diff Pair Uncoupled length DRC gives different results in SPB16.3,  SPB16.5, and SPB16.6.
1411936 CONCEPT_HDL    CORE             Font support for $PN is inconsistent
' o8 b6 Q5 p5 p1412878 ADW            COMPONENT_BROWSE Shopping cart tooltip for PPL error has a bad character
1413243 F2B            PACKAGERXL       Backannotation warnings about $PN not deleted from Property file (dcf)
- D! N% j" ]: f1413699 F2B            DESIGNVARI       Provide an option to create variant-specific schematics without any variant specific color overwrites
1414672 ALLEGRO_EDITOR PAD_EDITOR       Padstack designer Lock mechanisim fails to lock padstack when it's reopened.
0 R' L& M3 h/ p; V9 H' D1415863 CONSTRAINT_MGR OTHER            DCF import ignores Voltage property values
1416561 F2B            DESIGNVARI       When using the Replace Component command in DE-HDL, Component Browser takes a long time to load
1416704 ALLEGRO_EDITOR EDIT_ETCH        AiDT Turning Pattern Corner type option to Arc
1417283 CONCEPT_HDL    INTERFACE_DESIGN Provide an option to flatten a block when adding it from Component Browser
1417802 CONCEPT_HDL    CORE             Multiple ghost images while copying group or objects
1418134 CONCEPT_HDL    CORE             Some objects are removed from the group on using the group move command in Linux
& C8 ^4 w& r- ^- l( |1418484 SIG_INTEGRITY  SIMULATION       Estimated Xtalk and Simulated Xtalk results do not match in 16.6 ISR044
# Z, c" ^& F! s. Z& @5 u1419474 CONCEPT_HDL    CORE             CheckPlus, PDF Publisher, should detect invalid view files
" [4 c0 ^4 o! a8 P- ]* l7 z) C0 R1419560 ADW            COMPONENT_BROWSE Removing a value from the search criteria, removes the field from the displayed results
1419954 SIP_LAYOUT     DIE_ABSTRACT_IF  add abstract show ic details to the place codesign die abstract form
- v" E  d/ b0 M+ p3 j) [  m1420459 CAPTURE        STABILITY        Capture crashes when library has pages with parts where pin names or numbers have been moved
1420482 ADW            LRM              LRM deleting symbol properties during the UPDATE process
" k$ h- ~! v$ B- D, T4 N1420580 CONSTRAINT_MGR INTERACTIV       Constraint Manager crashes when displaying the Relative Propagation Delay worksheet
. B4 W" }/ G# f' @: F, E. H1420623 CONCEPT_HDL    CREFER           creferhdl fails with message std::bad_alloc on Windows and Linux
" R2 d  X- y1 ?7 F# Y* T1421106 ALLEGRO_EDITOR DATABASE         Get message "E- (SPMHDB-183): 'SHAPE' object may not exist on layer 'ETCH/WIRE'" when updating dyanmic shape.
4 B% `: x3 c( G! E  `$ `9 D1421352 ALLEGRO_EDITOR EDIT_ETCH        Application crashes when Create Fanout is executed with a blank end layer.
/ U5 V  h8 c! ]' H& n# S; i7 W1421769 ALLEGRO_EDITOR MANUFACT         NC Drill legend behavior changed from S040 to S048
1422131 APD            DXF_IF           dxf error
1422153 CONSTRAINT_MGR OTHER            The display in cmDiffUtility is corrupted after a Match Group is removed
1422372 CONCEPT_HDL    PDF              Publish PDF-generated file: Unable to click links or copy in Javascript window
% o" b5 C3 ~+ V2 A, m" {' H1422993 SIP_LAYOUT     DIE_STACK_EDITOR Diestack Editor graphics depicts die stack incorrectly. The complete stack isn't shown
" C+ D5 l- G( w: Q! w1423268 SIP_LAYOUT     SYMB_EDIT_APPMOD Update Die Extents causes Die layer change
1423539 ALLEGRO_EDITOR EDIT_ETCH        Timing Vision crashes for board.
7 J% ?* z2 R$ M: t0 A* _$ ^/ b1423988 ASI_SI         GUI              DesignLink system configuration file is not set automatically on SI-Base
% u. [3 |9 D6 `* z) \0 J/ K. c1424053 SIP_LAYOUT     ASSY_RULE_CHECK  DRC info of "Acute Angle Merged Metal Check" reports the same via object to itself
1424415 GRE            CORE             2 bundles are misbehaving during plan spatial.
1424773 CONCEPT_HDL    OTHER            How to delete schematic-defined netgroups with locked members in the top-level block
1425060 RF_PCB         DISCRETE_LIBX_2A Miscellaneous enhancements requested for discrete library translator
1425592 F2B            BOM              Generating BOM in CSV format changes the value format
1426286 ALLEGRO_EDITOR EXTRACT          Slotted hole within a footprint supported in STEP file
+ ^9 {9 L$ B& z! ]6 C1426593 CAPTURE        DRC              orcad Capture crashes on replaying DRC command.
1426939 CONCEPT_HDL    CORE             Error message SPCOCN-2208 can be misinterpreted
1427364 F2B            PACKAGERXL       Board does not backannotate and generates this message: ERROR (SPCOPF-2069): COMP_DEVICE_TYPE
. c, o0 }$ \: ~$ O, I4 n1427690 CONCEPT_HDL    PDF              PDF Publisher on remote display hangs if run on a design with a missing component
4 T5 ]2 H8 L0 b9 j) U& j5 }1427721 CONCEPT_HDL    CORE             The copy paste command on text doesn't preserve the text size
1428130 CONCEPT_HDL    CORE             LRM reports additional parts on schematic which were already synchronized with the cache ptf
1428925 CONCEPT_HDL    CORE             Global signal is not selected as base if it is synonymed to local signal with  ase suffix.
  U% {1 ?& E0 \* i! ^# Q1429526 ALLEGRO_EDITOR INTERFACES       Export PDF is blank if lanscape mode is selected.
7 N! T+ _2 R. m  A4 A& R1429840 SIP_LAYOUT     SYMB_EDIT_APPMOD pin numbers are not applied if I have used library manager
/ F7 n; J$ a3 d5 Y5 N& ^1430098 ORBITIO        ALLEGRO_SIP_IF   The Die Pads and Vias around Die are missing when the SiP database is imported in ORbitIO
1430564 ALLEGRO_EDITOR PLACEMENT        moving group separates Place Bound from group 不好意下载上传都比较慢让大家久等了。下载链接 ：http://pan.baidu.com/s/1qWwYnNI
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4 i) i! R7 ?( \: E8 {) ?

yueyuan2003

1 n' x2 |8 b, z2 l( T经我安装测试，这个丁丁为51，不过改动相当大，脸都变了
0 w+ N+ S/ g, O* e而且这个版本叫做Cadence 16.6_2015了，不再是之前的16.6了，
老版本的16.6提示最新版本是Latest Release: 16.6-S050
$ G% D% R8 x" x- V: C而这个Cadence 16.6_2015会提示Latest: 16.6-2015-S051
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zgyzgy

yueyuan2003 发表于 2015-6-30 10:51
7 _$ Y7 W7 u4 z, F, l( ~7 |# a恨不得再给你加两分，不给加了，
, |7 t6 K1 ]6 z6 Y; M* O# C* J他这个到底是52还是51啊？是52的话51跑哪去了

/ a- ^2 L* j7 T3 r$ V1 r% s网站上显示52 ，但是资料里面就是51，有次我更新了一个版本，原理图显示没有更新，但是PCB更新成了版本。

zgyzgy

crskynet008 发表于 2015-7-8 13:59
升级安装出问题！ 原来破解的许可证不可用了！怎么解决？

重新破解
2 f+ y0 o  @! f# L& j3 T

神话20121111

包包呢

haoyingxiang

好快，就是包包呢

tubegong

求安装包

yueyuan2003

继续发扬你那大无畏的分享精神

qiuzhang

挂52的羊头，卖51的狗肉

zgyzgy

下载链接在最下哈

wolfshiao

一直都有在用16.6,
  \: T( Y) S( l0 @雖然是偶爾才會安裝補丁,
但要感謝大大的熱情提供分享囉!!
; i' w. l5 `9 g$ R: M, T

yueyuan2003

恨不得再给你加两分，不给加了，
+ e/ Y" H  ], p2 z1 Z1 V他这个到底是52还是51啊？是52的话51跑哪去了
& V' |. K: v1 \! O) o

haoyingxiang

感谢楼主

stbear1017

安裝了
/ V. W/ s& D+ V' FLIC卻FAILED了

moneyzz

感谢分享啊，这个补丁DRL文件问题有没有解决呢

xidgli

感谢楼主