Hotfix_SPB16.60.052

zgyzgy · 发表于 2015-6-28 20:56

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本帖最后由 zgyzgy 于 2015-6-29 19:30 编辑

这次出大招了更新好多。官网显示是52，DATE里面介绍是51：
DATE: 06-26-2015 HOTFIX VERSION: 051
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
295747  allegro_EDITOR PLACEMENT       Place manual form takes a long time to open
713130  CAPTURE       GENERAL       Bias points get displaced when schematic is copied/pasted in MS Word
832170  SIG_INTEGRITY  SIMULATION    IBIS buffer results with two TV curves do not correlate with HyperLnx or MATLAB results
926138  SIG_INTEGRITY  SIMULATION    IBIS buffer results with two TV curves do not correlate with HyperLnx or MATLAB results
1056824 ALLEGRO_EDITOR INTERACTIV    Need a way to repeat the 'Snap pick to' selection
1131613 concept_HDL COMP_BROWSER    DE-HDL: inconsistent display of hyperlinks in Component Browser
1156766 ALLEGRO_EDITOR INTERACTIV    Retain selected options (lasso, polygon, or path)
1224882 CONCEPT_HDL CORE          Unable to modify the port position on the sym view if the signal names have double underscores
1225998 CAPTURE       NETGROUPS       Bug: Normal scalar hierarchical pin is getting changed to netgroup pin
1281668 ALLEGRO_EDITOR EDIT_ETCH       Arc bump of AiPT
1286749 FSP          PROCESS       FSP not allowing group swap across inteRFaces in same_vccaux_io region
1306988 SIG_INTEGRITY  SIMULATION    Support needed for the multiple VI and VT waveforms for the buffer with TLSIM
1311177 CONCEPT_HDL CORE          Save Hierarchy for read-only blocks should not produce ERROR(SPCOCN-2123)
1315888 SIP_LAYOUT    ASSY_RULE_CHECK  "Dummy" DRC violations with xhatched shapes filled with "crosshatch void fill" function
1319663 PCB_LIBRARIAN  VERIFICATION    con2con always reports the first part name when problems are reported for 2nd or 3rd part name from same primitive
1321192 APD          VIA_STRUCTURE When atttempting to delete a layer we get the warning messages stating its a symbol when its a Via Structure issue.
1324280 ALLEGRO_EDITOR COLOR          Layer Priority for user-defined Ref Des Layers
1327949 CONCEPT_HDL CORE          not able to add placeholder for VOLTAGE to bodies
1332123 APD          INTERACTIVE    Snap to pin is snapping to via.
1333113 F2B          PACKAGERXL    A hard LOCATION
1335908 CIS          RELATIONAL_DB Relational data fields order do not appear correctly in CIS BOM.
1336970 ADW          LRM             Replaced by report does not show the replacement part
1337197 ADW          LRM             DE-HDL crashes and corrupts design during LRM update
1337548 CONCEPT_HDL COMP_BROWSER    Component Browser in the cached mode crashes when doing a search
1341177 ALLEGRO_EDITOR PLACEMENT       Need the ability to resize the Place Replicate Unmatched Component Interface window
1341940 APD          OTHER          WIRE_COUNT check doesn't work for diepad to diepad bond
1341947 SIG_EXPLORER OTHER          Sigxplorer hangs when the Wizard_Template_Path variable is set
1343981 SIP_LAYOUT    MANUFACTURING add an option (Refdes) for Display Pin Text
1345577 TDA          CORE          TDO crashes when attempting to check-out block
1345601 TDA          CORE          Error message when attempting to change to ECO mode
1345629 ADW          LRM             LRM deletes worklib contents when updating schematic design
1346088 ADW          DSN_MIGRATION Parts missing in part_table.ptf after design migration
1346925 APD          STREAM_IF       Need ability to have same class/subclass mapped to more than one stream layer
1347102 CIS          GEN_BOM       MDB file is shown wrong variant name
1347145 CAPTURE       INTERFACES    Capture crash while editing comapre test bench settings for Pspice design
1348619 ADW          LRM             LRM does not update symbol and its attributes in the schematic
1351123 CONCEPT_HDL CORE          Changing Net Name in Attribute or using Text > Change deletes constraints
1351700 ADW          LRM             LRM Crashes while loading design
1353844 ALLEGRO_EDITOR SHAPE          When creating a copper shape on the M2 layer a void is created running top to the bottom.
1354049 SIP_LAYOUT    ASSY_RULE_CHECK  Exclude fillet shapes from the Continuous Solder Mask Coverage ADRC check
1354790 CONCEPT_HDL COMP_BROWSER    Remove limit of 2500 for Component Browser search results
1355258 ALLEGRO_EDITOR DATABASE       Matched Groups generating wrong pin pairs
1355882 ADW          TDA             ERROR(SPDWSD-58): Unable to copy file ... to folder ... /.sdm/tarballs
1357624 CONCEPT_HDL CORE          DEHDL fails to recognize PTF header changes resolved by LRM
1357760 CONCEPT_HDL OTHER          What arguments to use when starting DE-HDL with options?
1358018 CONCEPT_HDL CORE          PinPosition from template.tsg located at $CDS_SITE is not honoured for split hier block symbol generation
1358053 TDA          CORE          TDO and VarEdit: Check out variant_cbc.dat separately
1358511 ALLEGRO_EDITOR INTERACTIV    Replace padstack error message unclear
1359168 CAPTURE       TCL_INTERFACE Bug: CIS "Place database part check" tcl command not working
1359357 CONCEPT_HDL OTHER          HF039 BOM_IGNORE for complex hierarchy is not working normally
1360071 CONCEPT_HDL CORE          The Change Properties dialog does not show a cursor when selecting
1360554 ALLEGRO_EDITOR DRC_CONSTR    Same net DRC disappeared after update DRC.
1360653 CONCEPT_HDL CORE          CUSTOM_TXT_CDS not working for defprop in template.tsg
1360772 SIP_LAYOUT    INTERACTIVE    Cannot change Clines to a different layer.
1361281 ALLEGRO_EDITOR INTERACTIV    Unlike stacked vias, moving non-stacked vias requires an additional step of choosing a pick point
1362156 ALLEGRO_EDITOR PCAD_IN       PCAD import to PCB Editor fails with message "ERROR: netname not NULL for non-etch class"
1363298 ADW          PCBCACHE       Part Manager Error when replacing a part with a
1365794 ALLEGRO_EDITOR PCAD_IN       PCAD to Allegro translation does not generate the translated board file and also does not give any error message.
1366525 ALLEGRO_EDITOR INTERACTIV    The "replace via structure" command of APD and SiP is also required in Allegro PCB Editor
1366976 APD          EDIT_ETCH       Interactive edit etch slide command not working as expected.
1367224 ALLEGRO_EDITOR INTERACTIV    merge 'shape edit mode' into 16.69.
1367314 CONCEPT_HDL OTHER          Setting lock of Reference schematic.
1367609 F2B          DESIGNVARI    Variant overlay shows the ALT_SYMBOLS attribute for modified inductors
1368091 ALLEGRO_EDITOR INTERACTIV    A filled rectangle should be treated as a shape to use the "snap pick to" function with the "Shape Center" option
1368159 CONCEPT_HDL CONSTRAINT_MGR Make CM_DEFAULT_PRECISION a site.cpm directive
1370186 SIP_LAYOUT    EDIT_ETCH       Cannot add a via to the selected layer
1371015 CAPTURE       OTHER          Tools > Update properties displays Error (ORCAP-1579)
1371807 CAPTURE       SCHEMATIC_EDITOR Button Status for 'drag connected objects' hard to see
1372282 TDA          CORE          Integrator utility to refresh policy
1372351 CAPTURE       DRC             Browse DRC marker and search of DRC marker are giving different results.
1373118 CONCEPT_HDL CORE          Only generate $HOME/cdssetup/concept files when changes are made
1373412 ALLEGRO_EDITOR GRAPHICS       SigXP Print Canvas: Via model is filled by a black via box
1373575 CONCEPT_HDL INTERFACE_DESIGN Net Group name clash Pin Name
1374703 ALLEGRO_EDITOR SHAPE          Inconsistent behavior on shape voiding
1375127 ALLEGRO_EDITOR INTERACTIV    The errset skill command with axlSpreadsheetRead crashes the tool
1375940 PCB_LIBRARIAN  PTF_EDITOR    PTF Editor error messages are truncated.
1375974 ASI_SI       GUI             want to use SigWave on SI Base
1376591 ALLEGRO_EDITOR COLOR          Dehighlight command with "Dehighlight All" option does not remove the color marker swatches from Constraint Manager
1376634 ALLEGRO_EDITOR INTERACTIV    Snap pick to symbol center not working in symbol editor
1376765 CONSTRAINT_MGR ANALYSIS       Setup/Hold spreadsheet lists only one pin pair
1376851 CONSTRAINT_MGR UI_FORMS       CM workbooks change after simulating
1377555 ALLEGRO_EDITOR DRC_CONSTR    The "Line to SMD Pin Same Net Spacing" DRC appears and disappears each time Force Update is run for Dynamic Shapes
1377606 APD          REPORTS       APD16.6  Missing Fillets Report ?
1378094 CAPTURE       EE_INTERSHEET_RE intersheet References are wrong
1378625 ALLEGRO_EDITOR FSP_PINSWAP    FSP crashes while synchronizing design
1378703 CAPTURE       DRC             different DRC results even design and options not changed
1382541 PCB_LIBRARIAN  CORE          Show Pin Numbers in Global Rename Pin dialog for better understanding
1394552 CONCEPT_HDL OTHER          The link function enhancement.
1395007 CONCEPT_HDL INTERFACE_DESIGN Issue with NET_SPACING_TYPE and NET_PHYSICAL_TYPE properties depending on visibility
1395033 CAPTURE       HELP          Project opens as text file if the directory or project or project name has .v in it.
1395356 SIP_LAYOUT    SHAPE          When merging shapes, a certain void in one of the shapes changes location and is resized
1397564 CONCEPT_HDL CORE          Design Entry HDL crashes when opening from Part Developer
1398919 CONCEPT_HDL INTERFACE_DESIGN NG buss error
1399924 CAPTURE       OTHER          Error message location always shows in inches
1400086 CONCEPT_HDL CORE          Option to retain the distance between Pin number and wire/pin while moving a pin number.
1400691 CONCEPT_HDL INTERFACE_DESIGN Rename of netgroups is a must
1400755 ALLEGRO_EDITOR SHAPE          Updating shapes on design causes a short to a pad
1401320 ADW          COMPONENT_BROWSE Issues with filtering in Component Browser
1401900 ALLEGRO_EDITOR MANUFACT       Drill chart resized from V16.5 to V16.6
1402317 ADW          DSN_MIGRATION Design Migration hangs in the final stage  "saving the design"
1403716 SIP_LAYOUT    SYMB_EDIT_APPMOD SiP layout - Dynamic ability to applying expansion/compression of symbol using app mode
1404071 SCM          ERROR_WINDOW    About Violations window messages and Export Physical
1404754 TDA          CORE          setPermissions client API needs to be changed to pass only changed permissions
1404993 ALLEGRO_EDITOR DATABASE       dbdoctor falsely reports Illegal rectangle size error has been fixed.
1405018 ADW          COMPONENT_BROWSE Need a way to move the Attributes tab first, but make the Properties tab open by default
1405201 CONCEPT_HDL INTERFACE_DESIGN Provide mechanism to sort the Net Groups created in the Interface Browser
1405896 CIS          PLACE_DATABASE_P If FPLIST field is set to transfer to design in DBC, Capture CIS crashes
1406554 CONCEPT_HDL INTERFACE_DESIGN When trying to map a port group all members cant be selected
1406780 CONSTRAINT_MGR OTHER          Deleting cline segments when Constraint Manager is open on net properties bundle crashes PCB Editor
1407817 CONCEPT_HDL INTERFACE_DESIGN Port group mapping issues on saving design when using non-high speed license
1408001 ADW          COMPONENT_BROWSE Searchable only properties are missing from a shopping list in UCB
1408414 ALLEGRO_EDITOR DRC_CONSTR    Waived DRC does not move with the elements it is associated
1409474 CONCEPT_HDL GLOBALCHANGE    Global Replace does not retain refdes values
1410333 CONSTRAINT_MGR DATABASE       Unrouted net length does not match total Manhattan length
1410857 ALLEGRO_EDITOR DRC_CONSTR    Diff Pair Uncoupled length DRC gives different results in SPB16.3,  SPB16.5, and SPB16.6.
1411936 CONCEPT_HDL CORE          Font support for $PN is inconsistent
1412878 ADW          COMPONENT_BROWSE Shopping cart tooltip for PPL error has a bad character
1413243 F2B          PACKAGERXL    Backannotation warnings about $PN not deleted from Property file (dcf)
1413699 F2B          DESIGNVARI    Provide an option to create variant-specific schematics without any variant specific color overwrites
1414672 ALLEGRO_EDITOR PAD_EDITOR    Padstack designer Lock mechanisim fails to lock padstack when it's reopened.
1415863 CONSTRAINT_MGR OTHER          DCF import ignores Voltage property values
1416561 F2B          DESIGNVARI    When using the Replace Component command in DE-HDL, Component Browser takes a long time to load
1416704 ALLEGRO_EDITOR EDIT_ETCH       AiDT Turning Pattern Corner type option to Arc
1417283 CONCEPT_HDL INTERFACE_DESIGN Provide an option to flatten a block when adding it from Component Browser
1417802 CONCEPT_HDL CORE          Multiple ghost images while copying group or objects
1418134 CONCEPT_HDL CORE          Some objects are removed from the group on using the group move command in Linux
1418484 SIG_INTEGRITY  SIMULATION    Estimated Xtalk and Simulated Xtalk results do not match in 16.6 ISR044
1419474 CONCEPT_HDL CORE          CheckPlus, PDF Publisher, should detect invalid view files
1419560 ADW          COMPONENT_BROWSE Removing a value from the search criteria, removes the field from the displayed results
1419954 SIP_LAYOUT    DIE_ABSTRACT_IF  add abstract show ic details to the place codesign die abstract form
1420459 CAPTURE       STABILITY       Capture crashes when library has pages with parts where pin names or numbers have been moved
1420482 ADW          LRM             LRM deleting symbol properties during the UPDATE process
1420580 CONSTRAINT_MGR INTERACTIV    Constraint Manager crashes when displaying the Relative Propagation Delay worksheet
1420623 CONCEPT_HDL CREFER          creferhdl fails with message std::bad_alloc on Windows and Linux
1421106 ALLEGRO_EDITOR DATABASE       Get message "E- (SPMHDB-183): 'SHAPE' object may not exist on layer 'ETCH/WIRE'" when updating dyanmic shape.
1421352 ALLEGRO_EDITOR EDIT_ETCH       Application crashes when Create Fanout is executed with a blank end layer.
1421769 ALLEGRO_EDITOR MANUFACT       NC Drill legend behavior changed from S040 to S048
1422131 APD          DXF_IF          dxf error
1422153 CONSTRAINT_MGR OTHER          The display in cmDiffUtility is corrupted after a Match Group is removed
1422372 CONCEPT_HDL PDF             Publish PDF-generated file: Unable to click links or copy in Javascript window
1422993 SIP_LAYOUT    DIE_STACK_EDITOR Diestack Editor graphics depicts die stack incorrectly. The complete stack isn't shown
1423268 SIP_LAYOUT    SYMB_EDIT_APPMOD Update Die Extents causes Die layer change
1423539 ALLEGRO_EDITOR EDIT_ETCH       Timing Vision crashes for board.
1423988 ASI_SI       GUI             DesignLink system configuration file is not set automatically on SI-Base
1424053 SIP_LAYOUT    ASSY_RULE_CHECK  DRC info of "Acute Angle Merged Metal Check" reports the same via object to itself
1424415 GRE          CORE          2 bundles are misbehaving during plan spatial.
1424773 CONCEPT_HDL OTHER          How to delete schematic-defined netgroups with locked members in the top-level block
1425060 RF_PCB       DISCRETE_LIBX_2A Miscellaneous enhancements requested for discrete library translator
1425592 F2B          BOM             Generating BOM in CSV format changes the value format
1426286 ALLEGRO_EDITOR EXTRACT       Slotted hole within a footprint supported in STEP file
1426593 CAPTURE       DRC             orcad Capture crashes on replaying DRC command.
1426939 CONCEPT_HDL CORE          Error message SPCOCN-2208 can be misinterpreted
1427364 F2B          PACKAGERXL    Board does not backannotate and generates this message: ERROR (SPCOPF-2069): COMP_DEVICE_TYPE
1427690 CONCEPT_HDL PDF             PDF Publisher on remote display hangs if run on a design with a missing component
1427721 CONCEPT_HDL CORE          The copy paste command on text doesn't preserve the text size
1428130 CONCEPT_HDL CORE          LRM reports additional parts on schematic which were already synchronized with the cache ptf
1428925 CONCEPT_HDL CORE          Global signal is not selected as base if it is synonymed to local signal with  ase suffix.
1429526 ALLEGRO_EDITOR INTERFACES    Export PDF is blank if lanscape mode is selected.
1429840 SIP_LAYOUT    SYMB_EDIT_APPMOD pin numbers are not applied if I have used library manager
1430098 ORBITIO       ALLEGRO_SIP_IF The Die Pads and Vias around Die are missing when the SiP database is imported in ORbitIO
1430564 ALLEGRO_EDITOR PLACEMENT       moving group separates Place Bound from group 不好意下载上传都比较慢让大家久等了。下载链接：http://pan.baidu.com/s/1qWwYnNI

yueyuan2003 · 发表于 2015-7-1 17:41

本帖最后由 yueyuan2003 于 2015-7-6 10:06 编辑

经我安装测试，这个丁丁为51，不过改动相当大，脸都变了
而且这个版本叫做Cadence 16.6_2015了，不再是之前的16.6了，
老版本的16.6提示最新版本是Latest Release: 16.6-S050
而这个Cadence 16.6_2015会提示Latest: 16.6-2015-S051

zgyzgy · 发表于 2015-6-30 13:23

yueyuan2003 发表于 2015-6-30 10:51
$ _! g# a% t* x) A. j5 b恨不得再给你加两分，不给加了，; E+ F7 f$ t4 |; W. ~
他这个到底是52还是51啊？是52的话51跑哪去了

网站上显示52 ，但是资料里面就是51，有次我更新了一个版本，原理图显示没有更新，但是PCB更新成了版本。

zgyzgy · 发表于 2015-7-11 21:45

crskynet008 发表于 2015-7-8 13:59
1 F' E4 s' ^! J/ X z1 u7 V升级安装出问题！原来破解的许可证不可用了！怎么解决？

重新破解

神话20121111 · 发表于 2015-6-28 21:05

包包呢

haoyingxiang · 发表于 2015-6-28 22:20

好快，就是包包呢

tubegong · 发表于 2015-6-29 08:01

求安装包

yueyuan2003 · 发表于 2015-6-29 09:29

继续发扬你那大无畏的分享精神

qiuzhang · 发表于 2015-6-29 13:26

挂52的羊头，卖51的狗肉

zgyzgy · 发表于 2015-6-30 08:15

下载链接在最下哈

wolfshiao · 发表于 2015-6-30 09:11

一直都有在用16.6,
雖然是偶爾才會安裝補丁,
但要感謝大大的熱情提供分享囉!!

yueyuan2003 · 发表于 2015-6-30 10:51

恨不得再给你加两分，不给加了，
他这个到底是52还是51啊？是52的话51跑哪去了

haoyingxiang · 发表于 2015-7-1 21:38

感谢楼主

stbear1017 · 发表于 2015-7-5 18:42

安裝了
LIC卻FAILED了

moneyzz · 发表于 2015-7-5 23:46

感谢分享啊，这个补丁DRL文件问题有没有解决呢

xidgli · 发表于 2015-7-6 08:17

感谢楼主

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