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我在做数模混合仿真的时候,在config中调用模拟电路和数字模块的symble,但是在进行display partition>all active时,系统报错:
) x" Q$ y4 V* k2 g\o *SYSERR: Unable to hdbBind for inst I15 in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.4 s+ E' H: O) P) q0 ?, |. W9 G. V6 ]5 C/ q
\o *USRERR: Selected context view string 'spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl'
3 G0 m4 o; w8 q\o offers no suitable view for inst I15 referencing placed master design.add_and_mult.symbol% d6 V7 C- u& ^$ L
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
1 m. k" }8 \! L6 Y) v2 j( |\o Please check HDB configuration or library setup.
8 O, K7 ?5 N! E0 j8 O\o *USRERR: Selected context view string 'functional'
& M8 n: S. R; ?. H. T; b\o offers no suitable view for inst I14 referencing placed master design.average.symbol
7 L, J9 l# P C, t" A2 {5 D! C\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.+ J$ X" ^3 O; q# B0 e2 q
\o Please check HDB configuration or library setup.- R) B- C4 a8 I( t! A8 D
\o *USRERR: Selected context view string 'functional'& h! |! j3 ]8 \/ N/ a8 X) j* N- f
\o offers no suitable view for inst I12 referencing placed master design.unit2.symbol/ l. O6 O5 ^# ^5 y, I
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
0 |, e+ G1 d4 L\o Please check HDB configuration or library setup.+ \& t9 d9 q% B1 Y- `% k5 i& D
\o *USRERR: Selected context view string 'functional'% f) Z, f2 n% R4 o( b- `- A$ D
\o offers no suitable view for inst I11 referencing placed master design.unit1.symbol
# |; C% R& [, d/ V\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
5 G: n( Y+ @; X9 p\o Please check HDB configuration or library setup.
1 @3 x1 [! K" g6 l+ ^* p\o *USRERR: Selected context view string 'functional'
; ]8 Y0 y2 x& n3 C6 Y b\o offers no suitable view for inst I4 referencing placed master design.encode.symbol
p# Z0 r* U: M. Y, d- @, K: h\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
, }$ C9 g, t8 o) Z\o Please check HDB configuration or library setup.
* `% i0 ?, W0 f* R- G' \( Z K\o *USRERR: Selected context view string 'functional') `! X/ s2 i7 `( p8 x5 ?% a4 u
\o offers no suitable view for inst I2 referencing placed master design.encode.symbol7 Q( {* d- l: I: n+ x
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.# b2 Q( Z5 b G3 x8 A4 R
\o Please check HDB configuration or library setup.
9 o% v" m2 `- V& S6 J6 E\e *Error* Failed to partition the design.
3 ?7 o. e& `! L\e
9 L8 r5 Q8 f9 c( ]\e *Error* mspDisplayPartition: Failed to create network
% }8 n* v1 y$ V7 d/ S3 U/ w V& l8 J+ C. M. \% R/ @8 j
这是什么问题啊?求大神帮忙解决一下,鄙人不甚感激!!!8 r( T3 _0 {- y5 n0 ~$ K2 ^9 H T
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