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4 R$ I! K6 E1 ?* D) k补丁包更新列表！
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DATE: 11-20-2015 HOTFIX VERSION: 0611 ^( B+ q9 r& }8 F* H
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CCRID PRODUCT PRODUCTLEVEL2 TITLE" i3 ^ O' M8 o
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3 ~# j% g$ ?9 |- \1 i- j7 I0 w1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value5 _* y" p+ x+ w1 P k) H
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init
. f+ p4 }+ j. v' ^1413248 concept_HDL CORE Import from another TDO project makes the block read-only
$ t L9 a2 K" `, {4 Q/ t o1417429 allegro_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
4 a2 b; Z, e* H2 E c) I; \+ H0 d1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
; u0 T3 e$ q, I3 G1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
, g. o9 M ~# i M: g7 T/ D6 W1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin
# i: a% {% ^; j/ p$ A8 P# @1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
: @- f; _0 P2 ]: T- d, q/ j1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename
- h* M `0 P/ T+ Y/ j9 O+ I1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets: o+ F. X+ }/ @ M- x4 R
1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL5 W5 ^7 y+ q7 O; Y) d! ?: M8 P# U
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
. _6 p( D8 j$ a3 y. |% n1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable" _! Y5 u. _3 |) p) l" I
1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets
]7 ~5 A, Q7 @+ x" B$ r }7 g1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice! \ F+ w3 N% J
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
3 m, x: O+ @8 g& }; a8 Y( O7 T1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only7 D& U% W. n" b2 H
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project
+ `& D' R/ G! @# t! f N1 S+ }1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.
7 f& ?) J; ` k# d) t1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility* ^/ b3 Y" T$ e5 W }
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems) F) g" y1 [6 T$ P1 Z
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported
& o! T. I9 R) o7 @1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior
& q0 U i; g/ S; C* s1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
& v* @* Z+ p4 U( G6 s& M3 \" w+ u1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
2 S0 L4 F3 a( m% v3 {7 u, ~$ M1490299 SCM OTHER ASA does not update revision properly
; ^5 K. ~* I4 M1490744 ALLEGRO_EDITOR skill axlChangeLine2Cline changes line to cline and places it on the TOP layer
/ V% O1 f0 b+ w8 r+ c1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
7 y7 A8 K7 ]4 V |7 K% X& f" S$ q+ }0 G1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
, V$ W' k3 D _7 M1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong0 H; |( O- j! I6 e& \& V
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash5 E' E) f* {) h: i) q
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
: J M. l+ z Y2 M& h! L6 m1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC25813 F: x* q2 ?. }# V+ o/ w
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size
9 }2 L) j- L( n: S$ A* |6 L% r1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
* c; b( ~0 k# c$ u( E/ L( x# P! L1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file: ~. Y8 ^. c0 _- ] K _
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60# I+ L7 ~! U2 E3 _4 C7 T' w' X# m
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最新破解包列表！0 M( e( p- p( F* u
------------------------------------------------------------------------------9 G, F, Q$ L+ E. U
SPB 16.6 UPDATED KITS RELEASE: ISR 16.60.061 EST.DATE: 11-20-2015
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CompBrowser16.60-s037wint( F) c! O# ^9 D- e8 X2 l0 c
DSCoreUtils16.60-s077wint; H9 R g: a0 O7 {# S8 ~+ l
DSCore16.60-s055wint' b, B% i( `4 s. i1 ~$ A
DSSchgen16.60-s030wint
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DSTableEditor16.60-s018wint5 T: j7 b9 f) Z+ q+ {
DSTextEditor16.60-s015wint
3 ?. g: c( P0 H; R3 dDSUICommonIndep16.60-s019
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DSUIUtils16.60-s037wint
9 `$ L2 N7 K5 {. [0 d/ n6 CSPBIX06116.60-p002wint% S( g/ Q9 C5 M L6 D
adpPDFLibs16.60-s033wint$ z$ @% ^' M4 Z% |. N
advanPakgDsnr16.60-s129wint
v7 `$ B5 |: }9 ^: cadwLRM16.60-s033wint% ^. k+ C/ M% G% z8 b: }
adwSDM16.60-s044wint) | |2 q3 F" D5 G2 _5 \* E0 P5 c
algroAcad16.60-s122wint
# b2 c, E8 l) A7 R- a$ X& SalgroArtwork16.60-s122wint
$ g) H% I( @/ f- ?algroAxl16.60-s048+ k2 N+ ^( v z% v7 |. |; b& J" b
algroBase16.60-s129wint
: \( y+ O+ q; W( s4 i2 |algroCxt16.60-s077
" i0 \9 A. K v T+ ?algroDBTools16.60-s124wint! Y! T3 M& {" J& q' ^
algroDsign16.60-s122wint: R' n; P# {. q* J: i
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algroIDF16.60-s122wint$ u. A7 W# [- A7 P
algroIgin16.60-s122wint
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. @4 _% e. C3 C6 }5 l' _9 @% ValgroIpc16.60-s122wint
3 f6 _& X/ D4 }/ ~1 S! s2 D5 @2 ZalgroMfg16.60-s122wint1 F8 [3 N: n8 D$ Q! _* T! O) U' B
algroNetin16.60-s122wint. k/ J' Z8 u" }9 w, B- I( q
algroPlace16.60-s122wint4 p: K `- q" }, E& d( T
algroSgnse16.60-s122wint
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algroTextIndep16.60-s089
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algroUtlty16.60-s122wint
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capPSpLibMAB16.60-s018wint% ~4 {6 B& E* U F% T
capProg16.60-s044wint
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conceptNT16.60-s106wint* g9 Z( c0 Y' {& |. h8 s$ b
concptSetup16.60-s015wint- h; y( ?5 F6 D2 i
consMgr16.60-s104wint& |( V7 G4 D1 |2 D1 U
desSync16.60-s019wint
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icpCommon16.60-s122wint
$ w1 v! q3 f7 `0 Z! liff2hdl16.60-s010wint. A7 {* O) X+ T5 D, r/ ?
lmancore16.60-s036wint
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lman16.60-s023wint8 A3 W& K! e# m/ [- Q( s1 T+ y! H' j
productServer16.60-s084wint
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0 A4 a& l* V( n3 ?' {$ Q9 _; s+ BrfsipPcellIndep16.60-s005
( i3 [- a4 w/ N: S+ ?& N6 u0 TsipDsnr16.60-s128wint( B: j5 F4 D; `! J5 Q
spbFPGAPlanner16.60-s065wint2 ^% T/ n% O% V/ h- h
specctraQuest16.60-s122wint
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4 j6 E6 p' k* j3 \vedit16.60-s043wint
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# P4 R; x! Q3 {4 a7 z补丁包种子！7 f. W, c9 `5 K; O' @6 c8 ^5 k
cadence.spb.orcad.16.60.061.hotfix.rar
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发表于 2015-12-3 09:33
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