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EDA365欢迎您登录!您需要 登录 才可以下载或查看,没有帐号?注册    6 H+ W* y( H+ f; B# `1 w$ [补丁包更新列表!* t) Q. [6 Z' ?2 d% W
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 DATE: 11-20-2015   HOTFIX VERSION: 061' X7 s3 C6 r$ n
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 CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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 1306441 APD            OTHER            The Minimum Shape Area option in Layer Compare uses an unspecified value! [, F9 D6 s- v9 T
 1342644 ADW            COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init
 & P+ N, P6 E+ N- @  v6 U3 |) ~1413248 concept_HDL    CORE             Import from another TDO project makes the block read-only
 3 E& X: V: I% @- ~1417429 allegro_EDITOR INTERACTIV       Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle3 p& P' c/ j6 _( j
 1417442 ALLEGRO_EDITOR INTERACTIV       Spin via stack and only part of the stack spins& [) t& [' i& y- u; P
 1451977 CONCEPT_HDL    PDF              Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set5 J' u% z  c4 [" ?/ _" [. N
 1453527 ALLEGRO_EDITOR EDIT_ETCH        Contour route hugs the outer edge of the route keepin
 : h# q, }& g1 {/ [* F  }" s1 H1464948 PCB_LIBRARIAN  VERIFICATION     The errors/warnings do not match between the various tools
 4 z, P8 Q" Z" s' a- d2 v1467826 CONCEPT_HDL    PDF              PublishPDF from Console Window creates a long PDF filename
 # U2 h8 f% q; \. y# `3 {% O" p: W/ _1478639 CAPTURE        OTHER            Capture Browse Nets window does not display all nets
 ) r7 t7 D+ M1 f) z6 O+ ^5 M1479177 SIP_LAYOUT     OTHER            Pin pair constraints do not appear to be supported in Sip Layout XL' u' l0 e3 E" U; i9 \8 H
 1479227 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
 6 X: A5 s- e0 D. u1479454 CONCEPT_HDL    OTHER            DE-HDL issue: locked DIFF_PAIR property is editable
 0 @8 X5 q% T4 l( }' O7 X' V& {+ o1480293 CAPTURE        PROJECT_MANAGER  Capture hangs when searching for all nets
 5 _3 X$ [+ j6 N& v2 X( Z: p1483894 CONCEPT_HDL    CORE             Import Design hangs when pull-down arrow is clicked twice, [$ o# T8 `/ l# ?6 E( N
 1484781 CONCEPT_HDL    CORE             Three different Hierarchical Viewer issues
 . @+ v* T" G/ m1485059 PCB_LIBRARIAN  CORE             Part Developer pin attributes are randomly marked as read-only+ u' D3 e6 }- p! B7 B! n3 L# a
 1485960 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule is crashing the project- E+ Q  u. H4 C! p  [$ `/ p
 1486086 ALLEGRO_EDITOR ARTWORK          Cannot generate artwork.! f3 E2 W0 J! `! F
 1486834 CONSTRAINT_MGR OTHER            Restore the Status column in cmDiffUtility4 h/ J9 |$ O5 C4 j! v
 1487085 CONCEPT_HDL    CONSTRAINT_MGR   Import Physical with the Constraints only option reports problems9 e" S  N$ D0 ~, j4 E: e, z
 1487197 ALLEGRO_EDITOR DRC_CONSTR       Drill to Via DRCs are not being reported7 {: y2 ^% r! \: V  J  ^
 1487265 CONCEPT_HDL    CORE             Replace command in Windows mode shows incorrect behavior
 0 A" R4 S2 H) E) P9 Y1487733 CONSTRAINT_MGR OTHER            Running Export Physical - It takes over two hours to update the PCB Editor board
 8 W3 }% G7 n+ r! y5 J1488758 CONCEPT_HDL    CONSTRAINT_MGR   CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
 ) l( Q- [( }* I  x1490299 SCM            OTHER            ASA does not update revision properly
 2 P/ _2 U& W3 w) r# K; g0 K% T1490744 ALLEGRO_EDITOR skill            axlChangeLine2Cline changes line to cline and places it on the TOP layer
 3 ~, v5 u! i$ f' p+ V1490924 F2B            PACKAGERXL       Save Design/Export Physical is resetting Via constraints
 0 N3 y, C' f  C$ p9 O/ X; K1491351 ALLEGRO_EDITOR OTHER            Create Detail for bond fingers on a custom layer not working% g: Y6 I# k3 g( Q8 W3 o, U3 a7 Z
 1492595 ALLEGRO_EDITOR MANUFACT         Dimension character substitution help is wrong
 ' ~# z$ F5 Y" }( F- U2 K# L1492777 ORBITIO        ALLEGRO_SIP_IF   OrbitIO import of customer mcm results in crash
 0 @, O& \4 ~0 o7 B1492901 CONCEPT_HDL    CORE             Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
 6 _, M1 ~  t0 I0 t5 l1495621 ALLEGRO_EDITOR INTERFACES       Oval pins are placed with wrong orientation in IPC2581
 6 @0 i2 q( u; O# A  M! `6 W1497597 ALLEGRO_EDITOR DATABASE         Show Element on pin shows wrong drill size$ \. d; d' r; L; ^* n! A0 c- `
 1497956 CONCEPT_HDL    CORE             ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
 Q7 C& {* j; I% \1 {# O- M1498234 ALLEGRO_EDITOR ARTWORK          PCB Editor fails to create artwork and no error is listed in the log file
 " T8 X# f4 n  A3 P. M6 u$ Z: H1499363 CONCEPT_HDL    CORE             Custom attributes under variant management stopped working in Hotfix60" [3 _% m9 i* n: n) {6 J
 
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 最新破解包列表!
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 SPB 16.6   UPDATED KITS RELEASE: ISR 16.60.061    EST.DATE:  11-20-2015
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 CompBrowser16.60-s037wint
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 adwSDM16.60-s044wint
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 algroCxt16.60-s077
 2 _: y1 l) w1 h+ h1 d! k, O7 ?algroDBTools16.60-s124wint
 6 K: o$ \3 R0 K6 OalgroDsign16.60-s122wint
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 algroIDF16.60-s122wint$ C% C% U# D* d" {% ^
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 algroIgout16.60-s122wint$ c- ?. D* R5 f/ {
 algroIpc16.60-s122wint
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 algroPlace16.60-s122wint
 # n3 H! d( y* g& |: u; aalgroSgnse16.60-s122wint
 $ ]9 n2 u# T5 W% m2 DalgroSpif16.60-s122wint
 / Q1 j, Y6 ]4 @0 K; DalgroStrm16.60-s122wint
 , c. _& T/ a+ Y0 e4 @, x, ValgroTextIndep16.60-s089& `8 G2 j' }0 y" Q2 a3 V
 algroTransltr16.60-s121wint( w' Z" r* Q6 ~$ D; |- ?
 algroUtlty16.60-s122wint5 E; x# |/ M4 B; S# z, r
 bom16.60-s030wint/ l1 `4 y3 ?0 ]
 capPSpLibMAB16.60-s018wint; P& O; A6 d# r! E) I7 B) ~
 capProg16.60-s044wint
 , z: f" N; J/ ocheckplus_exp16.60-s023wint1 w9 u' T2 h" ~& d1 @
 conceptNT16.60-s106wint
 7 }& Q. `4 `' K8 W# U* GconcptSetup16.60-s015wint2 q1 N# ~. M' p  N+ e
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 desSync16.60-s019wint
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 * B7 B" J  a* _" X2 C. ]7 z4 biff2hdl16.60-s010wint! D* T1 g0 V" x: w
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 lman16.60-s023wint8 }( _9 _, c2 l  }7 A6 V
 productServer16.60-s084wint
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 pspProg16.60-s043wint
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 8 F6 Z$ \" V0 z( R/ }; }2 ~/ yrfsipPcellIndep16.60-s005  o" k, q, ~, E' W
 sipDsnr16.60-s128wint- `; `1 d7 p0 k) T) v1 v! F! ]
 spbFPGAPlanner16.60-s065wint* V; |: A, N# v) U! J
 specctraQuest16.60-s122wint
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 vedit16.60-s043wint
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  cadence.spb.orcad.16.60.061.hotfix.rar
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