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DATE: 11-20-2015 HOTFIX VERSION: 061
) r0 p* s! x5 O8 T===================================================================================================================================
2 H& x4 U4 N; ~8 E" t9 M/ Y% S/ d" {6 kCCRID PRODUCT PRODUCTLEVEL2 TITLE
2 R( R; Y& U. w, ^. e===================================================================================================================================- L# W0 y$ Y3 Q$ C1 r( }
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
! D2 F% t/ W( c1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init9 M0 q3 w, f* e0 S: x9 q4 G6 i9 z
1413248 concept_HDL CORE Import from another TDO project makes the block read-only9 U8 ]* N) I8 S ~" [" \
1417429 allegro_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
. l( m5 a1 j0 O$ e% q0 b- C1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins2 j8 W1 E1 c1 L2 ?# L3 A6 e
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
1 f* W9 v5 e w ]8 }! l1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin; c- }2 L; f: v }0 A: \2 ^ [' s) m
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
3 j! v3 w# s# k7 o1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename
3 `9 c3 n0 I& Y8 d1 n1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets6 z8 M1 @# J1 `
1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL7 D4 J: _0 C9 V$ v0 I& {
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy+ o E/ _6 [) D# n( Q* Y
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
8 t$ n0 f5 y; P+ U6 x* X0 }1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets
: \1 W8 J% J3 _/ t0 t1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice( Z' @, _& D1 P$ f
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
( ?* ~$ K) ?3 q$ k1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
, w0 f; |$ I$ [( F( c2 x }# {$ i' q1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project+ @# p- E9 e% m& i- ?' Z
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.! c9 {: I0 R" F7 y! ~
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility
- m* z, M# C# W1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems
3 N8 A4 w" S8 N/ @% ?4 Z$ ^1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported
" i9 P$ B( S+ h: F- _. z1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior
d4 I, y9 n8 @, o& M2 d$ C1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
5 k- C, p) I8 y6 f* U: P1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager5 V7 t& ^. j2 h3 F4 K: D0 s1 t
1490299 SCM OTHER ASA does not update revision properly
" W6 p m& Q3 f- c1490744 ALLEGRO_EDITOR skill axlChangeLine2Cline changes line to cline and places it on the TOP layer& E1 Z I6 \5 ^: u
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints( F8 z# Q8 H" \
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working$ G5 l9 E& T8 t. S5 ?% |3 Z0 P7 V
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong2 V; v$ {* q- F9 `$ L: V( @
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash/ u8 M+ R7 T& d" s! p/ b
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL3 X+ C+ ?* G6 `$ X2 o8 f# m: e# L3 V
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581
) W' [2 [5 _ n1 f; u; h1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size
t: @- a _, V: I! x, f8 X) D0 ?1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
! r* @# R% f+ s1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file- G. M+ }1 ]$ y" ^* p' o
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60
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% i# o# w; M! p+ `------------------------------------------------------------------------------$ F, @ s8 l9 F9 {
SPB 16.6 UPDATED KITS RELEASE: ISR 16.60.061 EST.DATE: 11-20-2015
& m# j8 `" S8 c# M------------------------------------------------------------------------------1 l* d) R; X. c0 E" c- v8 c# G; J. D% Q
CompBrowser16.60-s037wint
+ O5 p# o; `6 L# ]7 RDSCoreUtils16.60-s077wint
: d$ h, ?5 i: }; ~1 S" ZDSCore16.60-s055wint+ D: ?- |# X( t7 D! M6 |- ?
DSSchgen16.60-s030wint, [- g$ K7 f% S# U! g1 S- {
DSSetup16.60-s010wint
6 Z1 s/ f& `8 h; c# G& F) D8 KDSTableEditor16.60-s018wint$ n0 q8 L; |+ A; G% ^+ ~
DSTextEditor16.60-s015wint
) G( \+ T( d: N- x6 ^; i2 `DSUICommonIndep16.60-s019
' I7 e( g: x$ K# T$ g5 O- y) u1 s, BDSUICommon16.60-s026wint
" H" B1 @$ I. D& x- d0 }DSUIUtils16.60-s037wint' ^# u7 H( w, Q
SPBIX06116.60-p002wint
' a2 J9 X* w& y; q LadpPDFLibs16.60-s033wint: G6 V% \* F9 h9 ]
advanPakgDsnr16.60-s129wint2 h9 n( ^1 U. _% q* e4 [
adwLRM16.60-s033wint9 }! L" Z) W3 m4 s! H, n& k- _! M- \7 X
adwSDM16.60-s044wint$ z8 d" p3 w2 f' y
algroAcad16.60-s122wint
$ g2 x6 @0 k5 _' D4 p4 J! U0 QalgroArtwork16.60-s122wint
; `# V- E( L( k) I2 l3 t! ralgroAxl16.60-s048
" _5 \3 m: j5 R; g4 WalgroBase16.60-s129wint
) m" v. l# A% j* I" T/ yalgroCxt16.60-s077; N* Z+ p+ y. f: T7 n1 i) j c
algroDBTools16.60-s124wint
; D9 p9 P' s N9 e2 W$ q& d1 j3 Q! talgroDsign16.60-s122wint2 d- a" |/ Q* w. T/ p
algroF2B16.60-s122wint. b" p* ^4 Q, N* w% _# O, s
algroIDF16.60-s122wint
9 r. ^# ?. o8 E: Q* w% G5 ^6 v% z$ \, ealgroIgin16.60-s122wint
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algroIpc16.60-s122wint
8 U7 S0 [; ~4 CalgroMfg16.60-s122wint
0 s, A0 a' f9 W4 S" qalgroNetin16.60-s122wint) j$ @; u5 D1 D! V! I: A
algroPlace16.60-s122wint- O* W+ Y0 ?0 v; O! G
algroSgnse16.60-s122wint
3 i" i) v6 W8 R, f2 U9 O9 h# AalgroSpif16.60-s122wint, T' @+ I3 k* R; p
algroStrm16.60-s122wint O) A3 P5 X @# E) Z
algroTextIndep16.60-s089
% I1 C8 s4 q* d3 N ~2 f$ zalgroTransltr16.60-s121wint
5 Z9 K; D$ T# H) L y8 OalgroUtlty16.60-s122wint3 M9 ]8 m( D d$ x) \# \. u0 Z
bom16.60-s030wint
. `% O/ D3 k6 hcapPSpLibMAB16.60-s018wint9 q8 c+ I! o `( N' b6 g
capProg16.60-s044wint
/ O* R; Z2 m9 X! ~" E9 s$ {- A: Echeckplus_exp16.60-s023wint% Y9 h0 y1 c9 L1 M* F/ c& {# Y9 d2 i
conceptNT16.60-s106wint
+ ^9 }/ D% g5 n& h4 d* ~- \concptSetup16.60-s015wint
1 I8 A6 K9 B/ N9 N: i. F4 s3 E6 w8 FconsMgr16.60-s104wint
* `) @- ` l- f: ?9 [6 b3 XdesSync16.60-s019wint. t2 {/ x. U/ _
eCWCore16.60-s009wint
6 b0 x0 X4 J' Z# d! a& QfetBase16.60-s034wint! x% X& O, n# x; v3 C
icpCommon16.60-s122wint
; H) Y3 D+ X# ~( v" _% Piff2hdl16.60-s010wint
$ r% p4 v# t a6 ^# [lmancore16.60-s036wint- O+ G6 e' ]" F- f* p
lmanext16.60-s012wint+ A2 `5 n# ?9 J/ k6 T) P9 w9 [/ M
lman16.60-s023wint" t) v. Q% B: w2 R' R
productServer16.60-s084wint
; {. J# f8 E( p% q' lprojMgr16.60-s015wint
7 w& d- i+ ?8 U4 \- {: xpspProg16.60-s043wint
1 J0 a% w. v5 P. ?6 Drfpcbfe16.60-s026wint3 g/ y3 \% d3 e+ F
rfsipPcellIndep16.60-s005; k6 ?6 I9 A7 s2 \
sipDsnr16.60-s128wint3 d2 I8 f! l' Y( k) ]: [
spbFPGAPlanner16.60-s065wint
- q( i/ b. t( O' A5 g& m$ [2 TspecctraQuest16.60-s122wint
( G# p% j$ q8 W4 B" V& T0 aspgSignal16.60-s123wint
3 M' _1 \( m& a* Wvedit16.60-s043wint6 b4 k& `( m: G k
; V J ?3 q8 v2 \' e补丁包种子！$ e' v6 h0 d* v
cadence.spb.orcad.16.60.061.hotfix.rar
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发表于 2015-12-3 09:33
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