|
EDA365欢迎您登录!
您需要 登录 才可以下载或查看,没有帐号?注册
x
/ O' ]- |3 Y0 o( p补丁包更新列表!: @9 O, k' M$ Y6 z% g4 L, \
+ H0 g3 x2 b! [$ ] Z+ WDATE: 11-20-2015 HOTFIX VERSION: 061
3 H; b* p; B% x+ ^- w===================================================================================================================================
9 A3 n( i: Y7 p' T6 ~7 U9 D8 L8 QCCRID PRODUCT PRODUCTLEVEL2 TITLE
. T \/ M6 Q4 o" c===================================================================================================================================
/ e8 o5 \! L# N# V; J0 O3 i/ {1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
\$ D8 ^& G9 e5 K1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init: V9 y2 O0 @) H. c, e+ v7 _2 T/ W
1413248 concept_HDL CORE Import from another TDO project makes the block read-only
( K9 q& |# D( ?% b1417429 allegro_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
. }- x' T4 Q+ m) Q3 ^1 W1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
; j7 [" P: j* f8 R1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set( D: G( h9 G0 z2 c! s4 w4 X3 }
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin$ _& R* U8 F7 N6 y3 H, I
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools4 o S) f, m: v, ~
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename! E' H* Z0 k0 {$ `
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets) c, H+ P' d0 v4 @
1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL2 `# ]9 p' ]8 ?6 g4 C
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy$ w! j! x" w8 T/ ~9 j$ D
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
( O0 o% u8 x& L# k1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets' `, t% Y& _9 n% k5 C' T9 w2 h( O
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice# {& u+ k0 e: c) s; x7 I
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
^& c+ C) k1 n) n. r; |9 b1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
% h; Z( i& C# `' A1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project6 Q1 W4 B; U b' o/ e! |
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.1 g* h; c; ]+ w6 I& g% }% b' s
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility
3 K! F. A, D) X5 o/ Y1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems
% ?8 d5 ]8 H/ O9 n" j; u" s1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported
' q' K- f s% c1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior7 r9 z7 a% l* c) N C
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
2 G0 L' W( \4 b1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager. h# Z! X9 Q0 O) j
1490299 SCM OTHER ASA does not update revision properly6 F' l. v+ y* y5 y
1490744 ALLEGRO_EDITOR skill axlChangeLine2Cline changes line to cline and places it on the TOP layer
* }: q9 ^ Y0 }. d1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
0 g V: w& i- g. ~, q" Y1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
( ?+ w0 }1 J9 c: O4 l* N, d1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong
& _% i9 p+ D/ B! ]3 E1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash
5 [6 i$ ?9 L) i4 s5 w( h1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL# ]! V5 t5 _0 o( N
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581
7 w6 [* o @. @0 u9 l1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size* h7 Z7 r# s; _, a/ |. u4 W7 u7 a
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root1 l. r3 N N7 }4 x/ s
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file& d/ h8 c# \( `% K# W
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60
4 u% n3 _2 O# q. z' @) C4 H! ?7 |/ L) z! `" y* S+ j* V/ J$ Q
8 M; w6 V9 R& L* l; I) ]; k) y9 d$ s' l
最新破解包列表!7 x/ m- L3 e! }$ ^ p; R; {7 s# Q! S
------------------------------------------------------------------------------2 h' N/ o' Y; J, H! A* @( ^- W: Z
SPB 16.6 UPDATED KITS RELEASE: ISR 16.60.061 EST.DATE: 11-20-20157 q! d5 h) }) O" [
------------------------------------------------------------------------------: q* o$ N+ A6 ^ a4 D2 ^
CompBrowser16.60-s037wint
- d# z" w+ X. @; [5 Q! j( u) jDSCoreUtils16.60-s077wint
& O' S# Q* l+ S" j/ Y# J. s2 IDSCore16.60-s055wint2 Z9 _1 l8 u4 s' _
DSSchgen16.60-s030wint
; f. i5 K( ` h8 _DSSetup16.60-s010wint
+ ^& A) F, w8 i2 ^3 zDSTableEditor16.60-s018wint- I$ g, T7 w$ J/ E7 Z
DSTextEditor16.60-s015wint( _/ X, j+ P" u/ b n- U
DSUICommonIndep16.60-s019
/ w) [; `, I5 fDSUICommon16.60-s026wint1 x( _, e% w% y0 p0 f5 j8 D) \5 n
DSUIUtils16.60-s037wint
$ ]7 I2 _& O% T3 M8 r* W8 |SPBIX06116.60-p002wint7 [9 }( e; q! H9 l/ M1 k
adpPDFLibs16.60-s033wint
) q2 M+ u# g! t& v7 e8 RadvanPakgDsnr16.60-s129wint
3 h9 e% _2 b/ Z1 I. c2 @adwLRM16.60-s033wint
5 [' u+ R3 V E/ ^% k) K% aadwSDM16.60-s044wint8 m, n3 ?% h4 \0 ]
algroAcad16.60-s122wint
4 J: ^: B# {! I; {0 {algroArtwork16.60-s122wint1 j) P; U2 M: N3 z0 s
algroAxl16.60-s048
5 e$ Q9 i! _9 s: C3 QalgroBase16.60-s129wint
2 r1 [% B* f9 O9 }7 G" F% ualgroCxt16.60-s077- W& ~9 m1 _! W, q
algroDBTools16.60-s124wint
$ e0 R. p1 @7 N& w9 HalgroDsign16.60-s122wint
* Y% p6 X$ p9 ?" P3 `algroF2B16.60-s122wint
9 N% I; `( o0 s* y ZalgroIDF16.60-s122wint6 @" F$ v& ? q# I9 a* w% d
algroIgin16.60-s122wint( G& B2 \6 l- ?7 a5 v$ K" V
algroIgout16.60-s122wint9 I1 w% r5 J2 ^) Q! C
algroIpc16.60-s122wint
p) m. H' M7 A* xalgroMfg16.60-s122wint9 `1 O+ u. h7 z$ \: o6 Z2 w
algroNetin16.60-s122wint
1 B$ L' D; l f' q4 I$ K b7 halgroPlace16.60-s122wint8 `( H! r9 P; P9 q' K0 \1 V
algroSgnse16.60-s122wint; j' h% \+ R- y( g: H9 x3 T
algroSpif16.60-s122wint
* V6 ?0 j+ w8 ZalgroStrm16.60-s122wint
# F! A# ~5 e1 Y( V- r3 _algroTextIndep16.60-s0890 k; A/ D% w* W
algroTransltr16.60-s121wint9 e- Y6 @+ l5 |2 G0 e
algroUtlty16.60-s122wint
+ N0 @5 N$ ]4 h8 S; r6 F. ?- t& fbom16.60-s030wint0 z( j; G+ z: x4 `
capPSpLibMAB16.60-s018wint( ^* n" N6 Y" p" }: T
capProg16.60-s044wint
. R: ?. B2 Y' D! Y7 m: Echeckplus_exp16.60-s023wint! H; B; }4 j) \
conceptNT16.60-s106wint) g; ^5 K7 G* l1 [1 R/ K
concptSetup16.60-s015wint
! n% M% q% G0 s2 e) x! tconsMgr16.60-s104wint# c2 ~# A3 _# d$ W6 |
desSync16.60-s019wint
3 V( f9 E% g$ aeCWCore16.60-s009wint% ]) A2 F) Y, A" `3 r q
fetBase16.60-s034wint# |6 q+ \1 V- k' `
icpCommon16.60-s122wint5 O; q% y4 @1 z" d( c
iff2hdl16.60-s010wint
u6 x: q. u$ B5 b% X9 o& Llmancore16.60-s036wint$ ~0 M* e8 m! i0 `7 ]& x# r# M
lmanext16.60-s012wint& Q* J& v/ |- h9 w* w: x: B
lman16.60-s023wint
6 z2 w3 `- e' s. l* zproductServer16.60-s084wint6 |; u$ M! |# Q6 C% F
projMgr16.60-s015wint
, R0 g3 p8 V, _ opspProg16.60-s043wint+ ~8 D, {2 f4 N+ c A k8 f, d8 o4 q
rfpcbfe16.60-s026wint+ K7 u) a2 O8 }4 f! \
rfsipPcellIndep16.60-s005
/ _! }" o* w' A/ H& dsipDsnr16.60-s128wint
% t2 R4 r; `: ]spbFPGAPlanner16.60-s065wint
0 K! q: @$ N3 F1 a3 sspecctraQuest16.60-s122wint
! d5 Y! C- ^: U1 [+ PspgSignal16.60-s123wint% r! ]$ |( f" T& Y, D/ R
vedit16.60-s043wint
4 x+ p& U- t' J2 X6 Q
) Y. e6 L# ^: @: H4 J. b4 w补丁包种子!3 q1 r+ G& ^* R$ c
cadence.spb.orcad.16.60.061.hotfix.rar
(17.88 KB, 下载次数: 1069)
% i) ~' E% i; [5 u' s5 E
" Y6 u: D- P$ c2 @$ i/ x& z3 D" \* z+ k' M5 x8 z( k# c1 [; z4 u
2 u! l% \: o# F% d) @) `1 O
|
|