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EDA365欢迎您登录!您需要 登录 才可以下载或查看,没有帐号?注册    4 R$ I! K6 E1 ?* D) k补丁包更新列表!
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 DATE: 11-20-2015   HOTFIX VERSION: 0611 ^( B+ q9 r& }8 F* H
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 CCRID   PRODUCT        PRODUCTLEVEL2   TITLE" i3 ^  O' M8 o
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 3 ~# j% g$ ?9 |- \1 i- j7 I0 w1306441 APD            OTHER            The Minimum Shape Area option in Layer Compare uses an unspecified value5 _* y" p+ x+ w1 P  k) H
 1342644 ADW            COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init
 . f+ p4 }+ j. v' ^1413248 concept_HDL    CORE             Import from another TDO project makes the block read-only
 $ t  L9 a2 K" `, {4 Q/ t  o1417429 allegro_EDITOR INTERACTIV       Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
 4 a2 b; Z, e* H2 E  c) I; \+ H0 d1417442 ALLEGRO_EDITOR INTERACTIV       Spin via stack and only part of the stack spins
 ; u0 T3 e$ q, I3 G1451977 CONCEPT_HDL    PDF              Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
 , g. o9 M  ~# i  M: g7 T/ D6 W1453527 ALLEGRO_EDITOR EDIT_ETCH        Contour route hugs the outer edge of the route keepin
 # i: a% {% ^; j/ p$ A8 P# @1464948 PCB_LIBRARIAN  VERIFICATION     The errors/warnings do not match between the various tools
 : @- f; _0 P2 ]: T- d, q/ j1467826 CONCEPT_HDL    PDF              PublishPDF from Console Window creates a long PDF filename
 - h* M  `0 P/ T+ Y/ j9 O+ I1478639 CAPTURE        OTHER            Capture Browse Nets window does not display all nets: o+ F. X+ }/ @  M- x4 R
 1479177 SIP_LAYOUT     OTHER            Pin pair constraints do not appear to be supported in Sip Layout XL5 W5 ^7 y+ q7 O; Y) d! ?: M8 P# U
 1479227 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
 . _6 p( D8 j$ a3 y. |% n1479454 CONCEPT_HDL    OTHER            DE-HDL issue: locked DIFF_PAIR property is editable" _! Y5 u. _3 |) p) l" I
 1480293 CAPTURE        PROJECT_MANAGER  Capture hangs when searching for all nets
 ]7 ~5 A, Q7 @+ x" B$ r  }7 g1483894 CONCEPT_HDL    CORE             Import Design hangs when pull-down arrow is clicked twice! \  F+ w3 N% J
 1484781 CONCEPT_HDL    CORE             Three different Hierarchical Viewer issues
 3 m, x: O+ @8 g& }; a8 Y( O7 T1485059 PCB_LIBRARIAN  CORE             Part Developer pin attributes are randomly marked as read-only7 D& U% W. n" b2 H
 1485960 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule is crashing the project
 + `& D' R/ G! @# t! f  N1 S+ }1486086 ALLEGRO_EDITOR ARTWORK          Cannot generate artwork.
 7 f& ?) J; `  k# d) t1486834 CONSTRAINT_MGR OTHER            Restore the Status column in cmDiffUtility* ^/ b3 Y" T$ e5 W  }
 1487085 CONCEPT_HDL    CONSTRAINT_MGR   Import Physical with the Constraints only option reports problems) F) g" y1 [6 T$ P1 Z
 1487197 ALLEGRO_EDITOR DRC_CONSTR       Drill to Via DRCs are not being reported
 & o! T. I9 R) o7 @1487265 CONCEPT_HDL    CORE             Replace command in Windows mode shows incorrect behavior
 & q0 U  i; g/ S; C* s1487733 CONSTRAINT_MGR OTHER            Running Export Physical - It takes over two hours to update the PCB Editor board
 & v* @* Z+ p4 U( G6 s& M3 \" w+ u1488758 CONCEPT_HDL    CONSTRAINT_MGR   CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
 2 S0 L4 F3 a( m% v3 {7 u, ~$ M1490299 SCM            OTHER            ASA does not update revision properly
 ; ^5 K. ~* I4 M1490744 ALLEGRO_EDITOR skill            axlChangeLine2Cline changes line to cline and places it on the TOP layer
 / V% O1 f0 b+ w8 r+ c1490924 F2B            PACKAGERXL       Save Design/Export Physical is resetting Via constraints
 7 y7 A8 K7 ]4 V  |7 K% X& f" S$ q+ }0 G1491351 ALLEGRO_EDITOR OTHER            Create Detail for bond fingers on a custom layer not working
 , V$ W' k3 D  _7 M1492595 ALLEGRO_EDITOR MANUFACT         Dimension character substitution help is wrong0 H; |( O- j! I6 e& \& V
 1492777 ORBITIO        ALLEGRO_SIP_IF   OrbitIO import of customer mcm results in crash5 E' E) f* {) h: i) q
 1492901 CONCEPT_HDL    CORE             Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
 : J  M. l+ z  Y2 M& h! L6 m1495621 ALLEGRO_EDITOR INTERFACES       Oval pins are placed with wrong orientation in IPC25813 F: x* q2 ?. }# V+ o/ w
 1497597 ALLEGRO_EDITOR DATABASE         Show Element on pin shows wrong drill size
 9 }2 L) j- L( n: S$ A* |6 L% r1497956 CONCEPT_HDL    CORE             ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
 * c; b( ~0 k# c$ u( E/ L( x# P! L1498234 ALLEGRO_EDITOR ARTWORK          PCB Editor fails to create artwork and no error is listed in the log file: ~. Y8 ^. c0 _- ]  K  _
 1499363 CONCEPT_HDL    CORE             Custom attributes under variant management stopped working in Hotfix60# I+ L7 ~! U2 E3 _4 C7 T' w' X# m
 
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 最新破解包列表!0 M( e( p- p( F* u
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 SPB 16.6   UPDATED KITS RELEASE: ISR 16.60.061    EST.DATE:  11-20-2015
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  cadence.spb.orcad.16.60.061.hotfix.rar
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