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0 j5 `" V9 t2 Y* \( n4 A补丁包更新列表！
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DATE: 11-20-2015 HOTFIX VERSION: 061
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 q5 V0 N6 T' p" G===================================================================================================================================
: G3 E }& v' C; L- n1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value* y/ K( a' O# d$ N
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init8 O- W& t2 l, ?4 P$ V" F' P* C
1413248 concept_HDL CORE Import from another TDO project makes the block read-only
6 X, q% y* \- Z1 V9 R% h5 r9 i. u1 e7 j4 _1417429 allegro_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
. |# v" }7 ~! f1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins- j8 A: Q1 A; b5 m1 Y+ T; q) ~2 c- g
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
% b0 P6 O% n0 z, J# Y s$ F1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin9 `6 z0 E5 I6 N. F
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
1 t+ |+ E/ [0 o7 ]; M* p0 |1 A1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename, v# u- \8 P1 t4 w P3 S, y! j
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
9 y3 Y/ L/ z8 \% t1 p& {7 L( E& `1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL+ Z9 e# d8 g- G5 ^' t
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy5 O( ^! s* f8 @' g' a* k& t ?+ z$ z
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
4 F; }) h- G, u7 g0 m, q. N1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets
, @7 n; b/ \* j+ r1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice
! x5 Q0 w; o# q4 q" u) @. r4 _; q1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues4 n4 j8 w; K7 e( ]
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only9 Z T2 M0 c9 c: }6 D
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project4 L7 F$ L W! @* c
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.
, X5 F* O) o% ]& L) L1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility. m& k$ Y. L8 Z1 I
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems/ M6 D' j( `( }0 ]) g, E
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported
+ F: g' w0 l8 ~6 D, n# Q/ N2 j/ w1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior
* o) V% K" v% `# D7 L- x; V5 H3 a1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
h/ v0 x% ~% x) j6 O1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager) v3 k" t5 O5 ?& W. W7 h7 u* [ r& m
1490299 SCM OTHER ASA does not update revision properly; F) J0 N0 G$ g2 W6 [& D4 q5 G8 [
1490744 ALLEGRO_EDITOR skill axlChangeLine2Cline changes line to cline and places it on the TOP layer
6 G* p. Y+ L3 J$ d5 W% q) V0 s1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
2 M. i1 c, [* N v" ? L2 e4 [1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
9 H& M3 m% u5 {1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong
) i! {8 {+ |) o1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash
3 S2 s# w: i* ^1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL" c4 u5 R3 d2 L' q' r0 d) S5 R0 T
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC25812 p0 I2 u+ p8 ^0 O& D* @
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size# b! j) C% H- M
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
$ ~3 E4 C) N9 v. e) |5 u8 M( e1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file& O- N; u9 A+ K; u/ O4 f
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60
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+ v+ [% n$ ]4 Y* o8 r; P最新破解包列表！
/ O s, J/ M. [9 | \) [5 P d------------------------------------------------------------------------------
! L) S/ t! _3 Z0 ~& B0 N6 P, jSPB 16.6 UPDATED KITS RELEASE: ISR 16.60.061 EST.DATE: 11-20-2015
! k$ G/ \) n4 e' L1 @' c$ w8 V, G------------------------------------------------------------------------------
7 u# y1 D7 u1 r! sCompBrowser16.60-s037wint
( v6 a8 h0 Q: q6 m5 h6 q. _6 x5 YDSCoreUtils16.60-s077wint
6 m% e4 @9 v0 x sDSCore16.60-s055wint* Z" x% u9 O2 s" P; j
DSSchgen16.60-s030wint
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DSTableEditor16.60-s018wint7 C" x# t o8 J1 P& U. E6 E' q
DSTextEditor16.60-s015wint, r. |1 w! q. w- ~- P
DSUICommonIndep16.60-s019! Q$ P6 W; F& G1 Y' a
DSUICommon16.60-s026wint
3 i& W: u8 ^" p4 n2 mDSUIUtils16.60-s037wint$ B3 s, g" C2 l$ x2 b+ `& F
SPBIX06116.60-p002wint' H+ E! \; z8 k" b* U
adpPDFLibs16.60-s033wint2 l* A* K$ a1 \2 n% z# u: U$ D
advanPakgDsnr16.60-s129wint# Z. u+ o8 Q5 h( U# d% Z' |$ v
adwLRM16.60-s033wint x& v! P' N7 A
adwSDM16.60-s044wint* n1 z5 \. l, N- }: Y. V) Y. o# ]
algroAcad16.60-s122wint
9 ?/ c" B6 e; L: y; ~algroArtwork16.60-s122wint& ?* m: ?0 ^! \/ c- W6 g
algroAxl16.60-s0489 Q) \4 L* w1 `: O" h) e- l
algroBase16.60-s129wint8 M3 }: U' i' I+ Z1 J# ~' q. P
algroCxt16.60-s077
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algroDsign16.60-s122wint! M6 |% N+ P: T7 Z0 L/ D
algroF2B16.60-s122wint
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algroIgin16.60-s122wint, ~+ k( H% i% D
algroIgout16.60-s122wint/ L2 V0 s- S/ h ~9 q+ u2 r
algroIpc16.60-s122wint& _9 b/ Q) N6 T9 Z: r) p Z) ]
algroMfg16.60-s122wint
; A Y! `0 e/ H6 o ?algroNetin16.60-s122wint, R- H$ [3 x1 @/ [1 b
algroPlace16.60-s122wint
; E# W- o7 Y( r; G3 h, M) lalgroSgnse16.60-s122wint
, {9 d" J: t9 @' C; C5 RalgroSpif16.60-s122wint+ B, Q1 ~6 Y7 W; G" l0 j8 j' P# t
algroStrm16.60-s122wint1 z7 P }7 p9 [$ @, f
algroTextIndep16.60-s089) d5 x3 F( a. n! O. {
algroTransltr16.60-s121wint/ v6 X) n6 Y; B
algroUtlty16.60-s122wint' `0 }' @ M$ |8 j1 B
bom16.60-s030wint
1 m, c4 a% T$ IcapPSpLibMAB16.60-s018wint' `# r' ^1 q- E M/ I0 C/ ~- N$ e, r
capProg16.60-s044wint' U2 g9 c8 W! F
checkplus_exp16.60-s023wint
( z v7 E& A! n, [conceptNT16.60-s106wint# i* ]$ c; N) N( a0 Y I
concptSetup16.60-s015wint
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desSync16.60-s019wint
1 K5 z( ?# ^6 w4 ]eCWCore16.60-s009wint/ K7 D5 E4 R5 Z
fetBase16.60-s034wint" N2 U5 ~; d; _# g1 t. F" f* h
icpCommon16.60-s122wint) n- N( r7 V3 s9 m9 n+ Q1 s
iff2hdl16.60-s010wint% o( C/ A+ k7 o5 [. V0 r$ W" l' o
lmancore16.60-s036wint
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2 }7 f7 S8 d0 z, Nlman16.60-s023wint
- f5 D# r5 d2 p& SproductServer16.60-s084wint
5 v8 G7 W: f* s' W4 h4 N7 q+ aprojMgr16.60-s015wint; t4 r6 H5 n1 `$ O3 A
pspProg16.60-s043wint: U/ b- l1 `4 \0 \
rfpcbfe16.60-s026wint1 h* S2 U$ m2 `: Q! Q* ^; ]( @
rfsipPcellIndep16.60-s005& ]: J6 T4 t! Y' Z4 W, U9 I
sipDsnr16.60-s128wint/ L' ]4 d: b1 H$ M
spbFPGAPlanner16.60-s065wint
6 d: X# @- g% MspecctraQuest16.60-s122wint# p" Y$ ~0 R! b5 t7 C
spgSignal16.60-s123wint& z. U% `+ P3 {5 ] T/ P( M. V
vedit16.60-s043wint
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% z: U/ f8 E: c4 j) g补丁包种子！9 h6 S$ }! u5 L6 d) f# ~$ v$ u* {
cadence.spb.orcad.16.60.061.hotfix.rar
(17.88 KB, 下载次数: 1069)
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发表于 2015-12-3 09:33
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