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本帖最后由 紫菁 于 2017-9-14 16:05 编辑
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$ h1 j4 ~+ U! D$ |2 X1 Q: m+ f: E转 Hotfix_SPB17.20.015_wint_1of1
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Fixed CCRs: SPB 17.2 HF0151 h$ N+ y U. t
03-16-2017# _4 W# {, q7 i
========================================================================================================================================================6 M" q& n6 N8 x
CCRID Product ProductLevel2 Title5 m* e1 ~& [+ q
========================================================================================================================================================5 l- i1 g% j! T! V! {+ j" f7 C
1653366 allegro_EDITOR INTERFACES Unable to attach step model to symbol
. c4 g+ K% T1 j7 P2 b5 M4 [1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model
8 K1 ]: I! z. h1 O5 N1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function
N& Z- H0 u! |: O6 N; Z1 C1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file
$ D* a: _' n; A6 u. `8 q1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting padstack Editor results in incorrectly scaled forms* T/ q) x$ v/ R, t, b) M" U
1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design- ]6 e' p1 x) _, x: ]. b- i
1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees
8 z6 z- P1 T/ k6 K% S9 H1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.$ ~* B# ~, a. g) A$ p8 H6 g
1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
$ k. h$ k% i. g: X- h* ~: t1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor4 _4 B; | l Y; O# z
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not( B$ U) @, D! e8 J( N; q
1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used1 o$ y; `- K& R# l- ~
1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places
, h# T% s/ ]5 [6 ]2 H9 ?, J& x8 C1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value
* D& u. U) H3 j9 \/ v1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
1 B5 H# P E) z. O) o3 I1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad
# B' q# @/ r" L9 Q+ l, T8 o3 x/ O2 r1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout
5 m0 X: H& a8 S: V1 |! k/ q' T( j1698697 concept_HDL COPY_PROJECT Copy project corrupts the .dcf file
& x/ N7 }) ^- r7 J1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084
. U6 O" M; O& o5 @, A9 l9 O1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position
- n+ ]0 [- l& v# U3 _3 U: _3 r& c1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net
; r# a, u" ]* v/ V1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer0 x5 ]* j/ ] ?; N0 V- g
1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation! a0 c4 f# S$ Q9 G2 ~
1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
! A* h2 Y8 J) S. l( r1 g1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode
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/ Z9 N4 T# N, ?9 f) l0 Q$ ~8 o转：Hotfix_SPB17.20.014_wint_1of1.exe 链接：http://pan.baidu.com/s/1jHFB2Pg 密码：mxnk
( S" \+ r% g% R; K9 ?9 _Fixed CCRs: SPB 17.2 HF014
/ P7 s" t' R2 F0 @) O' F+ n- x========================================================================================================================================================
2 p' c' g( M( `5 N; g8 {CCRID Product ProductLevel2 Title
7 [- C6 z9 A9 d. T8 _========================================================================================================================================================; X2 ^3 x a8 C2 n* g' p3 z5 Y9 y, A# W
1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships
( z: t! ?( e& w- M1 _1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity4 E8 t( z! M' M" g4 c* W, r
1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-268
; L+ Z+ D0 {: n B7 V2 D; x1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data. s) ~4 u! O3 t' v) S# k) m
1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data
& f7 i0 [. `, a# ?' h( L1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors5 [- H1 z2 c, j( p2 c
1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.
, j0 r" ~# @" [% z+ [1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted
: n* b' t" a: L% `3 G1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location
7 e5 J ~; G8 }7 d9 d# W& m1685995 ALLEGRO_EDITOR skill All film sequence numbers are returned as 0 when using the SKILL function axlGetParam) Y4 d5 h, _ i$ d2 ]& h1 f* G1 L6 q
1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately
( Q; P) s: L, v @1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6
7 P& b& R4 t9 ^: Q4 S, \1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one
& L# ^- r0 g; r( h1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled; j2 l! H- i) [! |+ M$ d8 Q
1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved! u- ?, c6 `, \- Q" E& k8 E
1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components
& x$ f9 C4 k$ [( S' X1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers! K1 ]( g7 L) J; v" `; K0 ]/ W6 q+ w
1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase
: V/ P" k7 N. p. w- p/ n1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement
3 }# [6 c& ]+ C, Z1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message" B- \/ ^: L, F. m/ \; F( T
1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011
6 o1 b8 w3 d9 w$ ]/ N9 b, ?1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2
2 x3 o. b4 d* c4 U) s9 w1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers4 t' c0 I7 {/ i
1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016
5 R* ^. f* P* L2 y( j+ q1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design2 Z3 M5 _8 E Z
1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors& l5 a, @, `4 P& V, E
1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters
# c3 |3 f$ b5 H& T' G1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP
6 m. P0 g& o2 {4 p3 U5 z/ j3 a9 D1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'
9 s3 q3 G2 b6 `; F* h" o% R, V+ L& `! Q1705265 INSTALLATION DOWNLOAD_MGR Problem installing orcad Library Builder from Download Manager
* M( i9 K# I$ `/ b1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script
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cadence OrCAD and Allegro 17.20.013 Hotfix链接：http://pan.baidu.com/s/1kVmHGZ9 密码：smsv
0 W$ p0 A# F5 f; y. BFixed CCRs in SPB 17.2 HF013
' h' b4 E) o+ G5 J========================================================================================================================================================
. }& H8 E+ ^6 W. l, J9 E+ h; R bCCRID Product ProductLevel2 Title" b) a4 d7 e! ~6 O+ y
========================================================================================================================================================7 i' x0 `; j0 U
1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm
0 i4 Y8 O+ a4 ]) X: X, l" F1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer7 [9 W( d# [; w
1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version: H; V$ S/ a, R2 {7 g+ p
1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated
$ Q* A% z" F. {; h$ p2 C' K1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated
( h# T% _ f- x6 B1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board
. E* k9 N! O4 O6 ?; D7 a3 x1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
6 m2 l2 x. ~4 D% A' m/ r% q- n1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol$ j& G; _! d% h3 K' D( Z- n4 y8 h
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
+ T7 q: x! d1 I! x- C# i+ K1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components( O3 c. e+ [5 S
1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components
* I& Z2 z: p2 s, g9 u2 N1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets- U" J# v' r. d# I$ ~' S8 t
1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets
+ j: w, v5 e! ~& v( G% R9 P. G2 T1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF
- f5 ~$ x2 i$ O+ o$ _' f: ~- J1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement: b! Q2 ?: m7 K `3 r* ^" I. Z$ O
1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.2 {9 V4 ~# Z: k% d; _
1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file! s3 `; d0 o% e
1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.
4 K6 F: h# U3 Q# Q7 v' {' S" j1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker! N+ {$ y' x) M
1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates7 h' D9 g' I0 q' [ _
1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes) l: L' ~; j8 X/ O* Z; l1 T- d
1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.; o9 `1 R6 D& {& j' \
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发表于 2017-2-26 17:05
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发表于 2017-2-26 20:26
