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Fixed CCRs: SPB 17.2 HF021
; h! t' `5 w9 ]( g% J" m P) T06-3-2017
3 F/ m1 l& z8 P4 F2 d========================================================================================================================================================
; A! f7 Z7 _! f( R+ T! E" q0 DCCRID Product ProductLevel2 Title
& g% E* X' \, }* n& |& f k========================================================================================================================================================
7 [ x3 X0 l( n. @5 U6 C" y1401318 ADW DBEDITOR Bulk Edit - Previously modified cells do not turn blue when selected9 M7 {( b$ M( J
1621446 ADW DBEDITOR Bulk Edit - sorting highlights incorrect cells to mark them as changed0 x4 f( a: k- R; f W
1743997 ADW LIB_FLOW Match file for standard models is incorrect
& {; U, S! v" }1 p1746052 ALLEGRO_EDITOR DATABASE PCB Editor crashes when applying no drc property) L: N( C7 F6 F% `2 m7 i- j
1736067 ALLEGRO_EDITOR DRC_CONSTR Interlayer checks not reporting DRCs between cline and mask layer2 z* Z% s& I y. S! q
1738587 ALLEGRO_EDITOR EDIT_ETCH Line width changing on slide for ETCH - Conductor (Not on a NET)
& o6 i3 t: f; L# D* J$ h1745277 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using the slide command- G6 q$ [; a1 h# L: M
1747942 ALLEGRO_EDITOR EXTRACT Fabmaster Out does not export arc in pad_shape( f$ W3 b. b3 V6 }) n$ @! }
1737202 ALLEGRO_EDITOR GRAPHICS Setting the variable display_raster_ops
7 g* I. G/ }* K6 X; Z3 }1744042 ALLEGRO_EDITOR GRAPHICS Unused pad suppression is not working on few nets
" S# N# m8 r0 {1703848 ALLEGRO_EDITOR INTERFACES IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty( Z1 w: J; c. c4 K8 G1 Q* i
1743899 ALLEGRO_EDITOR MANUFACT Glossing dangling vias crashes PCB Editor
2 \. O. `, a8 I% F1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor$ ]3 S- }" Z7 n' \' Z. z7 N
1748520 ALLEGRO_EDITOR OTHER TDP fails to load on an empty database
- G3 {4 V4 t! l( b) y5 h( K1748581 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when changing default pad geometry
. D. n( j* Q* `1751469 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes/freezes when browsing for a shape symbol
# T! H" ^ U, R6 N' }1725948 ALLEGRO_EDITOR SHAPE Shape differences after conversion from release 16.6 to release 17.2-2016; D4 c- s2 H+ T
1729306 ALLEGRO_EDITOR SHAPE Seting shape_rki_autoclip variable causes no void to be generated; g6 n* N0 U* j- U: s
1698876 ALLEGRO_EDITOR UI_GENERAL Tabs are large and text is compressed in release 17.2-2016
, g( F6 L1 @/ K' M5 M1698883 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors! W- s! \5 d) S9 J$ Z# `1 {. V1 ~
1707933 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not locating menu as per x_location
+ e4 \2 `5 L% Q% [7 _/ [1741460 ALLEGRO_EDITOR UI_GENERAL Right-click, context menu options grayed in some cases after choosing Edit - Copy9 {% f- u* J+ s; o1 w5 X
1747588 ALLEGRO_EDITOR UI_GENERAL Interacting with PCB Editor by sending messages is not working( t8 g6 B$ Y# x0 Z- a( @/ E7 O
1747488 APD EDIT_ETCH Route connect is improperly affecting existing routes in locked high speed via structures
" U+ o: |% k' q% d* E1750182 APD STREAM_IF The stream out settings are not saved5 K. Y, k4 v) t; u
1752067 ASI_SI GUI Links to differential waveforms do not work in Sigrity SI report
/ a9 Z( }: N3 }7 Y1752131 CONCEPT_HDL COMP_BROWSER Symbol view in part manager doesn't match the symbol version2 O4 Z2 o# D7 E/ Y2 c
1754116 CONCEPT_HDL COMP_BROWSER Default Symbol selected is n°2 instead of n°1 in component Browser
+ h$ h+ a' l9 s! L A q1754949 CONCEPT_HDL COMP_BROWSER Part Information Manager displays preview window with the wrong symbol and missing footprint
0 f# s: d5 @- m1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic
6 r9 {- [7 l5 d1750916 CONCEPT_HDL CORE DE-HDL crashes when trying to uprev a project in release 17.2-20163 z$ |; E) Z O
1711487 CONCEPT_HDL INFRA Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design5 C! s) ^$ m" H6 ?6 ~ E
1746915 CONSTRAINT_MGR CONCEPT_HDL Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow
! K. x# f& q. P1 o, b! |1743523 CONSTRAINT_MGR DATABASE Suppress warning pop-ups from the constraint automation script
1 Q% R/ M" U. N* x1746941 CONSTRAINT_MGR UI_FORMS 'Go to Source' from DRC tab is not working in release 17.2-2016
, `* S1 A' V+ i; k+ v1753010 ECW METRICS Metrics not getting collected due to old license in use3 y6 M7 m7 T1 P7 C, s/ W) I
1713052 FSP GUI Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance
+ Z: U7 f z; U2 k, d! \9 y1719099 FSP GUI Net naming wrong after building block
k+ B1 J e1 m% i( y o1719105 FSP GUI Tabular sorting not working in FPGA System Planner' B9 v0 H. o3 A& [" Z) S
1720479 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems
9 s$ a( _3 i5 _) v" y" {1723411 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems% K8 S: R: O+ w) ~
1746628 PSPICE ENVIRONMENT PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016
* k. H8 U' O- W6 P* V/ [0 M x6 U( w1745976 SIG_INTEGRITY GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing
R& d: P0 g( ~6 e; J1690820 SIP_LAYOUT PLATING_BAR Cannot add fillets to pads with plating bars in release 17.2-2016+ S, X& M; a( g0 P
1725042 SIP_LAYOUT PLATING_BAR Creating a plating bar removes dynamic fillets9 |: l( V3 d5 V9 @4 x ]
1747534 SIP_LAYOUT SHAPE Moving fiducial crashes SiP Layout( ?; r$ x/ z% P3 ^% ?# T5 h1 I
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发表于 2017-7-2 18:37
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发表于 2019-2-27 16:42