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Fixed CCRs: SPB 17.2 HF021
+ ]6 y5 K9 N5 l! h6 M06-3-2017
' w5 ]' b2 ~3 ^3 p) u========================================================================================================================================================9 ]! u( c+ H! y q
CCRID Product ProductLevel2 Title
6 U: X5 J* K; z% R========================================================================================================================================================
. S y; ~6 p+ t" Z1401318 ADW DBEDITOR Bulk Edit - Previously modified cells do not turn blue when selected! R& E- z6 L2 b4 [2 L) z! g
1621446 ADW DBEDITOR Bulk Edit - sorting highlights incorrect cells to mark them as changed
- P! J* I" ^( L5 s4 U, \1743997 ADW LIB_FLOW Match file for standard models is incorrect9 w- p& `* T H2 B6 ^- n6 @/ d0 {
1746052 ALLEGRO_EDITOR DATABASE PCB Editor crashes when applying no drc property
4 g; c3 _% I/ a: D1736067 ALLEGRO_EDITOR DRC_CONSTR Interlayer checks not reporting DRCs between cline and mask layer3 j# u* D# |7 H1 X# ~) z* n
1738587 ALLEGRO_EDITOR EDIT_ETCH Line width changing on slide for ETCH - Conductor (Not on a NET)5 o6 a1 y# M7 W$ F
1745277 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using the slide command
6 p; r/ t" h) }. n9 _% c1747942 ALLEGRO_EDITOR EXTRACT Fabmaster Out does not export arc in pad_shape
3 t0 V/ G* H) i/ a1737202 ALLEGRO_EDITOR GRAPHICS Setting the variable display_raster_ops
6 O7 e. t1 f6 f1744042 ALLEGRO_EDITOR GRAPHICS Unused pad suppression is not working on few nets
+ S* L" e9 i0 x1703848 ALLEGRO_EDITOR INTERFACES IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty- j2 A8 j+ n/ n& }0 `
1743899 ALLEGRO_EDITOR MANUFACT Glossing dangling vias crashes PCB Editor6 j4 @, m9 n8 y* A; K6 f+ X8 V7 M
1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor
, \6 Y- J% g$ x2 _( B! c+ J# q# p1748520 ALLEGRO_EDITOR OTHER TDP fails to load on an empty database8 s8 _$ Y/ n0 [$ W$ C: ~" P
1748581 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when changing default pad geometry( O" r" G5 w- O0 ?2 H8 K. T( V# |+ @& }
1751469 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes/freezes when browsing for a shape symbol
/ k. C. n; s- h! S1 ]1 y7 q1725948 ALLEGRO_EDITOR SHAPE Shape differences after conversion from release 16.6 to release 17.2-2016; G" U, C/ [: w2 }
1729306 ALLEGRO_EDITOR SHAPE Seting shape_rki_autoclip variable causes no void to be generated
( g8 N; D8 R ]' q1698876 ALLEGRO_EDITOR UI_GENERAL Tabs are large and text is compressed in release 17.2-2016" t0 ^/ G, s: y- K/ R, D
1698883 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors
/ O) i K3 b- M) F0 n1707933 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not locating menu as per x_location
! s& c$ q* e; }1741460 ALLEGRO_EDITOR UI_GENERAL Right-click, context menu options grayed in some cases after choosing Edit - Copy
" A4 {1 N0 _, v, G, |, I6 T1747588 ALLEGRO_EDITOR UI_GENERAL Interacting with PCB Editor by sending messages is not working
, \1 Y" p0 h; ^) o1747488 APD EDIT_ETCH Route connect is improperly affecting existing routes in locked high speed via structures
5 l' w) X6 u1 a, e% B1750182 APD STREAM_IF The stream out settings are not saved. R5 V; I8 k, g
1752067 ASI_SI GUI Links to differential waveforms do not work in Sigrity SI report$ B$ `6 I& U: w" j6 H8 g6 i( `
1752131 CONCEPT_HDL COMP_BROWSER Symbol view in part manager doesn't match the symbol version
' c4 W' F# B; V4 s8 d) t( F' m' r1754116 CONCEPT_HDL COMP_BROWSER Default Symbol selected is n°2 instead of n°1 in component Browser
$ D9 q8 v: r: W [! W0 _# T$ A& a1754949 CONCEPT_HDL COMP_BROWSER Part Information Manager displays preview window with the wrong symbol and missing footprint. P' L! ?" u7 T: {( ? c" x
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic
5 f( y1 d/ m+ @: P" v* p( M1750916 CONCEPT_HDL CORE DE-HDL crashes when trying to uprev a project in release 17.2-20162 F. o% N: h/ q
1711487 CONCEPT_HDL INFRA Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design1 Y& s) [3 Z8 U
1746915 CONSTRAINT_MGR CONCEPT_HDL Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow
6 g; k$ b; d( v6 f3 ~1 b1743523 CONSTRAINT_MGR DATABASE Suppress warning pop-ups from the constraint automation script, q* [: i9 y8 b- b9 [
1746941 CONSTRAINT_MGR UI_FORMS 'Go to Source' from DRC tab is not working in release 17.2-20166 J0 R6 {* K i6 h; {
1753010 ECW METRICS Metrics not getting collected due to old license in use- @' @* x8 G0 d9 m$ \
1713052 FSP GUI Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance8 z$ \' Y; T" n2 T) W- ~
1719099 FSP GUI Net naming wrong after building block; Y! a+ ~9 \ ]6 g" K4 d
1719105 FSP GUI Tabular sorting not working in FPGA System Planner8 M7 r- b* i; {
1720479 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems! _" {2 G( o9 \+ M' W4 \
1723411 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems
0 t9 s0 b/ V1 Q2 V+ S! n1746628 PSPICE ENVIRONMENT PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016
+ X4 L. N. ~( B1 G- F; F1745976 SIG_INTEGRITY GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing7 ?% `# i9 |5 k* v- x2 O ^4 i
1690820 SIP_LAYOUT PLATING_BAR Cannot add fillets to pads with plating bars in release 17.2-2016# Q. Q( {: J, R1 t
1725042 SIP_LAYOUT PLATING_BAR Creating a plating bar removes dynamic fillets; {+ n7 D3 _1 K5 A3 B! M/ A
1747534 SIP_LAYOUT SHAPE Moving fiducial crashes SiP Layout
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发表于 2017-7-2 18:37
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发表于 2019-2-27 16:42