求Cadence SPB16.2 Hotfix

gr1x

9 w0 ^3 p3 A- H6 D4 Y& pTLF有了cadence SPB16.2 Hotfix。但级别太低，老连不上服务器，下不下来。谁有呢？分享一下？？
( U6 @! V, P; j: l7 p) e9 i, F
已上传至Cadence_SPB16.2_by_dzkcool目录下。
20 Dec 2008 SPB16.20.001, Version: SPB:Hotfix:16.20.001~wint
. _  S. A( G* |. m# |; b打了补丁后记得要重新用nolic破解一遍。
- b5 J) b! ?+ ^# _9 [! u2 {! i( ~& V
HOTFIX VERSION:  001
0 U/ h* ?$ Y. J========================================================================================================
+ z! Z  V/ i* L- OCCRID      PRODUCT          PRODUCTLEVEL2        TITLE
========================================================================================================
0 q, M( d/ l' [$ ~) t; Z8 ~191020     allegro_EDITOR   SHAPE                Shape edits results in same net DRC being reported.
230469     ALLEGRO_EDITOR   SHAPE                Allegro improve peRFormance of Dynamic Shapes
295039     ALLEGRO_EDITOR   DFA                  Allegro DFA to be enhanced to include height
, L% e3 F0 e. J! a, @346863     CIS              DESIGN_VARIANT       Variant View mode is not working for multi-section parts
400036     concept_HDL      HPF                  nihongo_vector_font should be listed in the Plot Setup GUI
. O- n8 ?) j- o+ K: C410092     CONCEPT_HDL      OTHER                The Imported sheets loses the write permission for the group
415462     CONCEPT_HDL      MARKERS              The SPB157 Markers does not normally display the Japanese fon
/ D2 \; K- c5 Z6 w2 U501802     ALLEGRO_EDITOR   GRAPHICS             When hilighting parts or nets the system is inconsistent on z
0 v( f; t4 ]" F; y# }5 k$ ?- z8 d503526     SPIF             OTHER                SPIF is NOT defining class for class to class rules.
511175     CONCEPT_HDL      CORE                 Copy All causes - No object selected error
# l# ]6 g5 c, Q4 a526774     LIBRARY          DEVELOPER            Pin抯 text size goes back to default size after change pin na
533536     CONCEPT_HDL      OTHER                The font used in published PDF is not identical.
3 h( U1 \+ S) j1 O2 O( I6 W537769     CONCEPT_HDL      CORE                 Sporadic behavior of DE HDL toolbars for adding components ge
9 v) z* ~  H( O# j8 `% a. b$ ^" j544519     ALLEGRO_EDITOR   mentor               mbs2lib Generating extra "b" version of footprint during tran
551528     LAYOUT           OTHER                Layout2Allegro L2A translator not translating reference desig
551614     SIG_INTEGRITY    IRDROP               Import and export of IR-Drop setup
3 g1 ?" s( u* g" j552127     LIBRARY          LIBUTIL              When -lib is missing from con2con PTF files get re-written in
/ T& ?$ S& X8 t; T5 w" J9 ~6 W/ g4 X560417     ALLEGRO_EDITOR   OTHER                Part Logic does not read part row from ptf file and assign in
564954     CONCEPT_HDL      CREFER               Crefer attaches $XR property to other $XR on RHEL.
* c+ D: m3 U$ b9 v565798     CIS              DESIGN_VARIANT       all the sections of mult part package are not coming as DNS i
7 h1 L' I& }# \. L* j3 \7 g571627     CONCEPT_HDL      CONSTRAINT_MGR       cmuprev fails to synchronize constraints on low assertion vec
577915     CONCEPT_HDL      ARCHIVER             zero folder is not archived how the archiver is working ?
581446     LAYOUT           TRANSLATION          L2A fails with pin numbers do not match between symbols from
583891     ALLEGRO_EDITOR   MENTOR               Mbs2brd will not run with PA5630 license (Allegro PCB SI GXL)
# Q5 V: v/ w& l3 z7 V586998     ALLEGRO_EDITOR   PLOTTING             Board shifts towards top left when plotting at higher resolut
587870     ALLEGRO_EDITOR   PCAD_IN              Import PCAD fails due to dupliate pad name.  Caused by a peri
5 l7 y/ N5 w# W9 ^6 K/ a0 z' n" u588949     CONCEPT_HDL      CORE                 Importing schematic pages from another project crashes Concep
592340     ALLEGRO_EDITOR   MENTOR               MBS2LIB not creating the correct shape in symbol
596530     ALLEGRO_EDITOR   pads_IN              PADS to Allegro Translator removing/renaming reference design
596638     ALLEGRO_EDITOR   EDIT_ETCH            The timing meter indicates untruthful violation
596716     Pspice           DEHDL                Flag error due to part pin mismatch while create netlist
597685     ALLEGRO_EDITOR   SCHEM_FTB            ratnest are out of date error in DBDoctor after import logic
597937     ALLEGRO_EDITOR   PADS_IN              Request PADs_in to translate keepout areas
598575     ALLEGRO_EDITOR   OTHER                During Split plane should it use settings regarding fill styl
$ j" |; E6 t7 m: k598814     APD              WIREBOND             bondfinger does not move relative to its origin using ipick
599823     CONCEPT_HDL      CONSTRAINT_MGR       Lost ref to dml-lib causes loss of cm data even if the refere
599886     APD              EXPORT_DATA          bodygen batch tool is failing to generate .css file
603425     SPECCTRA         PARSER               Do file fails Syntax error in command unexpected end-of-line
603987     APD              OTHER                Offset via generator should ensure pitch distance is met or e
604377     SCM              PACKAGER             Output board name containing a dash causes scm crash
604614     CONSTRAINT_MGR   OTHER                netrev is unable to update the Canonical paths with the new d
604794     ALLEGRO_EDITOR   PAD_EDITOR           Replace Padstack reports error pad missing not true.
605169     ALLEGRO_EDITOR   OTHER                Can design_compare handle swappable pins?
: n  I4 K$ ~% B606586     ALLEGRO_EDITOR   INTERFACES           Multiple drill in padstack cannot be shown in Pro/E IDF
607217     APD              IO_PLANNER           wirebond die replacement from IOP
6 v. k$ t) F9 M0 G0 f! P( j" v' n607222     APD              WIREBOND             auto wirebonding creates wirebond with DRC
607644     ALLEGRO_EDITOR   MANUFACT             Enhancement to increase the IDF export ''default package heig
3 K1 x) Q, `6 E& m607718     CONCEPT_HDL      HDLDIRECT            HDL Direct Errors reported while generating simulation netlis
608233     SIG_INTEGRITY    FIELD_SOLVERS        Convergence errors with analytical vias when drill size is 1
609549     ALLEGRO_EDITOR   INTERACTIV           Mirror Geometry command to change BB Via's layer.
610028     SIP_LAYOUT       IMPORT_DATA          De assign NC nets during aif import
" ?2 `% u, q) Y! d9 R8 z' M8 D610134     CONSTRAINT_MGR   INTERACTIV           Cross-probing from CM to Allegro no longer works on system le
+ O' d0 V' r8 W2 s& J610276     ALLEGRO_EDITOR   PADS_IN              PADS to Allegro translation is failing with error.
6 X4 K4 |) s; Q/ I- H, ^1 ]610482     ALLEGRO_EDITOR   SCHEM_FTB            Netlist swapped net names on 2 pins causing shape to lose its
610681     CONSTRAINT_MGR   DATABASE             An exported constraint file can not be re-imported in V16.01
& ~, q! r9 R# H4 Y611260     ALLEGRO_EDITOR   DRC_CONSTR           Routing a diff pair it does not follow Physical line width se
+ d5 Z, x& C7 {7 q611425     ALLEGRO_EDITOR   MENTOR               mbs2brd crashes when importing Mentor
2 W0 f2 }- o& V. b611697     SIP_FLOW         SIP_LAYOUT           octagonal bumps have offset in SIP compared to the chip view
# ~9 L6 u& k  B$ [- Z+ \0 T611807     APD              WIREBOND             Duplicate paths created on wirebond import for some cases.
! [: @9 ^4 |! X% w' ?, J- v7 t611856     CONCEPT_HDL      GLOBALCHANGE         Ref des deletions after runnning Global Change to change $LOC
611874     CONCEPT_HDL      OTHER                Crossprobing one symbol in Concept using Occurence edit mode
! i. ?2 u/ X: H* z  B; W  N* _6 j612088     PSPICE           DEHDL_NETLISTER      Fail to create the netlist for G value expression
4 C4 y, ]/ _/ L) x% s612195     ALLEGRO_EDITOR   DATABASE             Adding layers to the default cross section causes phantom tex
612237     ALLEGRO_EDITOR   skill                axlFormColorize does not change the full background area of a
& A5 n. y+ L% p- M612299     APD              DEGASSING            Degassing static shape creates voids inside of voided areas
612560     CONSTRAINT_MGR   OTHER                Diffpairs don't show the CSet assigned through Net Class
612587     APD              WIREBOND             Unchecked Allow DRC option creating disconnected wire bond.
7 k& ?2 P- u, ?1 t612884     SIG_INTEGRITY    SIMULATION           When using ViaModel
" x1 O; a1 D$ F( I612914     ALLEGRO_EDITOR   EDIT_ETCH            Centered via option in fanout command not available when swit
6 x5 B5 g: Y- l5 u, a/ v& P612939     SIP_LAYOUT       ASSY_RULE_CHECK      ADRC Continuous Solder Mask check problem
613553     CONCEPT_HDL      EDIF300              edif schematic writer crash on this design
, j1 [- h3 s) u$ ~! y; [613565     ALLEGRO_EDITOR   EDIT_ETCH            Allegro Editor Differential Pairs are routing incorrectly
" y/ l+ B6 J8 t5 S/ p9 x/ w/ K613736     SPIF             OTHER                Spif fails to write class data
/ C6 e4 n! x: g* m6 |  q613990     POWER_INTEGRIT   INTERACTIV           PI is crashing during capacitor selection
614278     CONCEPT_HDL      EDIF300              pin text note and flag are not visible on reloaded edif file
- U( }* ?: ]7 M3 Y# j. Z4 z4 P614371     SIP_LAYOUT       WIREBOND             Any wirebond command crashes the application
$ X8 d& F& c" A0 F6 Q614407     POWER_INTEGRIT   INTERACTIV           PI crashes when editing capacitors
/ B! H; @) e! O614727     SPECCTRA         GUI                  Allegro PCB Router can not process the dsn and rules file for
+ ?0 _, s4 c5 \% H0 f8 Q7 Y614972     ALLEGRO_EDITOR   SKILL                axlCNSSetSpacing does not change the value of the "testvia to
615144     SIP_LAYOUT       3D_VIEWER            die placement does not change with changing in soldermask thi
/ _4 i' d' {2 Q2 ?6 d615431     LAYOUT           TRANSLATORS          padstack names are crippled or renamed if it has over 18 Char
615506     APD              MANUFACTURING        Sort by die pin location for Manufacture Doc Bond finger brok
/ _! h: Q2 U1 a! y' \615745     SIP_LAYOUT       DATABASE             Move die symbol with stretch etch on is disconnecting wires f
615816     SPIF             OTHER                Allegro match group members not translating to PCB Router; mi
; s/ D5 E1 j/ q616104     CONSTRAINT_MGR   OTHER                allegroTechnologyFile XML format issue
7 H% E3 |; G& c+ f' E; i) c616122     LAYOUT           TRANSLATORS          protel to MAX translator problem with package outlines and re
616404     ALLEGRO_EDITOR   OTHER                Design compare fails with message "Invalid input argument" wh
# o* X3 @7 p5 [# F+ F  w/ ^616713     CIS              PLACE_DATABASE_PAR   property name with "&" charecter in access database causing c
616818     SCM              PACKAGER             BOMHDL -type scm fails on schematic block
616907     SCM              VERILOG_IMPORT       scm crash during Get Module Name
617058     APD              WIREBOND             wirebond space evenly does not work for fingers on power ring
- }. B/ T1 n6 a0 K617083     ALLEGRO_EDITOR   INTERACTIV           Windows tabs hangs on Linux
4 q  K: b! J5 _1 a617236     ALLEGRO_EDITOR   SHAPE                Editing a shape in a void causes the bigger shape to drop seg
617351     CIS              DBC_CFG_WIZARD       XML writer fails if DBC location doesnt have write permission
4 F& ]# e3 v5 C' m: f( S- c617515     SIP_LAYOUT       OTHER                Be able to invoke Velocity from cdnsip
( R2 |- s% n8 _, ~617761     LAYOUT           TRANSLATORS          Value property for Library symbol of orcad Layout is not tran
617890     SIP_LAYOUT       WIREBOND             Push and shove on Bond fingers with multiple bond wires cause
9 R  o" c% D4 _2 K6 k618184     APD              OTHER                database diary on unix/linux
2 S8 y. b3 a3 C4 ^" }0 L618201     ALLEGRO_EDITOR   OTHER                Dynamic fillets take a long time to complete
618545     ALLEGRO_EDITOR   INTERACTIV           Allegro crashes when we place a package symbol for Jumper usi
, v: a: U7 z! ~" u- y- _8 D8 Q, Z618610     ALLEGRO_EDITOR   MANUFACT             Delete a cline seg creates a fillet
618651     SIP_LAYOUT       IO_PLANNER           Bondfingers and die are shifted every time an update package
618712     ALLEGRO_EDITOR   EDIT_ETCH            Shove mode is not working on Diff pairs in PCB Design L
5 R9 D$ O# T6 h7 K6 Y/ ]618836     ALLEGRO_EDITOR   SCRIPTS              Allegro does not interpret recorded macro script files proper
3 c' I/ x5 Y3 C' Y8 t* j618946     ALLEGRO_EDITOR   INTERACTIV           Allegro crashes while using Place Manual -H
618984     ALLEGRO_EDITOR   COLOR                Layers on Allegro Canvas does not match Color Dialog Box
619007     ALLEGRO_EDITOR   SKILL                Skill command does not accept spaces in file path/name
8 f6 Z" B& Q* R+ T1 q619033     F2B              PACKAGERXL           Pinswap lost on backannotation
3 G! n$ E' ?# ?! _' \619268     POWER_INTEGRIT   SIMULATION           IR-Drop can't sees via on pad as open
619356     CIS              FOOTPRINT_VIEW       Footprint preview only from 1 directory in Capture.INI
- K; ^1 _7 ?' B619712     ALLEGRO_EDITOR   EDIT_ETCH            Unable to route in the Bubble Mode for Partitioned board
- }* @) o! F  e5 |0 C4 l619773     ALLEGRO_EDITOR   DATABASE             Uprev for 13.6 and 14.0 files not working with SPB 16.2 on Wi
620064     CONCEPT_HDL      CONSTRAINT_MGR       Loosing Diff pair constraints from lower blocks when packagin
622132     CAPTURE          NETLIST_ALLEGRO      Incorrect ALG0078 error for complex hierarchical design

gr1x

原帖由 jxnfhyz 于 2008-12-30 10:32 发表
TLF是什么哦,是不是指在FTP上啊!

www.eastgame.net

touhou

下到了SPB16.2 Hotfix的人路过

轩辕浪

软件还没出来几天，补丁就下来了？、、

zxfeng

分流
Hotfix_SPB16.20.001_wint_1of1.exe (243.01 MB)

gr1x

原帖由 zxfeng 于 2008-12-30 15:40 发表
% x( h3 e0 E4 C6 I分流
+ m- e* J! N0 c4 ~Hotfix_SPB16.20.001_wint_1of1.exe (243.01 MB)

: y) G" s9 ~" X( x$ p1 r+ M& v开了2天电脑，就下了30多k，谁能提供下载呢？

wanghanq

原帖由 jxnfhyz 于 2008-12-30 10:32 发表
TLF是什么哦,是不是指在FTP上啊!

看下面链接，你就知道了，里面的资源太多了：
. F( F7 A5 t& ~5 J" H

http://www3.eastgame.net/index.php

zxfeng

开了2天电脑，就下了30多k，谁能提供下载呢？
1 s8 ?4 k9 t* R4 d5 Y8 M- z$ zgr1x 发表于 2008-12-31 20:45

3 P$ O* P& t7 T: b我看到至少有三个人完成下载了，emule下载需要耐心.

rx_78gp02a

下载了的可以用qq或者是邮箱传一下的嘛！速度很快的，今天误删了license server 重新安装上去就不能用了

zhuyt05

我看到至少有三个人完成下载了，emule下载需要耐心.
  K$ F& P' }& j7 O  A' uzxfeng 发表于 2009-1-3 15:32

& V$ `& C: M: z! o1 b3 J这三个人中有一个是我，改天帮助大家加速

zlei

我就是在tlf的S15服务器下的。

DANYEHUA

DDD