C@dence.SPB16.20.winnt.Hotfix.001和002所更新的内容

zlei

HOTFIX VERSION:  002
, N* ~3 y) T2 L! w========================================================================================================
: |7 Y& Q% u, TCCRID      PRODUCT          PRODUCTLEVEL2        TITLE
# p9 U  O+ v  x5 T- d: P8 b: P========================================================================================================
511865     SPECCTRA         REGIONS              Diff pairs should adhere to constraint area
564589     allegro_EDITOR   OTHER                The show measure command should show the actually measured po
570861     concept_HDL      CORE                 Unconnected mark does not be removed even after wire is conne
572188     APD              PAKSI_E              3-D model extract failed
578164     CONCEPT_HDL      skill                Cnskill crash during Create Test Schematic step when large pi
& p+ q7 k" J7 ]' o, p578874     SIP_LAYOUT       DIE_STACK_EDITOR     Stackup editor in SiP fails to add layers above and below top
580315     APD              ETCH_BACK            Etchback trace fails with error "W- An etch-back trace cannot
582308     ALLEGRO_EDITOR   OTHER                Create Detail for bondpads rotated at (0,90,180 and 270) angl
594370     SIG_INTEGRITY    OTHER                Wrong description in case update form when changing preferenc
595755     CONCEPT_HDL      CORE                 Rumtime error happen when do Move Group in conceptHDL
6 {4 |; _  ?7 r0 u! H$ Q- t597922     SIG_INTEGRITY    TRANSLATOR           spc2spc doesn not handle inline RLGC DATAPOINTS
( j' O. v$ \4 B606620     ASSURA           DRC                  Problem with density checks in Assura
609866     SCM              SCHGEN               Schgen replaces CTAP with COMMENT symbol which causes net sho
( Z2 ~* e5 s, ], ~) ?2 F* W' u611678     ALLEGRO_EDITOR   GRAPHICS             During Place > Manual Pins disapear if component is on bottom
  f* s0 E+ B: k  ?: R+ g615630     ALLEGRO_EDITOR   GRAPHICS             Pins are not visible when place manually is used for Bottom s
6 R0 x* f+ P+ c) R3 z2 t: ^) y615764     CONSTRAINT_MGR   TDD                  BOM report does not filter parts with BOM_IGNORE
" y8 o% U+ T4 C" i7 k616529     CONCEPT_HDL      CORE                 15.7 Design Entry HDL fails with Out of Memory message
% b/ w2 J0 B9 C% S- x2 P616928     CONCEPT_HDL      CONSTRAINT_MGR       Net_physical_type and net_spacing _type constraints not sync'
617441     SIG_INTEGRITY    FIELD_SOLVERS        Reflection simulation fails when using wideband vias
617679     ALLEGRO_EDITOR   COLOR                The color palette will not be saved with the design unless co
4 h  b3 ]$ t# w; i; i3 @617805     CIS              PART_MANAGER         Capture_crash
618988     ALLEGRO_EDITOR   SCHEM_FTB            Long bus names being truncated
619588     APD              EDIT_ETCH            Poor routing peRFormance. 5 second delay after each mouse cli
& `- t8 m, r8 Z1 Q9 R" k619691     SIG_INTEGRITY    FIELD_SOLVERS        Problem of EMS2D by using FreqDepFile
. M% l+ a% }- D& a619867     ALLEGRO_EDITOR   DFA                  DFA_BOUND_TOP shape doesn't display DFA Audit conflicts
620359     CONSTRAINT_MGR   CONCEPT_HDL          ECSet and Netclass definitions lost in the FTB process
620424     CONCEPT_HDL      CONSTRAINT_MGR       CM restore from definition of subblock removes ECSets defined
1 i' v$ j1 V, A/ v2 `& e620700     ALLEGRO_EDITOR   PAD_EDITOR           Shape has bigger void on Y direction for Oblong SMD Pads
0 }. r) A5 u7 \( j. `! G& U2 m620868     SIG_INTEGRITY    PAKSI_E              Wirebond material conductivity is not used by PakSI, only a d
620895     ALLEGRO_EDITOR   DRC_CONSTR           About error message of cns_design command.
/ F; E% b0 @$ D2 P, R2 v620924     CONCEPT_HDL      OTHER                PDF Publisher 16.1/16.2 can not output some Japanese characte
621156     SIP_LAYOUT       ASSY_RULE_CHECK      ADRC Rule for 揟race Minimum Angle to Pad?not showing all th
621163     SIP_LAYOUT       ASSY_RULE_CHECK      Ambiguity about the how is the 搒tart of the wire" defined in
; l  n8 Y9 g+ G% [% s/ C3 z- i621298     CONSTRAINT_MGR   UI_FORMS             PCB SI crashes when importing a constraint file into Constrai
621315     ALLEGRO_EDITOR   PLACEMENT            Getting wrong component when using Place replicate unmatched
621848     CONSTRAINT_MGR   TECHFILE             techfile write fails with Failed writing object attributes
' Y- A# e* I* X3 G" D% |! ]621867     ALLEGRO_EDITOR   TESTPREP             Transcript window randomly locks up when running TestPrep
% M4 K! A7 r4 [2 R621901     SIG_INTEGRITY    OTHER                Incorrect extracted via drill/pad diameters and missing inter
622010     ALLEGRO_EDITOR   DATABASE             Undesired openings in Negative shape
7 j- k9 n$ ?3 @- l% S. F% h% ^3 a622062     CONSTRAINT_MGR   DATABASE             Importing dcf file at system level crashing the Allegro PCB e
622156     ALLEGRO_EDITOR   SHAPE                Thermal/Anti value producing incorrect void sizes
; W8 Q2 i& R  g, g622450     SIG_INTEGRITY    SIMULATION           Field solution failed
' Z6 N- H4 N: [- E; k; {- t$ h622466     ALLEGRO_EDITOR   COLOR                layer priority in 16.2
; ?8 e( \) p6 ?6 Z2 ?# t6 i622566     ALLEGRO_EDITOR   SCHEM_FTB            Replacing the components of same refdes on board after import
622700     APD              PLATING_BAR          Plating Bar Check is highlighting Nets that appear to be conn
622862     ALLEGRO_EDITOR   ARTWORK              Allegro crashes when we enter a value in the field file size
622989     SIP_LAYOUT       IMPORT_DATA          Type of Wirebond die changed after die import
623182     SIG_INTEGRITY    FIELD_SOLVERS        Extract topology crashed
623300     SIP_LAYOUT       3D_VIEWER            Wrong placement of Solder Mask Bottom in 3D view file
623384     ALLEGRO_EDITOR   VALOR                Valor output showing padstacks on 45 degree angle wrong in 16
0 U1 q' N/ g- J4 H: s1 U# e7 Z6 S! A623489     ALLEGRO_EDITOR   EXTRACT              Allegro tools Report etch length by pin pair takes forever to
623529     ALLEGRO_EDITOR   EDIT_ETCH            Manual tandem diff pair routing has been lost in the 16.2 rel
. H$ l/ Q6 G1 U* P% {623536     F2B              PACKAGERXL           packager fails with memory allocation error
+ t- B8 ~' }, G6 r' }! t* d623673     CAPTURE          OTHER                Unable to get capture window size to full-screen in dual disp
623701     ALLEGRO_EDITOR   OTHER                'Analyze' menu missing when opening Allegro PCB Editor L - Pe
623738     CAPTURE          PART_EDITOR          Create part from spreadsheet is not working correctly
2 ^, r' v9 t+ D0 t+ T3 t3 k623740     ALLEGRO_EDITOR   OTHER                Can we use variant.lst file as list file in find filter
7 S3 t# \6 S# L2 M; v9 S- n623745     CAPTURE          OTHER                Capture crashes when the user tries to place markers
3 {9 s) D! m+ B' O623813     SIP_LAYOUT       WIREBOND             Add wirerbond only is not working in this case with a bondfin
& t& M+ `% C5 w2 K# R7 x623830     ALLEGRO_EDITOR   MANUFACT             backdrilling is drilling through component pads on the bottom
624048     ALLEGRO_EDITOR   OTHER                Viewlog for Export to 16.01 is not closing from any of the 'C
' z6 @& k: M* E4 B0 K5 n+ G624223     ALLEGRO_EDITOR   GRAPHICS             disable_datatips variable is busted
624495     ALLEGRO_EDITOR   SHAPE                Static shape did not void to drill holes
* k6 }) c: O! S, [  l; k' l624599     SPECCTRA         ROUTE                PCB Router hangs on route of design
, v: A$ p$ D- f5 E624653     APD              BGA_GENERATOR        BGA Generator fails at 400um pitch
624812     CONSTRAINT_MGR   ANALYSIS             Importing dcf at the system level causes RPD constraints not
( N# i* h# g( M0 Y9 G624888     ALLEGRO_EDITOR   DRC_CONSTR           Regions and RCI's Cset not working as expected
3 s/ t" Q  N3 F8 A4 `8 k8 A624958     ALLEGRO_EDITOR   EDIT_ETCH            Slide in region is changing etch to min line width
- h3 S1 |& s4 r5 E3 \625251     ALLEGRO_EDITOR   COLOR                16.2 Linux allegro - new subclass created does not reflect in
625273     APD              IMPORT_DATA          Import a .mcm into SIP in order to edit the die pins. Edit ->
625279     APD              DIE_EDITOR           die text in fails when the function name is >31 characters wi
, j, e$ H! L; ?$ v9 K625304     SIG_INTEGRITY    IRDROP               Need a better understanding of absolute current values report
$ p8 g4 A0 E8 H% ~5 K" ^" e2 P+ B$ o0 b625367     ALLEGRO_EDITOR   DRC_CONSTR           drc_fillet_samenet does not work correctly
9 U9 g2 v6 N3 Q) I1 ^! P/ W625551     ALLEGRO_EDITOR   SHAPE                Dynamic shape is not voiding to route keepout correctly
3 l' {# M; P' u. B2 n9 H  \  S625852     ALLEGRO_EDITOR   DRC_CONSTR           Some buses in CM are disappeared after import CIS 3 .dat netl
625885     CAPTURE          DRC                  Report misleading Tap connections check for DRC reports error
625972     CONSTRAINT_MGR   TECHFILE             techfile import fails with Failed writing object attributes
0 _$ g( G! @  ^$ R* q% l626630     CAPTURE          NETLIST_ALLEGRO      Capture 16.20 hangs endlessly but Capture 16.0 prompts result
626669     SIP_LAYOUT       OTHER                16.2 radial router find filter does not have option for bond
* |0 d. d- E* _: e1 ?5 v9 ~$ @626671     SCM              OTHER                Adding signals in ASA is taking too long
  `2 d! I9 w/ L9 _627228     ALLEGRO_EDITOR   MANUFACT             Dynamic Fillet is disappered, when use slide command.
% r  p$ w% i2 y9 \627289     SIP_LAYOUT       DIE_GENERATOR        Pins connect at the same net name after Die Text In
6 Q9 \! j+ {3 q+ I% k8 w0 v) F% U* z627864     CONCEPT_HDL      EDIF300              EDIF c2esch crashes
628169     ALLEGRO_EDITOR   OTHER                write command changes design name in constraint manager
628220     SIG_INTEGRITY    SIMULATION           Reflection simulation failed with filed solver "EMS2D"
8 E( J/ Q+ y6 R$ x628261     APD              OTHER                no "Tangent Via Line Fattening" in APD products
628922     APD              REPORTS              Metal Area Report shows 0.00 on one layer
  P) n( u- E$ hHOTFIX VERSION:  001
========================================================================================================
CCRID      PRODUCT          PRODUCTLEVEL2        TITLE
========================================================================================================
% M3 U! m! {6 i3 Z+ |" }1 p191020     ALLEGRO_EDITOR   SHAPE                Shape edits results in same net DRC being reported.
230469     ALLEGRO_EDITOR   SHAPE                Allegro improve performance of Dynamic Shapes
295039     ALLEGRO_EDITOR   DFA                  Allegro DFA to be enhanced to include height
346863     CIS              DESIGN_VARIANT       Variant View mode is not working for multi-section parts
400036     CONCEPT_HDL      HPF                  nihongo_vector_font should be listed in the Plot Setup GUI
410092     CONCEPT_HDL      OTHER                The Imported sheets loses the write permission for the group
415462     CONCEPT_HDL      MARKERS              The SPB157 Markers does not normally display the Japanese fon
6 K; ^' b! I0 ^- o; p501802     ALLEGRO_EDITOR   GRAPHICS             When hilighting parts or nets the system is inconsistent on z
4 |' Q( U8 X% j7 s# f6 ?+ v2 I503526     SPIF             OTHER                SPIF is NOT defining class for class to class rules.
511175     CONCEPT_HDL      CORE                 Copy All causes - No object selected error
526774     LIBRARY          DEVELOPER            Pin抯 text size goes back to default size after change pin na
7 `& f; n6 Z) J2 ?533536     CONCEPT_HDL      OTHER                The font used in published PDF is not identical.
537769     CONCEPT_HDL      CORE                 Sporadic behavior of DE HDL toolbars for adding components ge
" R& g, H. l" M) ^544519     ALLEGRO_EDITOR   mentor               mbs2lib Generating extra "b" version of footprint during tran
) a- G3 O  C- I, f1 u: E! `551528     LAYOUT           OTHER                Layout2Allegro L2A translator not translating reference desig
! Z2 }- X( X. U* Z551614     SIG_INTEGRITY    IRDROP               Import and export of IR-Drop setup
( }5 D% f# y+ u6 {2 {( U  r4 b552127     LIBRARY          LIBUTIL              When -lib is missing from con2con PTF files get re-written in
5 V. L( G. t6 i) V560417     ALLEGRO_EDITOR   OTHER                Part Logic does not read part row from ptf file and assign in
564954     CONCEPT_HDL      CREFER               Crefer attaches $XR property to other $XR on RHEL.
7 }2 a3 e1 e5 R% z) E565798     CIS              DESIGN_VARIANT       all the sections of mult part package are not coming as DNS i
1 |/ F, m4 J& O571627     CONCEPT_HDL      CONSTRAINT_MGR       cmuprev fails to synchronize constraints on low assertion vec
( z) b% ~: I: v* a* Y0 t0 I% B577915     CONCEPT_HDL      ARCHIVER             zero folder is not archived how the archiver is working ?
581446     LAYOUT           TRANSLATION          L2A fails with pin numbers do not match between symbols from
583891     ALLEGRO_EDITOR   MENTOR               Mbs2brd will not run with PA5630 license (Allegro PCB SI GXL)
586998     ALLEGRO_EDITOR   PLOTTING             Board shifts towards top left when plotting at higher resolut
% J) M/ ~0 E3 w' L# [* n2 \$ S7 ~587870     ALLEGRO_EDITOR   PCAD_IN              Import PCAD fails due to dupliate pad name.  Caused by a peri
588949     CONCEPT_HDL      CORE                 Importing schematic pages from another project crashes Concep
: i  L$ L  g" [% y592340     ALLEGRO_EDITOR   MENTOR               MBS2LIB not creating the correct shape in symbol
2 B0 }6 Q) V& ^" D+ Z2 X7 t596530     ALLEGRO_EDITOR   PADS_IN              PADS to Allegro Translator removing/renaming reference design
9 k2 R; ?: G, i  }, v4 R/ L596638     ALLEGRO_EDITOR   EDIT_ETCH            The timing meter indicates untruthful violation
, N  t6 S! g: ~/ G" u- S596716     Pspice           DEHDL                Flag error due to part pin mismatch while create netlist
, b' {# Y3 {( k* V( l8 {$ w597685     ALLEGRO_EDITOR   SCHEM_FTB            ratnest are out of date error in DBDoctor after import logic
7 A" ^5 z& P" u) f0 J! F597937     ALLEGRO_EDITOR   PADS_IN              Request PADs_in to translate keepout areas
598575     ALLEGRO_EDITOR   OTHER                During Split plane should it use settings regarding fill styl
598814     APD              WIREBOND             bondfinger does not move relative to its origin using ipick
6 ]3 k) G# c$ x8 b; K% N599823     CONCEPT_HDL      CONSTRAINT_MGR       Lost ref to dml-lib causes loss of cm data even if the refere
/ M; f/ T1 U" c599886     APD              EXPORT_DATA          bodygen batch tool is failing to generate .css file
5 z+ F4 e* O" x/ ]9 k603425     SPECCTRA         PARSER               Do file fails Syntax error in command unexpected end-of-line
. Y+ z1 Y3 [8 P; d603987     APD              OTHER                Offset via generator should ensure pitch distance is met or e
604377     SCM              PACKAGER             Output board name containing a dash causes scm crash
2 ~/ E- q& R% n8 j6 z: M604614     CONSTRAINT_MGR   OTHER                netrev is unable to update the Canonical paths with the new d
604794     ALLEGRO_EDITOR   PAD_EDITOR           Replace Padstack reports error pad missing not true.
, u9 _0 [- l: {& W605169     ALLEGRO_EDITOR   OTHER                Can design_compare handle swappable pins?
606586     ALLEGRO_EDITOR   INTERFACES           Multiple drill in padstack cannot be shown in Pro/E IDF
1 A& ?" Q, p1 S$ `. G607217     APD              IO_PLANNER           wirebond die replacement from IOP
607222     APD              WIREBOND             auto wirebonding creates wirebond with DRC
607644     ALLEGRO_EDITOR   MANUFACT             Enhancement to increase the IDF export ''default package heig
, M' Q7 ?; {# A" ~607718     CONCEPT_HDL      HDLDIRECT            HDL Direct Errors reported while generating simulation netlis
608233     SIG_INTEGRITY    FIELD_SOLVERS        Convergence errors with analytical vias when drill size is 1
609549     ALLEGRO_EDITOR   INTERACTIV           Mirror Geometry command to change BB Via's layer.
" @" q+ g7 E8 m610028     SIP_LAYOUT       IMPORT_DATA          De assign NC nets during aif import
% a8 c! h! r$ s0 Q610134     CONSTRAINT_MGR   INTERACTIV           Cross-probing from CM to Allegro no longer works on system le
610276     ALLEGRO_EDITOR   PADS_IN              PADS to Allegro translation is failing with error.
, S1 h' l1 L, q. x: s610482     ALLEGRO_EDITOR   SCHEM_FTB            Netlist swapped net names on 2 pins causing shape to lose its
610681     CONSTRAINT_MGR   DATABASE             An exported constraint file can not be re-imported in V16.01
4 M" k1 \! A% U; ?% D" V611260     ALLEGRO_EDITOR   DRC_CONSTR           Routing a diff pair it does not follow Physical line width se
1 S1 S- l0 ?$ a8 f611425     ALLEGRO_EDITOR   MENTOR               mbs2brd crashes when importing Mentor
611697     SIP_FLOW         SIP_LAYOUT           octagonal bumps have offset in SIP compared to the chip view
611807     APD              WIREBOND             Duplicate paths created on wirebond import for some cases.
. t" A. ?' [  g$ \4 ?611856     CONCEPT_HDL      GLOBALCHANGE         Ref des deletions after runnning Global Change to change $LOC
611874     CONCEPT_HDL      OTHER                Crossprobing one symbol in Concept using Occurence edit mode
612088     PSPICE           DEHDL_NETLISTER      Fail to create the netlist for G value expression
- V# X! s+ \) U8 A6 h6 G) p612195     ALLEGRO_EDITOR   DATABASE             Adding layers to the default cross section causes phantom tex
. Y" p# ~. Q2 _/ O612237     ALLEGRO_EDITOR   SKILL                axlFormColorize does not change the full background area of a
5 ~- b0 l. A. J2 N612299     APD              DEGASSING            Degassing static shape creates voids inside of voided areas
612560     CONSTRAINT_MGR   OTHER                Diffpairs don't show the CSet assigned through Net Class
! v& U: {1 k( Z- R# R612587     APD              WIREBOND             Unchecked Allow DRC option creating disconnected wire bond.
612884     SIG_INTEGRITY    SIMULATION           When using ViaModel
2 o" c. H" Y$ H" H612914     ALLEGRO_EDITOR   EDIT_ETCH            Centered via option in fanout command not available when swit
' j" j8 _& ?' F612939     SIP_LAYOUT       ASSY_RULE_CHECK      ADRC Continuous Solder Mask check problem
& |, Z3 b& ^# K" a. h9 b613553     CONCEPT_HDL      EDIF300              edif schematic writer crash on this design
  G6 b5 r! ?0 g4 p( G2 L613565     ALLEGRO_EDITOR   EDIT_ETCH            Allegro Editor Differential Pairs are routing incorrectly
) b6 m2 l2 v( m613736     SPIF             OTHER                Spif fails to write class data
( x5 C" N7 A9 V( Y; V613990     POWER_INTEGRIT   INTERACTIV           PI is crashing during capacitor selection
614278     CONCEPT_HDL      EDIF300              pin text note and flag are not visible on reloaded edif file
5 Q2 D2 q+ M/ C/ m; s614371     SIP_LAYOUT       WIREBOND             Any wirebond command crashes the application
7 Q* b2 c& F+ _+ m/ M8 d8 Y614407     POWER_INTEGRIT   INTERACTIV           PI crashes when editing capacitors
0 I. j+ K& ^% a! t2 p3 t614727     SPECCTRA         GUI                  Allegro PCB Router can not process the dsn and rules file for
4 z1 X5 _5 o6 t" ?8 y- ^: x) Q6 M614972     ALLEGRO_EDITOR   SKILL                axlCNSSetSpacing does not change the value of the "testvia to
. Q$ Q+ p3 m3 J$ `# w) z615144     SIP_LAYOUT       3D_VIEWER            die placement does not change with changing in soldermask thi
: I  y0 q4 l  {$ D( ~3 i615431     LAYOUT           TRANSLATORS          padstack names are crippled or renamed if it has over 18 Char
615506     APD              MANUFACTURING        Sort by die pin location for Manufacture Doc Bond finger brok
  i& M/ E) s6 b% k' G6 c615745     SIP_LAYOUT       DATABASE             Move die symbol with stretch etch on is disconnecting wires f
* z& A# I2 k( f& r) W% }, ~615816     SPIF             OTHER                Allegro match group members not translating to PCB Router; mi
616104     CONSTRAINT_MGR   OTHER                allegroTechnologyFile XML format issue
616122     LAYOUT           TRANSLATORS          protel to MAX translator problem with package outlines and re
) C' @9 C/ D5 C( z$ c1 a4 F$ Q616404     ALLEGRO_EDITOR   OTHER                Design compare fails with message "Invalid input argument" wh
# w% m4 `. W8 G( F, M5 q616713     CIS              PLACE_DATABASE_PAR   property name with "&" charecter in access database causing c
: h2 g( z. e) |! U3 y616818     SCM              PACKAGER             BOMHDL -type scm fails on schematic block
616907     SCM              VERILOG_IMPORT       scm crash during Get Module Name
- w2 q3 x- \; a; b; r2 B4 R617058     APD              WIREBOND             wirebond space evenly does not work for fingers on power ring
617083     ALLEGRO_EDITOR   INTERACTIV           Windows tabs hangs on Linux
617236     ALLEGRO_EDITOR   SHAPE                Editing a shape in a void causes the bigger shape to drop seg
! _; O! k1 f2 v# H617351     CIS              DBC_CFG_WIZARD       XML writer fails if DBC location doesnt have write permission
8 |2 {  ^' h; E617515     SIP_LAYOUT       OTHER                Be able to invoke Velocity from cdnsip
617761     LAYOUT           TRANSLATORS          Value property for Library symbol of orcad Layout is not tran
  l- x! V( w$ p  ~; I9 T617890     SIP_LAYOUT       WIREBOND             Push and shove on Bond fingers with multiple bond wires cause
618184     APD              OTHER                database diary on unix/linux
8 `3 s* z/ n0 ^4 p, I4 G618201     ALLEGRO_EDITOR   OTHER                Dynamic fillets take a long time to complete
, i2 L8 Z% T0 {% S; v- i618545     ALLEGRO_EDITOR   INTERACTIV           Allegro crashes when we place a package symbol for Jumper usi
- w" I) B* N$ g& Z) H618610     ALLEGRO_EDITOR   MANUFACT             Delete a cline seg creates a fillet
' i" @, d, x. i$ J4 U1 g618651     SIP_LAYOUT       IO_PLANNER           Bondfingers and die are shifted every time an update package
618712     ALLEGRO_EDITOR   EDIT_ETCH            Shove mode is not working on Diff pairs in PCB Design L
618836     ALLEGRO_EDITOR   SCRIPTS              Allegro does not interpret recorded macro script files proper
618946     ALLEGRO_EDITOR   INTERACTIV           Allegro crashes while using Place Manual -H
+ ]" V$ x7 d3 T. g7 w0 p. ^8 ?618984     ALLEGRO_EDITOR   COLOR                Layers on Allegro Canvas does not match Color Dialog Box
! I, d2 r2 I" e. z/ v3 ?- q! S; `619007     ALLEGRO_EDITOR   SKILL                Skill command does not accept spaces in file path/name
# F, ?# J* E' f. G' H619033     F2B              PACKAGERXL           Pinswap lost on backannotation
619268     POWER_INTEGRIT   SIMULATION           IR-Drop can't sees via on pad as open
- c5 u& `% \. Y0 X619356     CIS              FOOTPRINT_VIEW       Footprint preview only from 1 directory in Capture.INI
619712     ALLEGRO_EDITOR   EDIT_ETCH            Unable to route in the Bubble Mode for Partitioned board
619773     ALLEGRO_EDITOR   DATABASE             Uprev for 13.6 and 14.0 files not working with SPB 16.2 on Wi
620064     CONCEPT_HDL      CONSTRAINT_MGR       Loosing Diff pair constraints from lower blocks when packagin
( p8 g* X) p1 Z% Q0 m8 B  t622132     CAPTURE          NETLIST_ALLEGRO      Incorrect ALG0078 error for complex hierarchical design