hsipce 不收敛的解决

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解决spice在tran时的internal timestep too small问题的方法
Transient Analysis: 也就是一般的暂态分析.一般错误的
Message 为:-"Internal timestep too small."
另外,也会常看到 "Singular Matrix", or "Gmin/Source Stepping
4 e8 i9 P8 }9 }# }8 Z" sFailed" 这样的 Error Message.解决这个问题没有一定的方法,根
# R4 p2 ?6 j0 n& w5 \1 r据我们的经验,我们大致把它们说明如後:
1. 电路错误:指的是由使用者本身电路,有不正常的接线或短路等,例如将电源
* d# K! @6 X, G8 o" i  y+ d  G接到输出端,而造成SPICE在运算的时候无法收敛.根据Ref[38] 的建议,请
& P$ [" @0 m* p( r6 d你确认以下之状况:
- y# X6 a6 N' p" f) p) x+ h) YMake sure that all of the circuit connections are valid. Check for
incorrect node numbering or dangling nodes. Also, verify component
polarity.
Make sure you didn't use the letter O instead of a zero (0).
7 V" U/ g* I, i( k- jCheck for syntax mistakes. Make sure that you used the correct SPICE
units (i.e. MEG instead of M(milli) for 1E6).
+ q+ \+ K+ N3 y5 k8 uMake sure that there's a DC path from every node to ground.
( P( A& ?0 e0 P8 ZMake sure that there are at least two connections at every node.
; ?2 F' D7 m$ j' DMake sure that there are no loops of inductors or voltage sources.
  K- ~6 c3 U% gMake sure that there are no series capacitors or current sources.
Place the ground (node 0) somewhere in the circuit. Be careful when
you use floating grounds; you may need to connect a large resistor from
1 [7 X" r& k  pthe floating node to ground.
6 [) v0 {4 f( g: KMake sure that voltage/current generators use realistic values, and
* _! g. S6 G5 ~3 x- Sverify that the syntax is correct.
9-46 VLSI 设计概论 / 实习
: J3 B6 a. m' A2 A/ j' L5 l7 F" ]# qMake sure that dependent source gains are correct, and that B element
5 j! Q. I& g7 X* O5 Y$ zexpressions are reasonable. If you are using division in an expression,
; D( f7 h8 s6 w, b- z# P& Bverify that division by zero cannot occur.
Make sure that there are no unrealistic model parameters; especially if
you have manually entered the model into the netlist.
Make sure that all resistors have a value. In SPICE 3, resistors without
$ _6 s" t; }9 S) c6 Xvalues are given a default value of 1k Ohm.
Negative capacitor and inductor values are allowed in SPICE 3. They
+ Q& d2 Q$ {$ U! w& o3 qwill not be flagged as an error, but can cause timestep problems,
depending on the topology of the circuit.
2. 检查Feedback : 所指的是在序向逻辑电路中所产生的,你可以检查一下你的
电路的FeedBack Path的Delay,在不影响电路功能的情形下,是否可以调快一
' M! B& P4 U* X( ~  t点或慢一点.
3 x: ?( c2 t( Z# {0 O

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wu68aq

谢谢分享

lxuande

好好学习，天天向上。