hsipce 不收敛的解决

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解决spice在tran时的internal timestep too small问题的方法
Transient Analysis: 也就是一般的暂态分析.一般错误的
6 F* b/ B# D/ e$ aMessage 为:-"Internal timestep too small."
; ]* v' j8 S/ U7 ^4 |, n另外,也会常看到 "Singular Matrix", or "Gmin/Source Stepping
6 K" h. l3 T: Z. q# H/ eFailed" 这样的 Error Message.解决这个问题没有一定的方法,根
据我们的经验,我们大致把它们说明如後:
& _+ b* R# x2 X9 y6 v) @1. 电路错误:指的是由使用者本身电路,有不正常的接线或短路等,例如将电源
接到输出端,而造成SPICE在运算的时候无法收敛.根据Ref[38] 的建议,请
! j0 B3 G$ t& v5 D你确认以下之状况:
5 J' N& R, \: x- }: P7 }Make sure that all of the circuit connections are valid. Check for
incorrect node numbering or dangling nodes. Also, verify component
polarity.
Make sure you didn't use the letter O instead of a zero (0).
- l( `+ f5 Y7 uCheck for syntax mistakes. Make sure that you used the correct SPICE
units (i.e. MEG instead of M(milli) for 1E6).
Make sure that there's a DC path from every node to ground.
. G) ^. b0 l. G5 m4 y2 I, eMake sure that there are at least two connections at every node.
* l% I; Q8 Y7 `# c. J" J7 iMake sure that there are no loops of inductors or voltage sources.
0 u) C7 ]" b8 @; A# W+ L0 w$ gMake sure that there are no series capacitors or current sources.
3 h; O. D5 u8 h, q/ ^- |Place the ground (node 0) somewhere in the circuit. Be careful when
you use floating grounds; you may need to connect a large resistor from
! ~4 X) o$ J# x0 {3 A# ~the floating node to ground.
7 _1 M& T' ~7 SMake sure that voltage/current generators use realistic values, and
verify that the syntax is correct.
6 |( }! Y* `+ c4 h9 |9-46 VLSI 设计概论 / 实习
Make sure that dependent source gains are correct, and that B element
expressions are reasonable. If you are using division in an expression,
verify that division by zero cannot occur.
! k+ N0 ]' w4 QMake sure that there are no unrealistic model parameters; especially if
you have manually entered the model into the netlist.
Make sure that all resistors have a value. In SPICE 3, resistors without
( p: o7 [+ H! a: U1 P$ Nvalues are given a default value of 1k Ohm.
Negative capacitor and inductor values are allowed in SPICE 3. They
8 w0 s* ~( s4 Y1 @% Q/ s+ ^will not be flagged as an error, but can cause timestep problems,
depending on the topology of the circuit.
: W8 e" U# x8 s3 U1 G$ w* N+ x8 P& F2. 检查Feedback : 所指的是在序向逻辑电路中所产生的,你可以检查一下你的
- s4 J- f2 [! ^% k2 J电路的FeedBack Path的Delay,在不影响电路功能的情形下,是否可以调快一
  V3 T3 k' \: E9 T点或慢一点.
: H& ~* E9 O' ^; L

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wu68aq

谢谢分享

lxuande

好好学习，天天向上。