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装完还是显示052 4 g q; Y. f" Z
Fixed CCRs: SPB 17.2 HF053
5 Y+ y7 P: w! {8 C+ s) I03-01-2019# j* k& u/ G, p5 }2 i: t" n
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CCRID Product ProductLevel2 Title1 T" m: X% i; P* s4 c1 t7 l
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, `2 w6 n1 G4 w7 f$ b2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right7 R& Z4 V; ?3 b- x6 `
2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag
- ^0 Y. b4 E$ G5 D/ F2 \: J2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name- y/ A/ i- m( D1 C, M
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
( n! y3 \2 F8 w* n& h7 d3 p; a8 X o2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error
$ j2 c4 ?3 s7 e) k2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
7 r/ k: R2 O" O% l: W2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer
8 Q) O, l4 @ M( b8 U2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down
, F- }/ \6 x) g7 l- [0 N1 x2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
6 [* m6 w$ x- S' ]- Z8 E# Q2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
/ X! {' O1 R+ p. ~2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned" N5 t) B. x7 v, M0 v. |8 j
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
1 _/ N+ e" i8 z2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
" |9 U! ]' g$ M1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.( y3 b/ n# X w' @ _
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization
: r9 j2 |# {/ A" \5 q2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack. H1 s3 h6 M* f0 ? p% U
1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols) d6 P2 |3 a& m$ s- a7 e
1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines
3 \0 o# B# `5 j: Z. @3 J% ?$ M1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.( Q% |2 `, l$ i ~) N. `
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types
1 H/ w" N$ N1 k% {% x3 G2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.
. n8 s0 x# _( m& _# I% t: g. H2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
" \4 ~; Q; G, {2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation/ i e0 L" @1 k
2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
7 s; J0 Y5 [- L: B2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column% K* p1 K v: h2 `3 c4 d
2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.
4 Y* H( V; ~# ~! d2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table% I! l5 ]9 o3 u: g: m% }4 K) I8 X
2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data( x% |6 l2 w2 F; ~2 B* v$ q
2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value+ k0 Z# _ _, T# P# ] }+ h
2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added9 `; z1 s0 |5 y/ k* H
2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created& L5 g( W& f+ `2 O$ Q- d! P: Q
2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev X" l6 }2 T y9 p
2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point6 L9 f1 y6 o$ _' W( q# w0 |0 S
2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding+ |4 H. S: n' K" j! ?
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
( @( e8 n5 {/ [" i" b% c* ?2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.
1 ^9 S9 D4 z. T- z$ A/ J5 o2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
' z1 O4 q: G3 a8 p2 S3 u1 t2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.
* h0 p1 B* Q) W2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash) J' G- @, [. V \
1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint9 i& k/ ~2 d, `9 h
2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB) ^$ s& u& A$ D& L1 Q. \
2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash1 ]' W- x. E1 c/ Z: L
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas: r& X+ h: i5 h; N) R) @0 A
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden: N9 o- M3 i+ b0 ^
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash' P& M/ H4 Y; e# S
1699433 APD EDIT_ETCH Field solver runs when not expected) u2 C8 ^. B% X) ]- I# |
1937159 APD EDIT_ETCH Routing clines takes long time
- H/ D. h$ Y* j4 K) D8 f; H; }8 u$ @3 e5 Y2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region) ?9 F! z1 f0 Y2 T$ X- \
2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 0513 z3 X( E- V' ?' K0 b$ z% t
2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture% l4 B# H& X7 `: `4 K
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved& D2 ^' s5 E9 I. D( l- F& X
2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project0 d7 \- C) w- r+ Y
2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification
# g* {) V* ?/ n! j9 P0 I2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
4 H& u3 R9 ?0 B/ R/ Q2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source1 f& s2 i' i+ K* y) Q; Q- C. s* M) q" K
2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol2 H5 |8 U0 h5 Z0 D2 z- `. k. J0 r/ E
2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks" C( X- s7 E. X" q* b
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
% x4 k2 D; Q1 ]! G. E5 i1 I2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library9 P: Q6 H7 h. F
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty1 \; p: a! O& }$ _% n6 n
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
- s+ w& @/ Q' u, x6 [1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled: o# p m/ N, g/ h1 a
1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components
/ A% u: D& _( u |1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names S9 f; p: b5 L1 I) b1 |! i
2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character" t8 Q! C+ ]2 s4 ~2 t2 S! A7 v
1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
4 Y% A: @0 P0 k3 w" B1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
( e& c& y3 B* n' {. E- U1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped
0 H6 |6 g; l1 C. `% y1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical
6 C8 v: K6 K6 m1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
1 ^" w+ K1 ^8 e6 q6 Z4 p9 U1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas
+ K0 f1 k; u5 [- A; J1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment& A% d8 E: q/ |: y- ?- @
1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast
" A) c5 F! o {& @7 J; O1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently4 d, j0 l5 K# X. u% O1 Q; G
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page, q( j% a8 }- n: Q0 o( J2 o
1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI: z) _. p5 T- P1 ~6 i4 [
1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created
0 k9 q0 d1 l+ ^. q2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
' W' g; A% a# Q9 O5 v& M1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it* U( {) n: q- {
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL7 E$ _! Y7 T. j* P% A
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
0 y4 P7 l5 `& y5 r1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message+ ]- ~2 i0 B+ i3 s* B t# B
1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor
0 L( x5 X1 ]/ Q, b: `/ a* n% f2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder n. J( [' t* a7 \; o' a3 l: w
1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message, Q+ C( D6 j. {! e; I0 d
2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component
# n* D9 P% I6 Z4 V& ?8 z9 }1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES
: V& W; Z8 O( Y1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option( Z/ ?* V- N; A* h3 z3 z& @
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor* C& j% p0 E3 } r0 y e8 v# G
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发表于 2019-4-8 19:46
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