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装完还是显示052
+ I; h% B, F5 ~# ]Fixed CCRs: SPB 17.2 HF053
& W# o; `( g" ~1 _2 N- s+ n03-01-2019
% U* W" l1 Q) d u/ F7 L======================================================================================================================================================== B: y$ y a, a$ h3 F: ?
CCRID Product ProductLevel2 Title1 o+ N; K. ?5 I! C; Y* Q) e
========================================================================================================================================================5 |' G6 Z+ I$ u$ b' [
2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right
# q5 e% y/ q% P+ T9 }& S# z: K" _2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag
8 }! d7 `: N& J2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
+ k4 J0 H$ S4 P% Y- \2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design% O, n5 r( i1 Y) H% Q& g
2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error5 y0 _# z- k/ k
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object5 ?% m! K, d1 p& K! ]- N: o
2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer% A* ^+ V2 j2 I* g
2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down
; @% G- _3 m/ q/ l1 _ w3 \& o2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
, \6 p' q3 z5 Y7 k3 J% u2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation3 H$ I8 B: e$ E% s
2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned0 ^/ Z2 T5 N, ?7 f- O
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded2 U1 R- X8 c1 A5 `! G* p5 n/ j
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone F- B- V" j5 S7 @' t" d
1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.5 P: e; e/ E$ q& d8 H
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization' M! w1 Y1 I6 H8 l: Q
2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack7 i) T) H$ \/ [1 H2 X
1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols
. c" L+ B3 e8 W1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines5 Q- S) M9 Q9 q1 h0 V( v/ n
1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.+ J8 s/ q8 ]8 a6 K8 G3 r
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types
, `8 d. P4 h3 i5 l: f2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.3 M" G/ h* ]) R. ~% ^; O
2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
9 `0 T. |5 F6 d) n _8 C2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation
5 ^' d% v; _. o2 [$ r2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design1 O! h5 e+ Q$ `! b- w. a6 Q( b
2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column
) `; ]) z$ i9 t+ E2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.$ J+ X( C# [, p: a
2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table. e4 f' V) @' D6 R4 W" L8 n2 W
2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
8 y! { g4 a w2 R2 f2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value
0 @' J8 C0 k$ N, j [7 @) O2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added
" R* X# E- x" Y* e6 J) {2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
; `/ B6 Y9 |5 g4 L/ R z( J2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev
' L O+ U/ t! @% Z; J2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point1 I! z6 I" t, q0 F+ E
2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding
2 I# l7 F! q/ e% g2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
( m/ g# w8 F3 l& \2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.6 _" T0 q- e: Z) O! Y' L: p# Q
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present, y* E5 ~+ n7 O7 Z; \2 E5 J2 v
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.% }$ z# j# b2 K8 p" _5 c0 x! h! F
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash* |: ?3 x3 q% ~" s- @/ q
1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
& L+ ? e( E- a2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB: c& d6 T; y# [1 @* j7 G
2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash8 h# A: x+ C: z1 l6 B
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas$ ^+ ~. e U" i1 F
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
# b( s# V; j) K" X7 k& U1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash& B% r, J2 s7 B& U# ~
1699433 APD EDIT_ETCH Field solver runs when not expected
9 {5 }% D; K0 I( h% w5 n$ H1937159 APD EDIT_ETCH Routing clines takes long time# T! u" c5 G2 Q' l- I: Y
2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region
_- ^& ^6 A. b: W s' w+ W% J2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051: O, ~7 \4 y+ x6 ~2 k& s4 r
2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture" Q2 S2 h' J0 f& U
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
+ i1 Q8 T; k) N: }2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project
5 k4 M$ h8 P. q W2 e$ J! ~, g2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification
9 f! Z7 F# A, ?5 _2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM6 O; h$ f [) W
2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source
& H3 t5 f1 [) J! {3 O) Z( k3 y2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol0 P) R3 M) U9 ^ H/ L0 |
2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks; _5 I: w" F+ y$ V
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor1 x9 h$ g$ u' m* N
2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library
0 f# b" X( [% Y, d0 L6 }6 f2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
) A6 @7 p! }. u) C( ~' V; r% g+ m1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
# ^- F0 j5 M- p4 p1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled7 H4 k- T& [" B+ _* ]6 x8 J/ h$ x( O" G1 A
1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components& \7 U4 p p% g: W5 f- g
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names5 y, K7 t" C6 K0 t- P4 }
2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character5 {" P# B% e7 m
1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas0 R: m! Y+ \( [, e! B
1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
( G. x2 f3 y* H# ]1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped1 F8 R2 b6 D& Z+ |, q
1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical# o) W4 v" g( e0 U( v# d2 \
1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
& f: g& \7 m4 ^# A3 `! w1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas% C4 ?' z- Z: R! v
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
# d% t" W( Q7 l% V6 Y; t1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast \' ^& ^6 d% O
1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently
$ Z/ U) m0 Z; }; I1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page6 \6 g1 F& E7 [4 s4 g
1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI
, A9 U! z9 J, @7 U3 r, q1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created8 U& Y" v! W2 D
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
' _" h7 k+ f6 l1 i1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it; j. j2 N$ W. M* Z( K0 L7 Z
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL
$ j1 x+ {( A' V) e5 w% U1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture1 G# }" l( [' T: y7 q" q0 W `2 k
1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message( q4 f) B2 ^7 X, s0 d/ d
1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor) s( _9 G2 J1 J5 I& W" _
2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder% r6 s6 a+ h& m( B, ]
1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message. R% e9 ?1 P# R' S" |. C5 R
2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component3 \! f+ ^; G& v0 g$ h/ ?
1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES
7 ]2 `9 W. P& g+ B1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option7 b& T0 c- \) w4 R
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor0 Q' k3 O* g( ]7 E
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发表于 2019-4-8 19:46
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