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装完还是显示052 % Z2 V, E S% v6 w8 D1 i q
Fixed CCRs: SPB 17.2 HF0539 E M' X8 p7 v, J A# {! F G
03-01-2019
. b. `( r5 y. b========================================================================================================================================================
& Y9 i! i( }. a9 O" c" q' a) @CCRID Product ProductLevel2 Title7 b7 j9 x& }) K: L( C6 ^9 B/ O$ T
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+ p6 }0 }$ R# M6 H2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right
' g5 n* ]3 w, J3 |4 F" l2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag
& z$ y/ a% R6 b( F' ^! c/ p* N2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
- p' G6 i) ?. x: z+ I5 ~# S2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design: I, m& b3 p& j& y, i
2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error
0 x6 X; Z5 E. u2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
$ E% Y5 S; T) t+ |: T2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer
. C. }. d4 p! f% S* J. t5 \6 j9 ?2 L2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down, T* s, @) H: `
2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction9 G5 A( L( y/ L$ j6 b
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
3 H0 V7 `% g) b/ N+ T- s2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned
2 F6 N9 e+ Q- i2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
0 J3 a9 o V! e0 D7 {- W2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
) t) a7 E4 O/ H0 `" }3 ^; i1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.: v5 M/ j7 D, Y8 c1 C
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization
* Q: O: c; @* R$ V2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack
) n% s; |8 V- G" h1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols
K% {# s) k- B2 N% l7 Y" Z1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines
7 ?( e& k2 L2 h- p/ l0 ]5 D1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.! V4 L; p c0 e S U6 [/ H
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types- W5 D0 T) K8 q- ~- L4 u# X8 J- t
2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.+ V: z a1 v: C8 |5 R, B" E( F
2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
9 Y8 J! P9 @: R4 S* i! g& U2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation) E9 h6 d a- L% @4 d" k6 M0 x
2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
$ B! ?" s+ c# U4 g3 E4 E$ G K9 O2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column# U; V2 J( N) F. Y+ |
2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table." D8 [/ f! ? Q) @2 _0 q/ j
2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table
- y2 c+ U8 S, H9 N0 t9 B. D! B2 q2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
1 y- @, W7 q4 m2 Q0 }: }$ r8 t2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value
5 c. c+ u1 |; S! |! ^6 ~2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added1 K1 [4 L7 X! A% |" T
2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created" x& }" b6 u ^; Q' J- j
2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev, e! i% ^! L k3 t
2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point0 n: \7 X# k/ X; @4 N
2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding6 l: Y. N/ f/ K0 |0 K. P2 Z
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update1 W9 g( J! O4 f2 y
2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.
+ r) y) g0 ~0 A" j2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present* D. D% ]- ]/ N" A
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.
: x+ ~( U7 @! H4 [. i2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash/ g3 t* b) y: A5 u0 _6 l1 [) @) E
1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint* `* G) v, t! u( b; x2 O
2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB- e3 Q4 B, @' e1 K0 e' }$ F( ?/ q
2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash4 n& P. d4 L: t9 }% Y; M
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas' |* W! G! x$ ?9 Z" R
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden& f) P$ S; A7 X" Q5 \) `
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash
, |8 ~* {0 H, w6 F& {" w1699433 APD EDIT_ETCH Field solver runs when not expected
& L4 i/ j" H0 m1937159 APD EDIT_ETCH Routing clines takes long time& }9 U, | x% j6 Q* L! m
2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region
! J1 \# o7 g; Q1 Z' e2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051 q7 T& w8 c/ \& V8 r4 R0 r4 ?
2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture( O2 w1 s5 u& v; U
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved/ Q( `% N9 e, v. P( j
2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project$ \" @+ T1 q/ x8 D
2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification
# V" e! k2 I" u4 q1 E2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
/ o! p: N% m! S) s: z2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source
8 W0 L" a5 e3 a/ u2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol
' B" I( Z t/ ], X3 Z) L2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
. b$ F' X% z4 C3 k2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
3 p! I! b1 f/ u7 j& t7 `2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library! P! B9 o9 }3 j8 E
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty& p4 ^9 [1 p% W5 ?7 E! c' d
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
) V H. Z7 t& |- k. X4 q1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled
; D, N& m2 I) t. `$ w1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components
3 D* g7 y: ~) B. R6 f: f% z1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names9 j# Z s* t2 `9 f
2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character/ E& O5 t6 f0 y2 i& |
1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas& [+ d' f' B* Z* W$ K- p* {$ Q
1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option) _7 d* f7 X. j$ e7 \
1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped
0 e6 C5 R! |$ {5 x$ v1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical
" Q4 X9 }$ m: K9 n; p" J1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
, y6 ~3 t4 i3 m1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas7 h$ ]5 w. J9 l3 g( c, y: F" E) e
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
+ F$ Y; Q) V' ~* S6 F4 K1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast
& E0 e9 @! o' U- e& f1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently0 G2 w% K9 P, }, D" M
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
" A9 y/ w( m0 P; W& P" y+ T1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI. \/ K. j* H8 D. U
1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created( j- d0 E& B& X
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library+ |$ ~* t8 u+ s- Y
1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
+ u7 V$ C% \5 Z3 m9 P1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL
/ Z: `, S. y* `% x- Q1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
; {% ^2 f0 F% _8 f1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message. C! `+ ^ n7 ^* v7 z- R
1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor
9 q" }. \' w" y8 ^1 B5 d2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder8 n+ m1 G* \3 A v7 N
1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
5 D4 a$ G8 N5 J1 V: `, [2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component. C) F+ h# o2 b5 S% ^
1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES( `, L; p' l, [4 e/ T1 v$ w0 o9 \
1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option6 \+ i4 r8 x# S' @( x% i- g% s Z9 A
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor' d2 a) {0 b& }4 A8 o
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发表于 2019-4-8 19:46
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