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装完还是显示052 ; d0 e- d6 b. R4 S$ s) @) y
Fixed CCRs: SPB 17.2 HF053
& c; m. j$ l- B X3 @$ I03-01-20191 O6 a% L9 n4 S6 q" B, C
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CCRID Product ProductLevel2 Title
" |( l7 M( P* ], U0 E$ D========================================================================================================================================================( b' C8 ]8 y! {# `3 _
2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right
) d E* W& U, M, [8 h2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag+ Y4 {1 t$ ~5 f- T, l- a
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
% n; `3 ~# }" m5 p# ]2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design1 V% S4 d) Q9 ^3 ^" d
2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error
* r- D6 `" @% f- J( M6 D% G2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object& T5 r0 [! C$ |
2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer
' W" E/ {) ]; n2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down
/ L1 S: A' u6 ^2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
* V& P7 r! C# E2 F2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation: B/ H; [6 U1 |8 Q
2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned
& F4 @* Q4 a7 z; f4 z6 m4 w2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded; V$ Q% _/ G y
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone. l3 `7 _6 M9 y1 B8 B0 R
1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.. A) N, |$ B, B! x
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization
! D! i* ~& p" p2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack5 g! P# Z. g2 q) Q9 b* Z. X
1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols
, \9 A6 O* j4 y) w, f/ r Z" } s1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines8 z# T% w' T ]1 G( R& P1 o8 m
1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.3 y* a% y5 j* c+ k" y
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types
! d+ m4 n1 o" A/ `' B6 ?% G- d2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.
+ z! J+ L% z9 ]1 F1 ]2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
* E- l9 _. U- k2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation% i" Z3 A- _2 H- i( X; Y
2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design2 ~- k f. ], Y) q9 `) f
2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column
7 `4 L+ J' M0 P; U1 X0 m2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.5 l0 [1 ^0 s- u8 P V
2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table/ K) l/ J0 K/ j4 I9 W
2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
$ n1 r8 U) n# `2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value
' t0 m; Q6 |. [) B+ }2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added4 d7 y( w7 O9 U
2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
2 f2 S- G) g1 O( x1 X7 X7 W/ M2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev& u( i: O6 ~7 d$ \5 n
2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
- {6 i) B# e6 m* N& t2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding% \- V. `4 e% @4 W" c
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
) `( }2 i9 n" O2 v5 B4 V5 T Z2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.- v) Z1 j0 ]; A0 x v; D5 B( m8 M
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present/ k7 a" d8 J6 ^5 G
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.0 j4 K8 E3 ^' h" a. i
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
6 T! Z8 ^1 Y& b1 E8 V! u* O$ @1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint. Q3 x5 g! n3 k( U& k
2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
6 G, K/ e0 U5 J7 q: a2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash
0 f, U& o/ S# G3 j3 A. b2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas# M+ I. K" m7 V; v/ x
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
s! P! ?4 I5 K) ~0 o0 k0 p' l1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash1 X( J$ x# g4 A* c f1 A( G) L/ v
1699433 APD EDIT_ETCH Field solver runs when not expected5 B/ i9 x8 D6 Q- F, c7 N+ w" R" w
1937159 APD EDIT_ETCH Routing clines takes long time
/ U5 Y, \- s3 \+ i4 E( l/ }! W2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region; n3 k3 W$ e r& O0 P L
2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051. W5 |' Z6 B) s/ [. t" }% B
2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture/ J P+ Y! o- w, f( s
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved* o _# Y' z8 B R
2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project) h) R* q* _8 x% n `# C
2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification4 Z! |. t3 k b( L2 u3 K, l
2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
" f- {- z2 o) b2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source! z2 ?1 M9 I3 u
2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol# D$ d5 z3 N4 O; S1 f4 X' w: @
2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
3 j+ m) Y. A4 Z+ Z" a. n2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor8 x1 d/ o# _6 X1 z9 k
2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library- Q8 Y; H% O/ ^1 F V
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
- Y6 {" d' @, b6 a1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
1 \8 Q0 _! W3 p4 m& g5 }; |( E; @1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled
, @. V/ J) i/ r0 r9 p p1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components
q |! O: ^ I& B; j# N1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names
- k9 u5 p: `9 r$ M" p$ `2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character
* V% j/ U* u# \( F8 o1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
" T# K+ J! Q* @0 a+ v- K* m+ S1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option4 w/ t! C5 t5 n7 z2 Q4 F6 j& o
1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped5 \# r# H2 Y5 X! B8 Z1 w
1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical) U) R \) `& D, O
1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
; O8 _9 x7 W8 ?( r0 d1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas) N. M" ~0 v# l
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
5 `, b0 S. g1 K* v1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast
' S* K% x) q% P2 _7 A1 \% M0 n1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently. w! k: Y1 d/ w3 m# ^4 w: E
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
2 Z0 \- Q$ Y n/ X6 h9 J0 w2 {+ C# L1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI5 J& V4 s$ j' I7 c8 ]' C& v
1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created
" f" L' E; M' x/ X' f# ]2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
! |/ `. K, C8 u" N. g, T" I7 f1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it, c) A5 H$ K- G1 T' A) p7 J5 J
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL7 \9 O9 e/ m$ q1 P& q
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
- I4 r! O2 N6 E# }: R1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message
; f$ }. J( j9 q/ }/ X) v1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor
! k4 o0 S$ f0 v( f$ h; a5 U% I2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder: T3 g0 w7 c% V& q f+ v, {8 h% y- P
1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
+ Y' i+ ?. h" O) H ~2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component' P/ V* y1 T7 n4 ?' x! F. G6 Y
1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES
: h- B( R5 V- D P7 R. D, w) Y1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option, @0 l& P% }, X$ f! k+ F( _: \
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor
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发表于 2019-4-8 19:46
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