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装完还是显示052 1 { S2 F; i7 o" ~! P/ |
Fixed CCRs: SPB 17.2 HF053
e( }/ n* S, Y W03-01-20198 \) A `( L9 R
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. \: B* c; c' G! i- {0 {CCRID Product ProductLevel2 Title+ M* k9 i/ J2 j
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2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right& B2 [6 G9 b- c9 ^" O! C* S* S% {$ h" f
2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag
; S' W7 y( R" T$ _ N6 \. M2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
* j' {. s& h9 r6 B, s3 T# a2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
4 c4 `, S' @6 ^8 J2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error
) B9 w& y- G, {; e" s2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
/ {1 i5 D( z' o3 d' b- z% K2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer
/ ^8 {! {, {/ ]+ F$ n2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down) G) p2 m* o+ g: V, K
2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
9 m% A) {/ U6 ~9 @) D( P* K% s2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation- G& k0 f: c! i
2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned$ K9 N7 |5 ^' w' ^
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
8 F+ @% o8 Z/ b9 n! c' S' K7 y2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
N6 }4 V1 M7 M) E7 v1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.
- D. b$ Q; Z$ @3 X. u4 ^6 L# r/ E7 i0 w1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization
2 T( _( O( _: U2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack( N$ h0 Y F7 A4 p5 }. k
1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols
2 i7 A" Q* r5 N9 {* X& }% @1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines: K4 A6 v5 W) u, P2 G4 B
1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.
- W: j" J# y$ ?8 E7 P2 z1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types' Q$ j8 Y) }6 j, w
2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.
# I+ H/ n3 ]9 @! Y( c7 c! n2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
$ x, U+ E6 o1 A. e2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation2 T; ~9 d1 K5 K0 P, m# b. h
2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
0 A9 _0 E0 H6 W5 v# \; D8 i+ b7 J* ^2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column% y3 m. I( B- V+ |
2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table." C' `3 B. W4 y8 E& g
2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table( t# |: D' h8 X' o3 U9 g
2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
! F5 |4 n! `2 z j4 Z9 q9 y( {+ U& _2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value0 _0 a- Q, B: z
2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added* |2 x2 \( @- V- a5 F" ]% w6 I% }
2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
+ P- q. ?. d Y& L2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev
, z" m6 W2 d( h6 _* S- R2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
( g0 x1 F4 t" ~- O; J2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding
/ @. v6 n5 Z4 j; u, p2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update7 N% S' ]7 b7 n: I
2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.
- v( m/ o" M3 D7 h$ y2 H2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present) @2 b9 {8 f7 D2 k9 A
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.
) g% ]1 h1 v+ f' H2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
/ Y$ w' |9 S$ {: \0 O1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
! ^9 r+ c1 K) ~. g4 x, h2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
! p* Q& P$ M4 P! l3 N3 t+ [) ^+ {2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash% C2 n. C4 y* ~
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas
+ `* i$ b2 |3 U& I1 s2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
% {% \! e- D- j- q1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash, k# M1 N7 g; T; }9 a) v, P+ N
1699433 APD EDIT_ETCH Field solver runs when not expected7 i" }6 ?0 ?( o" ^
1937159 APD EDIT_ETCH Routing clines takes long time
# x2 S9 c2 P% p9 t j2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region
/ `- X" S- b& ~- p! G2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051
) J2 V- J, \" ^" y2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture
3 J/ X2 p6 |: d" ^$ j2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
: R, J! k$ M \2 _, a2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project j" Y: s- x3 T8 E# Z/ p ^4 L1 T
2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification
& X" V r! J4 w- }4 l2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
% x( T& Z, R9 o& d3 b2 Y2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source3 O2 r( t5 [6 ~ b$ ^, l
2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol
! Z K! q2 y8 T% c {0 O2 n2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
. f; e3 J7 J4 J Q0 C1 ~( _2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
6 G6 X$ ^4 G. y% \( l% ?3 m6 q2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library
( V$ J5 O+ |+ ?! g1 a7 T2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty4 |! \6 S3 y2 h; M4 V
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
) i- y* K+ u% U& P1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled3 Q" a+ h/ S4 T+ |" Y: N7 I2 ~+ }
1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components+ F$ \2 t5 C. ?, C$ \ ^9 J
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names. L: s6 U- ]( w, `' f) B* \
2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character9 I! y; z$ k, y1 }6 G
1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas( h* s1 Z+ b Z* n. c9 d
1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
4 S6 H1 Z& B1 q1 n1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped
9 { }; g: V" g6 @1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical
4 R5 l& q0 O# v4 v6 X. |1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
6 C* }7 ~; D3 k" t9 w) d1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas
1 X; t! ] z' P) Q! N1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment7 {4 J' C1 m* I+ w3 L
1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast. U! R1 `' ^9 C* ~8 C' H
1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently
/ o7 W6 Y: u8 B8 i2 k; b5 W" ?8 F1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page- P1 e; M V6 J7 {1 _0 Q6 C9 U
1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI, Y# X7 |3 S/ Q$ _! O( ^7 J
1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created5 f" z. e Q0 y8 e* K+ x' f+ g
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
5 Q9 g9 u# M" M( @+ \( W7 A1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
2 G- p" o' K- z( s4 M g1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL' K( L5 f1 v) z4 p1 [
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture' O5 J- l" W! l6 |( j7 A
1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message
8 `( |9 j7 x# b0 h7 m1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor
2 [0 ?; z8 F" O( I2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder
6 o8 Y, X( N" Y! Z% e0 u1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
3 o% k0 d; J" C5 |$ v2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component- `! `2 {. X. `- o5 f" L$ Z2 h% I
1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES
7 R8 E# ], `% Q% Z1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option/ `0 q' v9 N O" K) r6 k4 W% Y
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor
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发表于 2019-4-6 21:51
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