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装完还是显示052
- a! I/ G/ W* J, A: G6 ?Fixed CCRs: SPB 17.2 HF053! [/ E9 E3 V; i0 n% Q* Y
03-01-2019: c) J) R8 O% }, s4 @# @. }
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CCRID Product ProductLevel2 Title% ^0 ~3 ~& Q6 y8 T- t4 P
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2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right
9 i$ [. C2 k5 s# o2 H% K$ {2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag) V0 U$ ^+ P3 E( J! Z
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
* ~6 k6 D f) S5 _' r/ E' c+ j2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
2 A; _' @/ K2 o8 K$ X2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error
/ m: N. f# F% s. i2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object" U: m& K( M, d" j! o8 Z# [2 G7 h
2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer" V7 }; Z$ D' T$ Z8 u. b
2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down
1 B+ e$ `: s g2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
9 m' _4 P4 x; {8 {0 ?3 {2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
9 N$ @* G$ e: D& j- @3 I2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned
% J4 Q: V/ S: o' e8 O2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
4 V# Y5 y8 h) A# Z2 A' w" G2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone: t- ]+ J: B& g+ [2 e
1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.4 h/ Y' G8 H6 Z1 u8 N+ H
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization
( A( h& ~& t$ s( K. Y8 ]3 P2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack
0 n3 M7 R% d. @7 N2 r5 c4 _1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols& k; J% P. Y; Y3 N0 p
1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines- X, M, g! ]+ X7 k
1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.3 o" O# m K4 t+ m- {2 C
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types7 ^4 P, J& y( _. i$ y/ J' K$ r
2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.: Q `8 l+ }: `9 O: N% y* c$ |
2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
/ x2 ]3 @5 t @/ w% R2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation z+ u) U0 o) {" w ^8 Z
2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design" r1 i3 R F9 A% |
2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column
* F* H1 X* t# ?% O0 }( ~2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.. H& e) w* t4 t, [6 e- \) U
2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table1 x& x6 V* o: D8 T: x, A
2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
4 L. u* }5 L+ P S9 _0 _* A5 Q2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value6 A3 j5 k2 ^) Q" T9 n( T
2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added
! S" G1 d4 t4 v/ i9 _2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
' R! k7 C5 W1 v2 ^$ D. \$ O2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev( K8 X- d5 \6 O I
2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
. `6 m, A9 W) J! j6 t; b1 n6 }2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding7 h/ ^) \9 g0 Z& v9 s# E6 j7 `) N
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update4 X. }# s* B7 h0 \5 U. E! m4 o$ l
2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.
0 G5 E, B: @2 \, w+ ]2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present( X- r8 j3 S5 e1 o- U# Y
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.$ T; i; h1 U& |. R/ Y
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash2 o' `1 H0 d, K
1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
/ p! o: K( P! z+ a* |- Q2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
8 S0 d6 w4 L4 S7 D2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash
& {" w- \1 e" `: y; }2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas
# n& @- j3 q' @) P2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden& o9 l) ^% K* {$ J1 u
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash
i) v$ m4 a* r+ E! z1699433 APD EDIT_ETCH Field solver runs when not expected* x: G( Q/ s! u0 V% X
1937159 APD EDIT_ETCH Routing clines takes long time3 {9 L& {5 m* [/ C5 f
2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region
. w8 h! y/ T: Z! H# i0 j2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051( r% S( n6 D# P, C2 E4 R+ O
2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture @! _* U6 o' d3 C
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved+ `7 ?6 }+ Z, }
2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project/ X) D/ h V3 p7 Q! \4 g
2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification
7 u: p9 z" H+ S0 i+ h8 E4 v( w2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
; t. o) V1 ^2 \9 f: y3 |/ t2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source
1 m, c4 U2 C: @$ M C+ ]9 Z, @2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol1 g' n* N; U! C! R! Z: T% ~( r
2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
$ ?3 H4 G* m* w% o G( Y6 c2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
% W: m, f: p4 _" P4 w2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library U1 \; A4 V; C* }5 d# e0 o
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
$ R3 U; o: [" V# z! j1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
+ d# L1 a) y8 U: H1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled. o8 l2 X* o% r, l a, ~/ @
1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components: R& `' y; a, Z8 q7 @
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names1 K2 ]& S/ H4 D: U4 F0 h" G
2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character% H/ }( `+ o4 P, s' E
1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
9 J& O( r$ s% Y6 t1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
# x$ e7 _1 p% Y% Q- J' q! n1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped7 H3 F2 B+ B2 |" r2 c' X
1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical
4 d' ~0 A: t1 }( i# V! _1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
/ E! Y8 i( @, q4 S% q1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas3 s, a! v) K% R# k% W
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment- Y1 d% _1 l& E \) F A
1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast. }3 M8 v8 U# c- T) I( C" x6 g
1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently
9 b' r3 [% V. m& e5 Q1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page6 c$ S K' Y3 P7 b; R# o
1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI8 i0 ]6 }* r" d+ c; H
1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created t$ A- ]% M- v6 R
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
$ V4 F& |) Q% \) s" t1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
) W. o0 Y4 F& ~4 a1 @1 S/ x1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL
, P [% x5 o" ?1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture5 ~! W+ { Q {5 ~& w4 j9 l% |
1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message8 L( Z6 Y( {# c5 P! G D
1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor
8 M$ B) f5 U+ M$ w+ s' L! y2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder3 S4 t- B3 Z% f8 n$ O. x
1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
* W( j3 g' }3 F2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component8 {% G3 @/ P1 w4 F; t, q
1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES4 }0 H- G7 M5 V' h) e( F Z
1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option/ ]; s% h5 \/ {' O. q
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor: S9 C+ c5 v( y6 q! c% t5 Y
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发表于 2019-4-6 21:51
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