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Placement Comment ▪ Switching regulator and PMU circuit should be on lower right side of MT7620A. ▪ Ethernet port should be on lower left side of MT7620A. ▪ DDR2 should be on left side of MT7620A. ▪ 3.3V to 1.8V LDO should be close to DDR2. ▪ RF circuit should be on the top of MT7620A. ▪ Xtal should be close to MT7620, and clock trace should have ground plane around to avoid interference, but far away from RF circuit as possible. Power Consumption MT7620A Main Power Pin and current ▪ RF part: PA2_V33N each pin 190mA PA1_V33A each pin 20mA VX_LDO each pin 25mA ▪ DDR2 part: DDRIO_V12D total 30mA DDRIO_V18D total 100mA ▪ EPHY part: EPHY_V12 total 58mA EPHY_V33 total 116mA Power layout Comment Bypass cap placement priority ▪ Of course, we hope every power pin has its own bypass cap and put cap close with. ▪ If can’t, priority is as followed RF Block: a. Soc_1.5VD for RF LDO. b. PA2_3.3V c. PA1_3.3V a. SOC_V1.2VD b. 3.3VD a. 1.8VD b. SOC_V1.2VD Ethernet Block: DDR2 Block: DDR2 layout Comment(Conti…) Suggest routing ▪ Routing order: 1) Data, VREF, 2) Address/Command, 3) Control, 4) Clocks, and 5) Power ▪ Referenced to the solid ground plane. ▪ Place the series at the line for group signals with a 0~33 ▪ Layer transition should accompany GND via. DQ trace should be shorter than 1600mil. Reserve damping resistors and place these close to MT7620A DDR trace length control : DQ<->DQS: +/-100mil CLK<-> DQS: +/-500mil CMD<-> CLK: +/-800mil DDR2 layout Comment(Conti…) ▪ VREF should be wider and as short as possible, is isolated from noisy aggressor. ▪ Keep at least a 20–25 mil clearance from VREF and CLK to other traces. If possible, isolate VREF with adjacent ground traces. ▪ By using resistor divider network as VREF generator, make sure both resistors the same value and 1% tolerance. 6 R4 x5 a! j$ G0 J0 g) g/ @: U
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发表于 2019-4-13 12:26
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