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Fixed CCRs: SPB 17.2 HF054" `' ^, ^) L4 W1 q& k+ D- t
04-26-2019
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CCRID Product ProductLevel2 Title
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2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes
& B* y% f) S) i. S. [0 `2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property
! e( l3 e* E8 K9 ] w4 B4 h+ [. X1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser
$ D- W0 ^9 {) |! W. B) q2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache
! Z" z# Z, C# W$ S5 V2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
6 l; J" Z9 h0 w! r2 y2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
% e7 I4 k- K2 M0 _# Q, d2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
' a* h) ]7 Z/ f2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas: z7 l6 k. [$ y/ \8 Z4 O V6 L
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
7 w) Q7 o4 M, v. K; H- |3 j* B8 K2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
6 |' i, g7 x( r1 {5 F& R8 _2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off( J3 M9 j. J; J# c4 G. o |( k6 r
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set. D" z) e* m9 E8 }- p% g! \
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
v$ I, j* _; s" a$ e2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements6 S. p+ P2 K2 s* m
2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin
1 A- {" |' ? U2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element: j9 |/ j% k1 o
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow) g( }- x' g+ n4 H% ?8 J
2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error
3 z! X% ~7 u4 W* v2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code& i, R- L6 K& `2 _3 |4 O% d
2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016+ G+ [3 q' q. b* ?( @- g
2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error" I' D# }. m9 o0 M) }7 u
2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets4 t0 s+ Y b% a' A; d% q5 Z' s
2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.& C6 W4 x- ?" M7 L' Y$ k! k5 i
2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.9 ^, U0 P9 A: r" [1 _
2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
$ ~# e6 g1 n' ^) y" X2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations+ o# {+ d% }, q' ]3 `
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
) z# K3 L: p$ k( L' c5 h: K2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill
3 N8 ?+ m1 X3 Z1 K6 Q2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets% }! u2 Z+ V, z
2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor" ]1 b' z6 ]4 U/ @
2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias
% {9 }. Q7 {" q! r& W2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor3 x0 b5 z# i* I. }
2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable
; L$ C) Z4 t$ u" b5 E5 e- r2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components0 ^* y# v4 e8 A4 ^
2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report j' a& [6 }6 ]
2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL1 N4 ~8 F$ i# X4 J
2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
+ W4 @5 y. w! L& U' p( M, ^1 T3 g2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
, s6 g! B3 x9 p& v$ u2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'( |( ~; X2 L/ o9 r0 O" j& V) D
2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
9 `' p2 J% N+ z* J0 L7 m$ \5 |2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present; C0 M& x/ r- J1 k8 j! V! D
2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes
; ~) c7 s! e9 s* B7 z" Q8 f2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'
* T8 t5 M' h7 a2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
: N& A7 y4 v6 k1 P. Q- N2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash H4 W/ `9 i* O) c0 H* \; {5 M
2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.
" M+ }" @6 x9 E) o4 v1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)& O5 v: {9 _( N; L$ P
1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
) ~- J$ ~. s1 |2 Y8 L' x2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
+ E3 C, b1 E- p2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design
$ ~0 ~! R/ l$ i2 p: k, j5 X2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas
, L- L% y4 T7 H8 z' ^2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice n( u( C$ [% W, L2 ]
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html
- d! h8 i3 E9 d, }, ]% e T2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
H$ l' j/ |* Z2 U2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.66 K% G7 [0 y, @$ c
2050674 APD PARTITION Cannot remove C-Point from a partitioned design4 f% W, n7 S9 z! J
2068814 APD WIREBOND Bond wires cross on auto-separate
/ L r& a" c! j1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open% N0 K( F( K W. Q2 p
1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
' W8 k) G. d5 L3 F2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL7 t% l- ~8 P- f. P
2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window+ |& S/ ~# v0 W& m0 ^. E% a
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
0 y2 p" t9 _6 w, ~4 C) ^: a; y2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix" O. o4 C" N. @
2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager
4 k' L4 E- e0 r% c# V; P9 D2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps
' i. x6 G) m1 w4 c2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM! ~9 p0 r, C V
2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties% P( e1 O1 \! G' C! @( X) W
2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.. S4 F8 b1 B3 t$ I) T6 c0 \
2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses+ S0 x* I/ _ M4 s8 g
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
- |# Q" G" k1 J# ?6 e2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.
" Z0 G0 S' H/ r+ I" ]; H# X/ N% y2 y/ {2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma
$ C* _! E" y1 l0 l$ n3 y- r2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.
( g2 [+ n. W) F' K3 E2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character' z2 l' B7 |; F u8 V# X
2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped; D" P# `4 R/ j+ Z0 X
2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties( J. j1 u% `7 Q7 m
1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated
, }6 w4 [. E e' y& l2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated1 M8 E1 W( d" O% E0 R1 R
2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated5 \% s, C& ~ ^
2038021 PSPICE FRONTENDPLUGI Bias display is not updated* ~4 v3 O9 T2 g0 \3 A
2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open! N ^, Q* d |% e/ S
2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component
% A" X& Y: y& J% N# t: Y* j* U0 x2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks
3 W3 X F7 l7 `9 b6 m* z/ e- x, Y2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.6 ? d- V7 _0 q0 e$ G6 A: b
2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign+ L; F4 r, m. X$ C: }
2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed$ K# f1 F) }0 V! A0 C6 ]: }) V
2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'/ Q* i% f6 ~" n% @9 G
2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
& X' K7 B' \; y2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode, e3 y( G% G' W5 b, k
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error7 r2 e+ U1 f) I% g
2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
; H" `- {" ?9 A: T/ L1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.
( [/ }" K; Z6 P7 Y, s) r8 |) _1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session9 B2 W7 H Q/ ?
1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
7 e* ] @; l# P* i5 b; N/ E- U, c2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written7 \5 d+ r6 T& Q* i- Q
1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping
/ Z+ o' P: S( T2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor+ b* c0 ^: a' R$ c' S
1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste0 b4 p0 P, i$ E, r
1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position
. F/ r4 H1 f n5 z1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM
( e8 G# ?0 k7 j. c: Z, G. o1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range
: g4 K# m& T9 y' F. m2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.
/ i2 \$ c/ b$ |# l+ Z/ T2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF. ^2 Q$ e8 R+ g3 ?9 ]1 }1 B
1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
h. h) q2 |" _5 @) u" z1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
+ i) S$ W' |" {3 g1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project |
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