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Fixed CCRs: SPB 17.2 HF054
0 E6 X4 m0 D& d5 O04-26-20199 h2 O( v; [+ s
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' w0 P) d" H4 ^4 \! eCCRID Product ProductLevel2 Title; f9 m' q- `. r, K3 V/ G9 `
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7 | L' _' K1 H8 e5 `, s2 ?+ q2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes4 j3 Q W7 C5 a) K
2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property# r) V' u# M l! O
1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser2 ?+ X+ \+ X5 S, [5 S6 v2 W Z
2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache
- A0 c4 |1 r0 `- _$ q0 J" |2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name7 v L" E3 A! `, v
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design( I* ~: a4 E; z
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object) \1 W. v1 ~( p5 ?
2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas: t- E5 M0 \+ Q/ s- X+ ^$ a# S
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation+ r" j) t2 n P% a1 F6 M
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
/ ]0 F' B' q! x) w, N( g5 W. m( F$ A) s+ F2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off& i- ~8 v: w( _. k2 T# o
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set
, W% m9 L% k$ s6 u( e7 k# \ j2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
% `. G/ ~; f0 T. r; Q2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements
; O) F) a A/ W: e \; A" x1 |2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin
$ i( ~ X/ |' q+ t; c8 I3 K2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element) C1 @3 y; F/ d0 O) |. P! @) T+ R1 p
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow
5 N6 K$ B3 x# u* U2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error* w6 }; h) v1 B9 j* b2 T
2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code/ F" l, d5 J6 w; B6 s. z- N
2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016, K/ c( n& S% |& `/ k: Z9 O
2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error2 n8 L% u4 O( j# }8 ?
2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets, w2 Q/ B; l$ H& a6 w
2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.
7 u8 Y/ V! b7 i+ E2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.. z5 H; Z! O! U6 t5 c
2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
( j. m; u' {6 e5 y2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations
3 Y2 B1 q2 [5 f, b. u. F# \/ b2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
+ \' T5 s: L1 M6 r2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill1 u" h5 m$ k* E( N- n5 a/ Y6 K
2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets8 X) o6 F' {; n: s
2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor- v* u5 r3 Q% G; Q
2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias
8 z( m; e2 Y0 p+ R v C+ R2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor' f! a/ S" D# x
2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable
! g1 }9 T$ N5 n2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components6 ?0 z: W) J+ I" h: c
2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report, A+ [9 S8 W2 [( Y8 }: z& f! Z% n
2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL1 T/ @5 m$ x0 q/ o6 x# L. @
2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
4 H! J$ e$ t4 }, t% {6 o" ^2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
- R& K. M& {& c) ^. O$ G4 F# y2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'
) t; K+ |# b6 I, F" d, S1 v1 P& F2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape ]) ?: o% s6 M: ?- C- V& m& Q
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
% @: V9 d& ~: P# q1 `3 W' X( l2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes( b, ^" ?/ X# a3 g
2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'0 S; G% Q! d7 Y$ P
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.& V! U5 X( N& E* Y, c
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash9 ]! c: B0 @( i$ R; a6 Z8 B. n
2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.
; O3 \9 X ?5 G1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)9 E8 l0 \+ |! {7 r% M$ K2 O- i+ ]3 N
1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
) P3 B3 W: \" A3 L3 S8 o$ J2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048& l9 b0 G8 I$ q5 z9 j2 u5 l( B
2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design3 J$ k* o8 o( A- P/ w2 n
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas8 L; M$ z" s& D! S- `. ^
2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice y4 p0 [4 x( } x, Y, e
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html+ V- x, X8 s! p' m( `. \" p0 y P
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
1 u/ i% u! F) w1 X. ~" T! q8 d2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.6* G( R9 H9 Q0 B) x K
2050674 APD PARTITION Cannot remove C-Point from a partitioned design
3 ]$ H/ J/ }! r2068814 APD WIREBOND Bond wires cross on auto-separate
3 p; p- W4 f- O* h, C5 a9 b* M1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open
: D' u( H. C; L) l" g1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
8 H( X I; P5 J- h( R2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL) j7 g e+ C9 y
2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
( x8 f1 O& O( g& s3 N, c2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
# a/ F- I9 l4 F# K/ j9 ?3 j8 `2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix8 H1 X& m; J& P% L1 [1 u6 t
2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager
8 ], b k0 z/ H3 r8 x3 a3 O- x- i5 V2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps5 Q; M- j+ n$ a9 X
2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM& R6 W3 d) h/ |4 i1 c
2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties) U, ?6 X2 T4 S5 @) \2 P; \. M
2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.
' g8 C6 b4 Z: x3 y5 i3 n2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses9 K6 u8 o- b1 j; \# v4 @3 ~
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
! [: _+ b4 G0 I' u$ c" k2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.
" W/ k% p2 C% u0 ~2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma8 p( [: N0 B% Y' G- ~3 J s. M( S
2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.
$ C* G/ y/ L) u Z- c8 N6 P2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character
5 f. q, y( o; J3 i, q$ ?2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped# N& e9 @* D7 P7 u
2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties1 s" \4 v! o& Z7 E4 e' u$ x/ l1 p( j
1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated5 Z1 \; i X9 I7 U0 \9 I
2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated9 M. w, K* e+ f; a) b S
2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated4 J0 Q6 J5 w% R E
2038021 PSPICE FRONTENDPLUGI Bias display is not updated* v0 E8 `1 z1 Z, H& A7 K
2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open
3 k7 Q$ A d2 X! D2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component( c8 w- l0 c. s6 O& _" \: S1 i3 X9 o
2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks, d+ C8 w1 b% s% a3 \5 V0 I1 n
2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
" R# {* p9 f r2 p6 Q2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign4 z0 _. v! O- P, A7 ^/ M
2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed
% p8 |9 ]9 s0 g6 Z2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'* R0 Z8 } {1 b/ w0 O
2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052, D5 X5 N( C% i; B! |( g
2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode# }" H2 b' L6 e/ T
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error2 P1 ?5 V: h4 T% ~% ]3 u
2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
; q) y. V' S) d( C @3 m, V" s1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.+ u* R' d$ Y) T
1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
% h% d5 d, V8 {/ X0 L1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name. @' X" {) Z5 |; M7 a
2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written
) G9 t! d1 Y/ t+ w$ \7 z1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping
8 p$ c& z! a' {% W' F2 d5 f2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor0 L! _1 b. }6 O/ k1 l$ B5 v
1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste4 e5 r& n' y9 E l
1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position$ f8 D, R, j; F
1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM
% N# z3 o2 ]8 v1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range
6 m4 |3 e; w6 J( U% T2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.
1 R( p+ |# y, h H/ N& U7 j6 k0 d2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF
9 ?2 W0 r( G- K- ~1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
) ]5 \. O& O! y1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
. B" J+ Z m, X5 G9 G6 Z1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project |
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